JPH0235547A - Test system for static ram block - Google Patents

Abstract

PURPOSE:To prevent trouble from being latent on a memory and to improve the use efficiency of the system by adding a circuit which reads data out when a static RAM block is not accessed and checks its contents. CONSTITUTION:When the system does not access the static RAM block 1 through a bus, a memory block select signal MS is held at H, and consequently a selector 3 is switched to a side B, i.e., the side of a check address counter 8. The check address counter 8 supplies an address to the static RAM block 1. The address is determined and read data is decided; and then a parity checker 7 checks the read data. Then when a check result is determined, the check significance signal CW from a timing control circuit 9 becomes H and the parity check result is read out during this error significance window and reported to the outside.

Description

[Detailed Description of the Invention] [Summary] Static R capable of detecting potential failures
Regarding the AM block test method, the objective is to provide a test method for static RAM blocks that can access all memory at all times and does not reduce system processing performance. In a system for writing and reading data using a static RAM block, the system includes an address generating means for generating an address for reading data from the static RAM block, and an address for switching the address of the bus and the address of the address generating means depending on whether or not there is an access from the bus. Static RAM
The block is provided with a selector that supplies data to the block, and when there is no access from the bus, the data in the static RAM block is filled and checked according to the address of the address generation means, and when it is accessed from the bus, the data is read and checked. It is configured by interrupting the access and restarting the operation after the access is completed.

[Industrial application field]

The present invention relates to a test method for static RAM (random access memory) blocks, and in particular to a test method for static RAM (random access memory) blocks.
The present invention relates to a static RAM block testing scheme capable of detecting potential faults in M.

In information processing equipment, static RA with fast memory access speed is used to improve system processing capacity.
M is adopted, and one with a particularly large capacity is often used,
In a large-capacity static RAM, not all of its addresses are constantly used, so there are addresses that are accessed only rarely. If data at such an address is destroyed due to a failure, there is a high possibility that the existence of the failure will remain undetected for a long period of time, and that it will be detected in an emergency such as a system switchover and have a serious impact. .

Therefore, it is desired to be able to detect potential failures in static RAM blocks without burdening the processing capacity of the system.

[Conventional technology]

Conventionally, such potential failures in static RAM have been detected by executing a memory patrol program that idle reads all addresses between processor operations.

In other words, in this case, a special program that can read all addresses is prepared in advance, and by accessing the static RAM block from the processor side and sequentially reading and checking all addresses, potential failures can be detected. Enable detection.

(Problems to be Solved by the Invention) However, the above method requires: (1) a special program for detecting potential failures in the static RAM;

■ Since memory patrol is performed between processor processing, the cycle becomes long and there are fewer opportunities for it to be executed in systems with high utilization rates.

■ While memory patrol is running, the system's processing capacity decreases.

It had the following problems.

The present invention aims to solve the problems of the prior art as described above, and provides a static RAM block that allows all memory to be constantly accessed in a system using static RAM and does not reduce the processing capacity of the system. The purpose is to provide a test method for

(Means for solving X!I!a) As shown in the embodiment of FIG.
In a system that includes an AM block 1 and writes and reads data in response to access from a bus, the system includes an address generation means 8 and a selector 3, and a static RAM block is generated by the address of the address generation means 8 when no access is made from the bus. In addition to reading and checking the data of No. 1, the data reading and checking operation is interrupted when the access is made from the high speed, and the operation is restarted after the access is completed. Here, the address generating means 8 generates an address for reading data from the static RAM block 1. Further, the selector 3 switches the address of the bus and the address of the address generating means 8 depending on whether or not there is an access from the bus and supplies the same to the static RAM block 1.

[For production]

In the present invention, a circuit is added to read data from the static RAM block when it is not accessed and check its contents.

When the data check is completed, the 7 address is updated, and if there is an external access to the static RAM block between the start of the access and the end of the data check, the data check process is interrupted and the It has the ability to restart the same process from the beginning upon access.

Therefore, according to the present invention, (1) Since the memory data check function constantly performs memory patrol using hardware, potential failures can be prevented.

■ Since data checking is interrupted when accessed from the outside and resumed when not accessed, it is possible to prevent a decrease in access speed due to the presence of the check function.

〔Example〕

FIG. 1 shows a block configuration of an embodiment of the present invention, in which 1 is a static RAM block, 2 is a system address bus, 3 is a selector, 4 is a system data bus, 5 is a buffer, 6 is a is a parity generator,
7 is a parity checker, 8 is a check address counter, and 9 is a timing control circuit.

FIG. 2 is a time chart showing the operation of each part in the configuration shown in FIG. This shows the operation.

The system connects static RAM block 1 via the bus.
When the memory block select signal MS is not accessed, the memory block select signal MS is kept at H (high level) as shown in FIG. .

The check address counter 8 receives the address update signal AN from the timing control circuit 9 (when the address update signal AN is at a low level)
When rising from to H, the address given to static RAM block 1 is updated. After the address in the static RAM block 1 is determined and the read data is determined, the read data is checked in the parity checker 7, and when the check result is determined, the check enable signal CW from the timing control circuit 9 becomes H. The parity check result is read out during this error valid window and is notified to the outside as a parity error occurrence signal.

Address update signal A again when error valid window ends
When N becomes L, the address is updated, and such 1
By repeating the periodic memory check, data at all addresses in the static RAM block 1 is checked.

When the system accesses the static RAM block 7 via the bus, memory access is given priority and the memory read check for static RAM block 1 is immediately interrupted as shown in FIG.

That is, when the memory block select signal MS becomes L, the selector 3 is switched to the A side, that is, the address bus 2 side, and thereby the bus is used for writing data.

Data is written or read according to the address designation from the address bus 2, depending on the read operation.

The data on the data bus 4 is passed from the buffer 5 to the parity generator 6, where parity is added, and static R
The data in the static RAM block 1 is written to the designated address of the AM block 1, and the data is parity checked through the parity checker 7, and then read out to the data bus 4 via the buffer 5. The parity check result in parity checker 7 is the check valid signal C.
When W is H, it is read out and notified to the outside as a parity error occurrence signal.

When the bus access to the status/RAM block 1 is completed, the memory block select signal MS goes high.
, the selector 3 is switched to the B side, that is, the check address counter 8 side, and one cycle of memory checking is restarted.

FIG. 3 shows a sequence flow of the timing control circuit in the configuration of FIG. 1.

At the time of system reset or start of power supply, etc., if the memory block select signal MS is H, that is, in the memory check state, when the check enable signal CW becomes L and the address update signal MS becomes H, the timing control circuit At 9, the time tl is obtained.

Here, the time t1 is the period from when the address update signal AN to the check address counter 8 ends to when the parity checker 7
This is the time it takes for the parity check result to be finalized.

Next, when the check valid signal becomes H, the timing control circuit 9 acquires time t2. Here, the time L2 is sufficient time for the outside to recognize that a parity error has occurred.

Next, when the error valid window ends and the check valid signal CW becomes L and the address update signal AN becomes L, the timing control circuit 9
3 is obtained. Here, the time [3] is sufficient time for the check address counter 8 to recognize that the counter value is updated.

This completes one cycle of data checking, and then the next cycle of data checking starts when the address update signal AN becomes H.

When the system accesses static RAM block 1 via the bus during memory check, time t1.
t2. At any time during t3, the memory check is interrupted when the memory block select signal MS becomes L, and the system transitions to a memory access state.

Check valid signal CW is L in memory access state
When the address update signal AN becomes H, the timing control circuit 9 acquires the time t4. Here, the time t4 is the time from when the memory block select signal MS is switched until the result of the parity check is determined. Then, when the check valid signal CW becomes H, the parity check result is output as a parity error occurrence signal.

In this case, the memory block select signal MS goes high during the elapse of time t4 or after the end of the memory access operation.
When this happens, the state transitions to the memory check state.

〔Effect of the invention〕

As explained above, according to the present invention, static RA
In a system using M, all memory is checked for reading at all times when the static RAM block is not accessed, so it is possible to reliably prevent potential memory failures.

Furthermore, since the system is not involved in memory check processing, the system usage efficiency can be improved.

Furthermore, since bus access is processed preferentially, there is no reduction in memory access speed by the system.

FIG. 3 is a diagram showing a sequence flow of the timing control circuit in the configuration of FIG. 1.

l- Static RAM block 2.～address bus 3...-Selector 4.-Data bus 5...Buffer 6- Parity generator 7- Parity Chekka 8-・Check attle counter 9...-Timing control circuit

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of each part in the configuration of FIG. 1,

Claims (1)

[Scope of Claims] A system that includes a static RAM block (1) and writes and reads data in response to access from a bus, comprising an address generating means () that generates an address for reading data from the static RAM block (1). 8), and a selector (3) which switches between the address of the bus and the address of the address generating means (8) depending on whether or not there is an access from the bus and supplies the address to the static RAM block (1). At the time of access, the data in the static RAM block (1) is read and checked according to the address of the address generation means (8), and at the time of access from the bus, the data read and check operation is interrupted and the operation is restarted after the access is completed. A static RAM block test method characterized by: