JP2000010871A - Method and system for memory patrol - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an adverse influence on the transfer characteristics of a storage device by setting the patrol unit large, executing a read instruction successively for the inspection of a correctable error, and additionally performing a correcting process which is large in loss in an instruction cycle only when a correctable error has occurred. SOLUTION: When a patrol main control part 1 sends a read instruction and judge that a correctable error has occurred, the patrol main control part 1 sends a correction instruction. Then, a correction instruction generation part 3 puts the values of an address counter 4 back to the head address of a current patrol unit first and then issues a correction request for four (patrol units) while making the address counter 4 count up. The correction instruction is processed in a cycle time as shown by an instruction cycle. Read data are read out of a memory part 6 and corrected by an ECC circuit 7, and further an ECC circuit 8 adds a check bit to generate write data, which are written back to the memory 6 lastly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a patrol control method for detecting and correcting an intermittent fault due to a soft error in a memory element, and more particularly to a memory patrol method and method for dealing with a large-capacity storage device in a short time with a small amount of hardware.

[0002]

2. Description of the Related Art FIG. 5 is a flow chart of a conventional example as a prior art. As in the case of the present invention, the amount of data handled by one instruction is 8 bytes and the amount of data processed by one patrol is 32 bytes. Is set.

[0003] Japanese Patent Publication No. Hei 2-132539 discloses a prior art.

FIGS. 6A and 6B illustrate an embodiment of the present invention.
Is shown.

FIG. 6A shows an example in which a parity check circuit 12 is used to check read data of each block.

FIG. 6B shows a case where the conventional ECC circuit 11 is used to check the read data of each block, which is not suitable for this example.

A plurality of blocks (four in this example) (BLK-0 to 3) 21 constituting the storage section 2 are simultaneously read, and each block (BLK-0 to 3) 2 is read.
For the read data (MRD-0 to 3) from 1
At the same time, a parity check is performed, and when an error is detected, updating of the address in the block is suppressed, and a plurality of blocks (BLK-0 to 3) 21 are updated with the address in the block in which the error is detected. Means which are sequentially activated by a normal patrol method and perform rewriting with corrected data (WD) to a block in which a correctable error is detected are necessary means for implementing this embodiment.

As described above, in this embodiment, read access is simultaneously issued to all blocks of the storage area divided into a plurality of blocks at a time, and the read data is inspected. The transfer to the operation causes a loss in transfer performance. On the other hand, the present invention is different from the present invention in that the instruction cycle is separated so that the maximum transfer performance can be used.

[0009]

Conventionally, a patrol operation involves reading data → checking and correcting data →
An instruction including four elements of generating a check bit → rewriting data was created and executed. Since this instruction has a small data width that can be handled and performs an operation of reading and then writing data to the RAM, the cycle time is long, so that there is much waste. When this instruction is applied to a storage device, there is a problem that transfer performance is reduced. In particular, when the storage capacity is increased, the patrol cycle is shortened, and the influence is increased.

An object of the present invention is to execute a read command continuously to check a large amount of data at a high speed, correct an error after a series of read instructions are completed, and always utilize the maximum transfer performance. It is to propose a memory patrol method and method.

[0011]

According to the memory patrol control method of the present invention for detecting and correcting an intermittent fault due to a soft error of a memory element, a read instruction signal is output to a read instruction generating unit 2 at each patrol cycle, and a read instruction is issued. When the completion is recognized by the instruction completion signal from the memory control unit 5, E
The correctable error signal received from the CC circuit 7 is confirmed. If there is no error, the patrol is terminated. If there is an error, a correction instruction is output to the correction instruction generating unit 3 and the correction instruction is completed. When the patrol control unit 1 recognizes the fact via the memory control unit 5 and ends the patrol, and when a read instruction is received, a read instruction is continuously issued to the memory control unit 5 by the patrol unit. When a read instruction generator 2 counts up the address counter 4 each time one is issued, and receives a correction instruction, the address counter 4 is first rewound to the head address of the patrol unit, and then the memory controller controls the corrected instruction for the patrol unit. The correction instruction is issued to the address counter 4 every time one correction instruction is issued. A generating unit 3, a read command generating unit 2
Executes the read instruction, an address counter 4 which counts up each time the correction instruction generation unit 3 issues the correction instruction, and executes the read instruction and the correction instruction at the address indicated by the address counter 4 and each time one instruction is processed. Control unit 5 that informs patrol main control unit 1 of instruction completion
In response to an instruction from the control unit 5, the memory unit 6 that executes data write / read, and the read data from the memory unit 6 are inspected, the presence or absence of a correctable error is notified to the patrol main control unit 1, and correction is possible. When there is an error, an ECC circuit 7 for correcting the read data and data corrected by the ECC circuit 7 are input, a check bit (data guarantee bit) is generated and added to the data, and the memory is used as write data. And an ECG circuit 8 for outputting to the section 6.

According to the method of the memory patrol performed in each patrol cycle of the present invention, the data of the address A is read by a read command, the data is inspected, and the result is stored in step 401 and the address is added by one step 40.
2 and steps 403 and 4 for repeating the same operation as above, respectively.
04, 405, 406 and 407, step 409 for determining the presence or absence of a correctable error, step 410 for returning the address to the start value when a correctable error is present, read data is read by a correction command, and the read data is corrected. ,
Step 411 for performing a series of operations for creating write data by adding a check bit and writing the data back to the memory 6, step 412 for adding one address, and steps 413, 414, 415, and 416 for repeating the same operation as described above, respectively.
And 417.

It is also a preferred embodiment of the present invention that the read instruction executes data read, inspection and result holding continuously, and executes the read instruction in a short time by utilizing the maximum transfer performance of the memory.

Further, in the present invention, the correction instruction may additionally execute read data read, error correction, creation of write data by adding a check bit, and writing back to the memory after a series of read instructions are completed. Is a preferred embodiment.

If it is determined in step 409 that there is no correctable error in the patrol unit set to be as large as possible, patrol is terminated.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the background of the memory patrol will be outlined.

When a RAM (semiconductor storage element) is used in a storage device, the stored contents may be inverted due to the influence of α-rays or the like, resulting in a data error. This is generally called a soft error. Although a soft error occurs with a certain small probability, a large-capacity storage device uses an enormous number of RAMs, and is a factor that cannot be ignored in reliability. For example, SE for every 8 bytes of data
Even if it is guaranteed by the ECC code of C-DED (1-bit error correction / 2-bit error detection), if two soft errors occur therein, the 8-byte data cannot be recovered. An effective function as a countermeasure is patrol, in which the probability of soft error occurrence (time interval) at the device level is calculated by dividing the probability of soft error occurrence (time) by the number of used RAMs. Then, the entire storage area is inspected, and a correctable failure is found to make a correction.

Next, a memory patrol system according to the present invention will be described. In the present invention, the patrol unit (the memory capacity for processing in one patrol) is set large, and
A large amount of data is inspected in a short time by utilizing the maximum transfer performance of the storage device by executing read instructions continuously in one patrol unit. , The adverse effect (performance degradation) of the patrol on the transfer performance of the storage device is reduced. Note that the loss of the instruction cycle of the correction process means that the conventional correction process performs a series of operations of reading data → checking and correcting data → generating a check bit (data guarantee bit) → writing back to memory. During this period, the memory cannot be accessed, and during this period, the transfer performance is lost.

In FIG. 1, when the patrol main controller 1 activates patrol, the read command generator 2 continuously outputs a read command for the patrol unit while counting up the address counter 4. This read command is transmitted to the memory unit 6 via the memory control unit 5, and the read data is taken out. The read data is inspected by the ECC circuit 7, and if there is no correctable error, the patrol process ends. If there is a correctable error, the correction instruction generator 3 is activated after the read instruction is completed. The correction instruction generator 3 first rewinds the address counter 4 to the start address of the patrol unit, and then executes the correction instruction for the patrol unit while counting up.

Next, the configuration of the embodiment of the present invention will be described. Referring to FIG. 1, the patrol main controller 1 outputs a read instruction to the read instruction generator 2 every patrol cycle, and when the completion of the read instruction is recognized by the instruction completion signal from the memory controller 5, the ECC circuit 7. The correctable error signal received from 7 is confirmed, and if there is no error, the patrol is terminated. If there is an error, a correction instruction is output to the correction instruction generating unit 3, and patrol is ended when the completion of the correction instruction is recognized via the memory control unit 5. When receiving the read instruction, the read instruction generating unit 2 continuously issues the read instruction to the memory control unit 5 by the amount of the patrol unit. At this time, every time one read instruction is issued, the address counter 4 is counted up. When receiving the correction instruction, the correction instruction generating unit 3 first rewinds the address counter 4 to the head address of the patrol unit, and then issues the correction instruction to the memory control unit 5 for the patrol unit. Each time it is issued, the address counter 4 is counted up. The memory control unit 5 executes the read instruction and the correction instruction for the address indicated by the address counter 4 and notifies the patrol main control unit 1 of the completion of the instruction each time one instruction is processed. The memory unit 6 writes and reads data according to an instruction from the memory control unit 5. The ECC circuit 7 checks the read data from the memory unit 6, notifies the patrol main control unit 1 of the presence or absence of a correctable error, and corrects the read data if there is a correctable error. ECG (Er
The error checking generation (ECC) circuit 8 is an ECC (Error Checking and).
(Correcting) circuit 7 receives the corrected data, generates a check bit (data guarantee bit), adds it to the data, and outputs it to the memory unit 6 as write data.

Next, the operation of FIG. 1 will be described with reference to the time charts of FIGS. 2 and 3 and the flowchart of FIG. 4 of an embodiment of the present invention.

FIG. 2 shows an operation in a case where a patrol is performed and no correctable error occurs, and FIG. 3 shows an operation in a case where a correctable error occurs. The signal names used in FIGS. 2 and 3 use the signal names described in FIG. In this embodiment, it is assumed that the data that can be processed by the read instruction and the correction instruction at one time is 8 bytes, the patrol unit is 32 bytes, and the cycle time of the read instruction and the correction instruction is 1T / 7T (T = clock cycle). ing.

First, the operation in the case where no correctable error has occurred will be described with reference to FIG. When the patrol time comes, the patrol main controller 1 outputs a read instruction for 1T, and activates the read command generator 2. The read instruction generator 2 issues four (patrol unit) read requests while counting up the address counter 4. As shown in the instruction cycle, the read instruction is R1 → R2 → R3 → R
Since processing is performed instantaneously in 4 and 1T cycles, there is almost no adverse effect such as waiting for a normal transfer instruction. After 5T, the read data D1, D2, D3, D
4 is read from the memory 6, inspected by the ECC circuit 7, and the presence or absence of a correctable error is notified to the patrol main control unit 1. At this time, the patrol main control unit 1 sequentially receives notification of completion of the read instructions R1 to R4. In this case, since no correctable error has occurred, the patrol main controller 1 has finished the patrol operation. The area behind the broken line shows the state of the next (next cycle) patrol operation. Since no error has occurred, the patrol operation has been completed without executing the correction instruction. Normally, correctable errors do not occur, so it works in this case.

Next, the operation in the case where a correctable error has occurred will be described with reference to FIG. In this case, similarly to the case of FIG. 2, when the patrol time comes, the patrol main control unit 1 issues a read instruction, and as a result, receives a signal indicating the presence or absence of a correctable error and an instruction completion notification signal of the read instruction.
When determining that a correctable error has occurred, the patrol main controller 1 issues a correction instruction. Then, the correction instruction generator 3 first rewinds the value of the address counter 4 to the head address of the current patrol unit, and then issues four correction requests (for the patrol unit) while counting up the address counter 4. As shown in the instruction cycle, the correction instruction is processed with a cycle time of C1 → C2 → C3 → C4 and 7T, and occupies an instruction cycle of 32T. Although it is considered that the period of 32T is caused by a decrease in the performance of the storage device, it does not actually cause a problem since the frequency of occurrence of correctable errors is low. The correction instruction (for example, C1)
During the time T, first, the read data D1 is read from the memory unit 6, this is corrected by the ECC circuit 7, and the ECG circuit 8
To create a write data W1 by adding a check bit,
Finally, an operation of writing back to the memory 6 is performed. C
After C1, C2 to C4 are processed, and when four command completions are notified to the patrol main control unit 1, the patrol operation in this case ends.

The control program is read from the recording medium 9 to a data processing device (not shown) of the patrol main controller 1 to control the operation of the data processing device. The patrol main controller 1 executes the following processing under the control of the control program. That is, a process of reading the data of the address A by the read instruction, checking the data and holding the result, a process of adding one address, a process of repeating the same operation as described above four times each, and correction is possible. If there is an error, a series of operations for returning the address to the start value, and for reading and correcting the read data by a correction instruction, adding check bits to create write data, and writing back to the memory 6 , A process of adding one address, and a process of repeating the same operation as described above four times each.

[0026]

An advantage of the present invention is that it is possible to reduce the adverse effect (performance degradation) on the transfer performance of the storage device due to the patrol operation. In particular, it is effective for application to a large-capacity storage device.

The reason is that the patrol unit is set large, and the check for correctable errors can be completed in a short time by utilizing the maximum transfer performance of the storage device by continuously executing read instructions, and there is a correctable error. This is because the correction processing with a large loss in the instruction cycle is additionally executed only in the case.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a memory patrol system to which a memory patrol method of the present invention is applied.

FIG. 2 is a time chart of an operation when there is no correctable error after performing patrol.

FIG. 3 is a time chart of an operation when a correctable error occurs during patrol.

FIG. 4 is a flowchart of one embodiment of a memory patrol method of the present invention.

FIG. 5 is a flowchart of a prior art memory patrol method.

FIG. 6 is a block diagram of a conventional memory patrol system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Patrol main control part 2 Read instruction generation part 3 Correction instruction generation part 4 Address counter 5 Memory control part 6 Memory part 7 ECC circuit 8 ECG circuit 9 Recording medium R _{1 to} R ₈ Read instruction C _{1 to} C ₄ Correction instruction D ₁ ~D ₈ read data W ₁ ~W ₄ write data

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[Procedure amendment]

[Submission date] April 23, 1999 (1999.4.2
3)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

3. A memory patrol executed every patrol cycle executes a read command continuously to check a large amount of data at a high speed, and corrects an error after a series of read instructions are completed, and always performs a maximum error correction. A storage medium on which a control program for utilizing the transfer performance of the above is recorded, in which a data of address A is read by a read command, the data is inspected, and a result is retained, and a procedure of adding one address 1 A procedure for repeating the same operation as described above four times each, a procedure for determining the presence or absence of a correctable error, a procedure for returning an address to a start value when a correctable error is present, A procedure for performing a series of operations for reading out, correcting this, adding check bits to create write data, and writing back to the memory 6; A step of one adds, recording medium recording a program for executing the procedures to be repeated by one respectively four times the same operation as above.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

[0011]

According to the memory patrol control method of the present invention for detecting and correcting an intermittent fault due to a soft error of a memory element, a read instruction signal is output to a read instruction generating unit 2 at each patrol cycle, and a read instruction is issued. When the completion is recognized by the instruction completion signal from the memory control unit 5, E
The correctable error signal received from the CC circuit 7 is confirmed. If there is no error, the patrol is terminated. If there is an error, a correction instruction is output to the correction instruction generating unit 3 and the correction instruction is completed. When the patrol control unit 1 recognizes the fact via the memory control unit 5 and terminates the patrol, and when a read instruction is received, a read command is continuously issued to the memory control unit 5 in units of the patrol to read data.
Read command generation unit 2 that continuously performs read / inspection and result holding , read data read, error correction, and check
Create write data by adding bits and write to memory
Additional execution of rewind operation after a series of read instructions is completed
A correction instruction generation unit 3 for issuing a correction instruction to be executed, an address counter 4 for counting up each time the correction instruction generation unit 3 issues a correction instruction, the read instruction generation unit 2 and a read instruction and a correction instruction. Address counter 4
And a memory unit for executing data write / read in accordance with an instruction from the control unit 5 by executing a command to the patrol main control unit 1 each time one instruction is processed. 6 and the read data from the memory unit 6 are checked, and the presence or absence of a correctable error is notified to the patrol main control unit 1. If there is a correctable error, the read data is corrected and there is no correctable error. If
An ECC circuit 7 for notifying the patrol main control unit and terminating patrol, and data corrected by the ECC circuit 7 are input, a check bit (data guarantee bit) is generated and added to the data, and the memory unit is written as write data. And an ECG circuit 8 for outputting the signal to the ECG circuit 6.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Deleted

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Deleted

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Deleted

[Procedure amendment 6]

[Document name to be amended] Drawing

[Correction target item name] Fig. 4

[Correction method] Change

[Correction contents]

FIG. 4

[Procedure amendment 7]

[Document name to be amended] Drawing

[Correction target item name] Fig. 5

[Correction method] Change

[Correction contents]

FIG. 5

Claims (6)

[Claims] 1. A memory patrol control method for detecting and correcting an intermittent failure due to a soft error of a memory element, wherein a read instruction signal is output to a read instruction generating unit (2) every patrol cycle, and the read instruction is completed. Is recognized by the instruction completion signal from the memory control unit (5), the correctable error signal received from the ECC circuit (7) is confirmed,
If there is no error, the patrol is terminated. If there is an error, a correction instruction is output to the correction instruction generation unit (3), and when the completion of the correction instruction is recognized via the memory control unit (5), the patrol is performed. When a read instruction is received from the patrol main control unit (1) and the read instruction is issued, the read instruction is continuously issued to the memory control unit (5) for the patrol unit. At this time, every time one read instruction is issued, Read instruction generator (2) that counts up the address counter (4)
When the correction instruction is received, first, the address counter (4)
Is rewound to the head address of the patrol unit, and then a correction instruction is issued to the memory control unit (5) by the amount of the patrol unit. At this time, each time one correction instruction is issued, the address counter (4) is counted up. An instruction generation unit (3); an address counter (4) that counts up each time the correction instruction generation unit (3) issues a correction instruction; and a read instruction and a correction instruction Is executed for the address indicated by the address counter (4), and each time one instruction is processed, a memory control unit (5) notifying the patrol main control unit (1) of instruction completion, and an instruction of the control unit (5) And a patrol main control unit for inspecting read data from the memory unit (6) for executing data write / read, and for determining whether a correctable error exists. Notify to (1), and when there is a correctable error, input the ECC circuit (7) that corrects the read data, and the data that has been corrected by the ECC circuit (7), generate check bits, and And an ECG circuit (8) that outputs the write data to the memory section (6) to the memory section (6). 2. A memory patrol method performed at each patrol cycle, comprising the steps of: reading data at an address A by a read instruction, inspecting the data, and holding the result; and adding one address. (402), and steps (403) and (4) of repeating the same operation as above.
04), (405), (406), and (407), and a step (409) of determining the presence or absence of a correctable error.
And step (410) of returning the address to the start value when a correctable error is present. Read data is read by a correction command, corrected, read data is added with a check bit, and written back to the memory 6. Step for performing a series of operations (411)
Adding one address (412), repeating the same operation as above (413),
(414), (415), (416) and (417);
The method of memory patrol including. 3. The memory patrol method according to claim 2, wherein the read command executes data reading, inspection, and holding of a result continuously, and executes the reading in a short time by utilizing a maximum transfer performance of the memory. 4. The correction command further executes read data read, error correction, write data creation by adding a check bit, and write-back to a memory after a series of read commands are completed. The described memory patrol method. 5. The memory patrol method according to claim 2, wherein the step 409 terminates the patrol when it is determined that there is no correctable error in the patrol unit set to a maximum value. . 6. A memory patrol performed every patrol cycle executes a read command continuously to check a large amount of data at a high speed, and corrects an error after a series of read commands is completed and always performs a maximum correction. A storage medium on which a control program for utilizing the transfer performance of the above is recorded, in which a data of address A is read by a read command, the data is inspected, and a result is retained, and a procedure of adding one address 1 A procedure for repeating the same operation as described above four times each, a procedure for determining the presence or absence of a correctable error, a procedure for returning an address to a start value when a correctable error is present, A procedure for performing a series of operations for reading out, correcting this, adding check bits to create write data, and writing back to the memory 6; A step of one adds, recording medium recording a program for executing the procedures to be repeated by one respectively four times the same operation as above.