JPH023288A - Insulated gate type bipolar transistor - Google Patents
Insulated gate type bipolar transistorInfo
- Publication number
- JPH023288A JPH023288A JP15150288A JP15150288A JPH023288A JP H023288 A JPH023288 A JP H023288A JP 15150288 A JP15150288 A JP 15150288A JP 15150288 A JP15150288 A JP 15150288A JP H023288 A JPH023288 A JP H023288A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- groove
- resistance
- face
- pressure resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 abstract description 56
- 239000012535 impurity Substances 0.000 abstract description 9
- 239000011229 interlayer Substances 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 238000001465 metallisation Methods 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
Ａ、産業上の利用分野
本発明は、絶縁ゲート型バイポーラトランジスタに係り
、特にオン抵抗を減らした素子構造に関する。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to an insulated gate bipolar transistor, and particularly to a device structure with reduced on-resistance.
Ｂ１発明の概要
本発明は、絶縁ゲート型バイポーラトランジスタにおい
て、
チャネルを縦方向に持つ構造とすることにより、面積利
用率、耐圧を向上しながらオン抵抗を低減できるように
したものである。B1 Summary of the Invention The present invention provides an insulated gate bipolar transistor with a structure in which the channel is vertical, thereby reducing on-resistance while improving area utilization and breakdown voltage.
Ｃ１従来の技術
電力変換装置用の電力素子は、装置の高効率化低騒音化
等の観点から高周波化が強く要求されてきている。高周
波用電力素子としてはパワーＭＯ９ＦＥＴが知られてお
り、この素子は電圧駆動型になる高入力インピーダンス
特性を有してパワートランジスタ等のバイポーラ型素子
に較べて駆動回路の構成を簡単、小型化する長所を持つ
が、この反面にオン抵抗が大きく高耐圧大電流化が困難
になるという短所を持つ。C1 Prior Art There is a strong demand for power elements for power conversion devices to have higher frequencies from the viewpoints of higher efficiency and lower noise of the devices. A power MO9FET is known as a high-frequency power device, and this device is voltage-driven and has high input impedance characteristics, making the structure of the drive circuit simpler and smaller than bipolar devices such as power transistors. This has advantages, but on the other hand, it has the disadvantage that it has a large on-resistance, making it difficult to achieve high withstand voltages and large currents.
そこで、Ｍ ＯＳ Ｆ Ｅ Ｔの短所を補うため、ＭＯ
ＳＦＥＴにバイポーラ動作を付加したバイポーラ・Ｍ
ＯＳ ＞ｆ；１合素子、いわゆるＩ Ｇ Ｂ Ｔ （Ｉ
ｎ５ｕｌａｔｅｄＧａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎ
ｓｉｓｔｏｒ）が開発されてきている。Therefore, in order to compensate for the disadvantages of MOS FET,
Bipolar M with bipolar operation added to SFET
OS >f; 1 coupling element, so-called I G B T (I
n5ulatedGate Bipolar Tran
sister) has been developed.
第２図は従来のＩ ＧＢＴの断面構造を示す。この素子
は、縦型のＭ ＯＳ Ｆ Ｅ Ｔのドレイン側にＰ。FIG. 2 shows a cross-sectional structure of a conventional IGBT. This element has P on the drain side of a vertical MOS FET.
１１を設けた構造にされ、Ｐ”（１）ウェハにｎ層２．
ｎ−層３をエピタキソヤル成長により形成し、この盾仮
を用いてＭ ＯＳ Ｆ Ｅ Ｔの製造プロセスと同様の
プロセスで層４〜９が形成される。ＩＯはエミッタ電極
である。11, an n-layer 2.
An n-layer 3 is formed by epitaxial growth, and layers 4 to 9 are formed using this shield in a process similar to the manufacturing process of a MOSFET. IO is an emitter electrode.
この構造において、ゲート層８に正のゲート電圧を印加
することによりｎ゛層６ｎ−層３間にチャネルが形成さ
れ、層６から層３に電子が流れ込み、この電子が層３の
電位を下げ、コレクタ側のＰ″ｎ−接合を順バイアスし
、Ｐ゛層ｌらｎ４３３に正孔が流れ込み、ｎ−層３のベ
ース抵抗を下げる。この正孔の流れ込みにより、素子オ
ン抵抗の大部分になるｍ１１の抵抗を下げてオン抵抗を
下げる。ｎ゛層２オン抵抗との兼ね合いをとりなからＰ
゛層１側からの正孔注入を抑制し、ｎ−層に蓄積するキ
ャリアを低減してターンオフを短縮する。In this structure, by applying a positive gate voltage to the gate layer 8, a channel is formed between the n layer 6 and the layer 3, electrons flow from the layer 6 to the layer 3, and these electrons lower the potential of the layer 3. , the P″n-junction on the collector side is forward biased, and holes flow into the P″ layer 1 to n433, lowering the base resistance of the n-layer 3. Due to this inflow of holes, most of the device on-resistance is The on-resistance is lowered by lowering the resistance of m11.
``Hole injection from the layer 1 side is suppressed, carriers accumulated in the n-layer are reduced, and turn-off is shortened.
Ｄ 発明か解決しようとする課題
従来のＩ ＧＢＴ構造において、素子の高耐圧化にはｎ
−層３を厚く形成すると共にＰ゛層４２層５を深く拡散
形成する必要がある。D. Problem to be solved by the invention In the conventional IGBT structure, it is difficult to increase the withstand voltage of the element.
- It is necessary to form the layer 3 thickly and to deeply diffuse the P layer 42 and the layer 5.
しかし、拡散層を深くするにつれて横方向への拡散１も
増大する。このため、ユニットセルの横方向の大きさが
増して面積利用率を悪くするし、深い拡散がオン抵抗を
増大させる。この結果、１０００Ｖ１５０Ａ素子でオン
電圧３Ｖを下回る素子を歩留り良く作成することは困難
になるものであった。However, as the depth of the diffusion layer increases, the lateral diffusion 1 also increases. This increases the lateral size of the unit cell, which impairs the area utilization efficiency, and the deep diffusion increases the on-resistance. As a result, it has become difficult to produce a 1000V, 150A device with an on-state voltage of less than 3V with a high yield.
本発明の目的は、面積利用率及び耐圧を低下さ仕ること
なくオン抵抗を小さくすることができる［ＧＢＴ素子構
造を提供することにある。An object of the present invention is to provide a GBT element structure that can reduce on-resistance without reducing area utilization and breakdown voltage.
９０課題を解決するための手段と作用
本発明は上記目的を達成するため、コレクタ側のＰ゛層
ウェハにｎ−層、Ｐ層及びパターン形成したエミッタ側
のｎ層層を有し、前記ｎ層層からｎ層に達する深さの溝
内壁面に絶縁膜を有して該溝内に制御電極を設けた構造
とし、ｎ層層からｎ−層に至る縦方向のチャネル形成に
よってＰ層の拡散形成を不要にして横方向の拡散を無く
して所期のチャネル長、ｎ゛層厚さを得る。90 Means and Effects for Solving the Problems In order to achieve the above object, the present invention has an n- layer, a P layer, and a patterned n-layer on the emitter side on a P layer wafer on the collector side, and The structure has an insulating film on the inner wall surface of a groove with a depth reaching from the layer to the n layer, and a control electrode is provided in the groove. By eliminating the need for diffusion formation and eliminating lateral diffusion, the desired channel length and n' layer thickness can be obtained.
Ｆ 実施例
第１図は本発明の一実施例を示すＩ ＧＢＴの断面図で
ある。同図が第２図と異なる部分は、０層６からｎ−層
３までのチャネルを縦方向に形成した点にある。F. Embodiment FIG. 1 is a sectional view of an IGBT showing an embodiment of the present invention. The difference between this figure and FIG. 2 is that the channels from the 0 layer 6 to the n- layer 3 are formed in the vertical direction.
この構造を得るための製造プロセスは、Ｐ゛層１なるＰ
型ウェハにｎ゛層２びｎ−層３をエビタキンヤル成長で
形成し、この基板にＰ型の不純物を全面に拡散して２層
４を形成する。次に、ｎ型の不純物を酸化膜をマスクと
して所定のパターンにｎ゛層６拡散形成し、さらに上記
ｎ型不純物用の酸化マスクを使用して反応性イオンエツ
チング等によりウェハの主面にｎ−層３に達する溝を掘
り込む。この溝部壁面にゲート酸化膜７を付けた後、該
溝部に低抵抗のポリシリコン８を充填してゲート電極と
し、この上面に層間絶縁膜９を付け、最後にエミッダ電
極ＩＯをメタル蒸着等によって形成する。The manufacturing process for obtaining this structure is as follows:
An n' layer 2 and an n- layer 3 are formed on a type wafer by epitaxial growth, and a p-type impurity is diffused over the entire surface of this substrate to form a second layer 4. Next, an n-type impurity is diffused into a predetermined pattern using the oxide film as a mask, and then an n-layer is formed on the main surface of the wafer by reactive ion etching using the oxide mask for the n-type impurity. - Dig a trench that reaches layer 3. After attaching a gate oxide film 7 to the wall surface of this groove, the groove is filled with low resistance polysilicon 8 to form a gate electrode, an interlayer insulating film 9 is attached to the upper surface of this, and finally an emitter electrode IO is formed by metal vapor deposition or the like. Form.
このように、２層４を全面に拡散形成し、その上面にｎ
層層をパターン形成し、ｎ°層６からｎ層に至る溝部に
縦方向にゲート層を形成することでチャネルを縦方向に
持つ構造とする。これにより、２層４を深く形成する素
子の高耐圧化にもユニットセル面積を広げる必要がなく
なる。従って、従来構造では高耐圧素子になるほどユニ
ットセル面積を広くし、また深い拡散がオン抵抗増大を
招くのに対して、本実施例の構造では同じチップ面積で
オン抵抗を低く又は高耐圧化を図ることがてきる。In this way, the two layers 4 are diffused over the entire surface, and the n layer 4 is formed on the upper surface.
By patterning the layers and forming a gate layer in the vertical direction in the groove extending from the n° layer 6 to the n layer, a structure having a channel in the vertical direction is obtained. This eliminates the need to increase the unit cell area even when increasing the withstand voltage of an element in which the two layers 4 are formed deeply. Therefore, in the conventional structure, the higher the withstand voltage element is, the wider the unit cell area is, and the deeper the diffusion, the higher the on-resistance.In contrast, the structure of this embodiment has the same chip area with a lower on-resistance or higher withstand voltage. You can plan for it.
本実施例に基づく実験として、１００ＯＶ１５０Ａクラ
スのＩＧＢＴ素子を第１図の構造と第２図の構造のもの
を同じチップ面積で得るよう試作し、５０Ａ通電時のオ
ン電圧を測定した。この実験では従来構造のものが３〜
４Ｖのオン電圧であるのに対して、本実施例の構造では
２〜３■のオン電圧に低下し、オン時の電力損失を大幅
に低減できることが判った。As an experiment based on this example, a 100 OV 150 A class IGBT element was prototyped so that the structure shown in FIG. 1 and the structure shown in FIG. 2 were obtained with the same chip area, and the on-voltage when 50 A was applied was measured. In this experiment, the conventional structure was
While the on-voltage is 4V, in the structure of this example, the on-voltage is reduced to 2 to 3V, and it has been found that the power loss during on-time can be significantly reduced.
また、従来構造のものはＰ型不純物導入のためのマスク
パターン及びｎ型不純物導入のためのマスクパターンの
２種類のパターンを必要とするが、本実施例のものでは
ｎ型不純物導入のためのマスクパターンのみで溝部掘り
込みもでき、製造プロセスの短縮、簡略化を図ることが
できる。In addition, the conventional structure requires two types of patterns: a mask pattern for introducing P-type impurities and a mask pattern for introducing n-type impurities, but the structure of this embodiment requires two types of patterns: a mask pattern for introducing P-type impurities, and a mask pattern for introducing n-type impurities. Grooves can also be dug using only a mask pattern, making it possible to shorten and simplify the manufacturing process.
なお、実施例においては等方性エツチングによるＵ字形
溝の場合を示すが、これは異方性エツチングによるＶ字
形溝の構造にして同様のプロセスによる製造が可能であ
る。In this embodiment, a U-shaped groove formed by isotropic etching is shown, but a V-shaped groove structure formed by anisotropic etching can be manufactured by a similar process.
Ｇ９発明の効果
以上のとおり、本発明によれば、縦方向のチャネルを持
つＩ ＧＢＴとするため、チャネルの形成にＰ層の横方
向の拡散が無くなり、同じチャネル長を得るにもユニッ
ト面積利用率が向上すると共に耐圧を向上でき、しかも
オン抵抗の増大が無くなる効果がある。また、拡散によ
るチャネル形成に較べてＰ層の厚さによるユニットセル
間のチャネル長均−化を図ることができ、歩留り及びマ
スクパターンの低減も含めて製造プロセスの短縮を図る
ことができる。G9 Effects of the Invention As described above, according to the present invention, since the IGBT has a vertical channel, there is no lateral diffusion of the P layer to form the channel, and the unit area can be utilized to obtain the same channel length. This has the effect of not only improving the efficiency but also improving the breakdown voltage and eliminating the increase in on-resistance. Furthermore, compared to channel formation by diffusion, channel lengths between unit cells can be equalized by the thickness of the P layer, and the manufacturing process can be shortened, including yield and mask pattern reduction.
第１図は本発明の一実施例を示す素子断面図、第２図は
従来のＩＣ；ＢＴ断面図である。
■・・・Ｐ層層、３・・・ｎ−層、４・・・Ｐ層、６・
・・ｎ層層、７・絶縁膜、８・・・ゲート電極。
第１図
デブ矩例のＩＧＢＴｖ旬図
コレクタ
第２図
詑釆楯哉のＩＧＢＴ餠面口
Φ
コレクタFIG. 1 is a sectional view of an element showing an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional IC; BT. ■...P layer layer, 3...n- layer, 4...P layer, 6...
...N layer, 7. Insulating film, 8. Gate electrode. Figure 1: Fat example of IGBTv collector Figure 2: Tateya Sokata's IGBT Mimyoguchi Φ collector
Claims (1)
びパターン形成したエミッタ側のｎ＾＋層を有し、前記
ｎ＾＋層からｎ＾−層に達する深さの溝内壁面に絶縁膜
を有して該溝内に制御電極を設けた構造を特徴とする絶
縁ゲート型バイポーラトランジスタ。(1) P^+ layer on the collector side The wafer has an n^- layer, a P layer, and a patterned n^+ layer on the emitter side, and a groove with a depth reaching from the n^+ layer to the n^- layer. An insulated gate bipolar transistor characterized by a structure having an insulating film on an inner wall surface and a control electrode provided in the groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15150288A JPH023288A (en) | 1988-06-20 | 1988-06-20 | Insulated gate type bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15150288A JPH023288A (en) | 1988-06-20 | 1988-06-20 | Insulated gate type bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH023288A true JPH023288A (en) | 1990-01-08 |
Family
ID=15519913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15150288A Pending JPH023288A (en) | 1988-06-20 | 1988-06-20 | Insulated gate type bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH023288A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0645612A (en) * | 1992-07-21 | 1994-02-18 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| US5304821A (en) * | 1990-10-08 | 1994-04-19 | Mitsubishi Denki Kabushiki Kaisha | MOS-gate-turnoff thyristor |
| EP0594049A1 (en) * | 1992-10-20 | 1994-04-27 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate bipolar transistor and manufacturing method thereof |
| US6040599A (en) * | 1996-03-12 | 2000-03-21 | Mitsubishi Denki Kabushiki Kaisha | Insulated trench semiconductor device with particular layer structure |
| US6107650A (en) * | 1994-02-21 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
-
1988
- 1988-06-20 JP JP15150288A patent/JPH023288A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5304821A (en) * | 1990-10-08 | 1994-04-19 | Mitsubishi Denki Kabushiki Kaisha | MOS-gate-turnoff thyristor |
| JPH0645612A (en) * | 1992-07-21 | 1994-02-18 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| EP0594049A1 (en) * | 1992-10-20 | 1994-04-27 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate bipolar transistor and manufacturing method thereof |
| US6107650A (en) * | 1994-02-21 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
| US6323508B1 (en) | 1994-02-21 | 2001-11-27 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
| US6331466B1 (en) | 1994-02-21 | 2001-12-18 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
| US6221721B1 (en) | 1996-02-12 | 2001-04-24 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing an insulated trench gate semiconductor device |
| US6040599A (en) * | 1996-03-12 | 2000-03-21 | Mitsubishi Denki Kabushiki Kaisha | Insulated trench semiconductor device with particular layer structure |
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