CN113838913B - Segmented injection self-clamping IGBT device and manufacturing method thereof - Google Patents
Segmented injection self-clamping IGBT device and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a sectional injection self-clamping IGBT and a manufacturing method thereof. A groove structure which is equipotential with an emitter is introduced at the right side of a cell, a P-type doped buried layer is introduced below an N-type charge storage layer, and the high-concentration P-type buried layer is distributed at intervals by changing openings of a mask plate, so that adverse effects of the high-concentration P-type buried layer on threshold voltage when a device is conducted are improved, and on-resistance is reduced. The self-biased PMOS structure turns on when the device is saturated, and the CS layer potential is clamped at a lower value, thereby reducing the IGBT saturation current. The high-concentration P-type buried layer distributed at intervals can ensure that the PMOS structure is normally opened under high collector voltage to clamp the potential of the CS layer, so that the saturation current is reduced, and the short circuit capability of the device is improved. On the basis of the traditional trench IGBT manufacturing process, the P+ buried layer distributed in a sectional mode along the z direction can be realized by adding one mask plate, the complexity of the process is not increased, and the implementation is easy.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, relates to an Insulated Gate Bipolar Transistor (IGBT), and in particular relates to a sectional injection self-clamping IGBT and a manufacturing method thereof.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a novel power device, combines the gate electrode voltage control characteristics of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and the low on-resistance characteristics of a Bipolar Junction Transistor (BJT), has the characteristics of voltage control, large input impedance, small driving power, small on-resistance, high current density, low switching loss, high operating frequency and the like, is a relatively ideal semiconductor power switching device, and is widely applied to various power conversion, motor driving and power electronic devices.
Since the advent of IGBTs, efforts have been made to improve the trade-off relationship between device on-voltage drop and turn-off loss. From a primary punch-through type IGBT (PT-IGBT) to a field stop type IGBT (FS-IGBT), the length of the IGBT is continuously thinned, and the compromise characteristic of the device is greatly improved. On the gate structure, the IGBT is developed from a planar gate to a trench gate, thereby eliminating the JEFT effect and further reducing the conduction voltage drop of the device. On these bases, IGBTs have been continuously improved to obtain many new structures. The carrier storage type IGBT (CSTBT) forms hole accumulation by introducing an N-type carrier storage layer with the concentration higher than that of an N-type drift region under a P base region, so that the carrier concentration at the emitter side is enhanced, and the conduction voltage drop of the device is reduced. However, a strong electric field is established at the PN junction between the introduced CS storage layer and the P base region, so that the device reaches an avalanche breakdown condition in advance under lower pressure bearing, and the blocking capability is reduced. And the saturation current of the device can be increased along with the increase of the concentration of the CS layer, thereby bringing adverse effects to a safe working area.
Disclosure of Invention
In order to solve the problems of large saturation current, poor short circuit performance, degradation of breakdown characteristics and increase of miller capacitance caused by deep trenches in the traditional CSTBT structure, the invention provides a sectional injection self-clamping IGBT structure, as shown in figure 2, wherein a trench structure which has the same potential as an emitter and the same depth as a trench gate is introduced at the right side of a cell, a high-concentration P-type doped buried layer is introduced below the N-type charge storage layer, and the high-concentration P-type buried layer is not continuously distributed but distributed at intervals by changing the opening of a mask plate, so that the adverse effect of the high-concentration P-type buried layer on threshold voltage when the device is conducted is improved, and electron current can flow into an N-type drift region through a part without doping P-type impurities, thereby greatly reducing the on-resistance. The P-type base region, the N-type charge storage layer, the P-type buried layer and the trench emitter form a self-bias PMOS structure, the PMOS is started when the device is saturated, the potential of the CS layer is clamped at a lower value, and the base current provided for the PNP transistor is reduced, so that the saturation current of the IGBT is reduced. The high-concentration P-type buried layer distributed at intervals can ensure that the PMOS structure is normally opened under high collector voltage to clamp the potential of the CS layer, reduce saturation current, improve the short circuit capacity of the device and improve a short circuit safety working area. According to the invention, on the basis of the traditional trench IGBT process method, the P+ buried layer distributed in a sectional manner along the z direction can be realized by adding one mask plate, the complexity of the process is not increased, and the realization is easy.
In order to achieve the above object, the present invention has the following technical scheme:
the self-clamping IGBT device comprises collector metal 10, a P-type collector region 9, an N-type field stop layer 8, an N-drift region 7 and a trench structure, wherein the collector metal 10, the P-type collector region 9, the N-type field stop layer 8 and the N-drift region 7 are sequentially stacked from bottom to top, the trench structure is positioned above the N-drift region 7, and comprises a gate dielectric layer 13, a polycrystalline gate electrode 12 in the gate dielectric layer 13 and a gate isolation dielectric layer 11 positioned above the polycrystalline gate electrode 12;
a P+ buried layer 6 and a separation gate structure are arranged above the N-drift region 7, and the separation gate structure comprises a separation gate dielectric layer 15 and a polycrystalline separation gate electrode 14 in the separation gate dielectric layer 15;
defining the 3-dimensional direction of the device in a 3-dimensional rectangular coordinate system: defining the direction of the device from the trench structure to the split gate structure as the x-axis direction, the direction from the trench structure to the N-drift region 7 as the y-axis direction, and the direction perpendicular to x and y as the z-axis direction;
the P+ buried layers 6 are distributed at intervals along the Z direction, and the area between the adjacent P+ buried layers 6 in the Z direction is an N-drift region 7; the P+ buried layer 6 is in contact with the groove structure and the separation gate structure; the upper part of the P+ buried layer 6 and the N-drift region 7 is provided with an N-type charge storage layer 5; the upper part of the N-type charge storage layer 5 is provided with a P-type base region 4; the upper part of the P-type base region 4 is provided with an N+ emitter region 2 and a P+ contact region 3 contacted with the N+ emitter region 2; the upper parts of the grid isolation dielectric layer 11, the upper parts of the N+ emission region 2 and the P+ contact region 3 are provided with emitter metal 1; the separation gate dielectric layer 15 is in short circuit with the emitter metal 1; the concentration of the P+ buried layer 6 is higher than that of the P-type base region 4; the width of the P+ buried layer 6 along the z direction is larger than or equal to the width of the N-drift region 7 between the adjacent P+ buried layers 6 on the same horizontal plane; the width of the p+ buried layer 6 along the y direction is smaller than the width of the N-type charge storage layer 5 along the y direction.
Preferably, the N-drift region 7 between any two adjacent p+ buried layers 6 in the Z direction is replaced by a P-buried layer 16; the width of the P-buried layer 16 along the Z direction is smaller than or equal to the width of the P+ buried layer 6 along the Z direction; the concentration of the P-buried layer 16 is smaller than or equal to that of the P-type base region 4, and the width of the P-buried layer 16 along the y direction is the same as the width of the p+ buried layer 6 along the y direction.
Preferably, a superjunction structure consisting of a superjunction N-pillar 17 and a superjunction P-pillar 18 is introduced in the N-drift region 7.
Preferably, a P-type floating region 20 is introduced to the right side of the separation gate structure, an isolation medium layer 19 is arranged above the P-type floating region 20, emitter metal 1 is arranged above the isolation medium layer 19, and the depth of the P-type floating region 20 along the y direction is equal to the depth of the separation gate structure.
Preferably, the depth of the P-type floating empty region 20 along the y direction exceeds the depth of the split gate structure along the y direction, and the P-type floating empty region 20 is partially contacted with the p+ buried layer 6.
Preferably, the metal on the upper part of the split gate structure is embedded in the P-type base region 4 and the split gate structure.
The invention also provides a manufacturing method of the sectional injection self-clamping IGBT device, which comprises the following steps:
step 1: selecting the doping concentration to be 10 13 ～10 14 /cm 3 Is used to form the N-drift region 7 of the device;
step 2: depositing a protective layer on the surface of the silicon wafer, photoetching a window to etch the groove silicon, and etching a gate electrode groove and a separation gate electrode groove;
step 3: growing a sacrificial oxide layer on the side wall of the groove, and then removing the sacrificial oxide layer; then a gate oxide layer grows on the side wall of the groove; then, polysilicon is deposited on the dielectric layer, and then, the superfluous polysilicon on the surface is reversely etched;
step 4: growing a pre-oxidation layer on the surface of a silicon wafer, and preparing P+ buried layers 6 distributed at intervals by implanting P-type impurities;
step 5: an N-type charge storage layer 5 is prepared by ion implantation of N-type impurities; p-type impurities are injected into the P-type base region 4 through ion implantation and annealing treatment; respectively injecting N-type impurities and P-type impurities to obtain an N+ emission region 2 and a P+ contact region 3 which are in contact with each other and are arranged side by side;
step 6: depositing silicon dioxide and etching redundant media to form a gate isolation medium layer;
step 7: depositing metal on the front surface of the device to manufacture emitter metal;
step 8: turning over the silicon wafer; the N-type field stop layer is prepared after laser annealing by ion implantation of N-type impurities; p+ collector region is prepared by ion implantation of P-type impurities; and depositing metal to obtain the metal collector.
The invention also provides a second manufacturing method of the sectional injection self-clamping IGBT device, which comprises the following steps:
step 1: selecting the doping concentration to be 10 13 ～10 14 /cm 3 Is used to form the N-drift region 7 of the device;
step 2: growing a pre-oxidation layer on the surface of a silicon wafer, and preparing P+ buried layers 6 distributed at intervals by implanting P-type impurities;
step 3: an N-type charge storage layer 5 is prepared by ion implantation of N-type impurities; p-type impurities are injected into the P-type base region 4 through ion implantation and annealing treatment; respectively injecting N-type impurities and P-type impurities to obtain an N+ emission region 2 and a P+ contact region 3 which are in contact with each other and are arranged side by side;
step 4: depositing a protective layer on the surface of the silicon wafer, photoetching a window to etch the groove silicon, and etching a gate electrode groove and a separation gate electrode groove;
step 5: growing a sacrificial oxide layer on the side wall of the groove, and then removing the sacrificial oxide layer; then a gate oxide layer grows on the side wall of the groove; then, polysilicon is deposited on the dielectric layer, and then, the superfluous polysilicon on the surface is reversely etched;
step 6: depositing silicon dioxide and etching redundant media to form a gate isolation medium layer;
step 7: depositing metal on the front surface of the device to manufacture emitter metal;
step 8: turning over the silicon wafer; the N-type field stop layer is prepared after laser annealing by ion implantation of N-type impurities; p+ collector region is prepared by ion implantation of P-type impurities; and depositing metal to obtain the metal collector.
The invention also provides a third manufacturing method of the sectional injection self-clamping IGBT device, which comprises the following steps:
step 1: selecting the doping concentration to be 10 13 ～10 14 /cm 3 Is used to form the N-drift region 7 of the device;
step 2: depositing a protective layer on the surface of the silicon wafer, photoetching a window to etch the groove silicon, and etching a gate electrode groove and a separation gate electrode groove;
step 3: growing a sacrificial oxide layer on the side wall of the groove, and then removing the sacrificial oxide layer; then a gate oxide layer grows on the side wall of the groove; then, polysilicon is deposited on the dielectric layer, and then, the superfluous polysilicon on the surface is reversely etched;
step 4: growing a pre-oxidation layer on the surface of a silicon wafer, and preparing P+ buried layers 6 distributed at intervals by implanting P-type impurities;
step 5: p-buried layer 16 is formed by ion implantation of a P-type impurity,
step 6: an N-type charge storage layer 5 is prepared by ion implantation of N-type impurities; p-type impurities are injected into the P-type base region 4 through ion implantation and annealing treatment; respectively injecting N-type impurities and P-type impurities to obtain an N+ emission region 2 and a P+ contact region 3 which are in contact with each other and are arranged side by side;
step 7: depositing silicon dioxide and etching redundant media to form a gate isolation medium layer;
step 8: depositing metal on the front surface of the device to manufacture emitter metal;
step 9: turning over the silicon wafer; the N-type field stop layer is prepared after laser annealing by ion implantation of N-type impurities; p+ collector region is prepared by ion implantation of P-type impurities; and depositing metal to obtain the metal collector.
The working principle of the invention is as follows:
when the polycrystalline gate electrode 12 is connected with a high potential higher than the threshold voltage of the device, the collector metal 10 is connected with a high potential, the emitter metal 1 and the polycrystalline separation gate electrode 14 are connected with a low potential, the device works in a conducting state, the P-type collector region 9 injects holes into the N-drift region 7, the N+ emitter region 2 injects electrons into the N-drift region 7, and the existence of electron hole pairs enables a conductivity modulation effect to occur in the drift region, meanwhile, due to the existence of the N-type charge storage layer 5, accumulation of surface holes is enhanced, carrier distribution of the drift region is improved, and forward conducting voltage drop of the device is reduced; because the P+ buried layers with high concentration are distributed at intervals, electron current can flow into the N-type drift region through gaps of the P+ buried layers, and therefore the conduction performance of the device cannot be affected by the introduction of the P+ buried layers.
When the collector 10 voltage is high, the device enters saturation. The P-type base region 4, the N-type charge storage layer 5, the p+ buried layer 6 and the polycrystalline separation gate electrode 14 form a self-bias PMOS structure, wherein the P-type base region 4 serves as a drain electrode, the N-type charge storage layer 5 serves as an N-type base region, the p+ buried layer 6 serves as a source electrode, and the polycrystalline separation gate electrode 14 serves as a gate electrode. The potential of the collector metal 10 rises, the N-type charge storage layer 5 also rises along with the rise, when the potential of the N-type charge storage layer 5 reaches the threshold voltage of the self-bias PMOS, the PMOS is started, the N-type charge storage layer serves as the drain electrode of the MOS structure in the IGBT, and the base current provided for the PNP transistor is reduced, so that the saturation current of the IGBT is reduced, and the bearing capacity of the device under the short-circuit working condition is improved.
When the polycrystalline gate electrode 12 and the emitter metal 1 are connected with low potential, and the collector metal 10 is connected with high potential, the device works in a blocking state, at the moment, the P+ buried layer 6 and the trench emitter structure can effectively shield the influence of the N-type charge storage layer 5 on the breakdown voltage of the device, meanwhile, the PMOS is started to provide an additional path for extracting holes, the switching speed of the device is improved, the turn-off loss of the device is reduced, and meanwhile, the grid capacitance is greatly reduced by the separation gate structure, and the switching loss is further reduced.
The beneficial effects of the invention are as follows:
the invention introduces a trench structure with the same potential as the emitter and the same depth as the trench gate on the right side of the cell, introduces a high-concentration P-type doped buried layer below the N-type charge storage layer, and ensures that the high-concentration P-type buried layer is not continuously distributed but is distributed at intervals by changing the opening of the mask. The P-type base region, the N-type charge storage layer, the P-type buried layer and the trench emitter form a self-bias PMOS structure, when the device is saturated, the potential of the N-type charge storage layer rises along with the rising of the collector voltage, when the potential of the N-type charge storage layer reaches the threshold voltage of the PMOS, the PMOS is started, the potential of the N-type charge storage layer is clamped at a lower value, the N-type charge storage layer is used as the drain electrode of the MOS structure in the IGBT, and the base current provided for the PNP transistor is reduced, so that the saturation current of the IGBT is reduced, the bearing capacity of the device under a short-circuit working condition is improved, and the short-circuit safe working area is improved. However, the high-concentration P-type buried layer can influence the formation of a channel inversion layer when the device is conducted, the threshold voltage of the device can be improved due to discontinuous distribution of the high-concentration P-type buried layer, and electron current can flow into the N-type drift region from a gap of the P+ buried layer, so that the problem of increasing on-resistance caused by the high-concentration p+ buried layer is solved, and the on-voltage drop is reduced. According to the invention, on the basis of the traditional trench IGBT process method, the P+ buried layer distributed in a sectional manner along the z direction can be realized by adding one mask plate, the complexity of the process is not increased, and the realization is easy.
Drawings
Fig. 1 is a schematic diagram of a half cell structure of a conventional trench charge storage IGBT device;
fig. 2 is a schematic diagram of a half cell structure of a segmented injection self-clamping IGBT according to embodiment 1 of the present invention;
fig. 3 is a schematic cross-sectional view of a half cell structure of a segmented injection self-clamping IGBT along line AB according to embodiment 1 of the present invention;
fig. 4 is a schematic cross-sectional view along a CD line of a half cell structure of a segmented-injection self-clamping IGBT according to embodiment 1 of the present invention;
fig. 5 is a schematic diagram of a half cell structure of a segmented injection self-clamping IGBT according to embodiment 2 of the present invention;
fig. 6 is a schematic cross-sectional view of a half cell structure of a segmented injection self-clamping IGBT along line AB according to embodiment 2 of the present invention;
fig. 7 is a schematic cross-sectional view along the CD line of a half-cell structure of a segmented-injection self-clamping IGBT according to embodiment 2 of the present invention;
fig. 8 is a schematic diagram of a half cell structure of a segmented injection self-clamping IGBT according to embodiment 3 of the present invention;
fig. 9 is a schematic cross-sectional view of a half cell structure of a segmented injection self-clamping IGBT along line AB according to embodiment 3 of the present invention;
fig. 10 is a schematic cross-sectional view along the CD line of a half-cell structure of a segmented-injection self-clamping IGBT according to embodiment 3 of the present invention;
fig. 11 is a schematic diagram of a half cell structure of a segmented injection self-clamping IGBT according to embodiment 4 of the present invention;
fig. 12 is a schematic cross-sectional view of a half cell structure of a segmented-injection self-clamping IGBT along AB line provided in embodiment 4 of the present invention;
fig. 13 is a schematic diagram of a half cell structure of a segmented injection self-clamping IGBT according to embodiment 5 of the present invention;
fig. 14 is a schematic cross-sectional view of a half cell structure of a segmented-injection self-clamping IGBT along AB line provided in embodiment 5 of the present invention;
fig. 15 is a schematic diagram of a half cell structure of a segmented injection self-clamping IGBT according to embodiment 6 of the present invention;
fig. 16 is a schematic cross-sectional view of a half cell structure of a segmented-injection self-clamping IGBT along AB line according to embodiment 6 of the present invention;
fig. 17 is a schematic process diagram of a segmented-injection self-clamping IGBT according to embodiment 1 of the present invention after forming an N-drift region 7;
fig. 18 is a schematic diagram of a process for etching a gate trench by using a segmented-injection self-clamping IGBT according to embodiment 1 of the present invention;
fig. 19 is a schematic diagram of a process of forming a gate dielectric layer 13 and a split gate dielectric layer 15 and depositing polycrystal to form a gate electrode 12 and a split gate electrode 14 by a segmented-injection self-clamping IGBT according to embodiment 1 of the present invention;
fig. 20 is a schematic process diagram of a segmented-injection self-clamping IGBT according to embodiment 1 of the present invention after forming a p+ buried layer 6;
fig. 21 is a schematic process diagram of a segmented-injection self-clamping IGBT according to embodiment 1 of the present invention after forming an N-type charge storage layer 5, a P-type base region 4, an n+ emitter region 2, and a p+ contact region 3;
fig. 22 is a schematic process diagram of a sectional-injection self-clamping IGBT according to embodiment 1 of the present invention after forming the gate isolation dielectric layer 11;
fig. 23 is a schematic process diagram of a segmented-injection self-clamping IGBT according to embodiment 1 of the present invention after forming an emitter metal 1;
fig. 24 is a schematic process diagram of a segmented-injection self-clamping IGBT according to embodiment 1 of the present invention after forming an N-type field stop layer 8, a p+ collector region 9, and a collector metal 10;
in fig. 1 to 24, 1 is an emitter metal, 2 is an n+ emitter region, 3 is a p+ contact region, 4 is a P-type base region, 5 is an N-type charge storage layer, 6 is a p+ buried layer, 7 is an N-drift region, 8 is an N-type field stop layer, 9 is a P-type collector region, 10 is a collector metal, 11 is a gate isolation dielectric layer, 12 is a polycrystalline gate electrode, 13 is a gate dielectric layer, 14 is a polycrystalline isolation gate electrode, 15 is a isolation gate dielectric layer, 16 is a P-buried layer, 17 is a superjunction N pillar, 18 is a superjunction P pillar, 19 is an isolation dielectric layer, and 20 is a P-type float zone.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Example 1:
the embodiment of the self-clamping IGBT device with the sectional injection comprises a half cell structure, a cross section along an AB line and a CD line, as shown in figures 2, 3 and 4, a collector metal 10, a P-type collector region 9, an N-type field stop layer 8, an N-drift region 7 and a trench structure, wherein the collector metal 10, the P-type collector region 9, the N-type field stop layer 8 and the N-drift region 7 are sequentially stacked from bottom to top, and the trench structure is positioned above the N-drift region 7 and comprises a gate dielectric layer 13, a polycrystalline gate electrode 12 in the gate dielectric layer 13 and a gate isolation dielectric layer 11 positioned above the polycrystalline gate electrode 12;
the method is characterized in that: a P+ buried layer 6 and a separation gate structure are arranged above the N-drift region 7, and the separation gate structure comprises a separation gate dielectric layer 15 and a polycrystalline separation gate electrode 14 in the separation gate dielectric layer 15;
defining the 3-dimensional direction of the device in a 3-dimensional rectangular coordinate system: defining the direction of the device from the trench structure to the split gate structure as the x-axis direction, the direction from the trench structure to the N-drift region 7 as the y-axis direction, and the direction perpendicular to x and y as the z-axis direction;
the P+ buried layers 6 are distributed at intervals along the Z direction, and the area between the adjacent P+ buried layers 6 in the Z direction is an N-drift region 7; the P+ buried layer (6) is in contact with the groove structure and the separation gate structure; the upper part of the P+ buried layer 6 and the N-drift region 7 is provided with an N-type charge storage layer 5; the upper part of the N-type charge storage layer 5 is provided with a P-type base region 4; the upper part of the P-type base region 4 is provided with an N+ emitter region 2 and a P+ contact region 3 contacted with the N+ emitter region 2; the upper parts of the grid isolation dielectric layer 11, the upper parts of the N+ emission region 2 and the P+ contact region 3 are provided with emitter metal 1; the separation gate dielectric layer 15 is in short circuit with the emitter metal 1; the concentration of the P+ buried layer 6 is higher than that of the P-type base region 4; the width of the P+ buried layer 6 along the z direction is larger than or equal to the width of the N-drift region 7 between the adjacent P+ buried layers 6 on the same horizontal plane; the width of the p+ buried layer 6 along the y direction is smaller than the width of the N-type charge storage layer 5 along the y direction.
The manufacturing method of the sectional injection self-clamping IGBT device of the embodiment comprises the following steps:
step 1: as shown in FIG. 17, a doping concentration of 10 is selected 13 ～10 14 /cm 3 Is used to form the N-drift region 7 of the device;
step 2: as shown in fig. 18, a protective layer is deposited on the surface of a silicon wafer, a window is etched by photoetching, and a gate electrode groove and a separation gate electrode groove are etched;
step 3: as shown in fig. 19, a sacrificial oxide layer is grown on the side wall of the groove, and then the sacrificial oxide layer is removed; then a gate oxide layer grows on the side wall of the groove; then, polysilicon is deposited on the dielectric layer, and then, the superfluous polysilicon on the surface is reversely etched;
step 4: as shown in fig. 20, a pre-oxidized layer is grown on the surface of a silicon wafer, and P-type impurities are implanted into the pre-oxidized layer to obtain p+ buried layers 6 which are distributed at intervals;
step 5: as shown in fig. 21, an N-type charge storage layer 5 is produced by ion implantation of N-type impurities; p-type impurities are injected into the P-type base region 4 through ion implantation and annealing treatment; respectively injecting N-type impurities and P-type impurities to obtain an N+ emission region 2 and a P+ contact region 3 which are in contact with each other and are arranged side by side;
step 6: as shown in fig. 22, silicon dioxide is deposited and redundant dielectric is etched away to form a gate isolation dielectric layer;
step 7: as shown in fig. 23, the front side of the device is deposited with metal to make emitter metal;
step 8: as shown in fig. 24, the silicon wafer is flipped; the N-type field stop layer is prepared after laser annealing by ion implantation of N-type impurities; p+ collector region is prepared by ion implantation of P-type impurities; and depositing metal to obtain the metal collector.
Example 2
An embodiment of a self-clamping IGBT device with segmented injection is presented on the basis of embodiment 1, and the difference between this embodiment and embodiment 1 is that: the N-drift region 7 between any adjacent two P+ buried layers 6 along the Z direction is replaced by a P-buried layer 16; the width of the P-buried layer 16 along the Z direction is smaller than or equal to the width of the P+ buried layer 6 along the Z direction; the concentration of the P-buried layer 16 is smaller than or equal to that of the P-type base region 4, and the width of the P-buried layer 16 along the y direction is the same as the width of the p+ buried layer 6 along the y direction.
The half cell structure and the cross section along the AB line and the CD line are shown in figures 5, 6 and 7, and the process manufacturing adds the steps between the step 4 and the step 5: p-buried layer 16 is formed by ion implantation of P-type impurities, the remaining process steps being the same as in example 1.
The manufacturing method of the sectional injection self-clamping IGBT device of the embodiment comprises the following steps:
step 1: selecting the doping concentration to be 10 13 ～10 14 /cm 3 Is used to form the N-drift region 7 of the device;
step 2: depositing a protective layer on the surface of the silicon wafer, photoetching a window to etch the groove silicon, and etching a gate electrode groove and a separation gate electrode groove;
step 3: growing a sacrificial oxide layer on the side wall of the groove, and then removing the sacrificial oxide layer; then a gate oxide layer grows on the side wall of the groove; then, polysilicon is deposited on the dielectric layer, and then, the superfluous polysilicon on the surface is reversely etched;
step 4: growing a pre-oxidation layer on the surface of a silicon wafer, and preparing P+ buried layers 6 distributed at intervals by implanting P-type impurities;
step 5: p-buried layer 16 is formed by ion implantation of a P-type impurity,
step 6: an N-type charge storage layer 5 is prepared by ion implantation of N-type impurities; p-type impurities are injected into the P-type base region 4 through ion implantation and annealing treatment; respectively injecting N-type impurities and P-type impurities to obtain an N+ emission region 2 and a P+ contact region 3 which are in contact with each other and are arranged side by side;
step 7: depositing silicon dioxide and etching redundant media to form a gate isolation medium layer;
step 8: depositing metal on the front surface of the device to manufacture emitter metal;
step 9: turning over the silicon wafer; the N-type field stop layer is prepared after laser annealing by ion implantation of N-type impurities; p+ collector region is prepared by ion implantation of P-type impurities; and depositing metal to obtain the metal collector.
In the embodiment, on the premise of not changing the complexity of the process, only two masks are added, the introduced P-buried layer 16 can not only adjust the threshold voltage of the device, but also clamp the potential of the CS layer better than that of embodiment 1, and lower saturation current is obtained.
Example 3
An embodiment of a self-clamping IGBT device with segmented injection is presented on the basis of embodiment 1, and the difference between this embodiment and embodiment 1 is that: a superjunction structure consisting of a superjunction N pillar 17 and a superjunction P pillar 18 is introduced in the N-drift region 7. The half cell structure and the cross section along the AB line and the CD line are shown in figures 8, 9 and 10,
the introduction of the superjunction structure further reduces the on-voltage drop of the device and improves the breakdown voltage of the device.
Example 4
An embodiment of a self-clamping IGBT device with segmented injection is presented on the basis of embodiment 1, and the difference between this embodiment and embodiment 1 is that: a P-type floating void 20 is introduced to the right side of the separation gate structure, an isolation medium layer 19 is arranged above the P-type floating void 20, emitter metal 1 is arranged above the isolation medium layer 19, and the depth of the P-type floating void 20 along the y direction is equal to the depth of the separation gate structure. The half cell structure and the cross section along AB line and CD line are shown in FIGS. 11 and 12
The introduction of the P-type floating void enhances the conductivity modulation effect, reduces the conduction voltage drop, reduces the channel density, further reduces the saturation current and improves the short circuit characteristic.
Example 5
An embodiment of a self-clamping IGBT device with segmented injection is presented on the basis of embodiment 4, the difference between this embodiment and embodiment 1 is that: the cross sections of the half cell structure and along the lines AB and CD are shown in fig. 13 and 14, the depth of the P-type floating void 20 along the y direction exceeds the depth of the separation gate structure along the y direction, and the P-type floating void 20 is partially contacted with the p+ buried layer 6.
The introduction of the P-type floating void enhances the conductivity modulation effect, reduces the conduction voltage drop, reduces the channel density, further reduces the saturation current, relieves the electric field peak at the groove and improves the breakdown voltage.
Example 6
An embodiment of a self-clamping IGBT device with segmented injection is presented on the basis of embodiment 1, and the difference between this embodiment and embodiment 1 is that: and a metal embedded device at the upper part of the separation gate structure. The half cell structure and the section along the AB line and the CD line are shown in figures 15 and 16, and the metal at the upper part of the trench emitter is embedded into the P-type base region 4 and the separation gate structure.
The introduction of the emitter embedded structure reduces the width of the mesa, improves the conduction characteristic of the device, and reduces the miller capacitance.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims of this invention, which are within the skill of those skilled in the art, can be made without departing from the spirit and scope of the invention disclosed herein.
Claims (8)
1. The self-clamping IGBT device comprises collector metal (10), a P-type collector region (9), an N-type field stop layer (8) and an N-drift region (7) which are sequentially stacked from bottom to top, and a groove structure above the N-drift region (7), wherein the groove structure comprises a gate dielectric layer (13), a polycrystalline gate electrode (12) in the gate dielectric layer (13) and a gate isolation dielectric layer (11) above the polycrystalline gate electrode (12);
the method is characterized in that: a P+ buried layer (6) and a separation gate structure are arranged above the N-drift region (7), and the separation gate structure comprises a separation gate dielectric layer (15) and a polycrystalline separation gate electrode (14) in the separation gate dielectric layer (15);
defining the 3-dimensional direction of the device in a 3-dimensional rectangular coordinate system: defining the direction of the device pointing to the separation gate structure from the trench structure as an x-axis direction, the direction of the device pointing to the N-drift region (7) from the trench structure as a y-axis direction, and the direction perpendicular to x and y as a z-axis direction;
the P+ buried layers (6) are distributed at intervals along the Z direction, and the area between the adjacent P+ buried layers (6) in the Z direction is an N-drift area (7); the P+ buried layer (6) is in contact with the groove structure and the separation gate structure; the upper part of the P+ buried layer (6) and the N-drift region (7) is provided with an N-type charge storage layer (5); the upper part of the N-type charge storage layer (5) is provided with a P-type base region (4); the upper part of the P-type base region (4) is provided with an N+ emitter region (2) and a P+ contact region (3) contacted with the N+ emitter region (2); the upper part of the grid isolation dielectric layer (11), the upper part of the N+ emission region (2), the upper part of the P+ contact region (3) and the upper part of the separation grid structure are provided with emitter metal (1); the separation gate dielectric layer (15) is in short circuit with the emitter metal (1); the concentration of the P+ buried layer (6) is higher than that of the P-type base region (4); the width of the P+ buried layer (6) along the z direction is larger than or equal to the width of an N-drift region (7) between adjacent P+ buried layers (6) on the same horizontal plane; the width of the P+ buried layer (6) along the y direction is smaller than the width of the N-type charge storage layer (5) along the y direction.
2. The segmented injected self-clamping IGBT device of claim 1 wherein: the N-drift region (7) between any two adjacent P+ buried layers (6) along the Z direction is replaced by a P-buried layer (16); the width of the P-buried layer (16) along the Z direction is smaller than or equal to the width of the P+ buried layer (6) along the Z direction; the concentration of the P-buried layer (16) is smaller than or equal to that of the P-type base region (4), and the width of the P-buried layer (16) along the y direction is the same as that of the P+ buried layer (6) along the y direction.
3. The segmented injected self-clamping IGBT device of claim 1 wherein: a super junction structure formed by a super junction N column (17) and a super junction P column (18) is introduced into the N-drift region (7).
4. The segmented injected self-clamping IGBT device of claim 1 wherein: a P-type floating void (20) is introduced to the right side of the separation gate structure, an isolation medium layer (19) is arranged above the P-type floating void (20), and an emitter metal (1) is arranged above the isolation medium layer (19);
the depth of the P-type floating void area (20) along the y direction is equal to the depth of the separation gate structure, or the depth of the P-type floating void area (20) along the y direction exceeds the depth of the separation gate structure along the y direction, and the P-type floating void area (20) is partially contacted with the P+ buried layer (6).
5. The segmented injected self-clamping IGBT device of claim 1 wherein: the metal at the upper part of the separation gate structure is embedded into the P-type base region (4) and the separation gate structure.
6. The method for manufacturing the segmented injection self-clamping IGBT device is characterized by comprising the following steps:
step 1: selecting the doping concentration to be 10 13 ～10 14 /cm 3 The lightly doped silicon wafer is used for forming an N-drift region of the device;
step 2: depositing a protective layer on the surface of the silicon wafer, photoetching a window to etch the groove silicon, and etching a gate electrode groove and a separation gate electrode groove;
step 3: growing a sacrificial oxide layer on the side wall of the groove, and then removing the sacrificial oxide layer; then a gate oxide layer grows on the side wall of the groove; then, polysilicon is deposited on the gate oxide layer, and then the superfluous polysilicon on the surface is etched back;
step 4: growing a pre-oxidation layer on the surface of the silicon wafer, and preparing P+ buried layers distributed at intervals by implanting P-type impurities;
step 5: an N-type charge storage layer is prepared by implanting N-type impurities; p-type impurities are implanted into the P-type base region through ions and annealing treatment is carried out to obtain the P-type base region; respectively injecting N-type impurities and P-type impurities to obtain an N+ emission region and a P+ contact region which are in contact with each other and are arranged side by side;
step 6: depositing silicon dioxide and etching redundant media to form a gate isolation medium layer;
step 7: depositing metal on the front surface of the device to manufacture emitter metal;
step 8: turning over the silicon wafer; the N-type field stop layer is prepared after laser annealing by ion implantation of N-type impurities; p+ collector region is prepared by ion implantation of P-type impurities; and depositing metal to obtain the metal collector.
7. The method for manufacturing the segmented injection self-clamping IGBT device is characterized by comprising the following steps:
step 1: selecting the doping concentration to be 10 13 ～10 14 /cm 3 The lightly doped silicon wafer is used for forming an N-drift region of the device;
step 2: growing a pre-oxidation layer on the surface of the silicon wafer, and preparing P+ buried layers distributed at intervals by implanting P-type impurities;
step 3: an N-type charge storage layer is prepared by implanting N-type impurities; p-type impurities are implanted into the P-type base region through ions and annealing treatment is carried out to obtain the P-type base region; respectively injecting N-type impurities and P-type impurities to obtain an N+ emission region and a P+ contact region which are in contact with each other and are arranged side by side;
step 4: depositing a protective layer on the surface of the silicon wafer, photoetching a window to etch the groove silicon, and etching a gate electrode groove and a separation gate electrode groove;
step 5: growing a sacrificial oxide layer on the side wall of the groove, and then removing the sacrificial oxide layer; then a gate oxide layer grows on the side wall of the groove; then, polysilicon is deposited on the gate oxide layer, and then the superfluous polysilicon on the surface is etched back;
step 6: depositing silicon dioxide and etching redundant media to form a gate isolation medium layer;
step 7: depositing metal on the front surface of the device to manufacture emitter metal;
step 8: turning over the silicon wafer; the N-type field stop layer is prepared after laser annealing by ion implantation of N-type impurities; p+ collector region is prepared by ion implantation of P-type impurities; and depositing metal to obtain the metal collector.
8. The method for manufacturing the segmented injection self-clamping IGBT device is characterized by comprising the following steps:
step 1: selecting the doping concentration to be 10 13 ～10 14 /cm 3 The lightly doped silicon wafer is used for forming an N-drift region of the device;
step 2: depositing a protective layer on the surface of the silicon wafer, photoetching a window to etch the groove silicon, and etching a gate electrode groove and a separation gate electrode groove;
step 3: growing a sacrificial oxide layer on the side wall of the groove, and then removing the sacrificial oxide layer; then a gate oxide layer grows on the side wall of the groove; then, polysilicon is deposited on the gate oxide layer, and then the superfluous polysilicon on the surface is etched back;
step 4: growing a pre-oxidation layer on the surface of the silicon wafer, and preparing P+ buried layers distributed at intervals by implanting P-type impurities;
step 5: forming a P-buried layer by implanting P-type impurities;
step 6: an N-type charge storage layer is prepared by implanting N-type impurities; p-type impurities are implanted into the P-type base region through ions and annealing treatment is carried out to obtain the P-type base region; respectively injecting N-type impurities and P-type impurities to obtain an N+ emission region and a P+ contact region which are in contact with each other and are arranged side by side;
step 7: depositing silicon dioxide and etching redundant media to form a gate isolation medium layer;
step 8: depositing metal on the front surface of the device to manufacture emitter metal;
step 9: turning over the silicon wafer; the N-type field stop layer is prepared after laser annealing by ion implantation of N-type impurities; p+ collector region is prepared by ion implantation of P-type impurities; and depositing metal to obtain the metal collector.
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| CN108183130A (en) * | 2017-12-27 | 2018-06-19 | 电子科技大学 | Double grid carrier storage characteristics IGBT device with p type buried layer |
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| CN108183130A (en) * | 2017-12-27 | 2018-06-19 | 电子科技大学 | Double grid carrier storage characteristics IGBT device with p type buried layer |
| CN109103257A (en) * | 2018-07-09 | 2018-12-28 | 苏州硅能半导体科技股份有限公司 | High reliability deep-groove power MOS component |
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