JPH02192156A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve a semiconductor integrated circuit device in latch-up resistance without making a semiconductor substrate large in area by a method wherein a well region whose conductivity type is opposite to that of the substrate is provided inside the semiconductor substrate and brought into ohmic contact with a power voltage wiring or a ground voltage wiring. CONSTITUTION:A power voltage wiring is provided between an inner circuit 2 and a peripheral circuit 4 when a semiconductor substrate is of a P-type, and a ground voltage wiring 31 is provided instead of the power voltage wiring when the semiconductor substrate is of an N-type, and a well region whose conductivity type is opposite to that of the semiconductor substrate is provided to the part inside the semiconductor substrate under the wiring 31 and brought into ohmic contact with the wiring 31. That is, the well region is formed into an N-type when the semiconductor substrate is of a P-type, or a P-type 32 when the semiconductor substrate is of an N-type. By this setup, external noises are prevented from penetrating into an inner circuit by absorbing them with a ground voltage wiring or a power voltage wiring. And, a well region whose conductivity type is opposite to that of the substrate is provided to an empty space under the power voltage wiring or the ground voltage wiring, so that a semiconductor integrated circuit device of this design can be improved in latch-up resistance without enlarging the substrate in area.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a semiconductor integrated circuit device in which an internal circuit is surrounded by ground voltage wiring or power supply voltage wiring as a countermeasure against disturbance noise, and the latch-up resistance is improved.

B. Conventional Technology As a conventional semiconductor integrated circuit device that takes countermeasures against disturbance noise, the one shown in FIG. 3 is known. this is,
Logic circuit section 2 as an internal circuit provided in semiconductor chip 1
is surrounded by power supply wiring 3 and shielded to remove external noise.

C1 Problem to be solved by the invention However, disturbance noise is placed on the power supply wiring 3 and the logic circuit section 2
Since the influence of noise on the semiconductor chip 1 is prevented, there is a possibility that the noise will escape to the power supply line of the semiconductor substrate and cause latch-up within the semiconductor chip 1. Furthermore, although there are cases where the internal circuit is surrounded by ground voltage wiring, latch-up is still unavoidable.

Here, the mechanism of latch-up occurrence is explained as follows.

FIG. 4 is an equivalent circuit diagram of parasitic transistors Ql and Q2 formed in this type of semiconductor chip 1. Terminal 5 and the base of parasitic transistor Q1 are connected through resistor R1, and terminal 6 and the base of parasitic transistor Q2 are connected through resistor R2. For example, in the semiconductor chip 1 shown in FIG. 3, in which the peripheral circuit 4 including a large current drive driver is provided around the semiconductor chip 1, the terminal 5 is connected to the P-type source region of the P-channel MO8FET in the logic circuit section 2. A substrate potential VDD is applied to the connected terminal. On the other hand, the terminal 6 is an N-channel MO in the peripheral circuit section 4.
A reverse substrate potential V8S is applied to a terminal connected to the N-type source region of the 8FET.

For example, if a voltage drop occurs when a large current drive driver is turned on, or if a substrate potential difference occurs due to the above-mentioned noise intrusion and a substrate current flows, this will cause the parasitic transistor Q1
A base current flows, and the parasitic transistors Ql and Q2 are turned on. As a result, the parasitic thyristor turns on and latch-up occurs. In addition, the reverse substrate potential VSS is applied to terminal 6.
Similarly, when the following voltage is applied, the parasitic transistor Q
l.

Q2 turns on and latch-up occurs.

A technical object of the present invention is to reliably prevent disturbance noise from entering the internal circuit and to improve latch-up resistance without increasing the board area.

Means for Solving the D0 Problem The present invention provides a semiconductor integrated circuit comprising an internal circuit formed on a P-type or N-type semiconductor substrate, and a peripheral circuit formed on a semiconductor substrate near the internal circuit. Applies to equipment.

The above technical problem is solved by the following configuration.

If the semiconductor substrate is P-type, at least a power supply voltage wiring is laid between the internal circuit and the surrounding circuit, and if it is N-type, at least a ground voltage wiring is laid between the internal circuit and the surrounding circuit. A well region having a conductivity type opposite to that of the semiconductor substrate is provided in ohmic connection with the wiring. That is, this well region is of N type in the case of a P type semiconductor substrate, and of P type in the case of a P type semiconductor substrate.

E1 action external noise is placed on the ground voltage wiring or power supply voltage wiring and is prevented from entering the internal circuit. Furthermore, a well region of a conductivity type opposite to that of the substrate is provided in the empty space below the ground voltage wiring or the power supply voltage wiring, so that the latch-up resistance can be efficiently improved without increasing the substrate area.

F. Embodiment An embodiment of the semiconductor integrated circuit device according to the present invention will be described based on FIGS. 1(a) and 1(b). FIG. 1(a) is a plan view, and FIG. 1(b) is a cross-sectional view taken along line bb--b. Note that the same parts as in FIGS. 3 and 4 will be described with the same reference numerals.

In FIG. 1(a), a logic circuit section 2 is provided as an internal circuit in the center of a semiconductor chip 1, and a peripheral circuit section 4, such as a large current drive driver circuit, is provided in the outer periphery. A dummy ground voltage wiring 31 is laid around the logic circuit section 2, which is connected to the ground voltage supply terminal 11 but not directly connected to the logic circuit section 2 or the peripheral circuit section 4. Reference numeral 12 designates a power supply voltage supply terminal, and 32 and 33 designate a P-type well region and a P1-type diffusion region, which will be described later.

In FIG. 1(b), 10 is an N'' type semiconductor substrate, 2
1 is a P-channel MO3FE provided in the logic circuit section 2
This is the P” type source region of T, and this P4 type source region 2
1 is provided with a vDD terminal 22. Further, 41 is a P- type well of the N-channel MO8FET provided in the peripheral circuit section 4, and 42 is an N+ type source region.
A VSS terminal 43 is provided in the + type source region 42 . 23, 24, 44, and 45 are LO for element isolation, respectively.
GO8 oxide film, 51.52 indicates PSG (IJ glass) film. A P- type well 32 is provided between the P+ type source region 21 and the N4 type source region 42.

A P1 type diffusion region 33 is provided on the upper surface of this P-type well 32, and the above-mentioned ground voltage wiring 31 is further provided on the upper surface of the P1 type diffusion region 33.
are ohmic connected. That is, the logic circuit section 2
is surrounded by a ground voltage wiring 31 and a P-type well 32. Note that in FIG. 1(b), source regions 21 of P-channel and N-channel MO8FETs are
．． 42 is shown, and illustration of the gate electrode and drain region is omitted.

In the semiconductor integrated circuit device shown in FIG.
2, a parasitic transistor Q1 is established, the N-type semiconductor substrate 10, the P-type well 41, and the N''''-type source region 42 cause a parasitic transistor Q2, and the P-type well 32 and the N-
A parasitic transistor Q3 is formed by the type semiconductor substrate 10 and the P-type well 41. A P- type well 32, which is a connection point between the collector of the parasitic transistor Q1 and the emitter of the parasitic transistor Q3, is connected to the ground voltage wiring 31 via a P+ type diffusion region 33.

In the semiconductor integrated circuit device configured in this way,
The ground voltage wiring 31 and the P-type well 32 surrounding the logic circuit section 2 exhibit a shielding function, and disturbance noise is prevented from entering the logic circuit section 2 by being carried on the ground voltage wiring 31 or the P-type well 32. Ru.

It also has the following latch-up prevention function.

Parasitic transistors Q1-Q3 are connected as shown in the equivalent circuit diagram of FIG. Now, if a voltage higher than the substrate potential vDD is applied to the terminal 22 due to various noises, or if a voltage effect occurs when the large current drive driver in the peripheral circuit section 4 is turned on and a substrate potential difference occurs, the parasitic transistor Q
1 turns on.

However, the collector current of parasitic transistor Q1 is
5 through the high resistance P-type well 32. P+
The voltage flows through the shaped diffusion region 33 to the ground voltage wiring 31 . At this time, since the collector and emitter of the parasitic transistor Q3 are at the same potential, the parasitic transistor Q3 is not turned on, and the base current of the parasitic transistor Q2 does not flow.
In other words, when a voltage higher than the substrate potential VDD is applied to the terminal 22, or when a substrate current flows when the large current drive driver is turned on, the current provided between the parasitic transistors Q1 and Q2 is prevented. Parasitic transistor Q2, which together with parasitic transistor Q1 constitutes a parasitic thyristor, is formed by parasitic blocking transistor Q3.
This prevents the base current from flowing and prevents its conduction, thereby preventing the parasitic thyristor from turning on and improving latch-up resistance.

In the above configuration, as shown in FIG. 1(a), a P-type well 32 is formed in the empty space below the dummy ground voltage wiring 31 surrounding the logic circuit section 2 to prevent disturbance noise from entering. Since this P-type well 32 is connected to the ground voltage wiring 31 via the P'' type diffusion region 33, the latch-up resistance can be improved while keeping the substrate area approximately the same as that of the conventional device.

Although the internal circuit is surrounded by the dummy ground voltage wiring in the above example, it may be surrounded by the ground voltage wiring connected to the internal circuit. In this case, a dummy wiring method is preferable because noise on the ground voltage wiring or power supply voltage wiring may affect the internal circuit. The present invention can also be applied to a semiconductor integrated circuit device using a P-type semiconductor substrate, in which case the internal circuit is surrounded by power supply voltage wiring, an N-well region is formed under this wiring, and ohmic connection is made with the power supply voltage wiring. . Further, specific examples of the internal circuit and peripheral circuit section are not limited to the embodiments.

G0 Effect of the Invention According to the present invention, a power supply voltage wiring or a ground voltage wiring is laid between an internal circuit section such as a logic circuit and a peripheral circuit, depending on the conductivity type of the semiconductor substrate, and furthermore, the semiconductor substrate under this wiring is laid. A well region of the opposite conductivity type to the substrate is provided inside, and ohmic connection is made to the power supply voltage wiring or ground voltage wiring.
External noise is absorbed by the power supply voltage wiring or ground voltage wiring, and the latch-up resistance is improved without increasing the semiconductor substrate area by using a reverse conductivity type well region provided in the empty space under the power supply voltage wiring or ground voltage wiring. can.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) show an embodiment of a semiconductor integrated circuit device according to the present invention, with FIG. 1(a) being a plan view and FIG. 1(b) being a sectional view taken along the line bb--b. FIG. 2 is an equivalent circuit diagram of a parasitic transistor generated within a semiconductor chip. FIG. 3 is a plan view of a semiconductor chip showing a conventional example. FIG. 4 is an equivalent circuit diagram of a parasitic transistor generated within the semiconductor chip. 2: Logic circuit section 4: Peripheral circuit section 11: Ground voltage terminal 31: Ground voltage wiring 32: P- type well 33: P+ type diffusion region Patent applicant Nissan Motor Co., Ltd.

Claims (1)

[Claims] An internal circuit formed on a P-type or N-type semiconductor substrate;
In a semiconductor integrated circuit device comprising a peripheral circuit formed on the semiconductor substrate near the internal circuit, if the internal circuit and the peripheral circuit are of P type, at least a power supply voltage is connected between the internal circuit and the peripheral circuit. In the case of an N-type wiring, at least a ground voltage wiring is laid, and a well region of a conductivity type opposite to that of the semiconductor substrate is provided in the semiconductor substrate under this wiring in an ohmic connection with the wiring. A semiconductor integrated circuit device characterized by: