JPH0215765U - - Google Patents
Info
- Publication number
- JPH0215765U JPH0215765U JP9329688U JP9329688U JPH0215765U JP H0215765 U JPH0215765 U JP H0215765U JP 9329688 U JP9329688 U JP 9329688U JP 9329688 U JP9329688 U JP 9329688U JP H0215765 U JPH0215765 U JP H0215765U
- Authority
- JP
- Japan
- Prior art keywords
- land
- recess
- hole
- semiconductor chip
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 239000012528 membrane Substances 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第1図は本考案による一実施例の斜視図、第2
図は本考案による他の実施例の斜視図、第3図a
,bは従来技術の斜視図である。
図において、1は多層回路基板、1aは導体パ
ターン、1bはくぼみ、1cは貫通孔、1dは外
部接続用電極、2は半導体チツプ、2aは電極、
2bは電極面、3は膜集積回路、4は表面実装部
品、5はマザー配線基板、5aは接続端子を示す
。
Fig. 1 is a perspective view of one embodiment of the present invention;
The figure is a perspective view of another embodiment of the present invention, FIG.
, b are perspective views of the prior art. In the figure, 1 is a multilayer circuit board, 1a is a conductor pattern, 1b is a recess, 1c is a through hole, 1d is an electrode for external connection, 2 is a semiconductor chip, 2a is an electrode,
2b is an electrode surface, 3 is a membrane integrated circuit, 4 is a surface mount component, 5 is a mother wiring board, and 5a is a connection terminal.
Claims (1)
み1bまたは貫通孔1cの外縁に導体パターン1
aに接続するランド1a―1と、裏面に外部接続
用電極1dとを備える多層回路基板1と、 該くぼみ1b、または貫通孔1cに収容しダイ
ボンデイングする半導体チツプ2と、 該半導体チツプ2の電極2aと前記ランド1a
―1とをワイヤボンデイングまたはテープ・オー
トメイテツド・ボンデイングするとともに該ラン
ド1a―1に接近して前記導体パターン1aとの
間に膜集積回路3および表面実装部品4を接続し
てなることを特徴とする混成集積回路モジユール
。[Claims for Utility Model Registration] A recess 1b or through hole 1c on the surface, and a conductive pattern 1 on the outer edge of the recess 1b or through hole 1c.
a multilayer circuit board 1 having a land 1a-1 connected to the surface of the semiconductor chip 1, and an external connection electrode 1d on the back surface; a semiconductor chip 2 accommodated in the recess 1b or the through hole 1c for die bonding; Electrode 2a and the land 1a
-1 by wire bonding or tape automated bonding, and a film integrated circuit 3 and surface mount component 4 are connected between the land 1a-1 and the conductor pattern 1a in proximity to the land 1a-1. Hybrid integrated circuit module.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9329688U JPH0215765U (en) | 1988-07-13 | 1988-07-13 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9329688U JPH0215765U (en) | 1988-07-13 | 1988-07-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0215765U true JPH0215765U (en) | 1990-01-31 |
Family
ID=31317742
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9329688U Pending JPH0215765U (en) | 1988-07-13 | 1988-07-13 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0215765U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006048932A1 (en) * | 2004-11-04 | 2006-05-11 | Renesas Technology Corp. | Electronic device and electronic device manufacturing method |
-
1988
- 1988-07-13 JP JP9329688U patent/JPH0215765U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006048932A1 (en) * | 2004-11-04 | 2006-05-11 | Renesas Technology Corp. | Electronic device and electronic device manufacturing method |
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