JPH02122741A - Multiplexing frame conversion circuit - Google Patents

Abstract

PURPOSE:To simply and easily respond to the increment of the number of channels by using a dual port memory having a required address area. CONSTITUTION:A frame disassembling circuit 1 disassembles an input multiplex frame A to be converted to each channel. And data D11-D31 from which frame synchronizing bits FA are eliminated are written on the duel port memory 3 having an address are of 16X3X2 bits, etc., that is at least twice the least common multiple between the bit length of 8X3 bits of the frame A, etc., and the bit length of 16X3 bits of a conversion multiplex frame B, etc., sequentially via a write address counter 2. Similarly, data D12-D32 in the frame A at a second frame are written, and the data are read out from the memory in sequence of D11, D12, D21, D22..., etc., corresponding to the address of a readout address counter 5, and the multiplex frame B converted at a frame generation circuit 4 is outputted, which simplifies and facilitates correspondence at the time of increasing the number of channels since no FIFO memories corresponding to the number of channels are used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention converts a certain multiplexed frame into another multiplexed frame having the same transmission speed in a time division multiplexing device.

The present invention relates to a multiplex frame conversion circuit for use in a multiplex frame conversion circuit.

(Conventional Technique'#i) An example of a multiplexed frame used for processing by this type of multiplexed frame conversion circuit is shown in FIG.

In FIG. 2, (a) shows a converted multiplexed frame A, in which FA is a frame synchronization bit and D
11 to D31 are channel data of the first frame, each consisting of 8 bits.

Therefore, the multiplexed frame A has 3 multiplexed channels and 1
It can be said that the frame has a 32-bit structure.

Similarly, DI2 to D32 in the same figure (a>) are channel data of the second frame to the multiplexed frame.

On the other hand, (b) in the same figure shows a multiplexed frame B to be generated by conversion, in which the frame synchronization bit FB is 16 bits and the channel data D11 to [)3.
2 is 16 bits each, and has a structure of 3 channels and 64 bits per frame.

As is clear from the frame structure shown in FIG. 2, in this type of conventional multiplex frame conversion circuit, when converting frame A to frame B, the 1st channel data of the first frame of frame A [) 11 and the 1st channel data [) 12 of the second frame are combined to create 1 of frame B.
Channel data D11°[)12 are converted into channel data D21 . D22 and 3 channel data [)31. [)32.

FIG. 3 shows the configuration of a conventional multiplexed frame conversion circuit that enables this type of frame conversion processing. A circuit 10 is provided.

In FIG. 3, when frame A [FIG. 2(a)] is input to the frame decomposition circuit 6, the frame synchronization bit FA
is removed, and data 011. D21°[)31 are outputted to 6-1.6-2°6-3 for each channel.

Each output data is transmitted through the FI provided for each channel.
They are written to FO memories 7, 8 and 9, respectively.

Second frame data DI2. D22. Similarly, D32 is inputted and outputted from the FIFO memory 7.8.9 in channel units.

The frame generation circuit 10 includes an F
Frame B [Fig. 2 (
b)] is accessed for reading according to the generation format of f-ta[)11. DI2 to 7-
Import via 1.

Similarly, the frame generation circuit 10 outputs data D21 . D22 via 8-1 and FIF
Data 031. from O memory 9. D32 is taken into each via 91, and frame synchronization bit FB is added to these.
By adding , frame B is generated and output.

In such conventional multiplex frame conversion circuits, frame conversion was performed using FIFO memories for the number of channels of multiplexed frames, which is good when the number of channels is small, but when the number of channels increases, the circuit scale becomes extremely large. I had no choice but to grow up.

(Problem to be Solved by the Invention) In this way, the conventional multiplex frame conversion circuit described above performs frame conversion using an FtFO memory that stores and reads out decomposed data from a frame to be converted for each channel. When the number of channels in a digital frame increases, there is a problem in that an increase in circuit scale is unavoidable because it is necessary to prepare FIFO memory for the number of channels.

The present invention has been made in view of the above-mentioned circumstances, and provides a multiplexed frame conversion capable of performing frame conversion while minimizing an increase in circuit size even when the number of channels in a multiplexed frame increases. The purpose is to provide circuits.

[Structure of the invention]

(Means for Solving the Problems) The multiplex frame conversion circuit of the present invention provides a multi-frame frame B
frame decomposition means for decomposing a multiplexed frame A into data for each channel for converting the multiplexed frame A into data for each channel; and an address for a number of bits that is at least twice the least common multiple of the data lengths of the multiplexed frame A and the multiplexed frame B. a dual photo memory having an area; and write address generation means for generating write addresses for sequentially writing data decomposed by the frame decomposition means into the dual port memory while using the address areas for each of the minimum number of bonds. , when reading the data written corresponding to the write address from the dual port memory in the order according to the format of the multiplexed frame B, an address area corresponding to the minimum number of bonds written immediately before the readout; read address generating means for generating a read address that is cyclically performed simultaneously with writing of the address area for the next minimum number of public bonds; and data read from the dual port memory based on the read address. frame generating means for adding a frame synchronization signal to the array of and outputting the multiplexed frame B as the multiplexed frame B.

(Function) According to the multiplexed frame conversion circuit of the present invention, a dual port memory having separate input and output ports and capable of simultaneous input and output is used, and data related to frame conversion can be written to and from the dual port memory. Frame conversion is performed by alternately performing readout (order according to the format of the post-conversion frame) for each address area corresponding to the minimum number of public bonds for the data length of the pre-conversion frame and post-conversion frame, respectively. Even if the number of channels increases, this can be easily handled by simply expanding the address area.

(Example) Hereinafter, an example of the present invention will be described in detail based on the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a multiplexed frame conversion circuit according to the present invention, where 1 is a frame decomposition circuit, 2 is a write address counter, 3 is a dual port memory, and 4 is a frame decomposition circuit.
5 is a frame generation circuit, and 5 is a read address counter.

This multiplex frame conversion circuit is similar to the conventional one as shown in Figure 2 (
Assume that a multiplexed frame A as shown in a) is converted into a multiplexed frame B as shown in FIG. 2(b).

In this case, the storage capacity of the dual port memory 3 is required to be at least twice the number of bits of the least common multiple of the number of bits of each data of frame A and frame B.

As is clear from Figure 2, the data length of frame A (not including frame synchronization bit FA) is 24 bits, and similarly, the data length of frame B (not including frame synchronization bit FB) is 48 bits. .

Therefore, the least common multiple of the data lengths of these two frames is 48
If a dual port memory 3 having an address area of 96 bits or more is used, frame conversion can be performed by the method described below.

In FIG. 1, when a frame A, which is an umbrella to be converted, is input, a frame decomposition circuit 1 inputs its frame synchronization bit FA.
is removed, and only data 1-1 is extracted and output to the dual port memory 3.

During such processing, the frame decomposition circuit 1 sends synchronization flags 1-2 to the write address counter 2 at the timing when the frame synchronization bit FA is detected.

The write address counter 2 starts counting based on this synchronization flag 1-2, and outputs the count value to the dual photomemory 3 as a write address 2-1.

Here, the write address counter 2 is composed of a 96-bit counter in accordance with the fact that the least common multiple of the data lengths of frame A and frame B is 48 bits, and after starting the operation based on the synchronization flag 1-2, the write address counter 2 is a 96-bit counter. The write address 2-1 indicated by the count value is cyclically output.

As a result, the dual port memory 3 sequentially stores data 1-1 output from the frame decomposition circuit 1 bit by bit into address areas O to 95 corresponding to the write address 2-1 from the write address counter 2.

In this way, in the dual port memory 3, each piece of data 1-1 of the disassembled frame A is written in order from the first data [) 11, but the write address counter 2, which specifies the address area related to this write, When the count of write addresses 2-1 of .about.47 is finished, a read permission signal 2-2 is output to the frame generation circuit 4.

This point is the point in time when all 48 bits (the least common multiple) of the 17th rem of frame A and the second frame have been written to the corresponding address areas 0 to 47.

Furthermore, the frame generation circuit 4 that has received the read permission signal 2-2 starts the read address counter 5 by outputting a read start signal 4-1.

After startup, the read address counter 5 reads address areas ○ to 47 of the dual port memory 3 (in which the data of the 1st frame and the 27th rem of frame A have already been written) according to the predetermined generation format of frame B. Dll, DI2. D
21. D22. D31゜[)32 order [Fig. 2(
A read address 5-1 for reading is created in [see b)] and outputted to the dual port memory 3.

In dual port memory 3, this read address 5-1
Accordingly, each of the above data is read bit by bit from address areas 0 to 47, and this is output to the frame generation circuit 4.

Then, the frame generation circuit 4 includes the dual port memory 3
Furthermore, frame synchronization bit FB is added to the output data 3-1 from
The pig 4-2 generated by this is added to frame B
Output as .

During this time, address area 48 of dual port memory 3
~95, each data of the third frame and the fourth frame is written to the frame based on the write address 2-1 from the write address counter 2, and at the same time as the writing is completed, a frame is generated again from the write address counter 2. A read permission signal 2-2 is output to the circuit 4.

At the same time, dual port memory 3 finishes reading each data from address areas O to 47 using the method described above, so dual port memory 3
Now, the process moves on to reading each data from the address areas 48 to 95 to which writing has been completed immediately before.

In this way, the frame generation circuit 4 is connected to the dual port memory 3.
While generating the second frame of frame B while reading each data in the address areas 48 to 95 of , the write address counter 2 reads the data of the fifth and sixth frames of frame A from the frame disassembly circuit 1. A write address 2-1 is designated to write the data in the address areas O to 47 of the dual port memory 3 again.

In this way, in the present invention, the FlFO memory is used as in the conventional manner while writing the converted frame A and reading the generated frame B are accessed alternately to the address areas O~47, 48~95 of the dual port memory 3. You can perform frame conversion without any need.

Incidentally, in the above embodiment, for the sake of simplicity, a case has been described in which a dual port memory 3 having a storage capacity for the number of bits twice the least common multiple of the data lengths of frame 8 and frame B is used. Needless to say, it can be expanded to an integer multiple.

This means that even if the number of channels increases, it can be dealt with simply by increasing the address area of the dual port memory 3, and even in this case, the increase in circuit scale can be kept to a minimum.

[Effects of the Invention] As explained above, according to the multiplex frame conversion circuit of the present invention, the dual frame conversion circuit has an address area for at least twice the number of bits of the least common multiple of the data lengths of the pre-conversion frame and the post-conversion frame. By using a port memory, writing and reading data related to frame conversion to and from this dual port memory (in an order according to the format of the converted frame) are performed alternately for each address area of the above-mentioned least common multiple. Because frame conversion is performed, even if the number of channels increases, it can be handled simply by expanding the address area of the dual port memory, and compared to conventional circuits of this type that use FIFO memory, This has the excellent advantage of minimizing the increase in circuit scale.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a multiplex frame conversion circuit according to the present invention, and FIGS. 2(a) and 2(b) show a pre-conversion multiplex frame A and an exchange for this type of multiplex frame conversion processing. FIG. 3 is a block diagram showing a schematic structure of a conventional multiplex frame converting circuit of this type. DESCRIPTION OF SYMBOLS 1... Frame decomposition circuit, 2... Write address counter, 3... Dual port memory, 4... Frame generation circuit, 5... Read address counter, 1-
1.3-1.4-2. ...Data, 1-2...Synchronization flag, 2-1...Write address, 2-2...Read permission signal, 4-1...Read start signal, ...Read address

Claims (1)

[Scope of Claims] Frame decomposition means for decomposing a multiplexed frame A into data for each channel for converting into a multiplexed frame B, and a least common multiple of the data lengths of the multiplexed frame A and the multiplexed frame B. a dual port memory having an address area for at least twice the number of bits, and a writing device for sequentially writing data decomposed by the frame decomposition means into the dual port memory while using the address area for each of the least common multiples. a write address generating means for generating an address; and when reading data written corresponding to the write address from the dual port memory in an order according to the format of the multiplexed frame B, the reading is performed immediately before the writing. read address generating means for generating a read address that is targeted at the address area corresponding to the least common multiple and is cyclically performed at the same time as writing of the address area corresponding to the next lowest common multiple; 1. A multiplex frame conversion circuit comprising: frame generating means for adding a frame synchronization signal to the data array read from a port memory and outputting the same as the multiplex frame B.