JP7583706B2 - Manufacturing method of semiconductor device and laminate - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device and a laminate used in the method for manufacturing a semiconductor device.

A method called DBG (Dicing Before Grinding) is known as a manufacturing process for semiconductor devices such as semiconductor chips in which semiconductor circuits are formed on a silicon substrate. DBG is a method in which grooves having a depth equivalent to the finished thickness are formed on the streets of a wafer, and the back surface of the wafer is ground to expose the previously formed grooves from the back surface of the wafer, thereby dividing the wafer into individual semiconductor chips.
A method called SDBG (Stealth Dicing Before Grinding) has also been proposed for the purpose of increasing the number of chips that can be obtained from one wafer. SDBG is a processing method in which a focal point of a laser having a wavelength that is transparent to the wafer is positioned inside the wafer, the wafer is irradiated with the laser along a planned division line, a modified layer is formed inside the wafer by multiphoton absorption, the back side of the wafer is ground to thin the wafer, and the wafer is divided into individual semiconductor chips using the modified layer as the division starting point.
When a processing method such as SDBG is used that makes the gaps between chips in a divided wafer very small, chips or cracks may occur in the individual semiconductor chips. For this reason, for example, Patent Document 1 proposes providing a chip prevention layer made of a metal film or the like at each intersection of the planned division lines on the surface of the wafer.

JP 2018-6653 A

However, there is an ever-increasing demand for smaller chip sizes, and as semiconductor chips become smaller, the problem of cracks and chipping in semiconductor chips becomes more pronounced. According to the inventors' studies, it has been found that when using a method in which the gaps formed by dicing in DBG are minimized, or a method such as SDBG in which the gap between adjacent chips is essentially zero at the time the wafer is divided, as the chip size becomes smaller, the problem of cracks and chipping due to contact between adjacent chips becomes more pronounced. Therefore, there is a demand for a new and useful method for manufacturing semiconductor devices that can more effectively prevent chipping and cracking in chips.

In consideration of the above problems, the present invention aims to provide a method for manufacturing a semiconductor device in which cracks or chips are less likely to occur in the chips during the manufacturing process, even when the distance between adjacent chips after individualization is small, and a laminate suitable for the method.

As a result of extensive research into solving the above-mentioned problems, the inventors discovered that the above-mentioned problems can be solved by appropriately setting the attachment direction of the adhesive sheet to be attached to the circuit layer forming surface of the wafer based on the area of the wafer to be singulated, and thus completed the present invention.
That is, the present invention provides the following [1] to [6].
[1] A method for manufacturing a semiconductor device having a rectangular planar shape, comprising the steps of:
A pressure-sensitive adhesive sheet is attached to a surface of a wafer including a plurality of rectangular regions to be singulated arranged in a matrix along a short side direction of the regions to be singulated;
A method for manufacturing a semiconductor device, comprising: grinding the back surface of the wafer to which the adhesive sheet is attached; and dividing the wafer along planned division lines that define the planned individualization areas.
[2] After the adhesive sheet is attached to the surface of the wafer, a modified portion serving as a starting point for division is formed inside the wafer at a planar position corresponding to the planned division line;
The method for manufacturing a semiconductor device according to the above-mentioned [1], further comprising: grinding a back surface of the wafer to which the adhesive sheet is attached, and dividing the wafer along the planned dividing lines.
[3] The method for manufacturing a semiconductor device described in [1] or [2] above, wherein the aspect ratio of the region to be divided, expressed as the length in the long side direction/the length in the short side direction, is 1.05 or more.
[4] The method for manufacturing a semiconductor device described in any one of [1] to [3] above, wherein the region to be diced has a length in the long side direction of 5 to 50 mm and a length in the short side direction of 2 to 20 mm.
[5] A transfer sheet is attached to the back surface of the wafer after grinding;
The method for manufacturing a semiconductor device according to any one of the above [1] to [4], wherein the adhesive sheet is separated from the wafer after the transfer sheet is attached.
[6] A wafer including a plurality of rectangular regions to be singulated arranged in a matrix;
A laminate comprising an adhesive sheet attached to the surface of the wafer while applying tension along the short side direction of the area to be singulated.

According to the present invention, it is possible to provide a method for manufacturing a semiconductor device in which cracks or chips are unlikely to occur in the chips during the manufacturing process, even when the distance between adjacent chips after individualization is small, and a laminate suitable for the method can be provided.

FIG. 1 is a schematic cross-sectional view of a wafer on which a circuit layer is formed, a laminate in which an adhesive sheet is attached onto the circuit layer of the wafer, and a semiconductor chip as a semiconductor device obtained by processing the wafer using the laminate. 1 is an explanatory diagram showing the relationship between the direction in which an adhesive sheet is attached to a wafer and regions on the wafer to be singulated. 3A to 3C are schematic cross-sectional views showing a manufacturing process of a laminate. 1A to 1C are schematic cross-sectional views showing a manufacturing process of a semiconductor device. 1A to 1C are schematic cross-sectional views showing a manufacturing process of a semiconductor device. 1A to 1C are schematic plan views showing, in comparison, a wafer used in a semiconductor device manufacturing method according to an embodiment of the present invention and a wafer used in a semiconductor device manufacturing method according to a comparative example.

Hereinafter, an embodiment of the present invention (hereinafter, sometimes referred to as "the present embodiment") will be described.
[Wafer, laminate, and semiconductor device]
The semiconductor device manufactured by the semiconductor device manufacturing method of this embodiment includes a wafer portion and a circuit portion formed on the surface thereof, and has a rectangular planar shape. In this specification, the term "semiconductor device" refers to devices that can function by utilizing semiconductor characteristics, such as those used in processors, memories, sensors, etc. Specifically, examples of such devices include wafers with integrated circuits, thinned wafers with integrated circuits, chips with integrated circuits, thinned chips with integrated circuits, electronic components including these chips, and electronic devices including such electronic components. Chips before packaging are also included.
A semiconductor device is obtained by dividing a wafer having a circuit layer formed on its surface into individual pieces.
In a process for processing a wafer provided with a circuit layer into a semiconductor device, a laminate in which an adhesive sheet is attached to the surface of the wafer on which the circuit layer is formed is used.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A wafer, a stack, and a semiconductor device according to embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a schematic cross-sectional view of a wafer on which a circuit layer is formed, a laminate in which an adhesive sheet is attached to the surface of the wafer on which the circuit layer is formed, and a semiconductor chip as a semiconductor device obtained by processing the wafer.
As shown in FIG. 1A, first, a wafer W having a circuit layer C formed on its surface by a semiconductor forming process including a photolithography method is prepared.
Next, as shown in FIG. 1(B), an adhesive sheet 1 is attached to the surface of the wafer W on which the circuit layer C is formed, to obtain a laminate 10.
1C, the back surface of the wafer W is ground as necessary, and the wafer W is divided along the division lines that define the regions to be divided into individual pieces to obtain the divided wafers WI. In this manner, the wafer W having the circuit layer C is divided into a plurality of pieces to obtain semiconductor chips CP as semiconductor devices. The regions to be divided will be described in detail later.

<Wafer>
The wafer W is a disk-shaped piece of high-purity single crystal silicon cut out. The diameter of the wafer W is, for example, 12 inches, although this is not limited thereto.
The circuit layer C is a layer including a semiconductor circuit formed on the surface of the wafer W by a semiconductor manufacturing process.
The semiconductor process includes a process of forming a thin film of the circuit material, such as silicon oxide or aluminum, on a silicon wafer by sputtering, electroplating, CVD, or the like, and then forming a semiconductor circuit by photolithography.
The photolithography method includes a step of covering the thin film formed on the silicon wafer with a resist film, a step of irradiating the resist film with UV light through a mask having a circuit pattern formed thereon, a step of developing and selectively removing uncured portions of the resist film, a step of etching and removing the thin film exposed by development, a step of injecting impurities such as phosphorus or boron into the silicon substrate exposed by etching to impart semiconductor properties, a step of activating impurity ions by heat treatment using a flash lamp, laser irradiation, or the like, and a step of peeling off the resist film.

<Semiconductor Device>
The wafer W is divided into a plurality of semiconductor chips, each of which is, for example, about 12 mm×6 mm in size when viewed from above. When divided into such sizes, about 1,000 semiconductor chips can be obtained from a wafer having a diameter of 12 inches.
As described above, the semiconductor chip, which is a semiconductor device, includes a wafer portion derived from the wafer W and a circuit portion derived from the circuit layer C formed on the surface thereof.
The semiconductor chip obtained by the method for manufacturing a semiconductor device according to the present embodiment has a rectangular planar shape, which makes it possible to impart various functions to the semiconductor chip and to easily grasp the top and bottom of the semiconductor chip.

<Laminate>
The laminate 10 is formed by attaching an adhesive sheet 1 to the surface of a wafer W on which a circuit layer C is formed.

(Adhesive sheet)
The adhesive sheet 1 is a laminate including a base layer and an adhesive layer laminated on the base layer, and is typically a laminate including a base layer, a buffer layer provided on at least one side of the base layer, and an adhesive layer provided on the other side of the base layer. The adhesive sheet 1 may include other constituent layers other than these, for example, a primer layer may be formed on the base surface on the adhesive layer side, and a release sheet for protecting the adhesive layer until use may be laminated on the surface of the adhesive layer. The base material may be a single layer or may be multilayered. The same applies to the buffer layer and the adhesive layer. The adhesive sheet 1 is attached to the wafer W so that the adhesive layer of the adhesive sheet 1 contacts the circuit layer C of the wafer W, and the adhesive sheet 1 serves as a protective film for protecting the circuit layer C of the wafer W.

(Base layer)
The material of the base layer is not particularly limited, but is preferably a resin film from the viewpoint of being suitable for electronic component processing members because it generates less dust than paper or nonwoven fabric, and is easy to obtain. By having the base layer of the adhesive sheet, the shape stability of the adhesive sheet can be improved and the adhesive sheet can be given stiffness. In addition, even if the circuit layer C of the wear W has large irregularities, the surface opposite to the adhesive surface of the adhesive sheet is likely to be kept smooth.
The substrate layer may be a substrate layer made of a single-layer film made of one resin film, or a substrate layer made of a multi-layer film in which a plurality of resin films are laminated.
The thickness of the base layer is preferably 5 to 250 μm, more preferably 10 to 200 μm, and even more preferably 25 to 150 μm, from the viewpoint of imparting appropriate elasticity to the pressure-sensitive adhesive sheet and from the viewpoint of ease of handling when the pressure-sensitive adhesive sheet is rolled up.
Examples of resin films that can be used for the base layer include polyolefin-based films, halogenated vinyl polymer-based films, acrylic resin-based films, rubber-based films, cellulose-based films, polyester-based films, polycarbonate-based films, polystyrene-based films, polyphenylene sulfide-based films, cycloolefin polymer-based films, and films made of a cured product of an energy ray-curable composition containing a urethane resin.
The polyester-based film used for the base layer may be a film made of a polyester copolymer, or may be a resin mixed film made of a mixture of the above polyester and a relatively small amount of other resin. Among these polyester-based films, a polyethylene terephthalate film is preferred from the viewpoints of easy availability and high thickness accuracy.

(Adhesive Layer)
The adhesive layer provided on the base layer or intermediate layer protects the circuit layer C by reliably fixing the adhesive sheet to the circuit layer C of the wafer W.
The adhesive layer contains an adhesive. Examples of the adhesive include acrylic adhesives, rubber adhesives, urethane adhesives, silicone adhesives, polyvinyl ether adhesives, olefin adhesives, etc. These adhesives may be used alone or in combination of two or more.
The thickness of the adhesive layer can be adjusted appropriately depending on the size of the irregularities in the circuit layer to be protected, but is preferably 5 to 200 μm, more preferably 7 to 150 μm, and even more preferably 10 to 100 μm.

(Middle class)
The intermediate layer is not particularly limited, but from the viewpoint of obtaining good unevenness absorbency, it is preferable that the intermediate layer is formed from a resin composition containing a urethane (meth)acrylate and a thiol group-containing compound.
The thickness of the intermediate layer can be adjusted appropriately depending on the size of the irregularities on the surface of the semiconductor to be protected, but from the viewpoint of being able to absorb relatively large irregularities, it is preferably 50 to 400 μm, more preferably 70 to 300 μm, and even more preferably 80 to 250 μm.

(Direction of adhesive sheet application)
FIG. 2 is an explanatory diagram showing the relationship between the direction in which the adhesive sheet 1 is attached to the wafer W and regions R on the wafer W that are to be singulated.
2A, a V-notch Wv indicating a reference direction for processing or machining the wafer W and semiconductor circuits provided in each of the regions R to be singulated defined by the planned dividing lines E are formed on the surface of the wafer W. The semiconductor circuits are formed based on the direction indicated by the V-notch Wv. In addition, bonding of an adhesive sheet, which will be described later, is also performed based on the direction indicated by the V-notch Wv.
Here, the region R to be singulated is rectangular in plan view. The planned division lines E that define the region R to be singulated are virtual, and it is sufficient that the individual circuits are formed so as not to straddle the planned division lines E. It is not necessary to physically form the planned division lines E that define the region R to be singulated on the surface of the wafer W or the circuit layer C. However, in order to make it easier to recognize the region R to be singulated and to make the division of the wafer W proceed smoothly, a processed groove or the like that becomes the planned division line E may be formed in advance by a photolithography method.
By making the region R to be singulated rectangular, the shape of the semiconductor chips finally obtained will also be rectangular.
2A, each circuit of the circuit layer C is formed such that the short-side direction d2 of each region R to be singulated coincides with the direction d3 (hereinafter also referred to as the vertical direction) indicated by the V-notch Wv. As a result, the long-side direction d1 of the region to be singulated coincides with the direction (hereinafter also referred to as the horizontal direction) perpendicular to the direction d3 indicated by the V-notch Wv.

The length of the long side of the region R to be diced is preferably 5 to 50 mm, more preferably 7 to 40 mm, and even more preferably 10 to 30 mm, from the viewpoint of easily preventing chipping or cracking of the semiconductor chip during the manufacturing process and making it easier to impart various functions to the semiconductor chip.
The length of the short side of the region R to be diced is preferably 2 to 20 mm, more preferably 3 to 18 mm, and even more preferably 4 to 15 mm, from the viewpoint of improving ease of handling and making it easier to impart the minimum necessary functions to the semiconductor chip.
The aspect ratio of the region R to be diced, expressed as the ratio of the length in the long side direction to the length in the short side direction (length in the long side direction/length in the short side direction), is preferably 1.05 or more, more preferably 1.10 or more, even more preferably 1.15 or more, from the viewpoint of maintaining an appropriate balance between the ability to prevent chipping or cracking of the semiconductor chip during the manufacturing process and the ability to impart functionality to the semiconductor chip, and is also preferably 10 or less, more preferably 7.0 or less, and even more preferably 5.0 or less.

In this embodiment, as described later, when manufacturing a semiconductor device, the wafer W is divided by the SDBG, so that the distance between adjacent chips is substantially zero. Therefore, the vertical and horizontal lengths of the region R to be singulated match the vertical and horizontal lengths of the semiconductor chip.
It is also possible to provide no semiconductor circuit outside the intended singulation region R, and to provide unused semiconductor circuits as dummy circuits outside the intended singulation region.

As shown in Fig. 2(B), the adhesive sheet 1 has a length and width sufficient to cover the entire surface of the wafer W. When a wafer W having a diameter of 12 inches is used, the adhesive sheet 1 may be, for example, a long one having a width of 400 mm. In Fig. 2(B), the wafer W covered by the adhesive sheet 1 and the regions R to be singulated are shown by thin lines for ease of understanding. If an optically transparent adhesive sheet is used as the adhesive sheet 1, the shape and arrangement direction of the regions R to be singulated can be confirmed through the adhesive sheet 1.
When attaching the adhesive sheet 1, the wafer W is set in the lamination device based on the direction d3 indicated by the V-notch Wv. At this time, the wafer W is set so that the attachment direction d4 of the adhesive sheet 1 by the lamination device is aligned with the direction d3 indicated by the V-notch Wv. As a result, in this embodiment, the short side direction d2 of the region R to be singulated is aligned with the direction d3 indicated by the V-notch Wv.
After the adhesive sheet 1 is attached onto the circuit layer C of the wafer W, if necessary, the adhesive sheet 1 protruding from the wafer W is cut and removed. As described later, when the adhesive sheet 1 is attached by a method of attaching the adhesive sheet 1 while applying tension so as to eliminate bending of the adhesive sheet 1, the adhesive sheet 1 is attached onto the circuit layer C with tension applied along the attachment direction d4 of the adhesive sheet 1. As a result, the laminate 10 is formed with tension applied in the direction along the short side direction d2 of the region R to be singulated.
Here, the attachment direction d4 of the adhesive sheet is set to be along the direction d3 indicated by the V-notch Wv (i.e., in this example, the short side direction d2 of the region R to be singulated), but as shown in Fig. 2(B), the attachment direction d4 of the adhesive sheet 1 may be set to be within a certain angle θ with respect to the direction d3 indicated by the V-notch Wv. Here, θ is preferably within a range of ±45°, more preferably ±40°, and even more preferably ±35° with respect to the direction d3 indicated by the V-notch Wv.

[Method of producing laminate]
3A and 3B are schematic cross-sectional views showing the steps of producing a laminate, in which a wafer W having a circuit layer C formed thereon is placed on a support 100, FIG. 3B is a diagram showing a state in which an adhesive sheet 1 is attached to the circuit layer C of the wafer W, and FIG. 3C is a diagram showing a state in which the adhesive sheet 1 is attached to the circuit layer C of the wafer W.
As shown in Fig. 3(A), the wafer W is placed on the support 100 so that the back surface of the wafer W on which the circuit layer C is formed is in contact with the support 100, and then, as shown in Fig. 3(B), the adhesive sheet 1 is attached to the circuit layer C of the wafer W. In this example, one end of the adhesive sheet 1 is wound up by a winding member or held by a holding member to be held in a floating state above the wafer W, while the adhesive sheet 1 is sequentially pressed from the other end by a pressing body 101, so that the adhesive sheet 1 is attached to the surface of the wafer W on which the circuit layer C is formed.
At this time, in order to eliminate slack in the adhesive sheet 1 as much as possible, a certain tension is applied to the adhesive sheet 1 in the longitudinal direction (i.e., the direction in which the adhesive sheet 1 is attached) or a pressing force from a pressing body is applied to the adhesive sheet 1 in the longitudinal direction, so that the adhesive sheet 1 is attached to the wafer W with tension applied in the attachment direction d4. The adhesive sheet 1 is attached to the circuit layer C of the wafer W with almost no tension applied to the adhesive sheet 1 in the lateral direction.
After the adhesive sheet 1 is attached onto the circuit layer C, if necessary, the adhesive sheet 1 protruding from the wafer W is cut and removed. In this way, as shown in Fig. 3(C), a laminate 10 is produced in which the adhesive sheet 1 is attached onto the circuit layer C of the wafer W.
The material constituting the support 100 is not particularly limited, and may be, for example, a metal material such as stainless steel.

[Method of Manufacturing Semiconductor Device]
An example of the manufacturing method of the semiconductor device of this embodiment includes the steps of processing a laminate in which an adhesive sheet is attached to a circuit layer of a wafer, dividing the wafer and grinding the back surface of the wafer, attaching a transfer sheet to the surface of the divided wafer opposite to the surface on which the circuit layer is formed (i.e., the back surface of the wafer), removing the adhesive sheet, and then dividing the wafer together with the transfer sheet into individual pieces. Each step will be described below in order. The transfer sheet is a sheet that is attached to the back surface of the wafer, and is used to transfer the wafer to its surface and hold the wafer after the wafer is separated from the adhesive sheet.

4 and 5 are schematic cross-sectional views showing the manufacturing process of a semiconductor device.
Fig. 4(A) is a diagram showing a state in which the laminate 10 is placed on a support 200 that is different from the support 100. As shown in Fig. 4(A), the laminate 10 is placed on the support 200 so that the adhesive sheet 1 is in contact with the support 200. Note that, as the support 200, for example, one made of the same material as the support 100 or a ceramic porous table can be used.
4B is a diagram showing how a laser is irradiated onto the wafer W from the back side. As shown in FIG. 4B, the position of the laser 103 is determined using a condenser 102 so that the focal point of the laser 103, which has a wavelength that is transparent to the wafer W, is inside the wafer W, and the laser 103 is irradiated onto the wafer W from the back side while moving the laser 103 and the wafer W relatively along the planned division line E that defines the planned singulation region R. As a result, a modified portion M is formed inside the wafer W at a planar position corresponding to the planned division line E. The modified portion M is a portion of the wafer W modified by the irradiation of the laser, and serves as a starting point for breaking the wafer W.
4C is a diagram showing how the back side of the wafer W is ground. As shown in FIG. 4C, the back side of the wafer W is ground using a grinder 104 until a desired thickness is obtained. This process reduces the thickness and weight of the wafer W. At the same time, the wafer W is split along the planned division lines E that define the planned individualization regions R, starting from the modified portions M. In addition, the modified portions M formed in the wafer W are removed by grinding.

In SDBG, when the wafer is divided during grinding, there are only cracks between adjacent chips due to stealth dicing (symbol P in FIG. 4C), and the distance between the chips is essentially zero. Therefore, even slight stress or impact can cause the chips to shift, resulting in contact, pressure, friction, or collision between the chips, making it easy for cracks to occur. In addition, when an adhesive sheet such as a protective sheet for back grinding is applied, tension is applied in the application direction, so stress is likely to remain in the laminate after the adhesive sheet is applied. For this reason, when the back surface of the wafer is ground, the wafer W is cut into individual chips starting from the modified portion M, and at the same time, the stress in the laminate is released, making it easier for the chips to move in the application direction of the adhesive sheet, which is presumably the result of contact, pressure, friction, or collision between the chips, inducing cracks.

In the manufacturing method of the semiconductor device of this embodiment, the reason why chipping and cracking of the chips are suppressed is, although not limited thereto, the following is one possible reason. That is, by making the vertical length and horizontal length of the chip different and attaching the adhesive sheet along the short side direction of the chip, the number of cutting lines between the chips in the attachment direction of the adhesive sheet increases compared to the case where the adhesive sheet is attached along the long side direction of the chip. This distributes the amount of movement of the chips in the attachment direction among more chips, reducing contact, pressure, friction, collision, etc. between the chips, which is presumably linked to the suppression of cracking and chipping.
In this embodiment, the modified portion is removed by grinding. However, for example, in applications where thinning of the wafer is not required or when the wafer is thick to begin with, at least a portion of the modified portion may remain on the wafer even after grinding.

Fig. 5(A) shows a process of separating the laminate 11 obtained by grinding and dividing the wafer W from the support 200. Fig. 5(B) shows a process of attaching the laminate 11 obtained by grinding and dividing the wafer W to a transfer sheet held by a ring frame 300. Fig. 5(C) shows a process of separating the adhesive sheet 1 from the laminate 11 attached to the transfer sheet 303. Fig. 5(D) shows an expansion process of separating individual chips together with the transfer sheet 303.
As shown in Fig. 5(A), the laminate 11 obtained by grinding and dividing the wafer W and separating it from the support 200 is attached to the film-like adhesive 301 of a transfer sheet 303 including a film-like adhesive 301 and a support sheet 302, the periphery of which is held by a ring frame 300, as shown in Fig. 5(B). Then, as shown in Fig. 5(C), the adhesive sheet 1 is separated from the laminate 11 obtained by grinding and dividing the wafer W, and further, as shown in Fig. 5(D), the support sheet 302 is pulled to cut the film-like adhesive 301 to match the chips (the film-like adhesive after cutting is shown by the symbol 301a), leaving gaps G between the chips and separating them into individual chips.
As the transfer sheet 303, for example, a support sheet 302 including a substrate made of the same material as the substrate layer of the adhesive sheet 1 described above, on which a curable film-like adhesive 301 is provided, if necessary via an adhesive layer, can be used.

The above manufacturing method makes it possible to suppress chipping and cracking during the manufacturing process and to produce semiconductor devices with a high yield rate.

In this embodiment, the wafer is divided by SDBG, but this is not limiting, and for example, the wafer may be divided using DBG. When DBG is used, it is easy to prevent chipping or cracking of chips when the distance between chips formed by dicing is small. When DBG is used, the wafer is half-cut from the front surface of the wafer on which the circuit layer is formed, and then an adhesive sheet is attached to the circuit formation surface of the wafer, and then the back surface of the wafer is ground.

Next, specific examples of the present invention will be described, but the present invention is not limited to these examples in any way.
[Examples and Comparative Examples]
The chips of Examples 1 to 3 and Comparative Examples 1 to 4 were fabricated by the following procedure. In Examples 1 to 3 and Comparative Examples 1 to 4, mirror wafers on which no circuit layers were formed were used in order to make the experimental conditions as uniform as possible and to facilitate the experiments.

Example 1
A mirror wafer of single crystal silicon with a diameter of 12 inches was prepared, and an adhesive sheet was attached to one surface of the wafer (hereinafter referred to as the first surface) along the direction indicated by the apex of the V-notch (hereinafter referred to as the vertical direction) based on a V-notch provided on the mirror wafer. The adhesive sheet used was backgrind tape "E-3135KN" manufactured by Lintec Corporation. The adhesive sheet was attached using an attachment device ("RAD-3510F/12" manufactured by Lintec Corporation) under the following conditions: a push-in amount of 15 μm, a protrusion amount of 150 μm, an attachment speed of 5 mm/s, an attachment stress of 0.35 MPa, and an attachment temperature of 23° C.
Next, SDBG was performed so that the length in the vertical direction was 6 mm and the length in the direction perpendicular to the vertical direction (hereinafter referred to as the horizontal direction) was 12 mm. Specifically, a stealth dicing laser saw "DFL7361" manufactured by Disco Corporation was used to irradiate the wafer with a laser from the surface (hereinafter referred to as the second surface) opposite to the first surface of the wafer, to form a modified layer inside the wafer so that 980 regions to be diced, each having a size of 6 mm vertical x 12 mm horizontal, were formed in a matrix.
Furthermore, a back grinding machine ("DPG8760" manufactured by Disco Corporation) was used to grind the other surface of the wafer (hereinafter referred to as the second surface) until the thickness of the wafer was 30 μm, thereby removing the modified layer inside the wafer and splitting the wafer along the planned division lines that defined each planned individual region.
Next, a dicing tape ("D-175" manufactured by Lintec Corporation) installed on a tape mounter "RAD-2700" manufactured by Lintec Corporation was attached to the second surface of the individualized wafer, and the adhesive sheet was removed. Then, the presence or absence of cracks was observed from the first surface side using an IR camera installed on the stealth dicing laser saw, and the number of chips in which cracks occurred was counted.
The number of chips in which a crack occurred was 1 out of 980 chips, and the crack occurrence rate was 0.10%.

Example 2
The wafer was processed by SDBG under the same conditions as in Example 1, except that a wafer with an adhesive sheet attached to its first surface was oriented in the vertical direction to have a vertical length of 4 mm and a horizontal length of 12 mm, and was diced into 1,471 chips.
Observation was carried out in the same manner as in Example 1, and it was found that cracks occurred in 1 out of 1471 chips, giving a crack occurrence rate of 0.07%.

Example 3
The wafer was processed by SDBG under the same conditions as in Example 1, except that the wafer had an adhesive sheet attached to its first surface along the vertical direction and had a vertical length of 8 mm and a horizontal length of 12 mm, and was diced into 735 chips.
Observation was carried out in the same manner as in Example 1, and it was found that cracks occurred in 1 out of 735 chips, giving a crack occurrence rate of 0.13%.

<Comparative Example 1>
The wafer was processed by SDBG under the same conditions as in Example 1, except that a wafer with an adhesive sheet attached to its first surface was oriented in the vertical direction to have a vertical length of 12 mm and a horizontal length of 6 mm, and was diced into 980 chips.
6 is a schematic plan view showing an example of the present invention and a comparative example in comparison. As shown in FIG. 6(A), in the wafer W1 of the examples 1 and 2, the attachment direction d4 of the adhesive sheet 1 and the short side direction d2 of the region R to be singulated are aligned with the direction d3 indicated by the V-notch Wv. On the other hand, as shown in FIG. 6(B), in the wafer W2 of the comparative example 1, the attachment direction d4 of the adhesive sheet and the long side direction d1 of the region R to be singulated are aligned with the direction d3 indicated by the V-notch.
Observation was carried out in the same manner as in Example 1, and it was found that cracks occurred in 11 out of 980 chips, giving a crack occurrence rate of 1.12%.

<Comparative Example 2>
As in Example 1, a wafer having an adhesive sheet attached to its first surface was processed using SDBG under the same conditions as in Example 1, except that the wafer had a vertical length of 12 mm and a horizontal length of 4 mm, and was diced into 1,471 chips.
Observation was carried out in the same manner as in Example 1, and it was found that cracks occurred in 14 out of 1471 chips, giving a crack occurrence rate of 0.95%.

<Comparative Example 3>
As in Example 1, a wafer having an adhesive sheet attached to its first surface was subjected to SDBG processing under the same conditions as in Example 1, except that the wafer had a vertical length of 12 mm and a horizontal length of 12 mm, and was diced into 490 chips.
Observation was carried out in the same manner as in Example 1, and it was found that cracks occurred in 6 out of 490 chips, giving a crack occurrence rate of 1.22%.

<Comparative Example 4>
As in Example 1, a wafer having an adhesive sheet attached to its first surface was processed by SDBG under the same conditions as in Example 1, except that the wafer had a vertical length of 12 mm and a horizontal length of 8 mm, and was diced into 735 chips.
Observation was carried out in the same manner as in Example 1, and it was found that cracks occurred in 9 out of 735 chips, giving a crack occurrence rate of 1.22%.

The results of Examples 1 to 3 and Comparative Examples 1 to 4 are shown in Table 1.

As is clear from the results in Table 1, in Examples 1 to 3, in which the direction of attachment of the adhesive sheet was aligned with the short side direction of the chip, the number of chips that developed cracks was small, and the crack occurrence rate was also very low.
In contrast, the number of chips in which cracks occurred increased in Comparative Examples 1, 2, and 4, in which the direction of attachment of the adhesive sheet was aligned with the direction of the long sides of the chips. In particular, the crack occurrence rate values in Comparative Examples 1 and 2 were more than 10 times higher than in Examples 1 and 2, and Comparative Example 4 was also nearly 10 times higher than in Example 3.
In addition, in comparison example 3, in which the chip shape was a square and the length of one side was equal to the length of the long side of the chips in examples 1 to 3, the number of chips that developed cracks increased, and the crack occurrence rate value increased to more than 10 times that of examples 1 and 2, and nearly 10 times that of example 3.

The method for manufacturing a semiconductor device of the present invention is less likely to cause chipping or cracking of chips even when processing methods such as SDBG are used to divide a wafer so that the distance between chips becomes very small, and can be suitably applied to the manufacture of semiconductor chips used in processors, memories, sensors, etc. Furthermore, the laminate of the present invention can be suitably used in the manufacturing method for the above-mentioned semiconductor device.

1: Adhesive sheet 10: Laminate 11: Laminate 100, 200 with wafer portion ground and divided: Support 101: Pressing body 102: Concentrator 103: Laser 104: Grinder 300: Ring frame 301: Film-like adhesive 301a: Cut film-like adhesive 302: Support sheet 303: Transfer sheet C: Circuit layer CP: Semiconductor chip (semiconductor device)
d1: Long side direction d2: Short side direction d3: Direction indicated by V notch d4: Adhesion direction (tension direction)
E: Planned division line G: Gap M: Modified portion P: Crack R: Planned region for individualization Wv: V-notch W: Wafer WI: Individualized wafer

Claims (6)

A method for manufacturing a semiconductor device having a rectangular planar shape, comprising the steps of:
A pressure-sensitive adhesive sheet is attached to a surface of a wafer including a plurality of rectangular regions to be singulated arranged in a matrix along a short side direction of the regions to be singulated;
After the adhesive sheet is attached to the surface of the wafer, a modified portion serving as a starting point for division is formed inside the wafer at a planar position corresponding to a planned division line that defines the individualized regions ;
a back surface of the wafer to which the adhesive sheet is attached is ground, and the wafer is divided along the planned division lines. A method for manufacturing a semiconductor device having a rectangular planar shape, comprising the steps of:
A pressure-sensitive adhesive sheet is attached to a surface of a wafer including a plurality of rectangular regions to be singulated arranged in a matrix along a short side direction of the regions to be singulated;
grinding the back surface of the wafer to which the adhesive sheet is attached, and dividing the wafer along a division line that defines the individual regions;
A method for manufacturing a semiconductor device, wherein the aspect ratio of the region to be divided into individual pieces, expressed as the length in the long side direction/the length in the short side direction, is 1.05 or more. A method for manufacturing a semiconductor device having a rectangular planar shape, comprising the steps of:
A pressure-sensitive adhesive sheet is attached to a surface of a wafer including a plurality of rectangular regions to be singulated arranged in a matrix along a short side direction of the regions to be singulated;
grinding the back surface of the wafer to which the adhesive sheet is attached, and dividing the wafer along a division line that defines the individual regions;
A method for manufacturing a semiconductor device, wherein the region to be divided has a long side length of 5 to 50 mm and a short side length of 2 to 20 mm. A method for manufacturing a semiconductor device having a rectangular planar shape, comprising the steps of:
A pressure-sensitive adhesive sheet is attached to a surface of a wafer including a plurality of rectangular regions to be singulated arranged in a matrix along a short side direction of the regions to be singulated;
grinding the back surface of the wafer to which the adhesive sheet is attached, and dividing the wafer along a division line that defines the individual regions;
A transfer sheet is attached to the back surface of the wafer after grinding;
the adhesive sheet is separated from the wafer after the transfer sheet is attached. A wafer including a plurality of rectangular regions to be singulated arranged in a matrix;
An adhesive sheet attached to the surface of the wafer in a state where tension is applied along a short side direction of the region to be singulated,
A laminate in which the aspect ratio of the region to be divided, expressed as the length in the long side direction/the length in the short side direction, is 1.05 or more. A wafer including a plurality of rectangular regions to be singulated arranged in a matrix;
An adhesive sheet attached to the surface of the wafer in a state where tension is applied along a short side direction of the region to be singulated,
The laminate, wherein the region to be divided has a long side length of 5 to 50 mm and a short side length of 2 to 20 mm.

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