JP7271057B2 - Chalcogenide memory device components and compositions - Google Patents

Description

The following relates generally to memory devices, and more specifically to the components and chemistries of chalcogenide (chalcogenide glass) memory devices.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices have two states, often represented by a logic '1' or a logic '0'. Other systems may store more than two states. To access the stored information, components of the electronic device can read or sense the memory state of the memory device. To store information, the components of the electronic device can write or program states in the memory device.

Magnetic Hard Disk, Random Access Memory (RAM), Dynamic RAM (DRAM), Synchronous Dynamic RAM (SDRAM), Ferroelectric RAM (FeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Read Only Memory (ROM), There are various types of memory devices such as flash memory, phase change memory (PCM), and others. Memory devices may be volatile or non-volatile. Non-volatile memories, such as FeRAM, can maintain stored logic states for long periods of time even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state over time unless they are periodically refreshed by an external power source. Advances in memory devices include, among other measures, increased memory cell density, increased read/write speed, increased reliability, increased data retention, reduced power consumption, or reduced manufacturing costs.

The chalcogenide material composition can be used in components or elements of PCM devices. These compositions can have a threshold voltage at which they become conductive (ie, they switch on and conduct electricity). The threshold voltage changes over time, sometimes called drift. Compositions that are highly prone to voltage drift can limit the usefulness and performance of devices using these compositions.

1 illustrates an example of one memory array that supports or employs chalcogenide memory device components according to embodiments of the present disclosure. 1 illustrates an example memory array that supports or employs chalcogenide memory device components, according to embodiments of the present disclosure. 4 shows plots of properties of components and compositions of chalcogenide memory devices, according to embodiments of the present disclosure. 4 shows plots of properties of components and compositions of chalcogenide memory devices, according to embodiments of the present disclosure. 1 illustrates a system including a memory array that supports or employs chalcogenide memory device components, according to embodiments of the present disclosure;

The effects of voltage drift in a selector device within a memory cell can be mitigated by introducing stability-enhancing elements into the composition of the selector device. For example, elements from Group III of the Periodic Table (also referred to as the Boron genus and Group 13) can stabilize or limit the voltage drift of the selector device for compositions that do not contain such elements. Group III (or boron group) elements include boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl).

For example, a chalcogenide material composition for a selector device (or other memory element) can include selenium (Se), arsenic (As), and germanium (Ge). This combination or element is sometimes called a SAG. Within memory cells, which can include memory storage elements and selector devices, the chalcogenide compositions or materials can be used for either or both of the storage elements or selector devices. Selector devices can have SAG compositions that can have stable threshold voltages and relatively desirable leakage characteristics. In some cases, silicon (Si) can be introduced into the SAG composition to enhance the thermal stability of selector devices without compromising drift or threshold voltage leakage. However, implementation of Si into SAG systems may not improve drift sufficiently to allow the technology to be scaled.

A higher concentration of Ge in the selector device can raise the threshold voltage and compromise the stability of the selector device. For example, Ge atoms may transition from a pyramidal bonding configuration to a tetrahedral bonding configuration. This transition can help widen the bandgap and increase the threshold voltage of the selector device.

As described herein, Group III elements can be introduced into the chalcogenide material composition to limit the presence of Ge in the selector device. For example, Group III elements can replace some or all of Ge in the composition of the selector device. In some cases, the group III element can form stable tetrahedral bond structures with existing elements (ie, Se, As, and/or Si) of the group III element center. Incorporation of group III elements into the chalcogenide material composition stabilizes the selector device, allowing for increased technology scale and increased cross-point technology development (e.g., three-dimensional cross-point architectures, RAM development, storage development, etc.). , or the like).

The features and techniques introduced above are described later in the description of the memory array. Specific examples are now provided of chalcogenide memory device components and compositions that provide low voltage drift relative to other devices and compositions. These and other features of the disclosure are further illustrated by, and described with reference to, device diagrams, system diagrams, and flow charts associated with reading or writing non-volatile memory cells.

FIG. 1 illustrates an example memory array 100, according to various embodiments of the present disclosure. Memory array 100 may also be referred to as an electronic memory device. Memory array 100 includes memory cells 105 that are programmable to store different states. Each memory cell 105 is programmable to store two states indicated by logic "0" and logic "1". In some cases, memory cell 105 is configured to store more than two logic states. Memory cells 105 can store charges representing programmable states in capacitors, for example, a charged capacitor and an uncharged capacitor can each represent two logic states. DRAM architectures can generally use such designs, and the capacitors employed therein can include dielectric materials with linear or paraelectric electrical polarization properties as insulators. In contrast, a ferroelectric memory cell may include a ferroelectric capacitor as an insulating material. Different levels of charge in the ferroelectric capacitor can represent different logic states. Ferroelectric materials have nonlinear polarization characteristics. Some details and advantages of ferroelectric memory cell 105 are discussed below. Also, in some cases, a chalcogenide base and/or PCM may be employed. The chalcogenides described herein can be used in either or both PCM storage devices or selector devices.

Memory array 100 may be a three-dimensional (3D) memory array in which two-dimensional (2D) memory arrays are formed on top of each other. This can increase the number of memory cells formed on a single die or substrate compared to 2D arrays, which in turn reduces production costs and improves memory array performance. It is possible to do either or both. According to the example shown in FIG. 1, memory array 100 includes two levels of memory cells 105 and can therefore be considered a three-dimensional memory array. However, the number of levels is not limited to two. Each level can be aligned or arranged such that the memory cells 105 can form a memory cell stack 145 and be substantially aligned with each other across each level. Memory array 100 may include compositions of Se, As, Ge, Si, B, Al, Ga, In, or Tl, or combinations of these elements.

Each row of memory cells 105 is connected to an access line 110 and each column of memory cells 105 is connected to a bitline 115 . Access lines 110 may be known as wordlines 110 and bitlines 115 may be known as digitlines 115 . The designations for wordlines, bitlines, etc. are interchangeable without impairing understanding or operation. Wordlines 110 and bitlines 115 may be substantially perpendicular to each other to create an array. Two memory cells 105 in memory cell stack 145 may share a common conductive line, such as digit line 115 . That is, digit line 115 can provide electronic communication between the top electrode of lower memory cell 105 and the bottom electrode of upper memory cell 105 . Other configurations are possible, for example, the third layer may share wordlines 110 with lower layers.

In general, one memory cell 105 may be located at the intersection of two conductive lines, such as wordline 110 and bitline 115 . This intersection may be called the address of the memory cell. The memory cell 105 of interest may be the memory cell 105 located at the intersection of the energized wordline 110 and bitline 115 . That is, wordline 110 and bitline 115 may be energized to read and write memory cell 105 at their intersection. Other memory cells 105 in electronic communication (eg, connected) on the same wordline 110 or bitline 115 may be referred to as non-target memory cells 105 .

As explained above, the electrodes may be coupled to memory cells 105 and wordlines 110 or bitlines 115 . The term electrode may refer to an electrical conductor and, in some cases, may be used as an electrical contact to memory cell 105 . Electrodes can include traces, wires, conductive lines, conductive layers, etc. that provide conductive paths between elements or components of memory array 100 .

Operations such as reading and writing are performed on memory cells 105 by activating or selecting wordlines 110 and bitlines 115, which may involve applying voltages or currents to the respective lines. Wordlines 110 and bitlines 115 may be made of metals (eg, copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti), etc.), metal alloys, carbon, conductively doped It may be of a conductive material, such as a semiconductor or other conductive material, alloy, or compound. When memory cell 105 is selected, the resulting signal can be used to determine the stored logic state. For example, a voltage can be applied and the resulting current can be used to distinguish the resistance states of the phase change material. Cell 105 may be selected when the selector device is biased. The selection of cells 105 can be made a function of the threshold voltage of the selector device, which in turn has a more predictable value when the selector device has a composition comprising group III elements. can be This results in less voltage drift in the selector device of cell 105 when the selector device has a composition containing group III elements than when the selector device has a pure SAG composition or a Si-SAG composition. can be made

Access to memory cells 105 can be controlled via row decoder 120 and column decoder 130 . For example, row decoder 120 may receive a row address from memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, column decoder 130 receives column addresses from memory controller 140 and activates the appropriate bit lines 115 . Thus, memory cell 105 can be accessed by activating word line 110 and bit line 115 .

Upon access, memory cell 105 may be read or sensed by sense component 125 . For example, sense component 125 may be configured to determine the stored logic state of memory cell 105 based on signals generated by accessing memory cell 105 . The signal may include voltage or current, and sense component 125 may include voltage sense amplifiers or current sense amplifiers, or both. For example, a voltage may be applied to memory cell 105 (using corresponding wordline 110 and bitline 115) and the magnitude of the resulting current may depend on the electrical resistance of memory cell 105. be able to. Similarly, a current may be applied to memory cell 105 and the magnitude of the voltage producing that current may depend on the electrical resistance of memory cell 105 . Sense component 125 may include various transistors or amplifiers to detect and amplify signals, sometimes referred to as latching. The detected logic state of memory cell 105 may be output as output 135 . In some cases, sense component 125 may be part of column decoder 130 or row decoder 120 . Alternatively, sense component 125 may be connected to or in electronic communication with column decoder 130 or row decoder 120 .

A memory cell 105 can be set or written to by similarly activating the associated wordline 110 and bitline 115 . For example, a logical value may be stored in memory cell 105 . Column decoder 130 or row decoder 120 can accept data, eg, input/output 135 , to be written to memory cells 105 . In the case of a phase change memory, memory cell 105 is written, for example, by passing a current through the memory element to heat it. This process is described in detail below.

each memory cell 105 having memory elements and selector devices, each selector device comprising a chalcogenide material having a composition of selenium, arsenic, and at least one of B, Al, Ga, In, and Tl; can be done. In some cases, the chalcogenide material composition includes germanium or silicon, or both.

In some memory architectures, accessing a memory cell 105 may degrade or destroy the stored logic state, and a rewrite or update process is performed to restore the original logic state to said memory cell 105. Operations can be performed. For example, in a DRAM, a logic storage capacitor can be partially or completely discharged during a sensing operation, corrupting the stored logic state. Therefore, the logic state can be rewritten after a sensing operation. Furthermore, activating one word line 110 can result in all memory cells in that row being discharged, so all memory cells 105 in that row must be rewritten. there is a possibility. However, non-volatile memories, such as chalcogenide-based or PCM, can prevent accessing memory cell 105 from corrupting the logic state, and thus memory cell 105 does not need to be rewritten after being accessed. be able to.

Some memory architectures, including DRAM, can lose their storage state over time unless they are periodically refreshed by an external power source. For example, a charged capacitor can discharge over time due to leakage currents and lose stored information. The refresh rate of these so-called volatile memory devices can be relatively high, for example ten refresh operations per second for a DRAM, which can result in significant power consumption. As memory arrays grow, increased power consumption can hamper deployment or operation of memory arrays, especially for mobile devices that rely on finite power sources such as batteries (e.g., power supply, heat generation, material limitations). Such). As discussed below, non-volatile chalcogenide-based or PCM cells can have beneficial properties that can improve performance over other memory architectures. For example, chalcogenide-based or PCM can provide similar read/write speeds to DRAM, but are non-volatile and allow for increased cell density.

Memory controller 140 controls the operation (read, write, rewrite, refresh, discharge, etc.) of memory cells 105 through various components, such as row decoder 120, column decoder 130, and sense component 125. be able to. In some cases, one or more of row decoder 120, column decoder 130, and sense component 125 may be collocated with memory controller 140. FIG. The memory controller 140 can generate row and column address signals to activate the desired wordlines 110 and bitlines 115 . Memory controller 140 may also generate and control various potentials or currents used during operation of memory array 100 . For example, it can apply a discharge voltage to wordline 110 or bitline 115 after accessing one or more memory cells 105 .

In general, the amplitude, shape, or duration of the applied voltages or currents described herein can be adjusted or varied for the various operations discussed in operating memory array 100, and can vary. can be made Further, one, multiple, or all memory cells 105 within memory array 100 may be accessed simultaneously. For example, multiple or all cells in memory array 100 may be accessed simultaneously during a reset operation in which all memory cells 105 or a group of memory cells 105 are set to a single logic state. be able to. Because the voltage required to access a cell 105 remains relatively constant over the lifetime of the cell 105, the memory controller 140 will be able to access the cell 105 as the threshold voltage drift of the selector device of each cell 105 decreases. can be made to increase reliability.

FIG. 2 illustrates an example memory array 200 that supports chalcogenide memory device components and compositions, according to various embodiments of the present disclosure. Memory array 200 may be an example of memory array 100 described with reference to FIG.

Memory array 200 includes memory cells 105-a, first access lines 110-a (eg, word lines 110-a), and second access lines 115-a (eg, bit lines 115-a), which are , may be examples of the memory cells 105, word lines 110, and bit lines 115 described with reference to FIG. Memory cell 105-a includes electrode 205, electrode 205-a, and memory element 220, which may be ferroelectric materials. Electrode 205-a of memory cell 105-a may be referred to as intermediate electrode 205-a. Memory array 200 may also include bottom electrode 210 and selector device 215, which may also be referred to as select components. In some cases, multiple memory arrays 200 may be stacked together such that a three-dimensional (3D) memory array is formed. The two stacked arrays may, in some examples, have common conductive lines such that each level may share wordlines 110 or bitlines 115 as described with reference to FIG. . Memory cell 105-a may be the target memory cell.

Memory array 200 is sometimes referred to as a crosspoint architecture. It is also sometimes referred to as a pillar structure. For example, as shown in FIG. 2, a pillar can contact a first conductive line (first access line 110-a) and a second conductive line (second access line 115-a), Here, the pillar comprises a first electrode (bottom electrode 210), a selector device 215, and a ferroelectric memory cell 105-a, which has a second electrode (electrode 205-a ), a memory element 220, and a third electrode (electrode 205). In some cases, electrode 205-a may be referred to as an intermediate electrode. In some cases, the first access line 110-a can be in electronic communication with the second access line 115-a through the memory cell 105-a. A first access line 110-a and a second access line 115-a can be arranged in a three-dimensional cross-point configuration and can be in electronic communication with a plurality of memory cells 105-a.

Such pillar architectures can provide relatively high densities of data storage at low production costs compared to other memory architectures. For example, a crosspoint architecture may have memory cells with reduced area and consequently increased memory cell density compared to other architectures. For example, the architecture may have a memory cell area of 4F ² , where F is the minimum feature size, compared to other architectures having a memory cell area of 6F ² such as with 3-terminal select. For example, DRAMs may use transistors, which are three-terminal devices, as the select component of each memory cell, and may have larger memory cell areas than pillar architectures.

Selector device 215 is, in some cases, between memory cell 105 and a conductive line, for example, memory cell 105-a and at least one of first access line 110-a or second access line 115-a. can be connected in series between them. For example, selector device 215 may be positioned between electrode 205-a and bottom electrode 210, as shown in FIG. Thus, selector device 215 is arranged in series between memory cell 105-a and first access line 110-a. Other configurations are also possible. For example, selector device 215 may be placed in series between memory cell 105-a and second access line 115-a. The select component either helps select a particular memory cell 105-a or prevents stray current from flowing through unselected memory cells 105-a adjacent to the selected memory cell 105-a. can help prevent. For example, the selector device 215 can have a threshold voltage such that current flows through the selector device 215 when the threshold voltage is met or exceeded.

Selector device 215 may be coupled with memory element 220 . Selector device 215 and memory element 220 are connected to first access line 110-a and second access line 115-a.
-a in a serial configuration. Selector device 215 can include a first chalcogenide material of a composition including Se, As, and at least one of B, Al, Ga, In, and Tl. In some cases, selector device 215 may comprise a first chalcogenide material and memory element 220 may comprise a different composition than selector device 215 (eg, a second chalcogenide material). . However, although not shown, in some cases cell 105 may not use separate memory elements and selector devices. This type of memory architecture can be called a self-selecting memory (SSM), and selector device 215 can function as a memory storage element. Thus, a memory device may include memory cells with self-selecting memory devices. For example, a single element comprising chalcogenide material can function as both a memory element and a selector device such that a separate selector device is not required . In some cases, memory element 220 may comprise a ferroelectric capacitor or memristor rather than a phase change material.

Selector device 215 may be separated from memory element 220 by intermediate electrode 205-a. As such, intermediate electrode 205-a may be electrically floating, i.e., not directly connected to electrical ground or a component that may be electrically grounded, and thus charge may accumulate. . Memory element 220 may be accessed via selector device 215 . For example, when the voltage across selector device 215 reaches a threshold, current may flow through memory element 220 between access lines 110-a and 115-a. This current flow can be used to read the logic value stored in memory element 220 . The threshold voltage across selector device 215 at which current begins to flow can be a function of the composition of selector device 215 . Similarly, the composition of selector device 215 can affect whether and how much the threshold voltage of selector device 215 can change over time.

As described herein, changes in threshold voltage over time are sometimes referred to as threshold voltage drift. Threshold voltage drift may be undesirable as the threshold voltage of the selector device changes, and operation (eg, application of the voltage required to drive current through the selector device) may change. This can complicate reading or writing the device, can lead to inaccurate reading or writing, can cause an increase in the power required to read or write the memory element, and so on. be. As described herein, employing a material composition that limits the likelihood or degree of threshold voltage drift for selector device 215 can help improve device performance. As such, the selector device 215 can comprise a composition that includes one or more Group III elements that can limit threshold voltage drift as described below.

Memory array 200 can be fabricated by various combinations of material formation and removal. For example, material layers corresponding to first access line 110-a, bottom electrode 210, selector device 215, electrode 205-a, memory element 220, and electrode 205 may be deposited. Material can then be selectively removed to create desired features, such as the pillar structure shown in FIG. For example, features can be defined by patterning photoresist using photolithographic techniques, and material can then be removed by techniques such as etching. A second access line 115-a may then be formed, for example, by depositing and selectively etching a layer of material to form the line structure shown in FIG. In some cases, electrically insulating regions or layers may be formed or deposited. The electrically isolated regions may include oxide or nitride materials such as silicon oxide, silicon nitride, or other electrically insulating materials.

Various techniques may be used to form the materials or compositions of memory array 200 . These are, for example, chemical vapor deposition (CVD), metalorganic vapor deposition (MOCVD), physical vapor deposition (PVD), sputter deposition, atomic layer deposition, among other thin film growth techniques. (ALD), molecular beam epitaxy (MBE). The material is caused to be removed using a number of techniques, which can include, for example, chemical etching (also called "wet etching"), plasma etching (also called "dry etching"), or chemical-mechanical planarization. be able to.

FIG. 3 shows a plot 300 of chalcogenide memory device component and composition properties, according to an embodiment of the present disclosure. As described herein, FIG. 3 shows a comparison of chalcogenide material compositions, including compositions containing Group III elements. FIG. 3 thus illustrates the relatively low voltage drift of a composition consisting of Se, As, and group III elements, depicted as composition 3 (Comp.3).

For example, Composition 3 should be about 53 wt% Se, about 23 wt% As, about 13 wt% Ge, and about 11 wt% In, based on the total weight of the composition. can be done. Composition 3 at point 305 can have a voltage drift of less than 250 millivolts after 3 days at 90 degrees Celsius.

The voltage drift of composition 3 can result in less total voltage drift over a period of time, which can allow for improved performance of the selector device. Thus, the addition of In (or other Group III elements) to chalcogenide compositions can minimize voltage drift compared to other chalcogenide material compositions. For example, compositions 1 and 2 may be pure SAG compositions (ie containing only Se, As, Ge). Compositions 4 and 5 may be pure Si—SAG alloys (ie containing only Se, As, Ge, Si). In some examples, compositions 4 and 5 can have amounts of about 30 wt% As, about 12 wt% Ge, and about 8 wt% Si, based on the total weight of the composition. . In some cases, the chalcogenide material compositions (i.e., composition 1 at point 310, composition 2 at point 315, composition 4 at point 320, composition 5 at point 325) were reduced after 3 days at 90 degrees Celsius. , can drift by more than 500 millivolts.

As described herein, the addition of In (or other Group III elements) into the chalcogenide mixture can enhance the stability of selector devices. A chalcogenide material composition (eg Composition 3) can yield the results shown in Table 1.

As shown in Table 1, the column headings Vth_FF and Vth_SF are read at the first activation (i.e., "first firing") and subsequent activation (i.e., "second firing") of the selector device having composition 3. , can be respectively expressed as: The column heading Vform may represent the threshold voltage difference between the first and second firings. In some examples, the column heading Vth_1000 may represent the threshold voltage after 1000 cycles. The column heading [email protected] Vt may represent the sub-threshold voltage leakage current in the selector device. The column heading STDrift may represent the drift of the selector device. As shown in Table 1 , chalcogenide compositions containing In or another Group III element (e.g. Composition 3) can result in stable threshold voltages during cycling and low drift over time. .

FIG. 4 shows a plot 400 of chalcogenide memory device component and composition properties, according to an embodiment of the present disclosure. For example, region 405 shows compositions of Se, As, and Ge that may be doped with group III elements. Dotted line 410 indicates the As ₂ Se ₃ -GeSe ₂ compositional line. As described herein, compositions with low voltage drift can be useful in selector devices or other memory elements, where Se, As, Ge, Si, or some of the Group III elements Can contain combinations. The chalcogenide _material composition can be reduced to _the general formula _{SexAsyGezSiwXu} , _where X is one of _the Group III elements. For example, a chalcogenide material composition can be reduced to the formula Se ₄ As ₂ GeSiIn, with In as one of the Group III elements. In another example, the chalcogenide material composition can be reduced to the general formula Se ₃ As ₂ GeSi ₂ B, with B being one of the Group III elements. The chalcogenide material composition may consist of the compositions shown in Table 2, which may provide compositional ranges by weight percentages of Se, As, Ge, Si, and Group III elements.

In some cases, Se may amount to 40% or more by weight relative to the total weight of the composition. In some cases, the amount of Se may be 45% or more by weight relative to the total weight of the composition. Arsenic may be present in an amount ranging from 10% to 35% by weight relative to the total weight of the composition. In some cases, the amount of As ranges from 12% to 32% by weight relative to the total weight of the composition. In some examples, Ge may be in an amount ranging from 1 wt% to 20 wt% based on the total weight of the composition.

In some examples, Si may be present in an amount ranging from 1% to 15% by weight based on the total weight of the composition. The combination of Si, Ge, and at least one element selected from the group consisting of B, Al, Ga, In, and Tl can be in an amount of 20% or more by weight relative to the total weight of the composition. .

The Group III element may be at least one element selected from the group consisting of B, Al, Ga, In, and Tl, and comprises 0.15% to 35% by weight of the total weight of the composition. There may be a range of amounts. In some cases, the Group III element may be at least one element selected from the group consisting of B, Al, Ga, In, and Tl , and the total weight of the composition is 0.15 % to 24% by weight.

The chalcogenide material compositions of Table 2 can be made to have a threshold voltage drift of 250 millivolts or less after 3 days at 90 degrees Celsius. In some examples, the chalcogenide material compositions of Table 2 may have a glass transition temperature greater than 280 degrees Celsius. Glass transition temperature and glass processing conditions can influence composition selection within the ranges given by Table 2.

As described herein, the Group III elements are incorporated into the composition of materials such as Se and As , or SAG , or Si-SAG compositions to produce pure SAG or Si-SAG compositions. Various problems associated with selector devices with objects can be mitigated. In some cases too little Ge can compromise the thermal stability of the chalcogenide material composition. On the other hand, SAG systems with Ge compositions above 15% may be too thermally unstable and absorbed into the crosspoint array. In some instances, a high composition of Se may result in a high bandgap energy that may sustain a trade-off between high threshold voltage and leakage.

As mentioned above, Group III elements can enhance the stability of selector devices through the formation of strong and stable bonds. In some instances, group III elements form tetrahedral bonds that may not reduce drift. Low voltage drift may be directly related to the coupling structure, as shown in FIG. For example, the Al—Se bond dissociation energy may be 318 kJ · mol ⁻¹ and the In—Se bond dissociation energy may be 245 kJ · mol ⁻¹ . Higher bond dissociation energies can be correlated with stronger and more stable bonds.

Group III elements can also provide increased thermal stability in selector devices. For example, Al ₂ Se ₃ can have a bandgap energy of 3.1 eV and In ₂ Se ₃ can have a bandgap energy of 2.1 eV. A wide bandgap can increase the threshold voltage over time and cause the selector device to operate at high temperatures. For example, _Al2Se3 can have a melting temperature of 1220K and _In2Se3 can have a melting temperature _{of 933K} . A high melting temperature can increase the thermal stability of the selector device. In some instances, the transition temperature of the chalcogenide material composition may also be increased.

As described herein, adding group III elements to the chalcogenide material composition in selector devices can provide additional benefits. For example, the introduction of B into the selector device can serve as an insulator. Therefore, a selector device with a B-SAG system can prevent leakage problems. In some instances, the introduction of Al may facilitate absorption into the crosspoint array. In another example, the introduction of In can minimize voltage drift. The introduction of group III elements (eg B, Al, Ga, In, Tl) into the chalcogenide material composition can increase the stability of the selector device.

FIG. 5 illustrates a system 500 including a memory array that supports or employs chalcogenide memory device components, according to an embodiment of the present disclosure. System 500 may include device 505, which is or includes a printed circuit board that connects or physically supports various components. Device 505 may include memory array 100-a, which may be an example of memory array 100 described in FIG. Memory array 100-a can include memory controller 140-a and memory cells 105-b, which are described with reference to memory controller 140 described with reference to FIG. 1 and FIGS. It may be an example of memory cell 105 .

Memory array 100-a may include a plurality of memory cells 105-a each having a memory element and a selector device, each selector device comprising at least one of boron , aluminum, gallium, indium, or thallium. Alternatively, a chalcogenide material having a composition of selenium and arsenic can be included. In some examples, the chalcogenide material composition includes germanium or silicon, or both. In some cases, the chalcogenide material composition includes a combination of at least one of boron , aluminum, gallium, indium, or thallium, silicon, and germanium, based on the total weight of the composition. It is contained in an amount of 20% by weight or more. Memory array 100-a may also include a plurality of access lines arranged in a three-dimensional cross-point configuration and arranged in electronic communication with a plurality of memory cells 105-a.

Device 505 may also include processor 510 , BIOS component 515 , peripheral components 520 , and input/output control component 525 . The components of device 505 can be in electronic communication with each other via bus 530 .

Processor 510 may be configured to operate memory array 100-a via memory controller 140-a. In some cases, processor 510 performs the functions of memory controller 140 described with reference to FIG. In other cases, memory controller 140 - a may be integrated into processor 510 . Processor 510 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. , or it may be a combination of these types of components, and processor 510 may perform various functions described herein. Processor 510, for example, may be configured to execute computer readable instructions stored in memory array 100-a, causing device 505 to perform various functions and tasks.

BIOS component 515 may be a software component that includes a basic input/output system (BIOS) that operates as firmware and is capable of initializing and running various hardware components of system 500 . BIOS component 515 can also manage data flow between processor 510 and various components such as, for example, peripheral components 520 and input/output control component 525 . BIOS component 515 may include programs or software stored in read-only memory (ROM), flash memory, or other non-volatile memory.

Peripheral component(s) 520 may be any input/output device integrated with device 505 or an interface for such a device. Examples include disk controllers, sound controllers, graphics controllers, Ethernet controllers, modems, universal serial bus (USB) controllers, serial or parallel ports, or peripheral component interconnect (PCI) slots or accelerated graphics ports (AGP). ) slots may include peripheral card slots.

Input/output control component 525 can manage data communication between processor 510 and peripheral components 520, input 535 devices, or output 540 devices. Input/output control component 525 can also manage peripherals that are not integrated with device 505 . In some cases, input/output control components 525 may represent physical connections or ports to external peripherals.

Inputs 535 may represent devices or signals external to device 505 that provide inputs to device 505 or components thereof. This may include user interfaces or interfaces between other devices. In some cases, input 535 may be a peripheral interfaced with device 505 via peripheral component 520 or managed by input/output control component 525 .

Output 540 may represent a device or signal external to device 505 configured to receive an output from device 505 or any of its components. Examples of output 540 can include data or signals sent to a display, audio speakers, a printing device, another processor or printed circuit board, or the like. In some cases, output 540 may be a peripheral interfaced with device 505 via peripheral component 520 or managed by input/output control component 525 .

Memory controller 140-a, device 505, and memory array 100-a components may be comprised of circuitry designed to perform their functions. This includes various devices configured to perform the functions described herein, such as, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements. It can include circuit elements.

The descriptions herein are examples and do not limit the scope, applicability, or examples set forth in the claims. Changes may be made in the function and combination of elements discussed without departing from the scope of the disclosure. Various embodiments may omit, substitute, or add various procedures or components as desired. Also, features described with respect to some embodiments may be combined in other embodiments.

The description herein, in conjunction with the accompanying drawings, presents example configurations and is not intended to represent all possible implementations or all implementations falling within the scope of the claims. As used herein, the terms "example," "exemplary," and "embodiment" mean "serving as an example, instance, or illustration," and are "preferred" or "advanced over other examples." No. The detailed description includes specific details for the purpose of providing an understanding of the technology represented. These techniques may, however, be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described embodiments.

In the accompanying figures, similar components or features may have the same reference label. Further, various components of the same type are differentiated by following the reference label with a distinguishing dash and a second level among similar components. Where a first reference label is used in the specification, the discussion applies to any similar component with the same first reference label regardless of the second reference label.

As used herein, "coupled" refers to components that are in substantial contact with each other. In some cases, two components may be bonded even though a third material or component is physically separated. This third component cannot substantially change the two components or their function. Alternatively, this third component can help or enable the connection of the first two components. For example, some materials may not adhere well when deposited on the substrate material. A thin layer (eg, on the order of a few nanometers or less), such as a lamina layer, may be used between two materials to enhance their formation or connection. In other cases, the third material can act as a buffer to chemically separate the two components.

As used herein, the term "layer" refers to a geometric structure stratum or sheet. Each layer has three dimensions (eg, height, width, and depth) and can cover some or all of the surface. For example, a layer may be a three-dimensional structure in which two dimensions are greater than the third dimension, eg, a thin film. Layers can include various elements, constituents, and/or materials. In some cases, a layer may consist of more than one sublayer. In some of the accompanying drawings, two dimensions of a three-dimensional layer are depicted for purposes of illustration. However, those skilled in the art will recognize that layers are three-dimensional in nature.

As used herein, the term "substantially" means that the modified property (e.g., a verb or adjective substantially modified by the term) need not be absolute, but Means close enough.

As used herein, the term "electrode" may refer to an electrical conductor, which in some cases may be used as an electrical contact to a memory cell or other component of a memory array. Electrodes may include traces, wires, conductive lines, conductive layers, or the like that provide conductive paths between elements or components of memory array 100 .

As used herein, the term "photolithography" can refer to the process of patterning with a photoresist material and exposing such material using electromagnetic waves. For example, a photoresist material may be formed on a substrate, such as by spin-coating the photoresist onto the substrate. A pattern can be created in the photoresist by exposing the photoresist to radiation. The pattern can be defined, for example, by a photomask that spatially maps where the radiation exposes the photoresist. The exposed photoresist areas can be removed, for example by chemical treatment, leaving the desired pattern. In some cases, the exposed areas can remain and the unexposed areas can be removed.

Information and signals in this specification may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may refer to voltages, currents, electromagnetic waves, magnetic fields or particles, light wave fields or photons, or any of them. is represented by a combination of Some drawings show groups of signals as one signal. However, those skilled in the art will appreciate that it may represent a bus that can have various bit widths of signal groups.

The term "electronic communication" refers to relationships between components that support the flow of electrons between the components. This may involve direct connections between components, or it may involve intermediate components. Electronic communication components can actively exchange electrons or signals (e.g., in powered circuits) or cannot actively exchange electrons or signals (e.g., in non-powered circuits), but can It may be configured and operable to exchange electrons or signals. As an example, two components physically connected via a switch (eg, a transistor) are in electronic communication regardless of the state of the switch (ie, open or closed).

The devices described herein, including memory array 100, can be formed on semiconductor substrates such as silicon (Si), germanium, silicon-germanium alloys, gallium arsenide (GaAs), gallium nitride (GaN), and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on- glass ( SOG) or silicon -on - sapphire ( SOP). or an epitaxial layer of semiconductor material formed on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled through doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed by ion implantation or other doping means during initial formation or growth of the substrate. A portion or slice of a substrate that contains a memory array or circuit may be referred to as a die.

The chalcogenide material may be a material or alloy containing at least one of the elements S, Se and Te. The phase change materials discussed herein may be chalcogenide materials. Chalcogenide materials include S, Se, Te, Ge, As, Al, Sb, Au, Indium (In), Gallium (Ga), Tin (Sn), Bismuth (Bi), Palladium (Pd), Cobalt (Co), Alloys of oxygen (O), silver (Ag), nickel (Ni), platinum (Pt) may be included. Examples of chalcogenide materials and alloys include, but are not limited to, Ge--Te, In--Se, Sb--Te, Ga--Sb, In--Sb, As--Te, Al--Te, Ge--Sb--Te , Te—Ge—As, In—Sb—Te, Te—Sn—Se, Ge—Se—Ga, Bi—Se—Sb, Ga—Se—Te, Sn—Sb—Te, In—Sb—Ge, Te -Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb -Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn -Pd, or Ge-Te-Sn-Pt.

Hyphenated chemical composition designations used herein indicate elements contained in a particular compound or alloy and represent all stoichiometry contained in the indicated element. For example, Ge—Te can include Ge _x Te _y , where x and y can be any positive integers. Other examples of variable resistance materials can include binary metal oxide materials or mixed valence oxides containing two or more metals, such as transition metals, alkaline earth metals, and/or rare earth metals. can. Embodiments are not limited to a particular variable resistance material or materials associated with the memory elements of the memory cells. For example, other examples of variable resistance materials can be used to form memory elements and can include chalcogenide materials, giant magnetoresistive materials, or polymer-based materials, among others.

The transistors described herein represent field effect transistors (FETs) and consist of a three-terminal device including a source, a drain, and a gate. The terminals can be connected to other electronic devices via conductive materials such as metals. The source and drain are conductive and can include semiconducting regions that are highly doped, eg, degenerate. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (ie, the carriers are mostly electrons), the FET can be called an n-type FET. Similarly, if the channel is p-type (ie, the majority of carriers are holes), the FET can be called a p-type FET. The channel can be covered by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. A transistor can be "on" or "active" when a voltage equal to or greater than the threshold voltage of the transistor is applied to the transistor gate. A transistor can be "off" or "inactive" when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

Various exemplary blocks, components, and modules described in connection with this disclosure may be general purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, discrete gate or transistor logic, discrete hardware components , or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but, in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. Also, a processor may be implemented as a combination of computing devices (e.g., a combination DSP and microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration). You can also

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. When implemented in software executed by a processor, the functions can be stored on or transferred as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired connections, or software executed by any combination thereof. Implementations of functionality may also be physically located at various locations, including being arranged such that each portion of functionality is implemented at different physical locations. Also, as used herein, used in a list of items (e.g., a list of items beginning with a phrase such as "at least one" or "one or more") as included in a claim. "or" may be used in any combination, such that, for example, at least one list of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C) points to a list containing

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk A memory device or other magnetic storage device or other device usable for carrying or storing desired program code means in the form of instructions or data structures and accessible by a general purpose or special purpose computer or processor. Any other non-transitory medium can be included.

Also, any connection is properly termed a computer-readable medium. For example, using coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave to transmit software from a website, server, or other remote source; If so, coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy discs, and Blu-ray discs. Disks typically reproduce data magnetically. Also, a disc reproduces data optically with a laser. Combinations of the above are also included within the scope of computer-readable media.

This specification is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein. be.

Claims (16)

A composition of matter comprising:
selenium in an amount of 40% or more by weight relative to the total weight of the composition;
arsenic in an amount ranging from 10% to 35% by weight relative to the total weight of the composition;
thallium in an amount ranging from 0.15% to 35% by weight relative to the total weight of the composition;
germanium and
Silicon and
including
A composition wherein said thallium, said germanium and said silicon, taken together, are in an amount of 20% or more by weight relative to said total weight of said composition. 2. The composition of claim 1, wherein said germanium is in an amount ranging from 1% to 20% by weight relative to said total weight of said composition. 2. The composition of claim 1, wherein said silicon is in an amount ranging from 1% to 15% by weight relative to said total weight of said composition. 2. The composition of claim 1, wherein the amount of selenium is 45% or more by weight relative to the total weight of the composition. 2. The composition of claim 1, wherein the amount of arsenic ranges from 12% to 32% by weight relative to the total weight of the composition. 2. The composition of claim 1, wherein said thallium is in an amount ranging from 0.15% to 24% by weight relative to said total weight of said composition. 2. The composition of claim 1, wherein the composition has a threshold voltage drift of no greater than 250 millivolts after 3 days at a temperature of 90 degrees Celsius. 2. The composition of claim 1, wherein said composition has a glass transition temperature above 280 degrees Celsius. a memory element;
a selector device coupled to the memory element;
An apparatus comprising:
The selector device has a composition, the composition comprising:
selenium in an amount of 40% or more by weight relative to the total weight of the composition;
arsenic in an amount ranging from 10% to 35% by weight relative to the total weight of the composition;
thallium in an amount ranging from 0.15% to 35% by weight relative to the total weight of the composition;
germanium and
Silicon and
including
The device wherein said thallium, said germanium, and said silicon, taken together, are in an amount of 20% or more by weight relative to said total weight of said composition. 10. The apparatus of claim 9, wherein said composition of said selector device comprises said germanium in an amount ranging from 1% to 20% by weight relative to said total weight of said composition. 10. The apparatus of claim 9, wherein said composition of said selector device comprises said silicon in an amount ranging from 1% to 15% by weight relative to said total weight of said composition. a first access line;
a second access line;
a memory cell comprising a first chalcogenide material comprising a composition of thallium, selenium and arsenic;
including
The apparatus of claim 1, wherein said first access line is in electronic communication with said second access line through said memory cell, said memory cell comprising a self-selected storage element. The composition of the first chalcogenide material comprises:
said selenium in an amount of 40% or more by weight relative to the total weight of said composition;
said arsenic in an amount ranging from 10% to 35% by weight relative to said total weight of said composition;
said thallium in an amount ranging from 0.15% to 35% by weight relative to said total weight of said composition;
13. The device of claim 12, comprising: The composition of the first chalcogenide material comprises:
14. The device of claim 13, comprising germanium in an amount ranging from 1% to 20% by weight relative to the total weight of the composition. The composition of the first chalcogenide material comprises:
14. The device of claim 13, comprising silicon in an amount ranging from 1% to 15% by weight relative to the total weight of the composition. A plurality of memory cells each having a memory element and a selector device, each selector device comprising a chalcogenide material having a composition comprising thallium, selenium, arsenic, germanium, and silicon a cell;
a plurality of access lines in electronic communication with the plurality of memory cells, the plurality of access lines being in a first plane and perpendicular to the first plane ; and a plurality of second access lines in a second plane at different positions in the plane, wherein the plurality of first access lines extend in a direction that intersects the plurality of second access lines. , a plurality of access lines, wherein one of the plurality of memory cells is located at each intersection of the plurality of first access lines and the plurality of second access lines;
An apparatus comprising:
The device, wherein the combination of said thallium, said germanium and said silicon together is in an amount of 20% or more by weight relative to the total weight of said composition.

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