JP6926261B2 - Semiconductor devices and their manufacturing methods - Google Patents

Description

An embodiment of the present invention relates to a semiconductor device and a method for manufacturing the same.

There is a high withstand voltage semiconductor device using silicon carbide (SiC). It is desired to reduce the on-resistance in semiconductor devices.

JP-A-2009-260253

An embodiment of the present invention provides a semiconductor device capable of reducing on-resistance and a method for manufacturing the same.

According to the embodiment of the present invention, the semiconductor device includes the first to fourth semiconductor regions, the first and second electrodes, and the first insulating film. The first semiconductor region includes a first partial region, a second partial region, and an intermediate partial region located between the first partial region and the second partial region, and is a first conductive type. The first electrode is separated from the first partial region in the first direction intersecting the direction from the second partial region toward the first partial region. The second electrode includes a first conductive region separated from the second partial region in the first direction, and a second conductive region separated from the intermediate partial region in the first direction. The second semiconductor region is provided between the intermediate portion region and a part of the second conductive region in the first direction, and the first conductive region and the second conductive region intersect with the first direction. It is the first conductive type provided between the first electrode and electrically connected to the second electrode. The third semiconductor region is provided between the intermediate portion region and another part of the second conductive region in the first direction, and the first conductive region and the second semiconductor region in the second direction. It is provided between the two electrodes and electrically connected to the second electrode, and is of the second conductive type. The fourth semiconductor region includes a third partial region and a fourth partial region, and is the second conductive type. The third partial region is provided between the second partial region and the first conductive region in the first direction. A part of the intermediate partial region is located between the third partial region and the first electrode. The fourth partial region is provided between the intermediate partial region and the second semiconductor region in the first direction, and between the intermediate partial region and the third semiconductor region in the first direction. The fourth partial region is located between the first conductive region and the first electrode in the second direction, and the fourth partial region is continuous with the third partial region. The first insulating film is formed between the first partial region and the first electrode in the first direction, between the fourth partial region and the first electrode in the second direction, and the second electrode. It is provided between the second semiconductor region and the first electrode in the direction.

It is a schematic cross-sectional view which illustrates the semiconductor device which concerns on 1st Embodiment. It is a graph which illustrates the characteristic of the semiconductor device which concerns on 1st Embodiment. It is a graph which illustrates the characteristic of the semiconductor device of 1st reference example. It is a graph which illustrates the characteristic of a semiconductor device. 5 (a) to 5 (f) are process-order schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. It is a schematic cross-sectional view which illustrates another semiconductor device which concerns on 1st Embodiment. It is a schematic cross-sectional view which illustrates another semiconductor device which concerns on 1st Embodiment. It is a schematic cross-sectional view which illustrates another semiconductor device which concerns on 1st Embodiment. It is a flowchart which illustrates the manufacturing method of the semiconductor device which concerns on 2nd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between the parts, etc. are not always the same as the actual ones. Even if the same part is represented, the dimensions and ratios of each may be represented differently depending on the drawing.
In the specification of the present application and each of the drawings, the same elements as those described above with respect to the above-described drawings are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.

(First Embodiment)
FIG. 1 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.
As shown in FIG. 1, the semiconductor device 110 according to the present embodiment has a first semiconductor region 10, a second semiconductor region 20, a third semiconductor region 30, a fourth semiconductor region 40, a first electrode 71, and a second electrode 72. And the first insulating film 75. The semiconductor device 110 is, for example, a MOS (Metal-Oxide-Semiconductor) transistor.

The first semiconductor region 10, the second semiconductor region 20, the third semiconductor region 30, and the fourth semiconductor region 40 include, for example, silicon carbide (SiC). These semiconductor regions may further contain impurities.

The first semiconductor region 10 includes a first partial region p1, a second partial region p2, and an intermediate partial region pi. The intermediate partial region pi is located between the first partial region p1 and the second partial region p2. The boundaries between these subregions may be unclear. The first semiconductor region 10 is a first conductive type.

The first conductive type is, for example, the n type. At this time, the second conductive type described later is a p type. In the embodiment, the first conductive type may be a p-type and the second conductive type may be an n-type. In the example described below, the first conductive type is the n-type and the second conductive type is the p-type.

For example, the first semiconductor region 10 is an n-layer.

The first electrode 71 is separated from the first partial region p1 in the first direction.

The first direction is the Z-axis direction. One direction perpendicular to the Z-axis direction is defined as the X-axis direction. The direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction.

The first direction (Z-axis direction) intersects the direction from the second partial region p2 to the first partial region p1.

The first electrode 71 functions as, for example, a gate electrode of the semiconductor device 110.

The second electrode 72 includes a first conductive region 72a and a second conductive region 72b. The first conductive region 72a is separated from the second partial region p2 in the first direction (Z-axis direction). The second conductive region 72b is separated from the intermediate partial region pi in the first direction. The boundaries between these conductive regions may be unclear. The second electrode 72 functions as, for example, a source electrode of the semiconductor device 110.

The second conductive region 72b of the second electrode 72 may include, for example, a portion 72p and a portion 72q.

In this example, a plurality of first conductive regions 72a are arranged in the X-axis direction. A first electrode 71 is provided between the two first conductive regions 72a. The first conductive region 72a and the first electrode 71 may be arranged alternately. When a plurality of first conductive regions 72a are arranged along the X-axis direction, attention is paid to the two closest first conductive regions 72a. The distance between the center of the two first conductive regions 72a in one X-axis direction and the center of the two first conductive regions 72a in another X-axis direction corresponds to the cell pitch Pc. When a plurality of first electrodes 71 are arranged along the X-axis direction, attention is paid to the two closest first electrodes 71. The distance between the center of the two first electrodes 71 in one X-axis direction and the center of the two first electrodes 71 in another X-axis direction corresponds to the cell pitch Pc.

The second semiconductor region 20 is provided between the intermediate partial region pi and a part of the second conductive region 72b (part 72p) in the first direction (Z-axis direction). The second semiconductor region 20 is provided between the first conductive region 72a and the first electrode 71 in the second direction. The second direction is, for example, the X-axis direction. The second semiconductor region 20 is electrically connected to the second electrode 72. The second semiconductor region 20 is a first conductive type (n type in this example). The second semiconductor region 20 is, for example, an n ⁺ layer.

The third semiconductor region 30 is provided between the intermediate partial region pi and another part (part 72q) of the second conductive region in the first direction (Z-axis direction). The third semiconductor region 30 is provided between the first conductive region 72a and at least a part of the second semiconductor region 20 in the second direction (X-axis direction). In this example, the entire third semiconductor region 30 is provided between the first conductive region 72a and the second semiconductor region 20 in the second direction (X-axis direction). The third semiconductor region 30 is electrically connected to the second electrode 72. The third semiconductor region 30 is a second conductive type (p type in this example). The third semiconductor region 30 is, for example, a p ⁺ layer.

The fourth semiconductor region 40 includes a third partial region p3 and a fourth partial region p4. The third partial region p3 is provided between the second partial region p2 and the first conductive region 72a in the first direction (Z-axis direction). In the second direction (X-axis direction), a part of the intermediate partial region pi is located between the third partial region p3 and the first electrode 71.

The fourth partial region p4 is between the intermediate partial region pi and the second semiconductor region 20 in the first direction (Z-axis direction) and between the intermediate partial region pi and the third semiconductor region 30 in the first direction. Provided. The fourth partial region p4 is located between the first conductive region 72a and the first electrode 71 in the second direction (X-axis direction). At least a portion of the third partial region p3 overlaps the fourth partial region p4 in the second direction. The fourth partial region p4 is continuous with the third partial region p3. The boundary between the third subregion p3 and the fourth subregion p4 may be unclear. The fourth semiconductor region 40 is a second conductive type (p type in this example).

The first insulating film 75 is between the first partial region p1 and the first electrode 71 in the first direction (Z-axis direction), and between the fourth partial region p4 and the first electrode 71 in the second direction (X-axis direction). It is provided between the second semiconductor region 20 and the first electrode 71 in the second direction (X-axis direction). The first insulating film 75 is provided between a part of the intermediate partial region pi and the first electrode 71 in the second direction. The first insulating film 75 functions as, for example, a gate insulating film.

The first insulating film 75 insulates between the first semiconductor region 10 and the first electrode 71. The first insulating film 75 insulates between the fourth semiconductor region 40 (fourth partial region p4) and the first electrode 71. The first insulating film 75 insulates between the second semiconductor region 20 and the first electrode 71.

In this example, the semiconductor device 110 further includes a second insulating film 76. At least a part of the second insulating film 76 is located between a part of the second electrode 72 and the first electrode 71 in the first direction (Z-axis direction). The second insulating film 76 insulates between the first electrode 71 and the second electrode 72.

In this example, a part of the second electrode 72 has a portion (part 72 g) that overlaps with the first electrode 71 in the first direction. At least a part of the second insulating film 76 is provided between the overlapping portion 72 g and the first electrode 71.

A part of the second insulating film 76 is located between the second conductive region 72b and the second semiconductor region 20 in the first direction (Z-axis direction).

In this example, the semiconductor device 110 further includes a third electrode 73. The third electrode 73 is electrically connected to the first semiconductor region 10. In the first direction (Z-axis direction), the second partial region p2 of the first semiconductor region 10 is provided between the third electrode 73 and the third partial region p3. In the Z-axis direction, the intermediate partial region pi of the first semiconductor region 10 is provided between the third electrode 73 and the fourth partial region p4. In the Z-axis direction, the first partial region p1 of the first semiconductor region 10 is provided between the third electrode 73 and the first electrode 71. The third electrode 73 functions as, for example, a drain electrode.

In this example, a semiconductor substrate 10S (for example, a SiC substrate) is provided between the first semiconductor region 10 and the third electrode 73.

As described above, the third semiconductor region 30 (for example, the p ⁺ layer) is electrically connected to the second electrode 72. The third semiconductor region 30 is a contact region. As will be described later, the third semiconductor region 30 is formed by a method such as ion implantation. In this case, the third semiconductor region 30 may contain many defects. When a high electric field is applied to such a third semiconductor region 30, the leakage current becomes large.

In the embodiment, the third semiconductor region 30 is aligned with the second semiconductor region 20 in the X-axis direction. The height of the third semiconductor region 30 (position in the Z-axis direction) is separated from the height of the bottom Bp3 (lower end) of the third partial region p3 of the fourth semiconductor region 40. Therefore, the electric field applied to the third semiconductor region 30 is low.

On the other hand, a ^{first reference example in which the contact region (p +} layer) is provided directly below the first conductive region 72a of the second electrode 72 can be considered. In the first reference example, in the first direction (Z-axis direction), between the first conductive region 72a of the second electrode 72 and the third partial region p3 of the fourth semiconductor region 40 (p layer), A contact area (p ⁺ layer) is provided. In such a first reference example, ^{the distance (length along the Z-axis direction) between the contact region (p +} layer) and the bottom Bp3 of the third partial region p3 of the fourth semiconductor region 40 is short.

On the other hand, in the embodiment, the third semiconductor region 30 (for example, the p ⁺ layer and the contact region) is provided at the same height as the second semiconductor region 20. Therefore, the distance between the third semiconductor region 30 and the bottom Bp3 of the third partial region p3 of the fourth semiconductor region 40 can be made longer than that of the first reference example. As a result, the electric field applied to the third semiconductor region 30 can be made lower than that of the first reference example. Thereby, in the embodiment, the leakage current can be suppressed even when the third semiconductor region 30 contains many defects.

In the example of FIG. 1, the first electrode 71 (gate electrode) is a trench-shaped electrode (electrode embedded in the trench). However, since the internal electric field is high in SiC, for example, the electric field applied to the gate insulating film at the bottom of the gate electrode becomes excessively high. Therefore, the characteristics of the insulating film fluctuate. For example, the insulating film deteriorates (including destruction). For example, the life may be shortened. On the other hand, it is considered that the increase of the electric field in the insulating film at the bottom of the gate electrode can be suppressed by forming the second electrode 72 (source electrode) as a trench-shaped electrode and providing the third partial region p3. ^{At this time, if the contact region (p +} layer) is provided directly under the second electrode 72 (source electrode) as in the first reference example, the leakage current becomes large as described later. Therefore, it is difficult to obtain a low on-resistance.

In the embodiment, the leakage current can be suppressed as described above. This makes it possible to design low on-resistance. For example, when a plurality of gate electrodes having a trench configuration are used, a low leakage current can be maintained even if the cell pitch Pc is reduced. This provides a low on-resistance.

Hereinafter, an example of the characteristics of the semiconductor device will be described.
FIG. 2 is a graph illustrating the characteristics of the semiconductor device according to the first embodiment.
The horizontal axis of FIG. 2 is the drain voltage Vd (V). The vertical axis is the drain current Id (A). As shown in FIG. 2, in the semiconductor device 110 according to the embodiment, the drain current Id is very small when the drain voltage Vd (about 1600 V) at which the avalanche breakdown occurs is less than. That is, there is virtually no source / drain leak.

FIG. 3 is a graph illustrating the characteristics of the semiconductor device of the first reference example.
FIG. 3 illustrates the characteristics of the semiconductor device 119 of the first reference example. In the semiconductor device 119 of the first reference example, the contact region (p ⁺ layer) is directly below the first conductive region 72a of the source electrode (second electrode 72). That is, the contact region (p ⁺ layer) is provided between a part of the first conductive region 72a and a part of the third partial region p3 of the fourth semiconductor region 40. FIG. 3 shows the characteristics of an example in which the distance W between the position of the end of the contact region (p ⁺ layer) in the X-axis direction and the position of the third partial region p3 in the X-axis direction is different. There is. In FIG. 3, the distance W is 0.1 μm, 0.2 μm, 0.3 μm or 0.4 μm. The distance W is related to the cell pitch in the semiconductor device 119. When the distance W is long, the cell pitch becomes large.

As shown in FIG. 3, in the semiconductor device 119 of the first reference example, when the distance W is short, the drain current Id is large in the low voltage region. That is, the source / drain leak is large. In order to reduce the source / drain leak, the distance W must be increased. This increases the on-resistance.

FIG. 4 is a graph illustrating the characteristics of the semiconductor device.
In FIG. 4, the horizontal axis is the cell pitch Pc (μm) (see FIG. 1). The vertical axis is the on-resistance RonA (mΩ · cm ² ). FIG. 4 shows the characteristics of the semiconductor device 110 according to the embodiment and the characteristics of the semiconductor device 119 of the first reference example. In the first reference example, the cell pitch Pc is linked to the above-mentioned distance W.

As shown in FIG. 4, in the semiconductor device 119 of the first reference example, a low on-resistance RonA can be obtained by reducing the cell pitch Pc. However, when the cell pitch Pc is small (when the distance W is 0.1 μm to 0.3 μm), a leak occurs. Therefore, in the configuration of the first reference example, the on-resistance RonA is large when the leak is small and practical.

On the other hand, in the semiconductor device 110 according to the embodiment, the leakage current is small as illustrated in FIG. Even when the cell pitch Pc is small, no leakage current is substantially generated. Then, as shown in FIG. 4, a low on-resistance RonA can be obtained in a state where a leakage current is substantially not generated.

As described above, according to the embodiment, it is possible to provide a semiconductor device capable of reducing the on-resistance.

In the semiconductor device 110, at least a part of the third semiconductor region 30 overlaps with the second semiconductor region 20 in the X-axis direction. For example, the position of the third semiconductor region 30 in the Z-axis direction is the same as the position of the second semiconductor region 20 in the Z-axis direction. For example, the side surface of the second semiconductor region 20 (the surface intersecting the X-axis direction) is in contact with the third semiconductor region 30.

For example, a second reference example in which the third semiconductor region 30 is provided below the second semiconductor region 20 in the Z-axis direction can be considered. In the second reference example, the side surface and the upper surface of the second semiconductor region 20 are in contact with the second electrode 72. Therefore, in the second reference example, the resistance (contact resistance) between the second semiconductor region 20 and the second electrode 72 can be lowered. However, in such a second reference example, the height of the third semiconductor region 30 is lower than that of the configuration according to the embodiment. Therefore, the leakage current tends to increase.

Generally, it is important to reduce the contact resistance. Therefore, even if the contact region (p ⁺ layer) is provided at a position not directly below the first conductive region 72a, the contact region (p ⁺ layer) is set to the second semiconductor region 20 in the X-axis direction. It's hard to come up with a side-by-side structure.

On the other hand, in the embodiment, the contact region (third semiconductor region 30) is aligned with the second semiconductor region 20 in the X-axis direction. Even if the resistance (contact resistance) between the second semiconductor region 20 and the second electrode 72 is higher than that of the second reference example, the third semiconductor region 30 is moved away from the bottom of the first conductive region 72a. The effect of suppressing the electric field in the third semiconductor region 30 to be low is great. In the configuration of the embodiment, an increase in the resistance (contact resistance) between the second semiconductor region 20 and the second electrode 72 is unlikely to be a problem in practical use.

As illustrated in FIG. 1, in the embodiment, the bottom B72a (bottom, bottom) of the first conductive region 72a is below the bottom B20 (bottom) of the second semiconductor region 20. For example, the bottom Bp4 (lower end) of the fourth partial region p4 is below the bottom B72a of the first conductive region 72a. For example, the bottom B71 of the first electrode 71 (bottom, bottom of the gate trench) is below the bottom Bp4 of the fourth partial region p4. For example, the bottom Bp3 of the third partial region p3 is below the bottom B71 of the first electrode 71. For example, the concentration of the electric field in the insulating film below the gate electrode can be suppressed, and a high withstand voltage can be obtained. For example, the destruction of the insulating film can be suppressed.

For example, the positions of the bottom B72a of the first conductive region 72a in the Z-axis direction are the positions of the bottom B20 of the second semiconductor region 20 in the Z-axis direction and the positions of the bottom Bp4 of the fourth partial region p4 in the Z-axis direction. Is between. The position of the bottom Bp4 of the fourth partial region p4 in the Z-axis direction is between the position of the bottom B72a of the first conductive region 72a in the Z-axis direction and the position of the bottom B71 of the first electrode 71 in the Z-axis direction. be. The position of the bottom B71 of the first electrode 71 in the Z-axis direction is between the position of the bottom Bp4 of the fourth partial region p4 in the Z-axis direction and the position of the bottom Bp3 of the third partial region p3 in the Z-axis direction. be.

In the embodiment, the length (width) of the third semiconductor region 30 along the X-axis direction is, for example, 0.04 times or more 1.3 times the length (width) of the first conductive region 72a along the X-axis direction. It is less than double. The length (width) of the third semiconductor region 30 along the X-axis direction is, for example, 0.04 times or more and twice or less the length (width) of the second semiconductor region 20 along the X-axis direction.

The length of the third semiconductor region 30 in the Z-axis direction is, for example, 0.03 times or more and twice or less the length of the first electrode 71 in the Z-axis direction. The length of the third semiconductor region 30 in the Z-axis direction is, for example, 0.1 times or more and 10 times or less the length of the second semiconductor region 20 in the Z-axis direction.

For example, the length (width) of the third semiconductor region 30 along the X-axis direction may be shorter than the length of the third semiconductor region 30 in the Z-axis direction.

In the semiconductor device 110 according to the embodiment, at least one of nitrogen (N), phosphorus (P) and arsenic (As) is used as the n-type impurity. In the embodiment, for example, at least one of aluminum (Al) and boron (B) is used as the p-type impurity.

For example, at least one of the first semiconductor region 10 and the second semiconductor region 20 includes at least one of N, P, and As. At least one of the third semiconductor region 30 and the fourth semiconductor region 40 includes at least one of Al and B.

For example, the concentration of impurities (described above) in the second semiconductor region 20 is higher than the concentration of impurities in the first semiconductor region 10. The concentration of impurities (described above) in the third semiconductor region 30 is higher than the concentration of impurities in the fourth semiconductor region 40.

For example, in the fourth semiconductor region 40, the p-type impurity concentration (carrier concentration) in the fourth partial region p4 (upper portion) is the p-type impurity concentration (carrier concentration) in the third partial region p3 (lower portion). Lower than. By lowering the p-type impurity concentration (carrier concentration) in the fourth partial region p4, for example, the threshold voltage can be easily adjusted appropriately. By increasing the p-type impurity concentration (carrier concentration) in the third partial region p3, for example, the electric field applied to the first insulating film 75 (gate insulating film) at the bottom of the first electrode 71 can be lowered. .. By increasing the p-type impurity concentration (carrier concentration) in the third partial region p3, for example, the electric field applied to the third semiconductor region 30 can be reduced.

The concentration of the n-type impurity in the first semiconductor region 10 is, for example, 1 × 10 ¹⁴ cm ^-3 or more and 5 × 10 ¹⁷ cm ^-3 or less. The concentration of the n-type impurity in the second semiconductor region 20 is, for example, 5 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less. The concentration of p-type impurities in the third semiconductor region 30 is, for example, 5 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less. The concentration of p-type impurities in the third partial region p3 of the fourth semiconductor region 40 is, for example, 1 × 10 ¹⁶ cm ^-3 or more and 1 × 10 ¹⁹ cm ^-3 or less. The concentration of p-type impurities in the fourth partial region p4 of the fourth semiconductor region 40 is, for example, 5 × 10 ¹⁵ cm ^-3 or more and 1 × 10 ¹⁸ cm ^-3 or less. For example, when the concentration of p-type impurities in the third partial region p3 is 7 × 10 ¹⁷ cm ^-3 or more and 1 × 10 ¹⁹ cm ^-3 or less, the concentration of p-type impurities in the fourth partial region p4 is, for example, It is 1 × 10 ¹⁶ cm ^-3 or more and less than 7 × 10 ¹⁷ cm ^-3. The impurity concentration is detected by, for example, SIMS (Secondary Ion Mass Spectrometry).

For example, the carrier concentration in the second semiconductor region 20 is higher than the carrier concentration in the first semiconductor region 10. The carrier concentration in the third semiconductor region 30 is higher than the carrier concentration in the fourth semiconductor region 40.

The carrier concentration in the first semiconductor region 10 is, for example, 1 × 10 ¹⁴ cm ^-3 or more and 5 × 10 ¹⁷ cm ^-3 or less. The carrier concentration in the second semiconductor region 20 is, for example, 5 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less. The carrier concentration in the third semiconductor region 30 is, for example, 5 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less. The carrier concentration in the third partial region p3 of the fourth semiconductor region 40 is, for example, 1 × 10 ¹⁶ cm ^-3 or more and 1 × 10 ¹⁹ cm ^-3 or less. The carrier concentration in the fourth partial region p4 of the fourth semiconductor region 40 is, for example, 5 × 10 ¹⁵ cm ^-3 or more and 1 × 10 ¹⁸ cm ^-3 or less. For example, when the carrier concentration in the third partial region p3 is 7 × 10 ¹⁷ cm ^-3 or more and 1 × 10 ¹⁹ cm ^-3 or less, the carrier concentration in the fourth partial region p4 is 1 × 10 ¹⁶ cm ^-3 or more 7 × 10 ¹⁷ cm ^{-3 or} less. The carrier concentration is detected by, for example, SCM (scanning Capacitance Microscope).

In embodiments, the first electrode 71 comprises, for example, polysilicon. The first electrode 71 may include, for example, at least one of TiN, Al, Ru, W and TaSiN.

At least one of the second electrode 72 and the third electrode 73 may contain at least one of Al and Ni. These electrodes may include, for example, a laminated film containing an Al film and a Ni film.

At least one of the first insulating film 75 and the second insulating film 76 includes, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, lanthanum oxide, and tantalum oxide.

For example, the second electrode 72 may include, for example, at least one of metal silicide and metal carbide. The second insulating film 76 may contain a metal silicide containing a metal contained in the second electrode 72. The second insulating film 76 may include a metal carbide containing a metal contained in the second electrode 72. An intermediate region containing at least one of metal silicide and metal carbide may be provided between the second electrode 72 and the second insulating film 76. At least one of the metal silicide and the metal carbide in the intermediate region contains a metal element contained in the second electrode 72.

As shown in FIG. 1, in the embodiment, for example, the third semiconductor region 30 is in contact with the first conductive region 72a. The second semiconductor region 20 is in contact with the second conductive region 72b.

Hereinafter, an example of a method for manufacturing the semiconductor device 110 according to the embodiment will be described.
5 (a) to 5 (f) are process-order schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment.

As shown in FIG. 5A, a first conductive type (for example, n type) first semiconductor film F1 is formed on the semiconductor substrate 10S. For example, epitaxial growth gives the first semiconductor film F1. A second conductive type (for example, p-type) second semiconductor film F2 is formed on the first semiconductor film F1. For example, the second semiconductor film F2 can be obtained by injecting a second conductive type impurity into the upper portion of the first semiconductor film F1. First conductive type impurities (first impurities I1, n type impurities) are injected into a part of the upper portion of the second semiconductor film F2. As a result, the first conductive type third semiconductor film F3 is obtained.

The first semiconductor film F1 is the first semiconductor region 10. The second semiconductor film F2 becomes a part of the fourth semiconductor region 40. The third semiconductor film F3 is the second semiconductor region 20.

After that, a trench is formed in a region (not shown), and the first insulating film 75 and the first electrode 71 are formed inside the trench. After this, the second insulating film 76 is formed.

As shown in FIG. 5B, the first mask M1 is formed on the third semiconductor film F3 (second semiconductor region 20). The first mask M1 covers at least a part of the third semiconductor film F3 (second semiconductor region 20). The other part of the upper portion of the second semiconductor film F2 is exposed from the opening of the first mask M1. Using the first mask M1 as a mask, the second conductive type (p type) second impurity I2 is injected into the other part of the upper portion of the exposed second semiconductor film F2. As a result, the fourth semiconductor film F4 is formed. The fourth semiconductor film F4 contains the second impurity I2 and is a second conductive type.

As shown in FIG. 5 (c), the second mask M2 is formed. The second mask M2 is a part of the above-mentioned part of the second semiconductor film F2 (a part covered with the first mask M1) and a part of the fourth semiconductor film F4 (a part into which the second impurity I2 is injected). cover. The second mask M2 does not cover the other part of the fourth semiconductor film F4. The other part of the fourth semiconductor film F4 is exposed from the opening of the second mask M2. The second mask M2 is formed, for example, by stretching the first mask M1. For example, the second mask M2 is formed by forming a film having a predetermined thickness on the first mask M1. The width of the opening of the second mask M2 is narrower than the width of the opening of the first mask M1. The second mask M2 is provided on the second semiconductor film F2 and on a part of the region in which the second impurity I2 is injected. Another part of the region injected with the second impurity I2 is not covered by the second mask M2.

As shown in FIG. 5D, the second mask M2 is used as a mask to form the trench T1 (source trench). That is, the other part of the fourth semiconductor film F4 exposed from the opening of the second mask M2 and a part of the second semiconductor film F2 are removed. As a result, the trench T1 is formed. For example, RIE (Reactive Ion Etching) is performed. The trench T1 penetrates a part of the region in which the second impurity I2 is injected and reaches a part of the second semiconductor film F2. The bottom of the trench T1 is between the upper end and the lower end of the second semiconductor film F2. The remaining portion of the region into which the second impurity I2 is injected becomes the third semiconductor region 30.

As shown in FIG. 5 (e), the second conductive type (p type) third impurity I3 is introduced into the bottom of the trench T1. A second conductive region is formed from a portion of the first semiconductor film F1 located below the bottom of the trench T1. This second conductive region is the third partial region p3 of the fourth semiconductor region 40. The second semiconductor film F2 becomes the fourth partial region p4 of the fourth semiconductor region 40. For example, using the second mask M2 as a mask, the p-type third impurity I3 is injected. The third impurity I3 is injected into a part of the first semiconductor film F1.

The introduction (injection) of the third impurity into the bottom of the trench T1 is an injection along the side wall of the trench T1. That is, vertical injection is performed instead of inclined injection in which the injection direction is inclined from the side wall of the trench. For example, the angle (absolute value) between the injection direction of the third impurity I3 and the side wall of the trench T1 is 5 degrees or less.

As shown in FIG. 5D, the second mask M2 is removed. After that, a conductive material is embedded inside the trench T1. As a result, the second electrode 72 is formed.

In the semiconductor device 110 manufactured by such a method, the third impurity I3 is injected vertically. That is, diagonal injection is not performed. Therefore, the region where impurities are injected can be controlled with high accuracy. For example, the third semiconductor region 30 is formed by the trench T1. Further, the trench T1 forms a third partial region p3 of the fourth semiconductor region 40. The third semiconductor region 30, the third partial region p3, and the first conductive region 72a are formed based on the trench T1. These parts are formed by self-alignment. Therefore, the accuracy of the relative positional relationship between the third semiconductor region 30 and the third subregion p3 is high. As a result, variations in characteristics can be suppressed.

For example, when impurities are injected by oblique injection, the third impurities I3 are injected from a plurality of directions. Therefore, the number of processes is large. On the other hand, according to the above method, the vertical injection is performed, so that the process is simplified.

By such a manufacturing method, a semiconductor device capable of reducing on-resistance can be easily manufactured with high accuracy.

When the semiconductor device 110 is manufactured by the above manufacturing method, the side surface of the third partial region p3 is likely to be positioned on a substantially extension of the side surface of the first conductive region 72a. As shown in FIG. 1, the first conductive region 72a has a side surface 72as. The side surface 72as intersects the second direction (X-axis direction). The boundary b1 between the third partial region p3 and the intermediate partial region pi is along the plane 72PL including the side surface 72as. In this example, the boundary b1 is on an extension of this side surface 72as. For example, the boundary b1 is located on the plane 72PL. The injected third impurity I3 (see FIG. 5E) may diffuse. In this case, as will be described later, the boundary b1 may be separated from the plane 72PL.

In the embodiment, the boundary b1 between the third subregion p3 and the intermediate subregion pi may be defined as follows. For example, the third partial region p3 contains impurities of the second conductive type (for example, p type). The position showing a value of 1/2 of the maximum concentration of the second conductive type impurities in the third partial region p3 is defined as the boundary b1.

As described above, the third semiconductor region 30 is formed by ion implantation. For example, the density of defects in the third semiconductor region 30 is higher than, for example, the density of defects in the fourth subregion p4 of the fourth semiconductor region 40. The density of defects in the third semiconductor region 30 is higher than, for example, the density of defects in the first semiconductor region 10.

For example, in the photoluminescence spectrum of the third semiconductor region 30, the maximum value of photoluminescence intensity in the wavelength range of 480 nm or more and 500 nm or less is larger than the maximum value of photoluminescence intensity in the wavelength range of 370 nm or more and 400 nm or less. high.

On the other hand, in the photoluminescence spectrum of the fourth semiconductor region 40, the maximum value of the photoluminescence intensity in the wavelength range of 480 nm or more and 500 nm or less is larger than the maximum value of the photoluminescence intensity in the wavelength range of 370 nm or more and 400 nm or less. Low.

For example, the maximum value of the photoluminescence of the third semiconductor region 30 in the wavelength range of 370 nm or more and 400 nm or less, whereas the maximum value of the photoluminescence of the third semiconductor region 30 in the wavelength range of 480 nm or more and 500 nm or less is the highest value. The ratio (first ratio) is high.

For example, the maximum value of the photoluminescence of the fourth semiconductor region 40 in the wavelength range of 480 nm or more and 500 nm or less with respect to the maximum value of the intensity of the photoluminescence of the fourth semiconductor region 40 in the wavelength range of 370 nm or more and 400 nm or less. The ratio (second ratio) is low. For example, the first ratio is higher than the second ratio.

It is considered that such a difference in the spectrum of photoluminescence is due to the high density of defects in the third semiconductor region 30. In the embodiment, when the third semiconductor region 30 having such a spectrum is provided, the third semiconductor region 30 is provided at a position overlapping the second semiconductor region 20 in the second direction (X-axis direction). As a result, a low on-resistance that can suppress the leakage current can be obtained.

FIG. 6 is a schematic cross-sectional view illustrating another semiconductor device according to the first embodiment.
As shown in FIG. 6, in another semiconductor device 111 according to the present embodiment, the first to fourth semiconductor regions 10, 20, 30, and 40, the first electrode 71, the second electrode 72, and the first insulating film 75 are also used. Is provided. Also in the semiconductor device 111, the boundary b1 between the third partial region p3 and the intermediate partial region pi is a plane 72PL including the side surface 72as (the surface intersecting the second direction) of the first conductive region 72a of the second electrode 72. Along with. In the semiconductor device 111, the boundary b1 is separated from the plane 72PL. Other than this, it is the same as the semiconductor device 110.

For example, when the injected third impurity I3 (see FIG. 5E) diffuses, the above configuration in the semiconductor device 111 is formed.

Also in the semiconductor device 111, vertical injection of the third impurity I3 is performed instead of diagonal injection. Therefore, the position of the boundary b1 is close to the plane 72PL.

For example, the distance along the second direction (X-axis direction) between the boundary b1 between the third partial region p3 and the intermediate partial region pi and the first insulating film 75 is defined as the first distance d1. The distance along the second direction (X-axis direction) between the boundary b2 between the second semiconductor region 20 and the third semiconductor region 30 and the first insulating film 75 is defined as the second distance d2. For example, the first distance d1 is longer than the second distance d2.

For example, the distance between the first conductive region 72a and the first insulating film 75 along the second direction is defined as the third distance d3. The first distance d1 (distance along the second direction between the boundary b1 between the third partial region p3 and the intermediate partial region pi and the first insulating film 75) is shorter than the third distance d3. ..

In the embodiment, the boundary b2 between the second semiconductor region 20 and the third semiconductor region 30 may be defined as follows. For example, the third semiconductor region 30 contains impurities of the second conductive type (for example, p type). The position showing a value of 1/2 of the maximum concentration of the second conductive type impurities in the third semiconductor region 30 is defined as the boundary b2.

Leakage current can also be suppressed in the semiconductor device 111. A low on-resistance can also be obtained in the semiconductor device 111.

FIG. 7 is a schematic cross-sectional view illustrating another semiconductor device according to the first embodiment.
As shown in FIG. 7, in another semiconductor device 112 according to the present embodiment, in the second direction (X-axis direction), a part of the third semiconductor region 30 is a part of the second semiconductor region 20. It is provided between the first conductive region 72a and the first conductive region 72a. Other than this, it is the same as the semiconductor device 110.

In the semiconductor device 112, in the first direction (Z-axis direction), a part of the second semiconductor region 20 is between the third semiconductor region 30 and the second conductive region 72b of the second electrode 72. In the semiconductor device 112, the area of the region where the second semiconductor region 20 and the second conductive region 72b are in contact with each other is large. A part of the side surface of the second semiconductor region 20 is in contact with the first conductive region 72a. Low contact resistance is obtained.

Leakage current can also be suppressed in the semiconductor device 112. A low on-resistance can also be obtained in the semiconductor device 112.

FIG. 8 is a schematic cross-sectional view illustrating another semiconductor device according to the first embodiment.
As shown in FIG. 8, another semiconductor device 113 according to the present embodiment further includes a fifth semiconductor region 50 in addition to the first to fourth semiconductor regions 10, 20, 30 and 40. Other than this, it is the same as the semiconductor device 110.

The fifth semiconductor region 50 is a second conductive type (p type in this example). The first semiconductor region 10 is provided between the fifth semiconductor region 50 and the fourth semiconductor region 40 and between the fifth semiconductor region 50 and the first electrode 71 in the first direction (Z-axis direction). ..

The semiconductor device 113 is, for example, an IGBT (Insulated Gate Bipolar Transistor). Leakage current can also be suppressed in the semiconductor device 113. The on-resistance can also be reduced in the semiconductor device 113 as well.

In the semiconductor device 113, the boundary b1 may be separated from the plane 72PL as in the semiconductor device 111.

In the semiconductor device 113, a part of the second semiconductor region 20 may be provided between the third semiconductor region 30 and the second conductive region 72b of the second electrode 72, similarly to the semiconductor device 112.

(Second Embodiment)
The present embodiment relates to a method for manufacturing a semiconductor device.
FIG. 9 is a flowchart illustrating a method for manufacturing a semiconductor device according to the second embodiment.
As shown in FIG. 9, in the method for manufacturing a semiconductor device according to the present embodiment, the upper portion of the second conductive type second semiconductor film F2 provided on the first conductive type first semiconductor film F1. The first conductive type first impurity I1 is partially introduced to form the first conductive type third semiconductor film F3 (step S110). For example, the process illustrated in FIG. 5A is performed.

Using the first mask M1 that covers at least a part of the third semiconductor film F3, the second conductive type second is applied to the other part of the upper portion of the second semiconductor film F2 that is exposed from the opening of the first mask M1. 2 The impurity I2 is introduced to form the second conductive type fourth semiconductor film F4 containing the second impurity (step S120). For example, the process illustrated in FIG. 5 (b) is performed.

A second mask M2 that covers a part of the second semiconductor film F2 and a part of the fourth semiconductor film F4 and does not cover the other part of the fourth semiconductor film F4 is used to cover the second mask M2. The other part of the fourth semiconductor film F4 exposed from the opening and a part of the second semiconductor film F2 are removed to form the trench T1 (step S130). For example, the processes illustrated in FIGS. 5 (c) and 5 (d) are performed.

The second conductive type third impurity I3 is introduced into the bottom of the trench T1 to form a second conductive type region from a portion of the first semiconductor film F1 located below the bottom (step S140). For example, the process illustrated in FIG. 5 (e) is performed. For example, the introduction of the third impurity I3 into the bottom of the trench T1 is an injection along the side wall of the trench T1.

A conductive material is introduced into the trench T1 to form an electrode (second electrode 72) (step S150). For example, the process illustrated in FIG. 5 (f) is performed.

According to the manufacturing method according to the embodiment, a semiconductor device capable of reducing on-resistance can be efficiently manufactured with high accuracy.

According to the embodiment, it is possible to provide a semiconductor device capable of reducing on-resistance and a method for manufacturing the same.

In the specification of the present application, "vertical" and "parallel" include not only strict vertical and strict parallel, but also variations in the manufacturing process, for example, and may be substantially vertical and substantially parallel. Just do it.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, with respect to the specific configuration of each element such as a semiconductor region, an electrode, and an insulating film included in a semiconductor device, the present invention can be similarly carried out by appropriately selecting from a range known to those skilled in the art, and the same effect can be obtained. As far as it can be obtained, it is included in the scope of the present invention.

Further, a combination of any two or more elements of each specific example to the extent technically possible is also included in the scope of the present invention as long as the gist of the present invention is included.

In addition, all semiconductor devices and manufacturing methods thereof that can be appropriately designed and implemented by those skilled in the art based on the semiconductor devices and manufacturing methods thereof described above as embodiments of the present invention also include the gist of the present invention. As long as it belongs to the scope of the present invention.

In addition, within the scope of the idea of the present invention, those skilled in the art can come up with various modified examples and modified examples, and it is understood that these modified examples and modified examples also belong to the scope of the present invention. ..

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

10 ... 1st semiconductor region, 10S ... semiconductor substrate, 20 ... 2nd semiconductor region, 30 ... 3rd semiconductor region, 40 ... 4th semiconductor region, 50 ... 5th semiconductor region, 71 ... 1st electrode, 72 ... 2nd Electrode, 72PL ... Flat surface, 72a ... First conductive region, 72as ... Side surface, 72b ... Second conductive region, 72g ... Part, 72p ... Part, 72q ... Part, 73 ... Third electrode, 75 ... First insulating film, 76 ... Second insulating film, 110-113, 119 ... Semiconductor device, B20, B71, B72a, Bp3, Bp4 ... Bottom, F1 to F4 ... First to fourth semiconductor films, I1 to I3 ... First to third impurities, Id ... Drain current, M1, M2 ... 1st and 2nd masks, Pc ... Cell pitch, RonA ... On resistance, T1 ... Trench, Vd ... Drain voltage, W ... Distance, b1, b2 ... Boundary, d1 to d3 ... 1st ~ Third distance, p1 to p4 ... 1st to 4th subregions, pi ... Intermediate subregions

Claims (12)

A first conductive type first semiconductor region including a first partial region, a second partial region, and an intermediate partial region located between the first partial region and the second partial region.
In the first direction intersecting the direction from the second partial region to the first partial region, the first electrode separated from the first partial region and
The second electrode
A first conductive region separated from the second partial region in the first direction,
A second conductive region separated from the intermediate partial region in the first direction,
With the second electrode including
It is provided between the intermediate partial region and a part of the second conductive region in the first direction, and is provided between the first conductive region and the first electrode in the second direction intersecting the first direction. The first conductive type second semiconductor region provided and electrically connected to the second electrode,
It is provided between the intermediate portion region and another part of the second conductive region in the first direction, and between the first conductive region and at least a part of the second semiconductor region in the second direction. Provided in the third semiconductor region of the second conductive type, which is electrically connected to the second electrode.
A fourth semiconductor region of the second conductive type including a third partial region and a fourth partial region, wherein the third partial region includes the second partial region and the first conductive region in the first direction. The fourth partial region is provided between the intermediate partial region and the second semiconductor region in the first direction, and the intermediate partial region and the third semiconductor region in the first direction. The fourth partial region is provided between the first conductive region and the first electrode in the second direction, and the fourth partial region is continuous with the third partial region. 4th semiconductor area and
Between the first partial region and the first electrode in the first direction, between the fourth partial region and the first electrode in the second direction, and the second semiconductor region in the second direction. And the first insulating film provided between the first electrode and the first electrode.
With
The first semiconductor region, the second semiconductor region, the third semiconductor region, and the fourth semiconductor region contain silicon carbide.
The carrier concentration of the second conductive type in the third semiconductor region is higher than the carrier concentration of the second conductive type in the third partial region, and higher than the carrier concentration of the second conductive type in the fourth partial region. high,
The first distance along the second direction between the boundary between the third partial region and the intermediate partial region and the first insulating film is the first conductive region and the first insulating film. A semiconductor device shorter than a third distance along the second direction between and. The semiconductor device according to claim 1, wherein the third partial region is in contact with the first conductive region. The semiconductor device according to claim 1 or 2, wherein the carrier concentration of the second conductive type in the fourth partial region is lower than the carrier concentration of the second conductive type in the third partial region. The carrier concentration of the second conductive type in the third semiconductor region is 5 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less.
The carrier concentration of the second conductive type in the third partial region is 1 × 10 ¹⁶ cm ^-3 or more and 1 × 10 ¹⁹ cm ^-3 or less.
The semiconductor device according to any one of claims 1 to 3, wherein the carrier concentration of the second conductive type in the fourth partial region is 5 × 10 ¹⁵ cm ^-3 or more and 1 × 10 ¹⁸ cm ^{-3 or less.} .. Claim that the first distance is longer than the second distance along the second direction between the boundary between the second semiconductor region and the third semiconductor region and the first insulating film. The semiconductor device according to any one of 1 to 4. The semiconductor device according to any one of claims 1 to 5, wherein the length of the third semiconductor region along the second direction is shorter than the length of the third semiconductor region along the first direction. The semiconductor device according to any one of claims 1 to 6 , wherein at least a part of the third partial region overlaps with the fourth partial region in the second direction. The semiconductor device according to any one of claims 1 to 7 , wherein a part of the second semiconductor region is between the third semiconductor region and the second conductive region in the first direction. .. The semiconductor device according to any one of claims 1 to 8 , wherein the density of defects in the third semiconductor region is higher than the density of defects in the fourth partial region. The maximum value of the photoluminescence of the third semiconductor region in the wavelength range of 370 nm or more and 400 nm or less, and the maximum value of the photoluminescence of the third semiconductor region in the wavelength range of 480 nm or more and 500 nm or less. The first ratio is the intensity of the photoluminescence of the fourth semiconductor region in the wavelength range of 480 nm or more and 500 nm or less with respect to the maximum value of the photoluminescence of the fourth semiconductor region in the wavelength range of 370 nm or more and 400 nm or less. The semiconductor device according to any one of claims 1 to 9 , which is higher than the second ratio of the highest value of. The first impurity of the first conductive type is introduced into a part of the upper portion of the second semiconductor film of the second conductive type provided on the first semiconductor film of the first conductive type, and the first of the first conductive type. 3 Form a semiconductor film,
The second conductive type second is exposed to the other part of the upper portion of the second semiconductor film exposed from the opening of the first mask by using the first mask covering at least a part of the third semiconductor film. The impurities are introduced to form the second conductive type fourth semiconductor film containing the second impurities.
An opening of the second mask is used by using a second mask that covers a part of the second semiconductor film and a part of the fourth semiconductor film and does not cover the other part of the fourth semiconductor film. The other part of the fourth semiconductor film exposed from the above and a part of the second semiconductor film are removed to form a trench.
The second conductive type third impurity is introduced into the bottom of the trench to form the second conductive type region from a portion of the first semiconductor film located below the bottom.
A conductive material is introduced into the trench to form an electrode, and the electrode is formed.
The second mask includes the first mask and a film formed on the first mask, and the width of the opening of the second mask is the width of the opening of the first mask. A narrower method of manufacturing semiconductor devices. The first semiconductor film, the second semiconductor film, the third semiconductor film, and the fourth semiconductor film contain silicon carbide.
The concentration of the first impurity in the second conductive form in the part of the fourth semiconductor film is in the region of the second conductive form in which the third impurity is introduced into the bottom of the trench and is located below the bottom. Higher than the second impurity concentration of the second conductive type,
The method for manufacturing a semiconductor device according to claim 11 , wherein the concentration of the third impurity in the second conductive type in the portion of the second semiconductor film into which the third impurity is not introduced is lower than the concentration of the second impurity.

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