JP6873791B2 - Power module and its manufacturing method - Google Patents

Description

The present embodiment relates to a power module and a method for manufacturing the same.

In recent years, high heat dissipation (low thermal resistance) of power modules has been required, and graphite substrates have been attracting attention. Compared to general copper thermal conductivity (about 398 W / mK) and aluminum thermal conductivity (about 236 W / mK), graphite has a high thermal conductivity of about 1500 W / mK (in-plane orientation direction). ..

JP-A-2007-19130 Japanese Unexamined Patent Publication No. 2005-210035

Yasushi Yamada, Atsushi Kuno, Seito Sawaki, Yasunori Narita, Katsuhiro Takema, "Applicability of Carbon-based Heterogeneous Heat Transfer Materials to Power Semiconductor Modules" Bulletin of Daido University Vol. 50 (2014) pp. 133-pp. 135

However, the thermal conductivity of graphite is about 5 W / mK in the normal direction perpendicular to the in-plane orientation direction, and the substrate is usually prepared so that the orientation is vertical (XZ orientation) (described later). In this case, anisotropy occurs in the XY direction of the substrate. In particular, since the CTE (Coefficient of Thermal Expansion) is about 25 ppm / K in the X direction and about -0.6 ppm / K in the Y direction, the graphite substrate is warped due to the mismatch of CTE in each direction. Resulting in. Repeating such warping for each heat generation may reduce reliability due to disconnection of wiring in the power module, deterioration of moisture resistance, and the like.

The present embodiment provides a power module capable of suppressing warpage of a graphite substrate used for the power module and improving reliability, and a method for manufacturing the same.

According to one aspect of the present embodiment, an anisotropic substrate, a semiconductor device mounted on the substrate, and a resin laminated on the substrate are provided, and an arbitrary direction of the substrate surface is provided. When the X direction and the direction orthogonal to the X direction are the Y direction, the substrate has a smaller thermal expansion rate in the Y direction than the X direction, and the resin has the Y direction as compared with the X direction. Is provided with a power module having a small thermal expansion rate.

According to another aspect of the present embodiment, a step of forming an anisotropic substrate, a step of mounting a semiconductor device on the substrate, and a step of laminating a resin on the substrate. When the arbitrary direction of the substrate surface is the X direction and the direction orthogonal to the X direction is the Y direction, the substrate has a smaller thermal expansion rate in the Y direction than the X direction. Provided is a method for manufacturing a power module, which is formed by injecting a resin from one end in the Y direction so that the thermal expansion rate is smaller in the Y direction than in the X direction.

According to the present embodiment, it is possible to provide a power module capable of suppressing warpage and a method for manufacturing the same.

A schematic bird's-eye view configuration diagram showing a main part of a power module according to a comparative example. A schematic bird's-eye view configuration diagram showing a main part of a power module according to an embodiment. The schematic side view which shows the anisotropy control method of the liquid crystal polymer provided in the power module which concerns on embodiment. It is a schematic bird's-eye view configuration diagram which shows the structural model of the simulation of the power module which concerns on embodiment, (a) decomposition structure, (b) laminated structure. The explanatory view of the parameter used for the simulation of the power module which concerns on embodiment. It is a schematic bird's-eye view configuration diagram showing the warp of the structural model that occurs when simulating under the conditions shown in FIGS. 4 and 5, and is (a) Low-CTE, (b) Middle-CTE, and (c) High-CTE. , (D) Simulation-CTE. The graph which compares the warpage of the four structural models shown in FIG. FIG. 5 is a schematic bird's-eye view configuration diagram showing Mises stress applied to the resin when simulated under the conditions shown in FIGS. 4 and 5, wherein (a) Low-CTE, (b) Middle-CTE, and (c) High-CTE. (D) Asym-CTE. The graph which compares the maximum value of Mises stress applied to the resin of four structural models shown in FIG. It is a schematic bird's-eye view configuration diagram showing the Mises stress applied to the graphite substrate when simulated under the conditions shown in FIGS. 4 and 5, and is (a) Low-CTE, (b) Middle-CTE, and (c) High-CTE. , (D) Asym-CTE. The graph which compares the maximum value of Mises stress applied to the graphite substrate of four structural models shown in FIG. It is explanatory drawing of the power module which concerns on Example 1, (a) schematic side structure view, (b) schematic plan structure view. The schematic side structure view of the power module which concerns on Example 2. FIG. FIG. 6 is a schematic bird's-eye view of a laminated structure of graphite sheets constituting a graphite plate applicable to the power module according to the embodiment. An example of a graphite plate applicable to the power module according to the embodiment, (a) a schematic bird's-eye view configuration diagram illustrating the first graphite plate GP (XY), and (b) the second graphite plate GP ( A schematic bird's-eye view configuration diagram illustrating XZ). The power module according to the embodiment, (a) a schematic circuit representation diagram of a SiC MOSFET of a one-in-one (1 in 1) module, and (b) a schematic circuit representation diagram of an IGBT of a 1 in 1 module. FIG. 6 is a detailed circuit representation diagram of a 1 in 1 module SiC MOSFET, which is a power module according to an embodiment. The power module according to the embodiment, (a) a schematic circuit representation diagram of a SiC MOSFET of a two-in-one (2 in 1) module, and (b) a schematic circuit representation diagram of an IGBT of a 2 in 1 module. FIG. 6 is a schematic cross-sectional structural view of a SiC MOSFET including a source pad electrode SPD and a gate pad electrode GPD, which is an example of a semiconductor device applicable to the power module according to the embodiment. FIG. 6 is a schematic cross-sectional structural view of an IGBT including an emitter pad electrode EPD and a gate pad electrode GPD, which is an example of a semiconductor device applicable to the power module according to the embodiment. FIG. 6 is a schematic cross-sectional structure diagram of a SiC DI (Double Implanted) MOSFET, which is an example of a semiconductor device applicable to a power module according to an embodiment. FIG. 6 is a schematic cross-sectional structure diagram of a SiC T (Trench) MOSFET, which is an example of a semiconductor device applicable to a power module according to an embodiment. In the circuit configuration of a three-phase AC inverter configured using the power module according to the embodiment, (a) a circuit configuration example in which a SiC MOSFET is applied as a semiconductor device and a snubber capacitor is connected between the power supply terminal PL and the ground terminal NL. , (B) A circuit configuration example in which an IGBT is applied as a semiconductor device and a snubber capacitor is connected between the power supply terminal PL and the ground terminal NL. FIG. 3 is a circuit configuration diagram of a three-phase AC inverter to which a SiC MOSFET is applied as a semiconductor device in a circuit configuration of a three-phase AC inverter configured by using the power module according to the embodiment. FIG. 3 is a circuit configuration diagram of a three-phase AC inverter to which an IGBT is applied as a semiconductor device in a circuit configuration of a three-phase AC inverter configured by using the power module according to the embodiment. FIG. 6 is a schematic bird's-eye view pattern configuration diagram of a 2 in 1 module (module with a built-in half bridge) to which a SiC MOSFET is applied as a semiconductor device, which is a power module according to the embodiment. A schematic bird's-eye view configuration diagram of a module with a built-in half bridge after resin molding as a mold type module, which is a power module according to an embodiment. FIG. 6 is a schematic bird's-eye view pattern configuration diagram of a six-in-one (6 in 1) module, which is a power module according to an embodiment. (A) A schematic bird's-eye view pattern configuration diagram and (b) a schematic plane pattern configuration diagram showing a schematic configuration of a power module according to an embodiment. (A) A schematic bird's-eye view pattern configuration diagram and (b) a schematic plane pattern configuration diagram showing a schematic configuration of a power module according to an embodiment.

Next, the present embodiment will be described with reference to the drawings. In the description of the drawings described below, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness of each component and the plane dimensions is different from the actual one. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that parts of the drawings having different dimensional relationships and ratios are included.

Further, the embodiments shown below exemplify devices and methods for embodying the technical idea, and do not specify the material, shape, structure, arrangement, etc. of each component. This embodiment can be modified in various ways within the scope of the claims.

[Comparison example]
First, the power module according to the comparative example will be described. The overall structure of the power module will be described later, and here, the structure that causes warpage will be focused on.

The main part of the power module according to the comparative example is shown as shown in FIG. As shown in FIG. 1, the power module according to the comparative example adopts a structure in which the surface of the anisotropic graphite substrate 61 is sealed with the isotropic resin 62A. Generally, the sealing resin is transfer-molded, and as the sealing resin, an epoxy resin having isotropic physical characteristics is used. As described above, the CTE of the graphite substrate 61 is about 25 ppm / K in the X direction and about −0.6 ppm / K in the Y direction, so that the graphite substrate 61 is warped due to the mismatch of the CTE.

[Embodiment]
Hereinafter, the power module according to the embodiment will be described.

(Thermoplastic resin)
The main part of the power module according to the embodiment is shown as shown in FIG. As shown in FIG. 2, the power module according to the embodiment employs a structure in which the anisotropy of the CTE of the thermoplastic resin 62 is combined with the anisotropy of the CTE of the graphite substrate 61. As a result, CTE matching becomes possible, and warpage can be suppressed.

Specifically, the CTE of the graphite substrate 61 is about 25 ppm / K in the X direction and about −0.6 ppm / K in the Y direction. In this case, the CTE of the thermoplastic resin 62 is also set to about 25 ppm / K in the X direction and about −0.6 ppm / K in the Y direction. The thermoplastic resin (particularly, the liquid crystal polymer) 62 is anisotropy according to the resin injection direction at the time of molding. This structure can be realized by controlling the molding conditions and the injection direction. In the following description, the same reference numeral 62 is used for the resin, the thermoplastic resin, and the liquid crystal polymer.

(Resin anisotropy control method)
The power module according to the embodiment is molded by injection molding, and a thermoplastic liquid crystal polymer 62 is used as the sealing resin. The liquid crystal polymer 62 has a small latent heat of crystallization and has anisotropy in the flow direction. CTE is controlled by controlling the orientation of the liquid crystal polymer 62. Specifically, the CTE in the X direction and the Y direction of the liquid crystal polymer 62 is matched with the CTE in the X direction and the Y direction of the graphite substrate 61.

Matching CTEs does not mean matching CTEs perfectly. At least, when the graphite substrate 61 has a smaller coefficient of thermal expansion in the Y direction than the X direction, the resin 62 may also have a smaller coefficient of thermal expansion in the Y direction than the X direction.

The method for controlling the anisotropy of the liquid crystal polymer 62 included in the power module according to the embodiment is shown in FIG. As shown in FIG. 3, since the liquid crystal is oriented in the flow direction 73 of the liquid crystal polymer 62, the injection gates 71 and 72 of the liquid crystal polymer 62 are arranged in the low CTE direction. The CTE of the liquid crystal polymer 62 in the X direction and the Y direction is controlled by adjusting the injection speed at which the liquid crystal polymer 62 is injected from the injection gates 71 and 72, the gate position of the injection gates 71 and 72, and the like. The injection directions 71A and 72A of the liquid crystal polymer 62 may be, for example, −45 degrees or more and +45 degrees or less with respect to the Y direction (flow direction 73).

When such an anisotropy control method is adopted, the liquid crystal polymer 62 is formed with gate marks 71B and 72B when the injection gates 71 and 72 are arranged in the low CTE direction. This makes it possible to confirm that the injection gates 71 and 72 are arranged in the low CTE direction based on the gate marks 71B and 72B.

In some cases, the orientation direction of the liquid crystal can be recognized by X-rays. In that case, it is also possible to confirm that the injection gates 71 and 72 are arranged in the low CTE direction based on the orientation direction of the liquid crystal recognized by X-rays.

(Simulation structural model)
The structural model of the simulation of the power module according to the embodiment is shown as shown in FIG. 4 (a). As shown in FIG. 4, a structural model in which a 40 mm × 40 mm × 3 mm graphite substrate 61 is sealed with a 50 mm × 50 mm × 6 mm resin 62 is used. FIG. 4B represents a 1/4 model of FIG. 4A, showing a state in which the surface and side surfaces of 61 are sealed by 62, and the lower right corner of the figure is the origin of displacement. The temperature condition is assumed to be the case of heating from 40 ° C. to 300 ° C.

The parameters used in the simulation are represented as shown in FIG. As shown in FIG. 5, the CTE of the graphite substrate GF is −0.6 ppm / K in the X direction, 25 ppm / K in the Y direction, and −0.6 ppm / K in the Z direction. The Young's modulus E of the graphite substrate GF is 50 GPa, and the Poisson's ratio ν of the graphite substrate GF is 0.3. On the other hand, as the resin 62, an isotropic resin (Low-CTE), a resin (Middle-CTE), a resin (High-CTE), and an anisotropic resin (Asym-CTE) are used. Hereinafter, the resin (Low-CTE) is referred to as resin RA, the resin (Middle-CTE) is referred to as resin RB, the resin (High-CTE) is referred to as resin RC, and the anisotropic resin (Asym-CTE) is referred to as resin RD.

The CTE of the resin RA is −0.6 ppm / K, the CTE of the resin RB is 12 ppm / K, and the CTE of the resin RC is 25 ppm / K. The CTE of the resin RD is −0.6 ppm / K in the X direction, 25 ppm / K in the Y direction, and 12 ppm / K in the Z direction. The Young's modulus E of these four resins RA, RB, RC, and RD is 10 GPa, and the Poisson's ratio ν is 0.3.

(simulation result)
Next, the simulation results will be described.

-Warp result-
The warpage of the structural model that occurs when simulating under the conditions shown in FIGS. 4 and 5 is represented as shown in FIGS. 6 and 7. FIG. 6A shows the warp of the structural model 62a in which the graphite substrate GF is sealed with the resin RA. FIG. 6B shows the warp of the structural model 62b in which the graphite substrate GF is sealed with the resin RB. FIG. 6C shows the warp of the structural model 62c in which the graphite substrate GF is sealed with the resin RC. FIG. 6D shows the warp of the structural model 62d in which the graphite substrate GF is sealed with the resin RD. FIG. 7 compares the warpage of the four structural models 62a, 62b, 62c, 62d shown in FIG.

As shown in FIGS. 6A and 7, the structural model 62a sealed with the resin RA has a warped end portion of about +280 μm. Further, as shown in FIGS. 6B and 7, the structural model 62b sealed with the resin RB has its end warped by about −130 μm to +130 μm. Further, as shown in FIGS. 6C and 7, the structural model 62c sealed with the resin RC has a warped end portion of about 280 μm. Further, as shown in FIGS. 6D and 7, the structural model 62d sealed with the resin RD hardly warps.

As described above, when the isotropic resin RA, the resin RB, and the resin RC are used, it is difficult to suppress the warp even if the CTE is changed. On the other hand, when the anisotropic resin RD is used, it is possible to suppress the warp.

-Stress result-
Next, the Mises stress applied to the resins RA, RB, RC, RD and the graphite substrate GF when simulated under the conditions shown in FIGS. 4 and 5 will be described. The Mises stress is one of the equivalent stresses used to indicate the stress state generated inside an object with a single value, as shown in the definition formula of [Equation 1]. In the definition formula, σ1 is the maximum principal stress, σ2 is the intermediate principal stress, and σ3 is the minimum principal stress.

_{The Mises stress σ R} applied to the resins RA, RB, RC, and RD when simulated under the conditions shown in FIGS. 4 and 5 is represented as shown in FIGS. 8 and 9. FIG. 8A shows the _{Mises stress σ R} applied to the resin RA of the structural model 62a. FIG. 8B shows the _{Mises stress σ R} applied to the resin RB of the structural model 62b. FIG. 8C shows the _{Mises stress σ R} applied to the resin RC of the structural model 62c. FIG. 8D shows the _{Mises stress σ R} applied to the resin RD of the structural model 62d. FIG. 9 compares the maximum values of the _{Mises stress σ R} applied to the resins RA, RB, RC, and RD of the four structural models 62a, 62b, 62c, and 62d shown in FIG.

As shown in FIGS. 8A and 9, the resin RA of the structural model 62a is subjected to a Mises stress σ _{R of} about 80 MPa at the maximum. Further, as shown in FIGS. 8 (b) and 9, the resin RB of the structural model 62b is subjected to a Mises stress σ _{R of} about 70 MPa at the maximum. Further, as shown in FIGS. 8C and 9, the resin RC of the structural model 62c is subjected to a Mises stress σ _{R of} about 140 MPa at the maximum. Further, as shown in FIGS. 8D and 9, the resin RD of the structural model 62d is subjected to a Mises stress σ _{R of} about 50 MPa at the maximum. That is, it can be seen that the _{von Mises stress σ R} applied to the resins RA, RB, RC, and RD in which the graphite substrate GF and CTE match is low.

_{The Mises stress σ G} applied to the graphite substrate GF when simulated under the conditions shown in FIGS. 4 and 5 is represented as shown in FIGS. 10 and 11. FIG. 10A shows the _{Mises stress σ G} applied to the graphite substrate GF of the structural model 62a. FIG. 10B shows the _{Mises stress σ G} applied to the graphite substrate GF of the structural model 62b. FIG. 10 (c) shows the _{Mises stress σ G} applied to the graphite substrate GF of the structural model 62c. FIG. 10D shows the _{Mises stress σ G} applied to the graphite substrate GF of the structural model 62d. FIG. 11 compares the maximum values of the _{Mises stress σ G} applied to the graphite substrate GF of the four structural models 62a, 62b, 62c, and 62d shown in FIG.

As shown in FIGS. 10A and 11, the graphite substrate GF of the structural model 62a is subjected to a Mises stress σ _{G of} about 310 MPa at the maximum. Further, as shown in FIGS. 10B and 11, the graphite substrate GF of the structural model 62b is subjected to a Mises stress σ _{G of} about 240 MPa at the maximum. Further, as shown in FIGS. 10C and 11, the graphite substrate GF of the structural model 62c is subjected to a Mises stress σ _{G of} about 350 MPa at the maximum. Further, as shown in FIGS. 10D and 11, the graphite substrate GF of the structural model 62d is subjected to a Mises stress σ _{G of} about 120 MPa at the maximum. That is, it can be seen that the _{Mises stress σ G} applied to the graphite substrate GF is lower in the RD having the same CTE than in the resins RA, RB, and RC.

(Example)
Next, the power module according to the embodiment will be described. Here, a 1in1 type power module is illustrated as a basic structure.

− Example 1-
The schematic side structure of the power module according to the first embodiment is shown as shown in FIG. 12 (a), and the schematic planar structure thereof is shown as shown in FIG. 12 (b). As shown in FIGS. 12A and 12B, the power module according to the first embodiment has an anisotropic substrate 61, a semiconductor device (chip) 64 mounted on the substrate 61, and a substrate 61. When the laminated resin 62 is provided and an arbitrary direction of the substrate surface is the X direction and the direction orthogonal to the X direction is the Y direction, the substrate 61 has a smaller thermal expansion rate in the Y direction than the X direction. The resin 62 has a smaller thermal expansion rate in the Y direction than in the X direction.

Specifically, the substrate 61 may be a graphite substrate 61.

Further, the graphite substrate 61 may have an orientation in which the thermal conductivity is relatively high in the thickness direction rather than the plane direction (described later).

Further, the resin 62 may be a thermoplastic resin 62.

Further, the thermoplastic resin 62 may be a liquid crystal polymer 62.

Further, the power module is molded by injection molding, the resin 62 is anisotropy according to the injection direction at the time of molding, and the gate marks 71B and 72B when the injection gates 71 and 72 are arranged in the low coefficient of thermal expansion direction. It may be provided (see FIG. 3).

Further, the injection directions 71A and 72A of the resin 62 may be −45 degrees or more and +45 degrees or less with respect to the Y direction (see FIG. 3).

Further, a copper layer 63 is formed on the substrate 61, a semiconductor device 64 is formed on the copper layer 63, the semiconductor device 64 is connected to the power terminal 66 via a wire 65, and a part of the power terminal 66 is removed. It may be sealed with a resin 62.

Further, the power module may include any of Si-based or SiC-based IGBTs, diodes, MOSFETs, and GaN-based FETs.

Further, the power module may constitute any one of a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, or a fourteen-in-one module.

As described above, according to the power module according to the first embodiment, since the resin is injected so as to match the CTE, the warp of the graphite substrate 61 can be suppressed.

− Example 2-
Next, only the differences between the power module according to the second embodiment and the first embodiment will be described.

The schematic side structure of the power module according to the second embodiment is shown as shown in FIG. As shown in FIG. 13, another graphite substrate 69 is arranged at a position facing the graphite substrate 61, and the facing surfaces and side surfaces of the graphite substrates 61 and 69 are sealed with the resin 62. The semiconductor device 64 is connected to the power terminal 66 via a spacer 67 (columnar electrode) such as copper and a copper layer 68 formed on the graphite substrate 69. Also in this case, the graphite substrates 61 and 69 have a smaller coefficient of thermal expansion in the Y direction than the X direction, and the resin 62 has a smaller coefficient of thermal expansion in the Y direction than the X direction, as in the first embodiment. is there.

As described above, in the power module according to the second embodiment, CTE matching is possible as in the first embodiment, and the warpage of the graphite substrates 61 and 69 cancel each other out, so that the warp is further suppressed. can do.

-Manufacturing method of power module-
Next, a method of manufacturing the power module according to the embodiment will be described.

The method for manufacturing the power module according to the embodiment includes a step of forming the anisotropic substrate 61, a step of mounting the semiconductor device 64 on the substrate 61, and a step of laminating the resin 62 on the substrate 61. When the arbitrary direction of the substrate surface is the X direction and the direction orthogonal to the X direction is the Y direction, the substrate 61 is formed so that the thermal expansion rate is smaller in the Y direction than in the X direction. , The resin 62 is formed so that the thermal expansion rate is smaller in the Y direction than in the X direction.

As described above, according to the power module manufacturing method according to the embodiment, since CTE matching is possible, it is possible to manufacture a power module capable of suppressing warpage.

Further, a step of arranging the second substrate above the semiconductor device so as to face the substrate (the coefficient of thermal expansion thereof is in the same direction as the anisotropy of the substrate), and each terminal, the substrate, and the second substrate. It may further have a step of sealing with a resin except for a part of the surface opposite to the opposite surface.

(Graphite substrate)
Next, the graphite substrate 61 (69) will be described in detail.

The schematic configuration (laminated structure example) of the graphite sheet (graphene) GS constituting the graphite substrate 61 is shown as shown in FIG.

The graphite plate GP has a first graphite plate GP (XY) having an XY orientation having a higher thermal conductivity in the plane direction than the thickness direction, and a first graphite plate GP (XY) having an XZ orientation having a higher thermal conductivity in the thickness direction than the plane direction. There are two graphite plate GPs (XZ), the first graphite plate GP (XY) is represented as shown in FIG. 15 (a), and the second graphite plate GP (XZ) is shown in FIG. 15 (b). It is expressed as shown in.

As shown in FIG. 14, the graphite sheets GS1, GS2, GS3, ..., GSn on each surface composed of n layers have a large number of hexagonal covalent bonds in one laminated crystal structure, and each surface has a covalent bond. The graphite sheets GS1, GS2, GS3, ..., and GSn are connected by van der Waals force.

That is, graphite, which is a carbon-based anisotropic heat transfer material, is a layered crystal body having a hexagonal network structure of carbon atoms, and has anisotropic thermal conductivity. Graphite sheets GS1, GS2, shown in FIG. GS3 ..... GSn has a higher thermal conductivity (high thermal conductivity) in the crystal plane direction (on the XY plane) than in the thickness direction of the Z axis.

Therefore, as shown in FIG. 15A, the first graphite plate GP (XY) having an XY orientation is, for example, about X = 1500 (W / mK), about Y = 1500 (W / mK), Z. It has a thermal conductivity of about 5 (W / mK).

On the other hand, as shown in FIG. 15B, the second graphite plate GP (XZ) having the XZ orientation is, for example, X = 1500 (W / mK), Y = 5 (W / mK), Z. It has a thermal conductivity of about 1500 (W / mK).

Both the first graphite plate GP (XY) and the second graphite plate GP (XZ) have a density of about 2.2 (g / cm ³ ) and a thickness of about 0.7 mm to 10 mm. Yes, the size is about 40 mm × 40 mm or less.

In the power module 2 according to the present embodiment, the 1 in 1 module (basic configuration) and the 2 in 1 module have been mainly described, but the present invention is not limited to this, and for example, a four-in-one (4 in 1) module and a six-in-one module. (6 in 1) module, 7 in 1 module with snubber capacitor in 6 in 1 module, eight in one (8 in 1) module, twelve in one (12 in 1) module, fourteen in (14 in) 1) It can also be applied to one module.

(Specific example of semiconductor device)
The schematic circuit representation of the SiC MOSFET of the 1 in 1 module 50, which is the power module according to the embodiment, is represented as shown in FIG. 16 (a), and the schematic circuit representation of the IGBT of the 1 in 1 module 50. Is represented as shown in FIG. 16 (b). FIG. 16A shows a diode DI connected in antiparallel to the MOSFET. The main electrode of the MOSFET is represented by a drain terminal DT and a source terminal ST. Similarly, FIG. 16B shows a diode DI connected in antiparallel to the IGBT. The main electrode of the IGBT is represented by a collector terminal CT and an emitter terminal ET.

Further, in the power module according to the embodiment, the detailed circuit representation of the SiC MOSFET of the 1 in 1 module 50 is shown as shown in FIG.

In the 1 in 1 module 50, for example, one MOSFET is built in one module, and the MOSFET may be one in which a plurality of (for example, 2 to 5) semiconductor chips are connected in parallel. When a SiC transistor is used, it is difficult to form it with a large chip size, which is a particularly useful method. It is also possible to mount a part of each chip for diode DI.

More specifically, as shown in FIG. 17, sense MOSFET Qs are connected in parallel with the MOSFET Q. The sense MOSFET Qs are formed as fine transistors in the same chip as the MOSFET Q. In FIG. 17, SS is a source sense terminal, CS is a current sense terminal, and G is a gate signal terminal. Also in the power module according to the embodiment, the sense MOSFET Qs may be formed as fine transistors in the same chip in the MOSFET Q.

(Circuit configuration)
The schematic circuit representation of the SiC MOSFET of the 2 in 1 module 100, which is the power module according to the embodiment, is represented as shown in FIG. 18 (a), and the schematic circuit representation of the IGBT of the 2 in 1 module 100. Is represented as shown in FIG. 18 (b).

A 2 in 1 type module in which two (sets) of semiconductor devices Q1 and Q4 are sealed in one mold resin, which is a power module according to the embodiment, will be described.

As shown in FIG. 18A, the 2 in 1 module 100 to which the SiC MOSFETs are applied as the semiconductor devices Q1 and Q4 has a half-bridge configuration in which two (sets) of SiC MOSFETs Q1 and Q4 are incorporated.

Here, each semiconductor device can be regarded as one large transistor, but the built-in transistor may be one chip or a plurality of chips. Further, there are 1 in 1, 2 in 1, 4 in 1, 6 in 1 and the like. For example, in one module, 2 modules have a half bridge composed of two transistors (chips). A module with two sets of in 1, 2 in 1 built in is called a module with three sets of 4 in 1, 2 in 1 built in, and a module with three sets built in is called 6 in 1.

As shown in FIG. 18A, the 2 in 1 module 100 contains two SiC MOSFETs Q1 and Q4 connected in series and diodes DI1 and DI4 connected in antiparallel to the SiC MOSFETs Q1 and Q4, respectively. .. In FIG. 18A, G1 is a lead terminal for the gate signal of MOSFET Q1, and S1 is a lead terminal for the source signal of MOSFET Q1. Similarly, G4 is a lead terminal for the gate signal of MOSFET Q4, and S4 is a lead terminal for the source signal of MOSFET Q4. P is a positive power terminal, N is a negative power terminal, and O is an output terminal electrode.

Further, as shown in FIG. 18B, in the 2 in 1 module 100 to which the IGBT is applied as the semiconductor devices Q1 and Q4, two IGBTs Q1 and Q4 connected in series and the IGBT Q1 and Q4 are inversely parallel to each other. The diodes DI1 and DI4 to be connected are built-in. In FIG. 18B, G1 is a lead terminal for the gate signal of the IGBT Q1, and E1 is a lead terminal for the emitter signal of the IGBT Q1. Similarly, G4 is a lead terminal for the gate signal of the IGBT Q4, and E4 is a lead terminal for the emitter signal of the IGBT Q4.

The same applies to the semiconductor devices Q2 and Q5 and the semiconductor devices Q3 and Q6 applicable to the power module according to the embodiment.

(Device structure)
An example of the semiconductor devices Q1 and Q4 applicable to the power module according to the embodiment, the schematic cross-sectional structure of the SiC MOSFET 130A including the source pad electrode SPD and the gate pad electrode GPD is shown as shown in FIG. Ru.

As shown in FIG. 19, the SiC MOSFET 130A has a ^{semiconductor layer 31 composed of an n-} high resistance layer, a p-body region 32 formed on the surface side of the semiconductor layer 31, and a source formed on the surface of the p-body region 32. The gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the region 33 and the p-body region 32, the gate electrode 35 arranged on the gate insulating film 34, and the source region 33 and the p-body region 32 are connected to each other. ^{The source electrode 36 is provided, an n +} drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a drain electrode 38 connected to the ^{n + drain region 37.}

The gate pad electrode GPD is connected to the gate electrode 35 arranged on the gate insulating film 34, and the source pad electrode SPD is connected to the source electrode 36 connected to the source region 33 and the p body region 32. Further, as shown in FIG. 19, the gate pad electrode GPD and the source pad electrode SPD are arranged on the passive interlayer insulating film 39 covering the surface of the SiC MOSFET 130A.

Although not shown, a transistor structure having a fine structure may be formed in the semiconductor layer 31 below the gate pad electrode GPD and the source pad electrode SPD.

Further, as shown in FIG. 19, in the transistor structure in the central portion, the source pad electrode SPD may be extended and arranged on the interlayer insulating film 39 for passivation.

In FIG. 19, the SiC MOSFET 130A is composed of a planar gate type n-channel vertical SiC MOSFET, but as shown in FIG. 22 described later, it is composed of a trench gate type n-channel vertical SiC TMOSFET 130D and the like. Is also good.

Alternatively, as the semiconductor devices Q1 and Q4 applicable to the power module according to the embodiment, a GaN-based FET or the like can be adopted instead of the SiC MOSFET 130A.

The same applies to the semiconductor devices Q2 and Q5 and the semiconductor devices Q3 and Q6 applicable to the power module according to the embodiment.

Further, as the semiconductor devices Q1 to Q6 applicable to the power module according to the embodiment, a semiconductor having a bandgap energy of, for example, 1.1 eV to 8 eV, which is called a wide bandgap type, can be used.

Similarly, as shown in FIG. 20, a schematic cross-sectional structure of the IGBT 130B including the emitter pad electrode EPD and the gate pad electrode GPD, which is an example of the semiconductor devices Q1 and Q4 applicable to the power module according to the embodiment, is shown. expressed.

As shown in FIG. 20, the IGBT 130B includes a ^{semiconductor layer 31 composed of an n-} high resistance layer, a p-body region 32 formed on the surface side of the semiconductor layer 31, and an emitter region formed on the surface of the p-body region 32. It is connected to the gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the 33E and the p-body region 32, the gate electrode 35 arranged on the gate insulating film 34, and the emitter region 33E and the p-body region 32. ^{The emitter electrode 36E is provided, a p +} collector region 37P arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a collector electrode 38C connected to the ^{p + collector region 37P.}

The gate pad electrode GPD is connected to the gate electrode 35 arranged on the gate insulating film 34, and the emitter pad electrode EPD is connected to the emitter electrode 36E connected to the emitter region 33E and the p body region 32. Further, as shown in FIG. 20, the gate pad electrode GPD and the emitter pad electrode EPD are arranged on the passive interlayer insulating film 39 covering the surface of the IGBT 130B.

Although not shown, an IGBT structure having a fine structure may be formed in the semiconductor layer 31 below the gate pad electrode GPD and the emitter pad electrode EPD.

Further, as shown in FIG. 20, even in the central IGBT structure, the emitter pad electrode EPD may be extended and arranged on the passive interlayer insulating film 39.

In FIG. 20, the IGBT 130B is composed of a planar gate type n-channel vertical IGBT, but it may be composed of a trench gate type n-channel vertical IGBT or the like.

The same applies to the semiconductor devices Q2 and Q5 and the semiconductor devices Q3 and Q6 applicable to the power module according to the embodiment.

As the semiconductor devices Q1 to Q6, a SiC power device such as a SiC DIMOSFET or a SiC TMOSFET, or a GaN power device such as a GaN-based HEMT, which will be described later, can be applied. In some cases, power devices such as Si-based MOSFETs and SiC-based IGBTs can also be applied.

-SiC DIMOSFET-
An example of a semiconductor device applicable to the power module according to the embodiment, the schematic cross-sectional structure of the SiC DIMOSFET 130C is shown as shown in FIG.

The SiC DIMOSFET 130C shown in FIG. 21 has a ^{semiconductor layer 31 composed of an n-} high resistance layer, a p-body region 32 formed on the surface side of the semiconductor layer 31, and an n ⁺ source region formed on the surface of the p-body region 32. The gate insulating film 34 arranged on the surface of the semiconductor layer 31 between the 33 and the p-body region 32, the gate electrode 35 arranged on the gate insulating film 34, and the source region 33 and the p-body region 32 are connected to each other. ^{The source electrode 36 is provided with an n +} drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31, and a drain electrode 38 connected to the ^{n + drain region 37.}

In FIG. 21, the SiC DIMOSFET 130C has a p-body region 32 and an n ⁺ source region 33 formed on the surface of the p-body region 32 formed by double ion implantation (DII), and the source pad electrode SPD has a source region 33. And connected to the source electrode 36 connected to the p-body region 32.

The gate pad electrode GPD (not shown) is connected to the gate electrode 35 arranged on the gate insulating film 34. Further, as shown in FIG. 21, the source pad electrode SPD and the gate pad electrode GPD are arranged on the interlayer insulating film 39 for passivation so as to cover the surface of the SiC DIMOSFET 130C.

As shown in FIG. 21, the SiC DIMOSFET 130C has a junction FET (junction FET) because a depletion layer as shown by a broken line is formed in a semiconductor layer 31 composed of ^{an n-high resistance layer sandwiched between p body regions 32.} _{A channel resistor R JFET} is formed with the JFET) effect. Further, as shown in FIG. 21, a body diode BD is formed between the p-body region 32 and the semiconductor layer 31.

-SiC TMOSFET-
An example of a semiconductor device applicable to the power module according to the embodiment, the schematic cross-sectional structure of the SiC TMOSFET 130D is shown as shown in FIG.

The SiC TMOSFET 130D shown in FIG. 22 includes a semiconductor layer 31N composed of n layers, a p-body region 32 formed on the surface side of the semiconductor layer 31N, and an n ⁺ source region 33 formed on the surface of the p-body region 32. The trench gate electrode 35TG formed through the p-body region 32 and formed through the gate insulating film 34 and the interlayer insulating films 39U / 39B in the trench formed up to the semiconductor layer 31N, and the source region 33 and the p-body region 32. ^{It includes a connected source electrode 36, an n +} drain region 37 arranged on the back surface opposite to the front surface of the semiconductor layer 31N, and a drain electrode 38 connected to the ^{n + drain region 37.}

In FIG. 22, the SiC TMOSFET 130D penetrates the p-body region 32, and the trench gate electrode 35TG is formed in the trench formed up to the semiconductor layer 31N via the gate insulating film 34 and the interlayer insulating films 39U / 39B, and the source pad is formed. The electrode SPD is connected to the source electrode 36 connected to the source region 33 and the p-body region 32.

The gate pad electrode GPD (not shown) is connected to the trench gate electrode 35TG arranged on the gate insulating film 34. Further, as shown in FIG. 20, the source pad electrode SPD and the gate pad electrode GPD are arranged on the passivation interlayer insulating film 39U so as to cover the surface of the SiC TMOSFET 130D.

In the SiC TMOSFET 130D, the channel resistor R _JFET associated with the JFET effect like the SiC DIMOSFET 130C is not formed. A body diode BD is formed between the p-body region 32 and the semiconductor layer 31N as in FIG. 21.

(Application example)
In the circuit configuration of the three-phase AC inverter 40A configured by using the power module according to the embodiment, a circuit configuration example in which a SiC MOSFET is applied as a semiconductor device and a snubber capacitor C is connected between the power supply terminal PL and the ground terminal NL is shown. , As shown in FIG. 23 (a). Similarly, a circuit configuration example of a three-phase AC inverter 40B in which an IGBT is applied as a semiconductor device and a snubber capacitor C is connected between the power supply terminal PL and the ground terminal NL is shown in FIG. 23 (b).

When the power module is connected to the power supply E and the switching operation is performed, the switching speed of the SiC MOSFET or the IGBT is high due to the inductance L of the connection line, so that a large surge voltage Ldi / dt is generated. For example, if the current change di = 300A and the time change dt = 100nsec accompanying switching, then di / dt = 3 × 10 ⁹ (A / s).

The value of the surge voltage Ldi / dt changes depending on the value of the inductance L, but the surge voltage Ldi / dt is superimposed on the power supply E. This surge voltage Ldi / dt can be absorbed by the snubber capacitor C connected between the power supply terminal PL and the ground terminal NL.

(Concrete example)
Next, with reference to FIG. 24, a three-phase AC inverter 42B to which a SiC MOSFET is applied as a semiconductor device will be described.

As shown in FIG. 24, the three-phase AC inverter 42A includes a power module unit 200 in which a plurality of switching elements are formed, a gate driver (GD) 180 for controlling the switching operation of each switching element, and each switching element. A three-phase AC motor unit 51 to which the outputs of the above are connected, a power supply or a storage battery (E) 53, and a converter 55 that converts the power of the power supply 53 and supplies power to each switching element. In the power module unit 200, U-phase, V-phase, and W-phase inverters are connected corresponding to the U-phase, V-phase, and W-phase of the three-phase AC motor unit 51.

Here, the GD180 is connected to each gate terminal of the SiC MOSFETs Q1 and Q4, the SiC MOSFETs Q2 and Q5, and the SiC MOSFETs Q3 and Q6, respectively, and controls the switching operation of each MOSFET.

The power module unit 200 is connected between the positive terminal (+) P and the negative terminal (-) N of the converter 55 to which the power supply or the storage battery (E) 53 is connected, and has an inverter configuration of SiC MOSFETs Q1, Q4, Q2, and so on. It includes Q5 and Q3 / Q6. Further, freewheel diodes DI1 to DI6 are connected in antiparallel between the source and drain of the SiC MOSFETs Q1 to Q6, respectively.

Next, with reference to FIG. 25, a three-phase AC inverter 42B configured by applying an IGBT as a semiconductor device and using the power module according to the embodiment will be described.

As shown in FIG. 25, the three-phase AC inverter 42B includes a power module unit 200, a GD 180, a three-phase AC motor unit 51, a power supply or a storage battery (E) 53, and a converter 55. In the power module unit 200, U-phase, V-phase, and W-phase inverters are connected corresponding to the U-phase, V-phase, and W-phase of the three-phase AC motor unit 51.

Here, the GD180 is connected to the IGBT Q1 · Q4, the IGBT Q2 · Q5, and the IGBT Q3 · Q6.

The power module unit 200 is connected between the positive terminal (+) P and the negative terminal (-) N of the converter 55 to which the storage battery (E) 53 is connected, and has an inverter configuration IGBT Q1 / Q4, Q2 / Q5, And Q3 and Q6 are provided. Further, freewheel diodes DI1 to DI6 are connected in antiparallel between the emitter and collector of the IGBTs Q1 to Q6, respectively.

[Another Embodiment 1]
Some power modules to which the configuration for suppressing warpage as described above can be applied will be illustrated. Even in the power module illustrated below, it is possible to use a graphite substrate as the substrate, laminate the resin on the graphite substrate, and match the CTE in the X and Y directions of the resin with the CTE in the X and Y directions of the graphite substrate. Is. In the following description, the power module may be referred to as "PM".

In PM1 according to the embodiment, a schematic bird's-eye view pattern configuration before the resin mold is shown as shown in FIG. Here, as a power device-based semiconductor device (power device), a 2 in 1 module type half-bridge built-in module to which SiC MOSFETs Q1 and Q4 are applied will be described as an example.

A schematic bird's-eye view configuration of the PM1 according to the embodiment after resin molding of the module with a built-in half bridge as a mold type module is shown as shown in FIG. 27.

The PM1 according to the embodiment includes a half-bridge built-in module in which two SiC MOSFETs Q1 and Q4 connected in series are built in one module.

As shown in FIG. 27, PM1 according to the embodiment has a positive power input terminal electrode (positive power terminal) P arranged on the first side of the ceramic substrate 21 coated on the resin mold layer 115 and a negative power terminal. Side power input terminal electrode (negative power terminal) N, gate terminal (gate) GT1 and source sense terminal SST1 arranged on the second side adjacent to the first side, and the first side facing the first side. It includes an output terminal electrode (output terminal) O arranged on the side 3 and a gate terminal GT4 and a source sense terminal SST4 arranged on the fourth side facing the second side.

The PM1 according to the embodiment is a power module having a 4-power terminal structure including two output terminals O.

Here, as shown in FIGS. 26 to 27, the gate terminal GT1 and the source sense terminal SST1 are connected to the gate signal electrode pattern GL1 and the source signal electrode pattern SL1 of the SiC MOSFET Q1, and the gate terminal GT4 and the source sense terminal SST4 are connected. , SiC MOSFET Q4 is connected to the gate signal electrode pattern GL4 and the source signal electrode pattern SL4.

As shown in FIGS. 26 to 27, the gate signal electrode patterns GL1 and GL4 and the source signal electrode patterns SL1 and SL4 are connected to the gate terminals GT1 and GT4 for external extraction and the source sense terminals SST1 and SST4 by soldering or the like. Will be done.

As shown in FIGS. 26 to 27, the gate signal electrode patterns GL1 and GL4 and the source signal electrode patterns SL1 and SL4 are arranged on the signal substrates 261, 264, and the signal substrates 261, 264 are soldered on the ceramic substrate 21. It is connected by soldering.

The signal substrates 261, 264 can be formed of a ceramic substrate. The ceramic substrate may be formed of, for example, Al2O3, AlN, SiN, AlSiC, or at least SiC having an insulating surface.

Further, although not shown in FIGS. 26 to 27, diodes may be connected in antiparallel between D1 and S1 and between D4 and S4 of the SiC MOSFETs Q1 and Q4.

The positive power terminal P / negative power terminal N, the gate terminals GT1 / GT4 for external extraction, and the source sense terminals SST1 / SST4 can be formed by, for example, Cu.

The electrode patterns 25D1, 25D4, and 25DN, which are the main wiring conductors, can be formed by, for example, Cu.

Here, in the example shown in FIGS. 26 to 27, in the module with a built-in half bridge of the 2 in 1 module type, the electrode pattern 25D1 functions as a drain electrode pattern for the high side device (SiC MOSFET Q1). ..

Further, the electrode pattern 25D4 functions as a drain electrode pattern for the low side device (SiC MOSFETQ4) and also as a source electrode pattern (25S1) for the high side device. That is, the drain electrode pattern 25D4 is a drain electrode of the SiC MOSFET Q4 and at the same time a source electrode of the SiC MOSFET Q1.

Further, the electrode pattern 25DN connected to the negative power terminal N also functions as a source electrode pattern (25S4) for the row side device.

That is, in PM1 according to the embodiment, as shown in FIGS. 26 to 27, the SiC MOSFET Q1 is mounted on the electrode pattern 25D1, the drain D1 is connected to the electrode pattern 25D1, and the source S1 is the lead frame. It is connected to the electrode pattern 25D4 via SM1. Similarly, the SiC MOSFET Q4 is mounted on the electrode pattern 25D4, the drain D4 is connected to the electrode pattern 25D4, and the source S4 is connected to the electrode pattern 25DN via the lead frame SM4.

In the following description, the joint between the source pad electrode SP1 and the lead frame SM1 is the device-side joint (first joint) DC, separated from the device-side joint DC, and generates more heat than the device-side joint DC. The joint portion between the lead frame SM1 and the source electrode pattern 25S1 which are less affected by the above and have a relatively low temperature is referred to as a land side joint portion (second joint portion) SC.

As shown in FIGS. 26 to 27, in the PM1 according to the embodiment, the source sense bonding wire (first bonding) for connecting the lead frame SM1 to the source signal electrode pattern SL1 on the land side bonding portion SC side. A wire) SSW1 and a gate signal bonding wire (second bonding wire) GW1 for connecting the gate pad electrode GP1 to the gate signal electrode pattern GL1 on the device-side bonding portion DC side facing the land-side bonding portion SC.

Similarly, on the land side bonding portion SC side, the source sense bonding wire (first bonding wire) SSW4 for connecting the lead frame SM4 to the source signal electrode pattern SL4 and the device side bonding portion DC facing the land side bonding portion SC. On the side, a gate signal bonding wire (second bonding wire) GW4 for connecting the gate pad electrode GP4 to the gate signal electrode pattern GL4 is provided.

The schematic bird's-eye view pattern configuration of the six-in-one (6 in 1) module of PM2 according to the embodiment is shown as shown in FIG. 28.

The PM2 according to the embodiment is an example in which three PM1s are arranged in parallel on a common ceramic substrate 21A to form a 6 in 1 module type switching module.

Here, in the case of a 6 in 1 module type switching module, the basic structure is the same as that of the 1 in 1 module type PM and the 2 in 1 module type PM. That is, in the PM2 according to the embodiment, the 6 in 1 module type switching module includes 2 in 1 module type PM11 / 12/13 as shown in FIG. 28.

PM11 is equipped with, for example, SiC MOSFETs Q1 and Q4 as semiconductor devices, PM12 is equipped with, for example, SiC MOSFETs Q2 and Q5, PM13 is equipped with, for example, SiC MOSFETs Q3 and Q6, and PM11, 12 and 13 are the same as PM1. Yes, detailed explanation is omitted.

In the PM2 according to the embodiment, as the 6 in 1 module type switching module, for example, the 2 in 1 module type PM11 / 12/13 are integrally formed by a common mold resin or a case (not shown). It has a sealed structure.

That is, in the 6 in 1 module type switching module (PM2 according to the embodiment), PM11, 12 and 13 are arranged in parallel on the common ceramic substrate 21A and integrated package (resin mold layer (not shown)). ), And the back surface electrode pattern 23R can be shared (integrated).

Alternatively, 2 in 1 module type PM11, 12 and 13 sealed separately by individual mold resins or cases are further arranged in parallel on a common ceramic substrate 21A to form a 6 in 1 module type switching module. It is also possible to.

Even when the PM2 configuration (6 in 1 module type switching module) according to such an embodiment is adopted, as shown in FIG. 28, the source pad electrodes SP1, SP4, SP2, and so on are formed in PM11 / 12/13. Lead frames SM1 / SM4 connected between SP5, SP3 / SP6 and the source electrode patterns 25S1 (25D4) / 25S4 (25DN), 25S2 (25D5) / 25S5 (25DN), 25S3 (25D6) / 25S6 (25DN). , SM2 / SM5, SM3 / SM6, and the lead frames SM1 / SM4, SM2 / SM5, SM3 / SM6 of the land side junction SC and the source signal electrode patterns SL1 / SL4, SL2 / SL5, SL3 / SL6. By providing the bonding wires SSW1 / SSW4, SSW2 / SSW5, and SSW3 / SSW6 for source sense, the influence of heat on the wire connection due to the operation of high temperature can be reduced, and the heat resistance and reliability of the wire connectivity can be improved. It is possible to improve.

The source sense bonding wires SSW1 / SSW4, SSW2 / SSW5, SSW3 / SSW6 have source electrode patterns 25S1 (25D4) / 25S4 (25DN), 25S2 (25D5) / 25S5 (25DN) on the land side bonding portion SC side. , 25S3 (25D6) and 25S6 (25DN) may be connected.

[Another Embodiment 2]
In PM1 according to the embodiment, the schematic bird's-eye view pattern configuration before wire bonding and resin molding is shown as shown in FIG. 29 (a), and the schematic plane pattern configuration is shown as shown in FIG. 29 (b). It is represented by. Note that FIGS. 29 (a) and 29 (b) show specific examples of the arrangement of semiconductor devices in PM1, and are 2 in 1 module types to which SiC MOSFETs Q1 and Q4 are applied as semiconductor devices Q. A module with a built-in half bridge is illustrated.

That is, the PM1 according to the embodiment includes a half-bridge built-in module in which two SiC MOSFETs Q1 and Q4 connected in series are built in one module.

PM1 according to the embodiment includes a positive power input terminal electrode (positive power terminal) P and a negative power input terminal electrode arranged on the first side of a ceramic substrate 21 coated with a resin mold layer (not shown). The (negative power terminal) N, the gate terminal GT1 (gate G1) and the source sense terminal SST1 (source S1) arranged on the second side adjacent to the first side, and the second side facing the first side. The output terminal electrode (output terminal) O arranged on the side of 3 and the gate terminal GT4 (gate G4) and the source sense terminal SST4 (source S4) arranged on the fourth side facing the second side are connected to each other. Be prepared.

The PM1 according to the embodiment is a power module having a 4-power terminal structure including two output terminals O.

Here, as shown in FIGS. 29 (a) and 29 (b), the two (set) SiC MOSFETs Q1 and Q4 each include three devices (chips), and each chip of the SiC MOSFET Q1 has a gate terminal. It is commonly connected to the GT1 and the source sense terminal SST1 (the connection of the GT1 is not displayed), and each chip of the SiC MOSFET Q4 is commonly connected to the gate terminal GT4 and the source sense terminal SST4 (the connection of the GT4 is not displayed).

The gate terminal GT1 and the source sense terminal SST1 are connected to the gate signal electrode pattern GL1 and the source signal electrode pattern SL1 of the SiC MOSFET Q1, and the gate terminal GT4 and the source sense terminal SST4 are the gate signal electrode pattern GL4 and the source signal electrode of the SiC MOSFET Q4. Connected to pattern SL4.

As shown in FIGS. 29 (a) and 29 (b), the gate signal electrode patterns GL1 and GL4 and the source signal electrode patterns SL1 and SL4 have gate terminals GT1 and GT4 for external extraction and source sense terminals SST1 and SST4. Is connected by soldering or the like.

As shown in FIGS. 29 (a) and 29 (b), the gate signal electrode patterns GL1 and GL4 and the source signal electrode patterns SL1 and SL4 are arranged on the signal boards 261, 264, and the signal boards 261 and 264 are It may be connected to the ceramic substrate 21 by soldering or the like.

The signal substrates 261, 264 can be formed of a ceramic substrate. The ceramic substrate may be formed of, for example, Al2O3, AlN, SiN, AlSiC, or at least SiC having an insulating surface.

Although not shown in FIGS. 29 (a) and 29 (b), diodes (DI1. DI4) may be connected.

The positive power terminal P / negative power terminal N, the gate terminals GT1 / GT4 for external extraction, and the source sense terminals SST1 / SST4 can be formed by, for example, Cu.

The surface electrode pattern 23 (23D1, 23D4, 23DN) which is the main wiring conductor can be formed by, for example, Cu.

Here, in the example shown in FIGS. 29 (a) and 29 (b), in the module with a built-in half bridge of the 2 in 1 module type, the surface electrode pattern 23D1 is for the high side device (SiC MOSFET Q1). Functions as a drain electrode pattern.

Further, the surface electrode pattern 23D4 functions as a drain electrode pattern for the low side device (SiC MOSFETQ4) and also as a source electrode pattern (23S1) for the high side device. That is, the drain electrode pattern 23D4 is a drain electrode of the SiC MOSFET Q4 and at the same time a source electrode of the SiC MOSFET Q1.

Further, the surface electrode pattern 23DN connected to the negative power terminal N functions as a source electrode pattern (23S4) for the row side device.

That is, in PM1 according to the embodiment, as shown in FIGS. 29 (a) and 29 (b), the SiC MOSFET Q1 is mounted on the surface electrode pattern 23D1 and the drain D1 is connected to the surface electrode pattern 23D1. At the same time, the source S1 is connected to the surface electrode pattern 23D4 via a bonding wire (bonding wire for a source signal (not shown)).

Similarly, the SiC MOSFET Q4 is mounted on the surface electrode pattern 23D4, the drain D4 is connected to the surface electrode pattern 23D4, and the source S4 is connected to the surface electrode pattern via a bonding wire (bonding wire for source signal (not shown)). Connected to 23DN.

Further, in PM1 according to the embodiment, although not shown, the source sense bonding wire for connecting the source sense pad electrode of the SiC MOSFET Q1 to the source signal electrode pattern SL1 and the gate pad electrode are connected to the gate signal electrode pattern. It includes a bonding wire for a gate signal connected to GL1.

Similarly, although not shown, a source sense bonding wire that connects the source sense pad electrode of the SiC MOSFET Q4 to the source signal electrode pattern SL4, and a gate signal bonding wire that connects the gate pad electrode to the gate signal electrode pattern GL4. To be equipped.

That is, a source sense bonding wire for connecting the source sense pad electrode is wedge-bonded to the source signal electrode patterns SL1 and SL4 of the SiC MOSFETs Q1 and Q4.

As shown in FIGS. 29 (a) and 29 (b), PM1 according to the embodiment includes a ceramic substrate 21, a graphite substrate 18GH arranged on the upper surface (first surface) of the ceramic substrate 21, and a graphite substrate. A surface electrode pattern (second electrode pattern) 23D1, 23D4, 23DN arranged on 18GH and a back surface electrode pattern (first electrode pattern) (not shown) arranged on the lower surface (second surface) of the ceramic substrate 21. A graphite insulating substrate comprising the above, and a plurality of SiC MOSFETs Q1 and Q4 arranged side by side along the direction of the arrow X shown on the surface electrode patterns 23D1 and 23D4.

In PM1 according to the embodiment, the GH (YZ) orientation of the graphite substrate 18GH is an orientation direction TD that is substantially orthogonal to the X direction of the arrangement of the plurality of SiC MOSFETs Q1 and Q4 and substantially coincides with the Y direction. That is, the allowable amount of deviation (allowable deviation amount) of the alignment direction PD1 of the SiC MOSFETs Q1 and Q4 arranged side by side in the X direction with respect to the orientation direction TD of GH (YZ) is the orientation direction PD corresponding to the X direction. On the plane (board surface) of the graphite substrate 18GH, a range of an angle θ of about −45 degrees or more and +45 degrees or less in the clockwise direction, preferably a range of an angle θ of about -30 degrees or more and +30 degrees or less. Will be done.

In FIGS. 29 (a) and 29 (b), when the semiconductor device Q is a SiC MOSFET, the GT1 and GT4 are lead terminals (so-called gate terminals) for the gate signals of the SiC MOSFETs Q1 and Q4, and SST1 The SST4 is a lead terminal (so-called source sense terminal) for the source signal of the SiC MOSFETs Q1 and Q4.

On the other hand, in the case of the IGBT, the GT1 and GT4 serve as lead terminals for the gate signals of the IGBT Q1 and Q4, and the SST1 and SST4 serve as lead terminals for the emitter signals of the IGBT Q1 and Q4.

According to PM1 according to the embodiment, by adopting the graphite insulating substrate to which the graphite substrate 18GH is applied, the direction PD1 of the arrangement of the plurality of semiconductor devices Q is set to the GH (XZ) / GH (YZ) orientation of the graphite substrate 18GH. A high thermal diffusion effect can be expected by approximating the orientation direction PD, which has a relatively low thermal conductivity and is substantially orthogonal to the orientation direction TD.

That is, the PM1 according to the embodiment can also be used as a power module having good thermal diffusivity, structurally simple, inexpensive, and capable of lowering thermal resistance.

The 2 in 1 module type PM1 can be applied to a structure in which a source electrode pattern is provided above the semiconductor devices Q1 and Q4, and is also limited to a 2 in 1 module type PM1. Absent.

The schematic bird's-eye view pattern configuration of PM1 according to the embodiment is shown as shown in FIG. 30 (a), and the schematic plane pattern configuration is shown as shown in FIG. 30 (b). In addition, in FIG. 30A and FIG. 30B, the case where it is applied to PM1 of the three-power terminal structure is illustrated.

Here, as shown in FIGS. 30A and 30B, the PM1 according to the embodiment has substantially the same configuration as the PM1 according to the embodiment except for the power terminal structure.

That is, as shown in FIGS. 30 (a) and 30 (b), the PM1 according to the embodiment includes the ceramic substrate 21, the graphite substrate 18GH arranged on the upper surface (first surface) of the ceramic substrate 21, and the graphite substrate 18GH. The surface electrode pattern (second electrode pattern) 23D1, 23D4, 23DN arranged on the graphite substrate 18GH and the back surface electrode pattern (first electrode pattern) arranged on the lower surface (second surface) of the ceramics substrate 21 (not shown). ), And a plurality of semiconductor devices (modules) Q1 and Q4 arranged side by side along the direction of the arrow X shown on the surface electrode patterns 23D1 and 23D4.

In PM1 according to the embodiment, the GH (YZ) orientation in the orientation direction TD of the graphite substrate 18GH is a direction substantially orthogonal to the orientation direction PD along the X direction of the plurality of semiconductor devices Q1 and Q4.

In FIGS. 30 (a) and 30 (b), P is a positive power input terminal electrode, N is a negative power input terminal electrode, and O is an output terminal electrode, which is one output. It is a PM with a three-power terminal structure equipped with a terminal electrode O.

In FIGS. 30A and 30B, GL1 is a gate signal electrode pattern to which a lead terminal (not shown) for a gate signal of SiC MOSFET Q1 is connected, and SL1 is a source signal of SiC MOSFET Q1. It is a source signal electrode pattern to which a lead terminal (not shown) is connected. Similarly, GL4 is a gate signal electrode pattern to which a lead terminal for a gate signal of SiC MOSFETQ4 (not shown) is connected, and SL4 is connected to a lead terminal for a source signal of SiC MOSFETQ4 (not shown). Source signal electrode pattern.

Further, BW1 in the figure is a bonding wire for a source signal for connecting the source pad electrode of SiC MOSFET Q1 to the surface electrode pattern 23D4 which also functions as a source electrode, and BW4 is a bonding wire for a source signal of SiC MOSFET Q4. It is a bonding wire for a source signal for being commonly connected to a surface electrode pattern 23DN that also functions as a source electrode.

Also in the PM1 according to the embodiment, the orientation PD1 of the arrangement of the plurality of semiconductor devices Q1 and Q4 on the substrate surface of the graphite substrate 18GH is set to the orientation direction (Y direction) TD corresponding to the GH (YZ) orientation of the graphite substrate 18GH. By setting the PD in the orientation direction (X direction) substantially orthogonal to the above, the thermal diffusivity is good, the structure is simple, the cost is low, and the thermal resistance can be further reduced.

As described above, according to the present embodiment, it is possible to provide a power module capable of suppressing warpage and a method for manufacturing the power module.

[Other embodiments]
As mentioned above, some embodiments have been described, but the statements and drawings that form part of the disclosure are exemplary and should not be understood to be limiting. This disclosure will reveal to those skilled in the art various alternative embodiments, examples and operational techniques.

As described above, the present embodiment includes various embodiments not described here.

The power module of this embodiment can be used for various semiconductor module technologies such as an IGBT module, a diode module, and a MOS module using a Si substrate, a SiC substrate, or a GaN substrate, and can be used for HEV (Hybrid Electric Vehicle) / EV. It can be applied to a wide range of application fields such as inverters for (Electric Vehicles), industrial equipment such as robots, and inverters and converters for home appliances.

61, 69, GF ... Substrate (graphite substrate)
64 ... Semiconductor device 62, RA, RB, RC, RD ... Resin (thermoplastic resin, liquid crystal polymer)
71, 72 ... (resin) injection gate 71B, 72B ... gate marks 71A, 72A ... (resin) injection direction 63, 68 ... copper layer 64 ... semiconductor device 65 ... wire 66 ... power terminal 67 ... spacer (columnar electrode)

Claims (20)

A substrate having anisotropy in the coefficient of thermal expansion and
The semiconductor device mounted on the substrate and
A resin laminated on the substrate and sealing the semiconductor device is provided.
When the arbitrary direction of the surface of the substrate on which the semiconductor device is mounted is the X direction, and the direction orthogonal to the X direction is the Y direction.
The substrate has a smaller coefficient of thermal expansion in the Y direction than the X direction.
The resin is a power module characterized in that the coefficient of thermal expansion is smaller in the Y direction than in the X direction. The power module according to claim 1, wherein the substrate is a graphite substrate. The power module according to claim 2, wherein the graphite substrate has an orientation in which the thermal conductivity is relatively higher in the thickness direction than in the plane direction. The power module according to any one of claims 1 to 3, wherein the resin is a thermoplastic resin. The power module according to claim 4, wherein the thermoplastic resin is a liquid crystal polymer. The resin of the power module is molded by injection molding.
The resin is anisotropy so that the coefficient of thermal expansion in the direction along the injection direction at the time of molding is small, and has a gate mark when the injection gate is arranged at one end in the direction of the low coefficient of thermal expansion of the substrate. The power module according to any one of claims 1 to 5, which is characterized. The power module according to claim 6, wherein the resin injection direction is −45 degrees or more and +45 degrees or less with respect to the Y direction. A copper layer having a wiring pattern is formed on the substrate, and a copper layer having a wiring pattern is formed.
The semiconductor device is mounted on the copper layer,
The semiconductor device is connected to the power terminal and the output terminal,
The power module according to any one of claims 1 to 7, wherein the power module is sealed with the resin except for a part of each terminal. The power module according to any one of claims 1 to 8, wherein the power module includes any one of a Si-based or SiC-based IGBT, a diode, a MOSFET, and a GaN-based FET. The power module comprises any one of a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, and a fourteen-in-one module. The power module according to any one of 9 to 9. The process of forming a substrate having anisotropy in the coefficient of thermal expansion,
The process of mounting a semiconductor device on the substrate and
It has a step of laminating a resin on the substrate so as to seal the semiconductor device.
When the arbitrary direction of the substrate surface is the X direction and the direction orthogonal to the X direction is the Y direction,
The substrate is formed so that the coefficient of thermal expansion is smaller in the Y direction than in the X direction.
A method for manufacturing a power module, wherein the resin is formed by injecting the resin from one end in the Y direction. The method for manufacturing a power module according to claim 11, wherein the substrate is a graphite substrate. The method for manufacturing a power module according to claim 12, wherein the graphite substrate has an orientation in which the thermal conductivity is relatively higher in the thickness direction than in the plane direction. The method for manufacturing a power module according to any one of claims 11 to 13, wherein the resin is a thermoplastic resin. The method for manufacturing a power module according to claim 14, wherein the thermoplastic resin is a liquid crystal polymer. The power module is molded by injection molding.
The claim is characterized in that the resin is anisotropy so as to have a low coefficient of thermal expansion along the injection direction at the time of molding, and the injection gate is arranged in the same direction as the direction of the low coefficient of thermal expansion of the substrate. The method for manufacturing a power module according to any one of 11 to 15. The method for manufacturing a power module according to claim 16, wherein the injection direction of the resin is −45 degrees or more and +45 degrees or less with respect to the Y direction. A step of arranging a second substrate above the semiconductor device so as to face the substrate, and
Any of claims 11 to 17, further comprising a step of sealing with the resin except for a part of each terminal, the substrate, and a surface opposite to the opposite surface of the second substrate. The method for manufacturing a power module according to item 1. The method for manufacturing a power module according to any one of claims 11 to 18, wherein the power module includes any one of a Si-based or SiC-based IGBT, a diode, a MOSFET, and a GaN-based FET. 11. The power module comprises any one of a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, and a fourteen-in-one module. The method for manufacturing a power module according to any one of 19 to 19.

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