JP6871241B2 - Devices and methods for driving displays - Google Patents

Description

(Refer to related applications)
This application claims the interests of US Provisional Application No. 62 / 219,606 filed on September 16, 2015.

The present application is also related to US Provisional Application No. 62 / 370,703 filed on August 3, 2016, which in itself is US Provisional Application No. 62 / filed on November 30, 2015. It is related to Nos. 261 and 104, and US Provisional Application Nos. 62 / 111,927 filed on February 4, 2015.

The present application is further related to the co-pending application No. 15 / 014,236 filed on February 4, 2015. The entire disclosure of the above application and all US patents and published and co-pending applications referenced below is also incorporated herein by reference.

The present invention relates to a method for driving a bistable electro-optical display and a device for use in such a method. More specifically, the present invention relates to a driving method and a device for adjusting a gate-on voltage value after an active update so as to reduce transistor degradation associated with voltage stress that can be caused by residual voltage discharge.

According to one aspect of the subject matter disclosed herein, a device for driving an electro-optical display is a first switch designed to supply a voltage to the electro-optical display during the first drive phase. , Combined with a second switch designed to control the voltage during the second drive phase and with the first and second switches to control the rate of voltage decay during the second drive phase. It may be equipped with a resistor. In some embodiments, only one of the first and second switches is engaged during the first or second driving phase. In yet some other embodiments, both the first and second switches are engaged and disengaged during the third driving phase.
The present specification provides, for example, the following.
(Item 1)
A device for driving an electro-optical display
A first switch designed to supply voltage to the electro-optic display during the first drive phase,
A second switch designed to control the voltage during the second drive phase,
A resistor coupled to the first and second switches to control the decay rate of the voltage during the second drive phase.
A device that comprises.
(Item 2)
The device of item 1, wherein only one of the first and second switches is engaged during the first or second driving phase.
(Item 3)
The apparatus of item 1, further comprising a capacitor coupled to the resistor in the second drive phase to control the attenuation of the voltage.
(Item 4)
The apparatus according to item 4, further comprising a resistor arranged in series with the capacitor in the second drive phase to control the attenuation of the voltage.
(Item 5)
The apparatus of item 2, further comprising a resistor coupled to the capacitor in series to control the attenuation of the voltage during the second drive phase.
(Item 6)
The device of item 1, wherein the first and second switches are engaged and disengaged during the third drive phase.
(Item 7)
10. The apparatus of item 10, further comprising a capacitor coupled to the resistor to control the attenuation of the voltage during the second and third drive phases.
(Item 8)
10. The apparatus of item 10, further comprising a resistor arranged in series with the capacitor to control the attenuation of the voltage during the second and third drive phases.
(Item 9)
A method for driving an electro-optical display,
A step of engaging the first switch of the control circuit and supplying a voltage to the electro-optical display during the first drive phase,
A step of engaging the second switch of the control circuit and controlling the voltage during the second drive phase,
A step of engaging and disengaging the first switch during the second drive phase and allowing a resistor coupled to the control circuit to control the attenuation of the voltage.
Including methods.
(Item 10)
13. The method of item 13, further comprising controlling the attenuation of the voltage through a capacitor coupled to the control circuit.
(Item 11)
13. The method of item 13, wherein the capacitor is in parallel with the resistor.
(Item 12)
13. The method of item 13, further comprising connecting a resistor in series with the capacitor and controlling the attenuation of the second voltage.
(Item 13)
13. The method of item 13, further comprising coupling a diode to the resistor to control the attenuation of the second voltage.
(Item 14)
13. The method of item 13, further comprising engaging and disengaging the first and second switches in a third driving phase to control the attenuation of the voltage.
(Item 15)
The method according to item 13, wherein the electro-optical display is an electrophoretic display.

Various aspects and embodiments of the present application will be described with reference to the following figures. It should be understood that the figures are not necessarily drawn to a certain scale. Articles appearing in multiple figures are indicated by the same reference number in all figures in which they appear.

FIG. 1A is a schematic diagram of a simple gate-on voltage electrical circuit for an electro-optical display according to some embodiments. FIG. 1B is a graph showing, according to some embodiments, the gate-on voltage relative to the time in the voltage decay phase, including the active update and post-drive discharge phases, where the gate-on voltage decays exponentially to ground. FIG. 1C is a graph showing the gate-on voltage relative to time in a voltage decay phase with active updates and a preferred voltage profile, according to some embodiments. FIG. 2A is a schematic representation of a gate-on voltage electrical circuit for an electro-optical display, including a resistor, according to some embodiments. FIG. 2B is a schematic schematic diagram illustrating the gate-on voltage over time for the circuit of FIG. 2A, according to some embodiments. FIG. 3A is a schematic representation of a gate-on voltage electrical circuit for an electro-optical display, including a resistor and a capacitor, according to some embodiments. FIG. 3B is a schematic schematic diagram illustrating the gate-on voltage over time for the circuit of FIG. 3A, according to some embodiments. FIG. 4A is a schematic representation of a gate-on voltage electrical circuit for an electro-optical display, including a resistor and a capacitor, according to some embodiments. FIG. 4B is a schematic schematic diagram illustrating the gate-on voltage over time for the circuit of FIG. 4A, according to some embodiments. FIG. 5A is a schematic representation of a gate-on voltage electrical circuit for an electro-optical display, including a resistor and a capacitor, according to some embodiments. FIG. 5B is a schematic representation of a gate-on voltage electrical circuit for an electro-optical display, including a resistor and a capacitor, according to some embodiments. FIG. 6A is a schematic representation of a gate-on voltage electrical circuit for an electro-optical display, including a plurality of capacitors and resistors, according to some embodiments. FIG. 6B is a schematic schematic diagram illustrating the gate-on voltage over time for the circuit of FIG. 6A, according to some embodiments. FIG. 7 is a schematic representation of a gate-on voltage electrical circuit for an electro-optical display, including a Zener diode, according to some embodiments. FIG. 8A is a schematic representation of a gate-on voltage electrical circuit for an electro-optical display, including a resistor and a capacitor, according to some embodiments. FIG. 8B is a schematic schematic diagram illustrating the gate-on voltage over time for the circuit of FIG. 8A, according to some embodiments. FIG. 9 is a schematic illustration of a comparison of the performance of the device illustrated in FIG. 8A with a conventional device. FIG. 10A is a graph showing the maximum gray tone shift for some updates, with and without residual voltage discharge, according to some embodiments. FIG. 10B is a graph showing the maximum afterglow deviation for some updates, with and without residual discharge, according to some embodiments. FIG. 11A is a graph showing the maximum gray tone shift for some updates with residual discharge, without residual discharge, and with residual discharge and negative bias, according to some embodiments. FIG. 11B is a graph showing the maximum afterglow shift for some updates, with residual discharge, without residual discharge, and with residual voltage discharge and reduced negative bias, according to some embodiments. is there. FIG. 12A is a schematic diagram of a signal timing diagram showing the gate voltage over time according to some embodiments. FIG. 12B is a schematic diagram of a signal timing diagram showing a voltage over time according to some embodiments.

The term electro-optical display comprises a layer of electro-optical material, the term of which is, in its conventional sense in imaging technology, a material having at least one different optical property with first and second display states. As used herein, it refers to a material that changes from its first display state to its second display state upon application of an electric field to. In the displays of the present disclosure, the electro-optical medium can be solid in the sense that the electro-optic medium has a solid outer surface (such a display may be hereafter referred to as a "solid-state electro-optical display" for convenience). The medium can have an internal liquid or gas filled space, often with it. Thus, the term "solid-state electro-optical display" includes encapsulated electrophoresis displays, encapsulated liquid crystal displays, and other types of displays discussed below.

The optical properties may be colors that are perceptible to the human eye, but this is the length of electromagnetic waves outside the visible range for displays intended for light transmission, reflectance, light emission, or machine reading. It may have another optical property such as pseudocolor in the sense of a change in reflectance. The term "L star" may be used herein and may be represented by ^{"L *".} L ^* has the usual CIE definition, L ^* = 116 (R / R0) l / 3-16, where R is the reflectance and R0 is the standard reflectance value.

The term "gray state" is used herein to refer to a state intermediate between the two extreme optical states of a pixel in its conventional sense in imaging technology, not necessarily black-white between these two extreme states. It does not imply a transition. For example, some of the patent and publication applications referenced below have electrophoretic displays whose extreme states are white and dark blue, so that the intermediate "gray state" would actually be light blue. explain. In fact, as already mentioned, the transition between the two extreme states may not be discolored at all.

The terms "bistable" and "bisstability", in their conventional sense in the art, include at least one display element having different first and second display states with different optical properties, the first or first of which. A finite duration addressing pulse is used to change the state of a display element after the addressing pulse has finished, after any given element has been driven so as to exhibit one of the two display states. As used herein to refer to a display, the state of which will last at least several times, for example, at least four times, the minimum duration of the addressing pulse used for. Some grayscale-enabled particle-based electrophoretic displays are stable not only in their extreme black and white states, but also in their intermediate gray states, and the same is true for some other types of electro-optical displays. This is shown in Published US Patent Application No. 2002/0186867. This type of display is not bistable and is appropriately referred to as "multistable", but for convenience the term "bisstable" is used herein to cover both bisstable and multistable displays. Can be used.

The term "residual voltage" refers to a sustained or attenuated electric field that can remain in an electro-optical display after an addressing pulse (a voltage pulse used to change the optical state of an electro-optical medium) is terminated. As used herein. The decay rate of the residual voltage of the electro-optical display can decrease as the residual voltage approaches the threshold. Even low residual voltages (eg, residual voltage of about 200 mV or less), but not limited to, optical state shifts associated with addressing pulses, display optical state drift over time, and / or residuals. It can cause artifacts in electro-optical displays, including shadows.

The persistence of the residual voltage over a significant period of time applies a "residual impulse" to the electro-optic medium, and strictly speaking, this residual voltage, not the residual voltage, is usually considered to be caused by the residual voltage, electricity. It may be involved in the effect on the optical state of the optical display. Such residual voltage to an image displayed on an electro-optic display, including, but not limited to, the so-called "afterglow" phenomenon in which traces of the previous image are still visible after the display has been rewritten. It can lead to undesired effects.

The "deviation" of the optical state associated with the addressing pulse is that the first application of a particular addressing pulse to the electro-optical display results in a first optical state (eg, a first gray tone) and is electrically charged. Subsequent application of the same addressing pulse to an optical display refers to a situation that results in a second optical state (eg, a second gray tone). The residual voltage can cause a shift in optical state because the voltage applied to the pixels of the electro-optical display during the application of the addressing pulse includes the sum of the residual voltage and the voltage of the addressing pulse.

"Drift" of the optical state of the display over time refers to a situation in which the optical state of the electro-optical display changes while the display is stationary (eg, during the period when no addressing pulse is applied to the display). .. The residual voltage can cause drift in the optical state because the optical state of the pixel can depend on the residual voltage of the pixel and the residual voltage of the pixel can decay over time.

As discussed above, "afterglow" refers to a situation in which the traces of the previous image are still visible after the electro-optical display has been rewritten. Residual voltage can result in "edge afterglow", a type of afterglow in which some contours (edges) of the previous image remain visible.

The term "impulse" is used herein in its conventional sense in imaging techniques for integrating voltage over time. However, some bistable electro-optic media act as charge transducers, in which an alternative definition of impulse, namely the integral of current over time (equal to the total charge applied), is used. Can be done. Appropriate definitions of impulses should be used, depending on whether the medium acts as a voltage-time impulse transducer or a charge impulse transducer.

Several types of electro-optical displays are known. One type of electro-optical display is, for example, US Pat. Nos. 5,808,783, 5,777,782, 5,760,761, 6,054,071 and 6,055. It is a rotating two-color member type as described in No. 091, No. 6,097,531, No. 6,128,124, No. 6,137,467, and No. 6,147,791 (this is a rotating two-color member type). A type of display is often referred to as a "rotating two-color sphere" display, but in some of the patents mentioned above, the term "rotating two-color member" because the rotating member is not spherical. However, it is preferable as a more accurate one). Such displays use a large number of small bodies (which can be spherical or cylindrical, but not limited), having two or more compartments with different optical properties and an internal dipole. These bodies are suspended in a liquid-filled vacuole in the matrix, which is filled with liquid so that the body is rotatable. The appearance of the display is altered by applying an electric field to it, thus rotating the body to various positions and varying which of the body compartments is visible through the visible surface. This type of electro-optical medium can be bistable.

Another type of electro-optical display comprises an electrochromic medium, eg, an electrode formed at least partially from a semi-conductive metal oxide, and a plurality of dye molecules attached to the electrode that are capable of reversible discoloration. An electrochromic medium in the form of a nanochromic film is used. For example, O'Regan, B.I. , Et al. "Nature" (1991, 353, 737) and Wood, D. et al. See "Information Display" (18 (3), 24 (March 2002)) by. In addition, Bach, U.S.A. , Et al. See also "Adv. Mater" (2002, 14 (11), 845). This type of nanochromic film is also described, for example, in US Pat. No. 6,301,038, International Application Publication No. WO 01/27690, and US Pat. No. 2003/0214695. This type of medium can be bistable.

Another type of electro-optical display is a particle-based electrophoretic display in which multiple charged particles move through a suspended fluid under the influence of an electric field. US Pat. No. 6,531,997, issued March 11, 2003, entitled "Methods for Adpressing Electrical Displacements," which incorporates several attributes of the electrophoretic display as a whole herein. Explained in the issue.

Electrophoretic displays can have the attributes of good brightness and contrast, wide viewing angle, state bistability, and low power consumption when compared to liquid crystal displays. Nevertheless, there may be problems with the long-term image quality of some particle-based electrophoretic displays. For example, the particles that make up some electrophoretic displays can settle and provide an inadequate useful life for such displays.

As mentioned above, the electrophoresis medium may include suspended fluid. The suspension fluid can be a liquid, but the electrophoresis medium can be produced using a gaseous suspension fluid. For example, Kitamura, T.M. , Et al, "Electronic toner movement for electrical paper-like display" (IDW Japan, 2001, Paper HCS1-1) and Yamaguchi, Y. et al. , Et al. See "Toner display using particles charged triboelectrically" (IDW Japan, 2001, Paper AMD4-4). Also, European Patent Applications Nos. 1,429,178, 1,462,847, and 1,482,354, and International Applications WO 2004/090626, WO 2004/079442, WO 2004. / 077140, WO 2004/059379, WO 2004/055586, WO 2004/008239, WO 2004/006006, WO 2004/001498, WO 03/091799, and WO 03 See also / 0884495. Some gas-based electrophoresis media are several due to particle settling, for example, when the medium is used in an orientation that allows such settling, in labels where the medium is placed in a vertical plane. It can be prone to the same type of problems as the liquid-based electrophoresis medium. In fact, particle settling is somewhat more than some liquid-based ones because the lower viscosity of the gaseous suspended fluid allows for faster settling of electrophoretic particles when compared to liquid ones. It will be a more serious problem in gas-based electrophoresis media.

Massachusetts Institute of Technology (MIT), E Ink Corporation, E Ink California, LLC. , And numerous patents and applications, assigned to or in their name, describe various techniques used in encapsulation and microcell electrophoresis and other electro-optic media. Each encapsulated electrophoresis medium comprises a large number of small capsules each comprising an internal phase containing electrophoretic movable particles in the fluid medium and a capsule wall surrounding the internal phase. Typically, the capsules are held within the polymer binder so that they themselves form a coherent layer located between the two electrodes. In microcell electrophoretic displays, charged particles and fluids are not encapsulated within microcapsules, but instead are retained within a propagation medium, typically multiple cavities formed within a polymer film. [[Hereinafter, the term "microcavity electrophoresis display" can be used to cover both encapsulation and microcell electrophoresis displays. ]] The techniques described in these patents and applications include:

(A) Electrophoretic particles, fluids, and fluid additives (see, eg, US Pat. Nos. 7,002,728 and 7,679,814).

(B) Capsules, binders, and encapsulation processes (see, eg, US Pat. Nos. 6,922,276 ^*** , 7,411,719 ^*** ).

(C) Microcell structures, wall materials, and methods of forming microcells (see, eg, US Pat. No. 7,072,095 and US Patent Application Publication No. 2014/0065369).

(D) Methods for filling and sealing microcells (see, eg, U.S. Pat. Nos. 7,144,942 and U.S. Patent Application Publication No. 2008/0007815).

(E) Films and subassemblies containing electro-optic materials (see, eg, US Pat. Nos. 6,982,178, 7,839,564).

(F) Backplanes, adhesive layers, and other auxiliary layers, and methods used in displays (see, eg, US Pat. Nos. 7,116,318 and 7,535,624).

(G) Color formation and color adjustment (see, eg, US Pat. Nos. 7,075,502 and 7,839,564).

(H) Method for driving the display

(I) Display applications (see, eg, US Pat. Nos. 7,312,784, and 8,009,348, and 9,197,704).

(J) Non-electrophoretic display (see, eg, US Pat. No. 6,241,921 and US Patent Application Publication No. 2015/0277160, and US Patent Application Publication Nos. 2015/0005720 and 2016/0012710).

In many of the aforementioned patents and applications, the walls surrounding the discrete microcapsules within the encapsulated electrophoresis medium are replaced by continuous phases, so that the electrophoresis medium is a polymer with multiple discrete droplets of the electrophoresis fluid. A so-called polymer-dispersed electrophoresis display can be produced that comprises a continuous phase of material, and the discrete droplets of the electrophoresis fluid in such a polymer-dispersed electrophoresis display are individual droplets of any discrete capsule membrane. Recognize that it can be considered a capsule or microcapsule, even though it is not associated with. See, for example, 2002/0131147, supra. Therefore, for the purposes of the present application, such polymer-dispersed electrophoresis media are considered variants of encapsulated electrophoresis media.

A related type of electrophoresis display is the so-called "microcell electrophoresis display". In microcell electrophoretic displays, charged particles and suspended fluids are not encapsulated within microcapsules, but instead are retained within a propagation medium, eg, multiple cavities formed within a polymer film. For example, both are Shipix Imaging, Inc. See International Application Publication No. WO 02/01281 and Published US Application No. 2002/0075556 assigned to.

Many of the aforementioned E Ink and MIT patents and applications also consider microcell electrophoresis displays and polymer-dispersed electrophoresis displays. The term "encapsulated electrophoresis display" can refer to all such display types, which can also be collectively described as "microcavity electrophoresis display" as generalized over the form of the wall.

Another type of electro-optical display was developed by Philips, Hayes, R. et al. A. , Et al, "Video-Speed Electronic Paper Based on Electrowetting" (Nature, 425, 383-385 (2003)), an electrowetting display. A pending application No. 10 / 711,802, filed October 6, 2004, shows that such electrowetting displays can be made bistable.

Other types of electro-optical materials may also be used. Of particular note is a bistable ferroelectric liquid crystal display (FLC), which is known in the art and exhibits residual voltage behavior.

The electrophoresis medium is opaque (for example, in many electrophoresis media, because the particles substantially block the transmission of visible light through the display) and can operate in reflection mode, but some electrophoresis. The display can be made to operate in a so-called "shutter mode" in which one display state is substantially opaque and one is light transmissive. For example, US Pat. Nos. 6,130,774 and 6,172,798, and US Pat. Nos. 5,872,552, 6,144,361, 6,271,823, 6. , 225, 971, and 6, 184, 856. Electrophoretic displays that are similar to electrophoretic displays but rely on fluctuations in electric field strength can operate in similar modes. See U.S. Pat. No. 4,418,346. Other types of electro-optical displays may also be able to operate in shutter mode.

Encapsulated or microcell electrophoresis displays may not suffer from the agglomeration and sedimentation failure modes of traditional electrophoresis devices, such as the ability to print or coat the display on a wide variety of flexible and rigid substrates. It can provide additional benefits. (The use of the word "print" is not limited, but is limited to patch die coatings, slot or extrusion coatings, slide or cascade coatings, pre-weighing coatings such as curtain coatings, roll coatings such as knife overroll coatings, forward / reverse roll coatings, etc. , Gravure coating, immersion coating, spray coating, meniscus coating, spin coating, brush coating, air knife coating, silk screen printing process, electrostatic printing process, heat sensitive printing process, inkjet printing process, electrophoretic deposition, and other similar techniques. It is intended to include all forms of printing and coating, including.) Therefore, the resulting display can be flexible. Moreover, since the display medium can be printed (using various methods), the display itself can be inexpensively made.

The bistability or polystable behavior of particle-based electrophoretic displays and other electro-optical displays that display similar behavior (such displays may be referred to hereafter as "impulse-driven displays" for convenience) This is in sharp contrast to that of liquid crystal displays (“LCD”). Twisted nematic liquid crystals are not bistable or polystable, but applying a given electric field to the pixels of such a display is concrete in the pixels, regardless of the gray level previously present in the pixels. Acts as a voltage transducer to produce a target gray level. In addition, the LC display is driven in only one direction (non-transparent or "dark" to transparent or "bright") and reverses from a brighter state to a darker state by reducing or eliminating the electric field. A transition is brought about. Also, the gray levels of pixels in LC displays are sensitive only to their magnitude, not the polarity of the electric field, and for technical reasons, commercial LC displays usually have drive field polarity at frequent intervals. To reverse. In contrast, bistable electro-optic displays have a number of pixels so that the final state of the pixel depends not only on the applied electric field and the time the main electric field is applied, but also on the state of the pixel prior to the application of the electric field. It acts as an impulse transducer for the approximation of 1.

High resolution displays may include individual pixels that can be addressed without interference from adjacent pixels. One way to obtain such pixels is to provide an array of non-linear elements such as transistors or diodes in which at least one non-linear element is associated with each pixel to produce an "active matrix" display. An addressing or pixel electrode that addresses one pixel is connected to the appropriate voltage source through the associated non-linear element. When the non-linear element is a transistor, the pixel electrode may be connected to the drain of the transistor, and this arrangement is essentially arbitrary, as will be assumed in the description below, and the pixel electrode is Can be connected to the source of the transistor. In a high resolution array, the pixels are arranged in a two-dimensional array of rows and columns so that any concrete pixel is uniquely defined by the intersection of one defined row and one defined column. May be good. The sources of all the transistors in each column may be connected to a single column electrode, while the gates of all the transistors in each row may be connected to a single row electrode and again. , Sources to rows and gate assignments to columns may be reversed if desired.

The display may be written in a line-by-line format. The row electrodes apply a voltage to the selected row electrodes to ensure that all the transistors in the selected row are conductive, while the row electrodes of these unselected rows Connected to a row driver, which can apply a voltage to all other rows, such as to ensure that all the transistors in it remain non-conductive. The column electrodes are connected to a column driver that applies a voltage selected to drive the pixels in the selected row to their desired optical state to the various column electrodes. (The voltage described above can be provided from the nonlinear array to the opposite side of the electro-optic medium and is for a common front electrode that extends across the entire display.) Known as "line address time". After the preselected interval, the selected row is deselected, another row is selected, and the voltage on the column driver is changed to write the next line on the display.
(Residual voltage discharge)

Preferred Practices for Dissipating Residual Voltage, as described in US Provisional Application No. 62 / 111,927, filed February 4, 2015, which is incorporated herein by reference in its entirety. The form makes all pixel transistors conductive over a long period of time. For example, all pixel transistors use the gateline (referred to herein as the "selection line") voltage relative to the sourceline voltage to isolate pixels from the sourceline as part of a normal active matrix drive. It can be made conductive by setting the pixel transistor to a value that makes it relatively conductive as compared to the non-conductive state.

In some embodiments, a specially designed circuit may be provided to address all pixels at the same time. In standard active matrix operation, the selection line control circuit typically does not set all gate lines to values that achieve the above conduction states for all pixel transistors. A convenient way to achieve this condition is to allow the external signal to provide a condition to receive the voltage supplied to the selected driver in which all selected line outputs are selected to conduct the pixel transistors. It is provided by a selection line driver chip with an input control line. All transistors may be made conductive by applying an appropriate voltage value to this special input control line. As an example, for displays with n-type pixel transistors, some selection drivers have a "Xon" control line input. By selecting the voltage value to be input to the Xon pin input to the selection driver, the gate-on voltage is distributed to all selection lines. For simplicity, the description of the present invention describes a backplane that employs n-type pixel transistors. In this case, the gate-on voltage is positive. However, for backplanes made using p-type pixel transistors, all the methods described herein can be employed by reversing all the voltages described and shown in the present invention. In this case, the gate-on voltage will be negative.

The gate-on voltage is an important voltage for the purpose of dissipating the residual voltage of the electro-optical active matrix display. The application of a gate-on voltage across the display is typically applied at the end of the "active drive phase" (also referred to herein as the "image update" or "active update period"), the "drive". It is indispensable for "post-discharge". The “post-drive discharge phase” (also referred to herein as the “residual voltage discharge phase” or “residual voltage discharge”) is part of the “voltage decay phase” and the post-drive discharge phase becomes the voltage decay phase. If they are equal, these terms may be used synonymously (used herein synonymously).

However, it is required for residual voltage discharge as described in US Provisional Application No. 62 / 219,606 filed September 16, 2015, which is incorporated herein by reference in its entirety. Retaining a pixel transistor in a conductive state for the alleged long duration can cause deterioration of the pixel transistor and / or deviation of the optical performance of the display. It is advantageous to be able to adjust the gate-on voltage value during the post-drive discharge phase to reduce and / or prevent the effects of holding the pixel transistor over a long duration. Post-drive discharge may occur after all active updates, after a specified number of active updates, after a specified time period, or when requested by the user. In addition, the post-drive discharge may be interrupted by an active update so that the gate-on voltage value cannot reach zero.

The present invention describes an apparatus and method for adjusting a gate-on voltage value after an active update phase.
(E / O electronic equipment)

As explained above, long periods of high gate voltage values, such as those received during residual voltage discharge, can cause pixel transistor degradation. Reducing the high gate voltage value during residual voltage discharge and / or accelerating the decay rate to dissipate the residual voltage can reduce or prevent pixel transistor degradation. The optimum decay rate for dissipating the residual voltage in the display can be empirically determined by balancing the allowable level of discharge effectiveness and the effect on the transconductance of the pixel transistors. One advantage of the present invention is that post-drive discharge can be achieved at lower voltages, reducing pixel transistor degradation and preventing optical shift.

The various aspects described above as well as additional aspects are here described in detail below. It should be understood that these aspects can be used alone, all together, or in any combination of two or more, to the extent that they are not mutually exclusive.

The electro-optical display may receive power from an external electronic device such as a display controller and supply voltage from a "power management" circuit. The power management circuit supplies multiple voltages, "including a gate-on voltage", that are supplied to the gate line (also referred to herein as the "selection line") to conduct the transistors on the selected line. You may. The power management circuit may be a discrete component or an integrated circuit (eg, a power management integrated circuit (“PMIC”)). The additional circuit may include a pull-down resistor and / or a pull-down capacitor.

FIG. 1A is a schematic diagram of a simple gate-on voltage electrical circuit for an electro-optical display using the PMIC 102, showing a gate-on voltage line 104 from the PMIC 102 to the gate driver 106 of the active matrix display. The circuit of FIG. 1 makes it possible to control the gate-on voltage 104 at the end of active drive by changing the value of the pull-down resistor R108. A high value of R108 will slow down the gate-on voltage decay rate, while a low value of R108 will accelerate the gate-on voltage decay rate. Assuming a certain level of capacitive element (“C”) (not shown) on the line 104 from the PMIC to the gate driver, the pull-down resistor (“R”) 108 is the line capacitance (“C”). The gate online 104 will be attenuated exponentially to zero volts with a time constant determined by the resistor value multiplied by (“R”). The voltage attenuation through the R resistor 108 can be calculated as follows.

In the equation, _VO is the initial voltage and line capacitance C includes the parasitic capacitance of the voltage line and any capacitance designed as part of the PMIC to stabilize the voltage. ..

The post-drive discharge method described in US Provisional Application 62 / 111,927, cited above, utilizes slow attenuation of the gate-on voltage. During the post-drive discharge phase, which usually occurs after the active update phase, the gate-on voltage is typically allowed to decay through a resistor connected to ground. In post-drive discharge, all active matrix selection lines are placed at a gate-on voltage that attenuates from that value to ground during active display drive.

FIG. 1B is a graph showing the gate-on voltage relative to the time in the voltage decay phase, including the active update and post-drive discharge phase, where the gate-on voltage decays exponentially to ground. Time t = 0 is the end of active update. 1B, the "driving after discharge" period begins at time t _1, is defined as ending at time t _2. The time t ₁ can be as small as zero, in which case the post-drive discharge may begin immediately after the update or be delayed until the gate-on voltage value decays or decreases to a desired value. Time t ₂ is chosen so that the post-drive discharge is effective in reducing the dielectric polarization in the display sufficiently, or, if time allows, to be large enough until the gate-on voltage decays to zero volts. Will be done.

As explained above, it is advantageous to apply a "gate-on" voltage that is large enough to allow draining of the pixel residual voltage to reduce transistor degradation, but not higher. .. A higher voltage scale than necessary is unlikely to increase TFT bias stress and improve residual voltage drain. As shown in FIG. 1B, the simplest implementation of post-drive discharge allows the "gate-on" voltage to decay exponentially during post-drive discharge. A higher initial voltage value is sufficient for a timely drain of the residual voltage, even if the subsequent lower voltage values are too small to allow a timely drain of the residual voltage. In addition, all selection lines are turned on to allow sufficient residual voltage discharge, but it is advantageous to minimize the time so that it is not longer. The present invention controls the "gate-on" voltage to achieve these advantages by forming a time profile of the "gate-on" voltage during the post-drive discharge phase. The present invention utilizes a metric K, which is useful for assessing the advantageous properties of a "gate-on" voltage profile during the post-drive discharge phase.

In the formula, T _m is, "gate-on" voltage, beginning from the end of the display update, update after the end of the time low voltage scale (V _L) of the time in the domain of up to t ₂ and the high voltage scale and (V _H) located between a total time, T _h is "gate-on" voltage is above V _H, the total time. t ₂ is the time to end the post-drive discharge when not interrupted by another display process such as the next image update. The values _VL and V _H may be subsequently defined or demarcated based on display performance and use. Assigning a value of V _L and V _H are described in further detail below. Voltages are defined for different voltages, all for "zero voltage" or "ground" for drive electronics (source and / or selective drivers and display controllers).

Natural K (“K _natural ”) may be defined as follows.

In the equation, V ₀ is the "gate-on" voltage applied during the image update or active update (as described above, all voltages are relative to the "gate-off" voltage for the display under consideration. Is defined). For convenience, the normalization K referred to here is defined as follows.

In the equation, K, K _natural , and alpha (“α”) are all functions of _{time t 2} and voltage parameters _VL and V _H. The preferred voltage profile has an alpha greater than 2 and an alpha greater than 5, or preferably greater than 20, and _{the values of VL and DH} have the following constraints: 1) _VL of V ₀ . At least 5%, 2) V _H is less than 80% of _{V 0 , 3) V H exceeds VL} , and 4) (V _H - _VL ) / [(V _H + _VL ) / 2 ] Satisfies at least two of the constraints of> 0.1. The fourth constraint can be met to ensure that the separation between the V _H and V _L is significant compared to the average of the V _H and V _L.

FIG. 1C is a graph showing the gate-on voltage relative to time in a voltage decay phase with active updates and a preferred voltage profile. The chain lines depicted and described in FIG. 1B above show typical exponential decay after active update. The solid line shows an example of a more favorable voltage profile of the post-drive discharge phase in which the gate-on voltage value decays rapidly or is reduced to a lower value and then decays from this reduced value over the time of post-drive discharge. .. As shown in FIG. 1C, the first rapid reduction of the gate-on value after active update is completed prior to "turning on" all selection lines. Alternatively, all selection lines may be turned on at t = 0. Alternatively, all selection lines may be turned on after the gate-on voltage value is initially reduced and attenuated to the desired value, or after a predetermined time. All selection lines may be turned off after the post-drive discharge has been effective in reducing the dielectric polarization in the display sufficiently, or, as an alternative, after the gate-on voltage has decayed to zero voltage (t _2). ).

FIG. 2A is a simple electrical circuit of FIG. 1A further comprising a "single pole single throw" switch ("SW1") 210 ("open" as shown) between the PMIC 202 and the gate driver 206. It is a schematic diagram of a layout. When the SW1 switch 210 is closed, the circuit actively drives the gate driver 206. When the SW1 switch 210 is opened (at the end of active drive), the PMIC 202 stops driving the gate high voltage 206 and the gate-on voltage decay rate is the various statics received by the pull-down resistor R208 and the gate online 204. It will be determined by the capacitance.

FIG. 2B is a schematic schematic diagram illustrating the gate-on voltage of the circuit of FIG. 2A in the active drive phase 220 when the SW1 switch is closed and the voltage decay phase 222 when the SW1 switch is open. is there.

FIG. 3A is a schematic diagram of a gate-on voltage electrical circuit according to an embodiment of the present invention. FIG. 3A shows a gate-on voltage line 304 with a first "single pole single throw" switch ("SW1") 310 from the PMIC 302 to the gate driver 306 of the active matrix display. The circuit further includes a resistor R308, a second "single pole double throw" switch ("SW2") 312 (at position "a" as shown), and a pull-down capacitor ("C ₁ ") 314. To be equipped.

Switches SW1 and SW2 are programmed to open and close at about the same time so that only one switch is engaged at a time. During operation, SW1 closes and SW2 opens during active display drive, while SW1 opens and SW2 closes during voltage decay phase and post-drive discharge. SW1 is an embodiment of a single pole single throw switch that is connected only when it is in the closed position. SW2 is an embodiment of a single pole double throw switch that is switched between two points so that it is always connected to either position "a" or position "b".

By incorporating a pull-down capacitor C ₁ 314 and a second switch SW 2 312, the gate-on voltage value may be reduced to a lower value and then attenuated from this reduced voltage value. At the end of active drive, SW1 is open, SW2 is in position "b", and drive voltage ("V") attenuation may be calculated according to the following equation.

In the equation, C is the line capacitance of the gate online 304 and V ₀ is the initial voltage.

FIG. 3B shows the active drive phase 320 when the SW1 switch is closed and the SW2 switch is in position “a”, and the voltage attenuation phase 322 when the SW1 switch is open and the SW2 switch is connected to position “b”. FIG. 5 is a schematic schematic diagram illustrating a gate-on voltage over time for the circuit of FIG. 3A in. As shown in FIG. 3B, the PMIC drives the gate driver 306 during the active drive phase 320 (when SW1 is closed and SW2 is in position "a"). During voltage decay phase (SW1 switch is opened, when the switch SW2 is connected to the position "b"), the voltage value is rapidly pulled down to a smaller voltage value _{(i.e., V O C / (C +} C 1 )), at a rate that is determined by the capacitance of the pull-down resistor R308 and C and _{C 1,} decays from this value less than 322.

FIG. 4A is a schematic diagram of a gate-on voltage electrical circuit according to another embodiment of the present invention. FIG. 4A shows a gate-on voltage line 404 with a first switch (“SW1”) 410 from the PMIC 402 to the gate driver 406 of the active matrix display. The circuit further includes a resistor R408, a second switch (“SW2”) 412 (at position “a” as shown), a pull-down capacitor (“C ₁ ”) 414, and a second pull-down resistor. It is equipped with a vessel (“R ₁ ”) 416. The pull-down capacitor C ₁ 414 and the pull-down resistor R ₁ 416 are in series with SW2 412. However, those positions with respect to SW2 may be exchanged.

As shown in FIG. 4B, during the active drive phase 420 (when SW1 is closed and SW2 is in position "a"), the PMIC drives the gate driver 406 at the active drive gate-on voltage value and the capacitor C. ₁ 414 is charged. Determined during voltage decay phase 422 (SW1 switch is opened, SW2 when switch is in position "b"), the gate-on voltage is reduced to a value of the capacitor _C 1 414, by resistors R408 and _R 1 416 Decays at the speed at which it is. The addition of capacitor C ₁ and resistors R and R ₁ allows for an initial reduction in the gate-on voltage value and a further degree of control over the decay rate.

FIG. 5A is a schematic representation of a gate-on voltage electrical circuit according to another embodiment of the invention, which is equivalent to FIG. 3A. FIG. 5A shows a gate-on voltage line 504 with a first switch (“SW1”) 510 from the PMIC 502 to the gate driver 506 of the active matrix display. The circuit further comprises a second single pole double throw switch (“SW2”) 512 (located at position “a” as shown) located on the gate-on voltage line 504. SW2 512 engages the pull-down resistor R508 and the pull-down capacitor C _{1 514.} During the active drive phase (as depicted in 320 in FIG. 3B), the capacitor C ₁ 514 will be charged when SW1 is closed and SW2 is in position "a". During the voltage decay phase (as depicted in 322 of FIG. 3B), when SW1 is open and SW2 is in position "b", the voltage value first drops to the value of _{capacitor C 1 514 and then.} , Will decay at the rate determined by the resistor R508.

Using FIG. 5A as an exemplary electrophoresis display, the PMIC may drive the gate-on voltage at +22 volts during the active update phase. During the post-drive discharge phase (“residual voltage discharge”), the +22 volt gate-on voltage value is excessive and a reduced gate high voltage value is preferred. For some displays, residual voltage discharge may be achieved by using a voltage value of about +8 volts. Preferred circuit of Figure 5A contains sufficient capacitor C ₁ in order to lower up quickly to about 10 to 12 volts on voltage after active driving phase. Preferred capacitor C ₁ value is attached to the display (SW2 is in position "b") is, when the PMIC is disconnected (SW1 is in position "b"), approximately equal to the capacitance of the gate-line .. Since different displays and drive electronics have different gate-on capacitances, a single capacitance value C ₁ may not apply to all displays, but based on the desired initial voltage drop. May be selected. Similar to resistor R508, a single resistor value may not apply to all displays, but may be selected based on the desired voltage decay rate.

FIG. 5B is a schematic diagram of a gate-on voltage electrical circuit according to another embodiment of the present invention, which is equivalent to FIG. 4A. FIG. 5B is a schematic diagram of the electrical circuit of FIG. 5A further comprising a pull-down resistor R _{1 516.} In FIG. 5B, SW2 512 engages the pull-down resistor R508, the pull-down capacitor C ₁ 514, and the pull-down resistor R ₁ 516. During the active drive phase (as depicted in 420 in FIG. 4B), when SW1 is closed and SW2 is in position "a", capacitor C ₁ 514 will discharge to 0V. During the voltage decay phase (as depicted in 422 of FIG. 4B), when SW1 is open and SW2 is in position "b", the voltage value first drops to the value of _{capacitor C 1 514 and then.} It would decay at a rate determined by resistor R508 and _R 1 516.

FIG. 6A is a schematic diagram of a gate-on voltage electrical circuit according to another embodiment of the present invention. FIG. 6A shows a gate-on voltage line 604 with a first switch (“SW1”) 610 from the PMIC 602 to the gate driver 606 of the active matrix display. The circuit further includes a pull-down resistor R608, a pull-down capacitor (“C ₁ ”) 614, a second pull-down resistor (“R ₁ ”) 618, and a second pull-down capacitor (“C ₂ ”) 616. It includes a second switch (“SW2”) 612 (“open” as shown) located between the _{resistor R 1} 618 and the pull-down capacitor C _{2 616.} The pull-down capacitor C ₁ 614, the pull-down resistor R ₁ 618, and the pull-down capacitor C ₂ 616 are in series.

PMIC is closed SW1, by opening the SW2, when the gate line to _{V o} volts, the voltage across the _{C 1 is} raised to ^{_{V o * C 2 / (C}} 1 + C 2). Capacitors C ₁ and C ₂ are selected to set this voltage to the desired low level during the post-drive discharge period. The resistor R ₁ 618 was chosen to avoid current spikes, which cannot be supported by the PMIC, and _{the value of R 1} can be 0 ohms, in which case R ₁ is not required. It should also _{be noted here that the positions of R 1} 618 and C ₁ 614 can be exchanged. Then, during the driving after the discharge period, the gate line is held at a lower voltage, voltage, so slowly attenuated through through composite resistance of resistor R608 and R ₁ 618 discharge, SW1 is opened, SW2 is closed. The advantages of this alternative embodiment over the previous embodiment are: 1) the switch SW2 is "single pole single throw" which can be easily mounted with a transistor, and 2) desired. The lower voltage can be set more easily, almost independently of the gateline capacitance, by choosing _{C 1} and C ₂ values that are much larger than the other capacitances received by the gateline 604. Can be done.

As shown in FIG. 6B, during the active drive phase 620 (when SW1 is closed and SW2 is open), the PMIC drives the gate driver 606 at the gate-on voltage value for active drive, " Charge the _{capacitors C 1} and C ₂ to a voltage value that sums the "gate on" voltage value. During voltage decay phase 622 (SW1 switch is opened, when the switch SW2 is closed), the gate-on voltage value, drops to the level of the voltage across C ₁ during an active drive, then this lower value Decays from. The addition of capacitors C ₁ and C ₂ and resistors R and R ₁ provides a better degree of control over the initial reduction of the gate-on voltage value in both time and amount of reduction, as well as the decay rate after the initial drop of the value. to enable. These values may be set to optimize the reduction of the voltage value during the voltage decay phase, or one or both of these resistors may be removed from the electrical circuit.

FIG. 7 is a schematic diagram of a gate-on voltage electrical circuit according to another embodiment of the present invention. FIG. 7 shows a gate-on voltage line 704 with a first switch (“SW1”) 710 from the PMIC 702 to the gate driver 706 of the active matrix display. The circuit further comprises a second switch (“SW2”) 712 (“open” as shown) located on the gate-on voltage line 704. SW2 712 engages the pull-down resistor R708 and the Zener diode 714. During the discharge phase, when SW1 is opened and SW2 is closed, the Zener diode quickly drops the gate-on voltage value to a predetermined value (the "break voltage" value described below) and the voltage becomes this value. The rate of descent to is affected by the optional resistor R708.

Zener diodes, like ideal diodes, allow current to flow in the forward direction, but can also flow in the opposite direction when a voltage exceeds a certain value (the "break voltage"). It is a commercially available diode. Zener diodes are available with different breakdown voltages and may be selected based on the desired breakdown voltage value for a particular display. Zener diodes are non-linear between voltage and current, but it is predictable how they react to voltage and current. Zener diodes drop the voltage quickly when the current is high, but once the breakdown voltage is reached, the current is cut off. This is another way to quickly drop the gate-on voltage value during the voltage decay phase. It may be desirable to use more than one Zener diode instead of the one shown in FIG. It is common practice to use a series of two or more Zener diodes to achieve the desired voltage, above which a series of Zener diodes will conduct current. A series of Zener diodes may be employed to gain the flexibility of selecting the voltage above which the voltage drops through conduction through the Zener diode. In this case, the effective "breakdown voltage" of such a series of Zener diodes is the sum of the respective "breakdown voltages" of the constituent Zener diodes.

This circuit has advantages over previous versions. In previous versions, SW2 is a "single pole double throw" switch, relying on the capacitor value to achieve the desired voltage at the start of the post-drive discharge session. In this version, SW2 is a much simpler, "single pole single throw" switch. This provides more reliable control of the voltage in the discharge phase than circuits that use Zener diodes to control the desired voltage and employ capacitors to control the voltage during the discharge phase. The resistors in the figure are optional. Perhaps not only in this example, but also those without resistors should be shown, or it should be explained that the resistor value can be zero.

According to another embodiment of the invention, the power management circuit (power management integrated circuit, PMIC, etc.) may be configured to actively control the gate-on voltage. During an active update, the gate-on value may be set to allow the pixels to be fully charged to the desired voltage for successful display operation. After active renewal, during the post-drive discharge time, the gate-on voltage may be set to a reduced value, where a lower scale is sufficient to achieve post-drive discharge. The PMIC manages gate-on voltage control using a switch that switches the gate-on voltage output to the display between a voltage value for actively driving the display and a different voltage value for post-drive discharge. In some embodiments, the switch is inside the PMIC. In other embodiments, the switch and electrical circuit are external to the PMIC.

FIG. 8A illustrates yet another embodiment according to the subject presented herein. FIG. 8A illustrates a gate-on voltage line 804 coupled to a first switch (“SW1”) 810 from the PMIC to the gate driver 806 of the active matrix display, where SW1 provides the display with a first voltage. It is coupled to a first voltage source 812 configured in. In addition, a second voltage source 816, usually a low voltage source, is also coupled to the gate-on voltage line 804 through a second switch (“SW2”) 814 to provide a second voltage to the active matrix display. It may be configured. In addition, the capacitor C818 and resistor R820 may be connected in parallel in connection with the voltage line 804 and the gate driver 806 to provide better control over the attenuation of the gate-on voltage.

FIG. 8B illustrates the attenuation of the gate-on voltage as configured by the circuit illustrated in FIG. 8A. As shown, during the active phase 840 (when SW1 is closed and SW2 is in position "a"), the PMIC drives the display at the active drive gate-on voltage value and charges the capacitor C818. During the second active phase 842 (when SW1 is in position "b" and SW2 is closed), the PMIC drives the display at a voltage determined by the second voltage source 816. In this second active phase 842, the display is driven at a voltage level close to the voltage value supplied by the second voltage source 816, and the capacitor C818 refers to the voltage value of the second voltage source 816. It is charged or discharged accordingly. Finally, during the discharge phase 844 (when SW1 is in position "b" and SW2 is in position "a"), the gate-on voltage decays at the rate determined by the combination of capacitor C818 and resistor R820. Designed to do. This configuration allows for a faster initial reduction of gate-on voltage, thus facilitating the overall attenuation process and improving device reliability.

During use, as illustrated in FIG. 9, after a long period of use (eg, 100,000 updates), the configurations illustrated in FIG. 8A are some conventional configurations (lines 906 and 908). Provides better reliability (lines 902 and 904).
(Transistor and typical charge ratio / transistor deterioration)

Therefore, in some aspects, the subject matter described herein also provides a method of driving a bistable electro-optical display having multiple pixels in an active matrix array. In particular, various types of active matrix transistors are commercially available, including amorphous silicon, microcrystals, polysilicon, and organics. Transistors in an active matrix display are typically designed to support a 1: 1000 on: off ratio, as most active matrix displays have about 1000 rows. For n-channel (“n-type”) amorphous silicon thin film transistors (“a-Si TFTs”) in active matrix displays, the transistors are in their on state when there is a positive voltage on the gate source (“n-type”). The row is selected) and is in its off state when there is a negative voltage on the gate source. Therefore, an n-type thin film pixel transistor typically receives a positive to negative charge ratio of 1: 1000. For p-channel (“p-type”) a-Si TFTs in the active matrix display, the voltage polarity is reversed. A p-type transistor is in its on state when there is a negative voltage on the gate source and in its off state when there is a positive voltage on the gate source. Therefore, a p-type thin film pixel transistor typically receives a negative to positive charge ratio of 1: 1000. When the on: off ratio is changed so that the transistor is on more often than usual, the transistor can degrade the optical performance of the display and have a negative effect. Amorphous silicon transistors are highly susceptible to degradation due to atypical charge bias. One way to reduce this type of transistor degradation is to make the transistor closer to its typical value of 1: 1000 on: off ratio, as more fully described herein. The on: off ratio is standardized by setting it to the off position.

It should be understood that the typical on: off ratio of an active matrix display can differ from the 1: 1000 ratio and the aspects of the invention described herein still apply.
(Charge bias based on reduction of residual voltage of electro-optical display)

Charge bias is further fully disclosed in US Provisional Application No. 62 / 111,927, filed February 4, 2015, which is disclosed herein and incorporated herein by reference in its entirety. It can occur when the residual voltage is discharged from the electro-optical display according to the technique used. The residual voltage of a pixel in an electro-optical display is obtained by activating the transistor in the pixel (ie, turning on all the transistors) and setting the voltage on the front and back electrodes of the pixel to approximately the same value over a period of time. It may be discharged. The amount of residual voltage discharged by a pixel during a residual voltage discharge pulse can depend, at least in part, on the rate at which the pixel discharges the residual voltage and the duration of the residual voltage discharge pulse. In some embodiments, the duration of the period during which the residual voltage discharge pulse is applied (in the on position) is at least 50 ms, at least 100 ms, at least 300 ms, at least 500 ms, at least. It may be 1 second, or any other suitable duration.

For example, all pixel transistors compare the gateline voltage to the source line voltage with the non-conductive state used to isolate the pixel from the source line as part of a normal active matrix drive. It can be made conductive by setting it to a value that makes it relatively conductive. For n-type thin film pixel transistors, this can be achieved by making the gate line substantially higher than the source line voltage value. For p-type thin film pixel transistors, this can be achieved by making the gate line substantially lower than the source line voltage value. In an alternative embodiment, all pixel transistors can be conducted by making the gateline voltage zero and the source line voltage negative (or positive for p-type transistors).

Alternatively, a specially designed circuit may be provided to address all pixels at the same time. In standard active matrix operation, the selection line control circuit typically does not set all gate lines to values that achieve the above conduction states for all pixel transistors. A convenient way to achieve this condition is to allow the external signal to provide a condition to receive the voltage supplied to the selected driver in which all selected line outputs are selected to conduct the pixel transistors. It is provided by a selection line driver chip with an input control line. All transistors may be made conductive by applying an appropriate voltage value to this special input control line. As an example, for displays with n-type pixel transistors, some selection drivers have a "Xon" control line input. By selecting the voltage value to be input to the Xon pin input to the selected driver, a "gate high" voltage is placed on all selected lines and puts all transistors on.

When the residual voltage is dissipated using these techniques, for example, the positive-to-negative charge ratio received by an n-type transistor can vary from about 1: 1000 to about 1:10 or even 1: 1. .. This atypical charge bias can cause transistor degradation and reduced display performance. As the atypical charge bias and transistor degradation increase over time, the current and voltage-voltage (“IV”) curves of the display shift values. If the IV curve shifts to a higher value, more voltage is needed to activate the transistor switch. The effect of the IV curve shift can be demonstrated by optically measuring the gray tone shift and afterglow shift resulting from the display reflectance ^{(measured at the L star (L *)).} ..
(Gray tone shift / afterglow shift)

256 transitions are defined that typically switch the display from the 16 possible gray states currently on the display (including extreme black and extreme white) to the same gray state in the next image to be displayed. Has been done. Gray tone shift measures 16 of these transitions. Afterglow shift measures the nature of the remaining 240 transitions.

The gray tone arrangement (“GTP”) causes the optical state to result from applying 16 transitions to all possible gray tones (including black and white) when starting with a white image. Measure. As shown in FIG. 1A, the gray tone placement shift can be defined by the number of sequences minus the gray tone shift at time zero, the absolute value ^{of the maximum L * shift over 16 gray tones at time k.} Is. The GTP shift, also referred to herein as the gray tone shift, may be calculated using the equation, ie, GTP shift (k) = max | (GTP (k) -GTP (0)) |. , In the equation, GTP (0) is the initial GTP and GTP (k) is the GTP measurement at time k. GTP shift is an absolute measurement of 16 transitions.

Afterglow measures the remaining 240 transitions from all possible 16 gray tones except white to all possible 16 gray tones and is finally displayed. Divide the GTP value of the gray tone. That is, the afterglow measurement compares the optical state of the gray tone when transitioning from the non-white gray tone with the optical state of the same gray tone when transitioning from white. As shown in FIG. 1B, the afterglow deviation is the absolute value of the maximum afterglow at time k, which can be defined by the number of sequences minus the afterglow at time zero. The afterglow shift may be calculated using the equation, ie, GHOST shift (k) = max | (GHOST (k) -GHOST (0)) |, in which GHOST (0) is the initial It is an afterglow measurement, and GHOST (k) is an afterglow measurement at time k. Afterglow shift is a relative measurement based on the GTP value.

Prior to making measurements of GTP shift and afterglow shift, the display should be black, white, white, white from its current state, as shown in FIGS. 10A, 10B, 11A, and 11B. It was cleared by switching. However, any display clearing technique may be used as long as the measured values are consistent to be comparable.

The various aspects described above, as well as additional aspects, are now described in detail below. It should be understood that these aspects can be used alone, all together, or in any combination of two or more, to the extent that they are not mutually exclusive.

FIG. 10A measures the optical response shift due to the maximum absolute gray tone shift with respect to the number of updates, 1002 with residual voltage discharge and 1004 without residual voltage discharge, according to some embodiments, at 45 degrees Celsius. It is a graph which shows the result of the accelerated reliability test. Each year of use is assumed to have 50,000 updates. As shown in FIG. 10A, the additional on-time that the transistor receives as a result of residual voltage discharge (atypical charge bias) is significant ^{about 2 L * after about 100,000 updates (or over about 2 years).} It results in a gray tone shift.

FIG. 10B measures the optical response shift due to the maximum absolute afterglow shift with respect to the number of updates, 1006 with residual voltage discharge and 1008 without residual voltage discharge, according to some embodiments, at 45 degrees Celsius. It is a graph which shows the result of the accelerated reliability test. Each year of use is assumed to have 50,000 updates. As shown in FIG. 10B, the additional on-time that the transistor receives as a result of residual voltage discharge (atypical charge bias) is significant of ^{about 3 L * after about 100,000 updates (or over about 2 years).} It causes afterglow shift.

FIG. 11A shows 1102 with residual voltage discharge, 1104 without residual voltage discharge, and 1110 with residual voltage discharge and on-to-off ratio standardization, maximum absolute graytone bias relative to the number of updates, according to some embodiments. It is a graph which shows the result of the acceleration reliability test at 45 degrees Celsius which measures the optical response deviation by a transfer. Each year of use is assumed to have 50,000 updates. As shown in FIG. 11A, the additional on-time that the transistor receives as a result of residual voltage discharge 1102 (atypical charge bias) is after about 100,000 updates (compared to update 1104 without discharge). It results in a significant gray tone shift of ^{about 2 L *} (or over about 2 years). When an update with residual voltage discharge is standardized or offset by turning the transistor off for an additional time period, 1110, the result of the gray tone shift after about 100,000 updates is with discharge. Compared to no update 1104, it is ^{only about 0.25L *.}

FIG. 11B shows, according to some embodiments, 1106 with residual voltage discharge, 1108 without residual voltage discharge, and 1112 with residual voltage discharge and on-to-off ratio standardization, maximum absolute afterglow bias relative to the number of updates. It is a graph which shows the result of the acceleration reliability test at 45 degrees Celsius which measures the optical response deviation by a transfer. Each year of use is assumed to have 50,000 updates. As shown in FIG. 11B, the additional on-time that the transistor receives as a result of residual voltage discharge 1106 (atypical charge bias) is about 100,000 updates after update 1108 without discharge (as shown in FIG. 11B). It results in a significant afterglow shift of ^{about 3 L *} (or over about 2 years). When an update with residual voltage discharge is standardized or offset by turning the transistor off for an additional time period, 1112, the result of afterglow shift after about 100,000 updates is with discharge. Compared to no update 1108, it is ^{only about 0.75L *.}

FIG. 12A is a schematic signal timing diagram showing the gate voltage over time according to some embodiments. FIG. 12A depicts a diagram of the applied gate voltage of one optical update over time, including an active update period 1202, where each positive and negative transition is active in an active matrix display with n-type transistors. During the update period, the residual voltage discharge (on state) period 1204, and the off state period, it reflects a single frame in a series of multiple frames. In the n-type transistor, the positive gate voltage is applied to achieve the on state 1204, while the negative voltage is applied to achieve the off state 1206. In one embodiment, the active renewal period may be 500 milliseconds, the on period may be 1 second, and the off period may be 2 seconds. These time periods may vary depending on the number of optical updates required, eg, every minute, every hour, etc., within the display usage and / or defined time period. As depicted, the residual voltage discharge pulse (on state) 1204 is activated after an active update (ie, optical update) 302 to expel the residual charge. The off state is activated after the on state to achieve an on: off ratio that is closer to the typical 1: 1000 ratio. The 1: 1000 ratio may not be achieved, but even if the on: off ratio approaching the 1: 1000 ratio is only 1:10, it will reduce transistor degradation.

FIG. 12B is a schematic signal timing diagram showing multiple voltages over time using a display that utilizes an Xon connection to turn on all transistors at the same time, according to some embodiments. FIG. 12B shows an active matrix display with n-type transistors applied over time for one optical update, including an active update period 1202, a residual voltage discharge (on state) period 1204, and an off state period. Draw a diagram of the voltage. The four voltages shown are the high level gate line voltage (“ VDDH”) 1212, the low level gate line voltage (“VEE”) 1218, the front electrode voltage (“VCOM”) 1216, and the Xon voltage 1214. Each voltage has a separate zero voltage axis depicted as a solid gray line. A voltage above the solid gray line indicates a positive voltage, while a voltage below the solid gray line indicates a negative voltage. In FIG. 12B, the overall gate voltage depicted in FIG. 12A is a combination of VDDH and VEE voltages. The gate driver output allowed a voltage (“VGDOE”) (not shown) that controls which gate voltage (ie, VEE or VDDH) is applied. The Xon voltage activates all transistors simultaneously when grounded, thus turning on all transistors during the discharge period 1204. During the off-state period 1206, VDDH is grounded and the transistor receives an applied VEE (negative voltage) that is controlled to approach zero towards the end of the period. By putting the transistor in its off position over an additional time period, the on: off ratio more closely reflects its typical value of 1: 1000. It is preferable to maintain the on: off ratio at 1: 1000, but any on that shifts the ratio towards its typical value, even if it is only 1:10, 1:50, or 1: 100. : Off period can prevent transistor deterioration.

During the off period, time is added to each update. Therefore, the off period may be reassigned a defined amount of time, determined by the controller based on the frequency of updates, and / or interrupted. The off period preferably occurs after the on period, but may occur at other times, including before the active renewal period. The off period may range from 500 milliseconds to 4 seconds, preferably 1 to 2 seconds. The off period may be extended up to 10 seconds, depending on the optical update time and the number of optical updates over a period of time.
(Further description of some embodiments)

It should be understood that the various embodiments shown in the figures are exemplary representations and are not necessarily drawn to a constant scale. References to "one embodiment" or "some embodiments" or "several embodiments" throughout this specification are specific features, structures, materials, or properties described in connection with an embodiment. Means that, but not necessarily in all embodiments, is included in at least one embodiment. As a result, the appearance of the terms "in one embodiment", "in some embodiments", or "in some embodiments" in various places throughout the specification does not necessarily refer to the same embodiment. I'm not.

Throughout this disclosure, the words "comprising," "comprising," and their equivalents are not meant to be exclusive or exhaustive, unless the context explicitly requires otherwise. In contrast, it is interpreted in a comprehensive sense, that is, "including, but not limited to,". In addition, the words "in the present specification", "below the present specification", "above", "below", and words having similar meanings are not specific parts of the present application, but as a whole. Point to. When the word "or" is used with reference to a list of two or more articles, the word is the list of all of the following interpretations of the word, i.e. one of the articles in the list. Covers all of the articles in, and any combination of articles in the list.

Although some aspects of at least one embodiment of the technique have been described in this way, it should be appreciated that various modifications, modifications, and improvements will be readily recalled to those skilled in the art. Such modifications, modifications, and improvements are intended to be within the spirit and scope of the technology. Therefore, the above description and drawings provide only non-limiting examples.

Claims (9)

A device for driving an electro-optical display
A first switch configured to supply a voltage to the electro-optical display during the first drive phase,
A resistor coupled to the electro-optic display to discharge the voltage during the second drive phase.
With a capacitor coupled to the second switch,
The second switch is configured to be switchable between a first position and a second position, where in the first position the second switch is from the electro-optical display to the capacitor. In the second position, the second switch couples the capacitor to the resistor to control the discharge of the voltage in the second drive phase. The device of claim 1, wherein only one of the first and second switches is engaged during the first or second driving phase. The apparatus according to claim 1, further comprising a second resistor arranged in series with the capacitor in the second driving phase to control the discharge of the voltage. The device of claim 1, wherein the first and second switches are engaged and disengaged during the third driving phase. A device for driving an electro-optical display
With a capacitor
With a resistor
A first switch configured to supply a voltage to the electro-optical display during the first drive phase,
It comprises the capacitor and a second switch coupled to the resistor to discharge the voltage during the second drive phase.
The second switch is configured to be switchable between a first position and a second position, where at the first position the second switch is from the electro-optical display to the capacitor. And the resistor is isolated, and in the second position, the second switch electroopticals the capacitor and the resistor to control the discharge of the voltage in the second drive phase. A device that couples to a display. The apparatus according to claim 5, wherein the capacitor and the resistor are connected in parallel. The device of claim 5, further comprising a second resistor connected in series with the capacitor. A device for driving an electro-optical display
A first resistor connected to a first capacitor, wherein the first resistor and the first capacitor are coupled to the electro-optical display.
With the second capacitor coupled to the first resistor,
A first switch configured to supply a voltage to the electro-optical display during the first drive phase,
A second switch coupled to the second capacitor is provided.
The second switch is configured to be switchable between a first position and a second position, where the first capacitor and the first resistor are Connected to ground through the second capacitor, in the second position, the second switch is the second capacitor and the first to control the discharge of the voltage in the second drive phase. A device that creates a ground connection to and from a resistor. A device for driving an electro-optical display
A resistor connected to a capacitor in a parallel configuration, wherein the resistor and the capacitor are coupled to the electro-optical display.
A first switch connected to a first voltage source, said first switch is configured to drive the electro-optic display at a first voltage level during a first drive phase. The first switch and
A second switch connected to a second voltage source, said second switch, configured to drive the electro-optic display at a second voltage level during the second drive phase. Equipped with a second switch
The first and second switches are so separated from their respective first and second voltage sources during the third drive phase to discharge the second voltage through the resistor and capacitor. A device to be configured.

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