JP6806213B2 - Semiconductor element - Google Patents

Description

The present invention relates to semiconductor devices used, for example, for switching large currents.

In recent years, insulated gate bipolar transistors (IGBTs) have been widely used for home appliances such as air conditioners and refrigerators, which are becoming more power-saving and miniaturized, railway inverters, and motor control of industrial robots. In order to improve the efficiency of electric power equipment, it is required to reduce the steady-state loss and turn-on loss of the IGBT.

In Patent Document 1, an IGBT having a trench structure has dummy gates connected to emitter electrodes on both sides of an active trench gate connected to the gate, and an n-type source is placed in the p-type base layer between the active trench gate and the dummy gate. Is disclosed to form.

Patent Document 2 discloses an IGBT that forms an n-type source in the p-type base layer between adjacent active trench gates.

JP-A-2002-016252 Japanese Unexamined Patent Publication No. 2003-188382

The emitter of the p-side semiconductor element whose collector is connected to the high potential side (p side) of the power supply may be connected to the collector of the n-side semiconductor element whose emitter is connected to the low potential side (n side) of the power supply. .. The load is connected to the connection point between the p-side semiconductor element and the n-side semiconductor element. One freewheeling diode is connected to each of the p-side semiconductor element and the n-side semiconductor element. A freewheeling diode connected in antiparallel to a p-side semiconductor element is called a p-side diode, and a freewheeling diode connected in antiparallel to an n-side semiconductor element is called an n-side diode.

When the p-side semiconductor element is turned on while the reflux current is flowing through the n-side diode, the recovery current flows through the n-side diode. For example, when the semiconductor element disclosed in Patent Documents 1 and 2 is adopted as the p-side semiconductor element, the recovery dV / dt of the n-side diode changes according to the collector current of the p-side semiconductor element. Specifically, the recovery dV / dt of the n-side diode at the time of turn-on loss at a low current of the p-side IGBT is larger than the recovery dV / dt at the rated current of the p-side IGBT. This is shown in FIG. In FIG. 15, the “low current side” means that the collector current of the p-side semiconductor element is small, and the “rated current side” means that the collector current of the p-side semiconductor element is large. When the collector current of the p-side semiconductor element is small, the recovery dV / dt of the n-side diode is large, whereas when the collector current of the p-side semiconductor element is large, the recovery dV / dt of the n-side diode is small.

As described above, when the diode recovery dV / dt has a current dependence, the following problems occur. That is, the gate resistance of the semiconductor element is set so that a large recovery dV / dt becomes a predetermined value. Therefore, for example, when the gate resistance is determined so that the recovery dV / dt on the low current side is 20 kV / μs, the dV / dt on the rated current side (evaluating the turn-on loss) is about 10 kV / μs. As a result, the switching time of the semiconductor element becomes long, and the turn-on loss (turn-on loss) at the time of turn-on increases. That is, if the diode recovery dV / dt has a current dependence, the turn-on loss increases.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device capable of suppressing the recovery dV / dt of a freewheeling diode from being dependent on the collector current of the semiconductor device.

The semiconductor element according to the present invention includes a semiconductor substrate, an emitter electrode formed on the semiconductor substrate, a gate electrode formed on the semiconductor substrate, and a third unit formed on the upper surface side of the semiconductor substrate. 1 Conductive type source layer, 2nd conductive type base layer formed on the upper surface side of the semiconductor substrate, collector electrodes formed under the semiconductor substrate, and formed on the upper surface side of the semiconductor substrate. , A plurality of active trench gates connected to the gate electrode, and a plurality of dummy trench gates formed on the upper surface side of the semiconductor substrate and not connected to the gate electrode, and the three active trench gates are provided. The first structure in which the above is arranged and the second structure in which three or more of the dummy trench gates are arranged are alternately provided, and the number of the dummy trench gates in the second structure is larger than the number of the active trench gates in the first structure. The base layer is large in number and is characterized in that the base layer is connected to the emitter electrode between the first structure and the second structure.

Other features of the present invention will be clarified below.

According to the present invention, by providing a semiconductor element in which a first structure in which three or more active trench gates are lined up and a second structure in which three or more dummy trench gates are lined up are provided alternately, recovery dV / of a freewheeling diode is provided. It is possible to suppress that dt depends on the collector current of the semiconductor element.

It is a partial cross-sectional perspective view of the semiconductor element which concerns on Embodiment 1. FIG. It is sectional drawing of the semiconductor element. It is a circuit diagram which shows the circuit structure example using a semiconductor element. It is a figure which shows how the depletion layer grows at the time of operation of a semiconductor element. It is a figure which shows the relationship between the arrangement of a trench gate and Cge. It is a figure which shows the leveled recovery dV / dt. It is a figure which shows the reduced turn-on loss. It is a partial sectional view of the semiconductor element which concerns on Embodiment 2. FIG. It is a partial sectional view of the semiconductor element which concerns on a modification. It is a partial cross-sectional view of the semiconductor element which concerns on Embodiment 3. FIG. It is a partial sectional view of the semiconductor element which concerns on a modification. It is a partial sectional view of the semiconductor element which concerns on Embodiment 4. FIG. It is a top view of the semiconductor substrate which comprises the semiconductor element which concerns on Embodiment 5. It is a partial cross-sectional perspective view of the semiconductor element which concerns on Embodiment 6. It is a figure explaining a problem.

The semiconductor device according to the embodiment of the present invention will be described with reference to the drawings. The same or corresponding components may be designated by the same reference numerals and the description may be omitted.

Embodiment 1.
FIG. 1 is a partial cross-sectional perspective view of the semiconductor device according to the first embodiment of the present invention. This semiconductor element is an IGBT. This semiconductor element includes a semiconductor substrate 10. An n-type drift layer 12 is formed on the semiconductor substrate 10. An n-type buffer layer 14 is formed under the drift layer 12. A p + type collector layer 16 is formed under the buffer layer 14.

An n + type source layer 18 and a p + type contact layer 20 are formed on the surface side of the semiconductor substrate 10. A p-type base layer 22 is formed under the source layer 18. An n-type carrier accumulation layer 24 is formed under the base layer 22. And below the carrier accumulation layer 24, there is the above-mentioned drift layer 12.

A plurality of active trench gates A1 and A2 and a plurality of dummy trench gates D1 are formed on the upper surface side of the semiconductor substrate 10. The active trench gate is a trench gate electrically connected to the gate electrode, and the dummy trench gate is a trench gate electrically connected to the emitter electrode. The plurality of active trench gates A1 and A2 and the plurality of dummy trench gates D1 are formed by forming a groove in the semiconductor substrate 10, forming an insulating film 26 on the wall surface of the groove, and then embedding the groove with the conductor 28. To. The plurality of active trench gates A1 and A2 and the plurality of dummy trench gates D1 penetrate the source layer 18, the base layer 22, and the carrier storage layer 24 from the surface of the semiconductor substrate 10 and reach the drift layer 12.

The source layer 18 may be formed in contact with one or both side walls of the active trench gates A1 and A2, respectively. However, the source layer 18 may be formed in the region sandwiched between the dummy trench gates D1.

A collector electrode 40 is formed under the semiconductor substrate 10. An interlayer insulating film 42 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 42 is provided with an opening, and the opening is provided with an emitter contact 44 that contacts the contact layer 20 and the source layer 18. The emitter contact 44 is formed on the base layer 22. An emitter electrode 46 that contacts the emitter contact 44 is formed on the interlayer insulating film 42.

FIG. 2 is a cross-sectional view of the semiconductor element. The arrangement of trench gates will be described with reference to FIG. An emitter electrode 46 and a gate electrode 50 are formed on the semiconductor substrate 10. The three active trench gates A1 and the three active trench gates A2 are connected to the gate electrode 50. The three dummy trench gates D1 and the three dummy trench gates D2 are not connected to the gate electrode 50 but are connected to the emitter electrode 46.

The emitter contact 44 is in contact with the portion of the source layer 18 adjacent to the active trench gates A1 and A2. Therefore, the portion of the source layer 18 adjacent to the active trench gates A1 and A2 is connected to the emitter electrode 46. On the other hand, the portion of the base layer 22 sandwiched between the dummy trench gates D1 and D2 is not connected to the emitter electrode 46.

The first structure 60 is formed by arranging three active trench gates A1. The second structure 62 is formed by arranging three dummy trench gates D1 next to the first structure 60. The first structure 64 is formed by arranging three active trench gates A2 next to the second structure 62. The second structure 66 is formed by arranging three dummy trench gates D2 next to the first structure 64. In this way, the first structure composed of three active trench gates and the second structure composed of three dummy trench gates are alternately provided.

FIG. 3 is a circuit diagram showing a circuit configuration example using a semiconductor element. The load 78 is connected to the connection point P1 between the p-side semiconductor element 70 and the n-side semiconductor element 74. A p-side diode 72 is connected to the p-side semiconductor element 70 as a freewheeling diode, and an n-side diode 76 is connected to the n-side semiconductor element 74 as a freewheeling diode. As the p-side semiconductor element 70 and the n-side semiconductor element 74, the semiconductor element according to the first embodiment of the present invention is adopted.

Returning to the description of FIG. The distance L1 between the active trench gates in the first structures 60 and 64 was set to 1.5 μm or less. The distance L2 between the active trench gate and the dummy trench gate and the distance L3 between the dummy trench gate and the dummy trench gate are not particularly limited, but are set to, for example, about 1.5 μm.

An example of a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described. First, an n-type semiconductor substrate is prepared. Next, an oxide film is formed as a mask, and a resist pattern is formed on the oxide film by a photoengraving method. The oxide film is etched using the resist pattern as a mask. Then, the resist pattern is removed.

Then, a mask is used to inject phosphorus (P) ions to form an n-type carrier accumulation layer. Then, boron (B) ions may be injected with the same mask. This can reduce the number of masks used, but separate masks may be used. The injected phosphorus and boron are then diffused by a drive. As a result, the n-type carrier accumulation layer 24 and the p-type base layer 22 are formed. The impurity concentration of the carrier accumulation layer 24 may be higher than that of the drift layer 12 and lower than that of the base layer 22, and is, for example, 1 × 1015 to 1 × 1016 cm-3. The diffusion depth of the carrier storage layer 24 is, for example, 2.0 μm. The surface concentration of the p-type base layer 22 is, for example, 1 × 1017 to 1 × 1018 cm-3, and the diffusion depth is, for example, 2.0 μm.

Next, using a mask made of an oxide film, arsenic (As) ions are injected as impurities, and the injected arsenic is diffused by a drive. As a result, the n-type source layer 18 is formed on the p-type base layer 22. For example, the impurity concentration of the source layer 18 is, for example, 5 × 1018 to 5 × 1019 cm-3, and the diffusion depth is, for example, 0.5 μm.

Next, an active trench gate and a dummy trench gate are formed. A trench is formed through the base layer 22 and the carrier storage layer 24 by dry etching using a mask made of an oxide film patterned so that the active trench gate is connected to the gate electrode and the dummy trench gate is connected to the emitter electrode. To. For example, the depth of the trench is 6.0 μm and the width is 1.0 μm.

Next, the oxide film mask is removed to form an oxide film (insulating film 26) that covers the side wall of the trench. Subsequently, the trench covered with the insulating film 26 is filled with a conductor 28 such as polysilicon. Next, an interlayer insulating film 42 made of an oxide film or the like for insulating the conductor 28 in the trench is formed. The film thickness of the interlayer insulating film 42 is, for example, 1.0 μm.

The emitter contact 44 is then formed using a mask made of an oxide film. Next, the emitter electrode 46 is formed. The material of the emitter electrode 46 is, for example, aluminum or aluminum silicon. The film thickness of the emitter electrode 46 is, for example, 4.0 μm. Further, a gate electrode 50 insulated from the emitter electrode 46 is also formed.

Next, P ions and B ions are injected into the lower surface of the semiconductor substrate 10 and annealed to form a p-type collector layer 16 and an n-type buffer layer 14. Annealing may be performed once as described above in order to reduce the number of steps, or may be performed in two steps after injecting P ions and B ions, respectively. Next, the collector electrode 40 is formed. The material and film thickness of the collector electrode 40 can be arbitrarily set.

In order to suppress that the recovery dV / dt of the freewheeling diode depends on the collector current of the semiconductor element, the inventor sets the gate electrode-collector electrode capacitance (Cgt) of the semiconductor element to the gate electrode-emitter electrode capacitance ( It was found that it is effective to increase the value (Cgc / Cge) divided by Cge). More specifically, by increasing the Cgt of the semiconductor element, it is possible to suppress an increase in recovery dV / dt at a low current. Further, by reducing the Cge of the semiconductor element, the recovery dV / dt at the time of a large current (at the rated current) can be increased. By increasing the value of Cgc / Cge, the switching time can be shortened and the turn-on loss can be reduced. The semiconductor device according to the first embodiment of the present invention is manufactured based on this knowledge.

The semiconductor device according to the first embodiment of the present invention has a configuration suitable for reducing Cge while maintaining the value of Cgc. This will be described with reference to FIG. 4, which shows how the depletion layer grows during the operation of the semiconductor element. When a voltage Vge is applied between the gate electrode 50 and the emitter electrode 46, the depletion layer 80 spreads from the side wall of the active trench gate A1 in the base layer 22. For example, the depletion layer 80 is formed in the region indicated by the broken line. The Cge of the semiconductor element depends on the oxide film capacity (capacity with the insulating film 26 as the dielectric layer) and the depletion layer capacity. Therefore, the larger the distance d of the depletion layer 80 and the smaller the surface area S, the more Cge can be reduced.

When the applied voltage Vge becomes large, the depletion layer formed from the side wall of the active trench gate and the depletion layer formed from the adjacent active trench gate overlap, and the distance d of the depletion layer becomes large. In the first embodiment of the present invention, since the distance between the active trench gates in the first structure is 1.5 μm or less, the depletion layer can be overlapped even at a low applied voltage Vge. When the depletion layers overlap, one depletion layer having a large distance d is formed, so that Cge can be sufficiently reduced.

Reducing the surface area S of the depletion layer was realized by adjusting the impurity concentration of the carrier accumulation layer 24. That is, the impurity concentration of the carrier accumulation layer 24 was made higher than the impurity concentration of the drift layer 12. Further, the impurity concentration of the carrier accumulation layer 24 was made smaller than the impurity concentration of the source layer 18. Since the impurity concentration of the carrier storage layer 24 is made higher than the impurity concentration of the drift layer 12, it is possible to prevent a large-scale depletion layer from being formed in the carrier storage layer 24. That is, an increase in the surface area S of the depletion layer can be suppressed. Further, by making the impurity concentration of the carrier storage layer 24 smaller than the impurity concentration of the source layer 18, the impurity concentration of the carrier storage layer 24 becomes extremely large, and it is prevented that holes are difficult to escape above the carrier storage layer 24. it can.

Since the distance L1 between the adjacent active trench gates is 1.5 μm or less and the impurity concentration of the carrier storage layer 24 is larger than the impurity concentration of the drift layer 12, the depletion layer capacity can be reduced. If the impurity concentration of the carrier accumulation layer is not realized, Cge cannot be sufficiently reduced and Cgc is increased.

By the way, in the portion where the active trench gate and the dummy trench gate are adjacent to each other, the depletion layer spreads from the side wall of the active trench gate, but the depletion layer does not spread from the side wall of the dummy trench gate. Therefore, it is not possible to obtain the effect of reducing Cge by overlapping the two depletion layers. Therefore, it is necessary to determine the arrangement of the active trench gate and the dummy trench gate in consideration of the density of the adjacent portion between the active trench gate and the dummy trench gate.

FIG. 5 is a graph showing the relationship between the arrangement method of the active trench gate and the dummy trench gate and the Cge. 2: 1 means that the ratio (number ratio) of the number of active trench gates to the number of dummy trench gates is 2: 1. 1: 1 means that the ratio of the number of active trench gates to the number of dummy trench gates is 1: 1 and 1: 2 means that the ratio of the number of active trench gates to the number of dummy trench gates is 1: 2. Represents that.

The multiple of the trench gate on the horizontal axis indicates how many trench gates 1 in the above ratio is composed of. Specifically, the six plots in the case of 1: 1 in FIG. 5 will be focused on. In the case of 1: 1 and if the multiple of the trench gate is x1, one active trench gate and one dummy trench gate are alternately provided. Since the sum of one active trench gate and one dummy trench gate is 2, and one of them is active, it is called 1/2 decimation. In the case of 1: 1 and if the multiple of the trench gate is x2, two active trench gates and two dummy trench gates are alternately provided.

In the case of 1: 1 and if the multiple of the trench gate is x3, three active trench gates and three dummy trench gates are alternately provided. The semiconductor element according to the first embodiment of the present invention corresponds to the case where the ratio is 1: 1 and the multiple of the trench gate is x3. The sum of the three active trench gates and the three dummy trench gates is 6, and three of them are active, so it is called 3/6 decimation.

In the case of 1: 1 and if the multiple of the trench gate is x4, four active trench gates and four dummy trench gates are alternately provided. Then, if the multiple of the trench gate is x5, five active trench gates and five dummy trench gates are alternately provided. If the multiple of the trench gate is x6, six active trench gates and six dummy trench gates are alternately provided.

For example, in the case of 2: 1 and if the multiple of the trench gate is x3, 6 active trench gates and 3 dummy trench gates are alternately provided. For example, in the case of 1: 2, if the multiple of the trench gate is x3, three active trench gates and six dummy trench gates are alternately provided. By using the term "thinning out" described above, each of the 18 plots in FIG. 5 can be briefly described. For example, in the case of a number ratio of 2: 1, if the multiple of the trench gate is x1, it is called "1/3 thinning out", and in the case of a number ratio of 1: 2, if the multiple of the trench gate is x1. It is called "2/3 thinning out".

As is clear from the explanation so far, increasing the multiple of the trench gate means multiplying each number by an integer while keeping the number ratio of the active trench gate and the dummy trench gate fixed.

Since "3/6 thinning out" is adopted in the first embodiment of the present invention, Cge can be reduced by 20% as compared with the semiconductor element of 1/2 thinning out. Moreover, there is no increase in Cgc. Therefore, Cgc / Cge can be increased by 20% as compared with 1/2 thinning out. Therefore, it is possible to suppress that the recovery dV / dt of the freewheeling diode depends on the collector current of the semiconductor element.

From FIG. 5, it can be seen that a low Cge can be obtained even when the ratio (number ratio) of the number of active trench gates to the number of dummy trench gates is 1: 2. However, when the number ratio is 2: 1, the Cge is larger than when the number ratio is 1: 1. Since the 1/3 thinning, which is the reference structure when the number ratio is 2: 1 is a structure in which the active trench gates are adjacent to each other, the Cge reduction effect due to the active trench gates being adjacent to each other has already been obtained. Even if the multiple of the gate is increased, the Cge cannot be significantly reduced.

In the first embodiment of the present invention, 3/6 thinning is adopted, but another arrangement may be adopted. By adopting a configuration in which the first structure in which three or more active trench gates are lined up and the second structure in which three or more dummy trench gates are lined up are provided alternately, the number of adjacent active trench gates is increased, and the active trench gate and the active trench gate Since the adjacent density of the dummy trench gate can be reduced, Cge can be reduced. On top of that, the number of dummy trench gates in the second structure is made larger than the number of active trench gates in the first structure (for example, 1: 2), so that the Cge can be particularly lowered. In the first embodiment of the present invention, the carrier storage layer 24 is formed, but the present invention is not limited to this, and the carrier storage layer 24 may not be formed.

FIG. 6 is a diagram showing the relationship between the collector current of the semiconductor element according to the first embodiment of the present invention and the recovery dV / dt of the freewheeling diode. Since the semiconductor element of the first embodiment realizes a small Cge, the Cgc / Cge becomes large, and it is possible to suppress that the recovery dV / dt of the freewheeling diode depends on the collector current of the semiconductor element. FIG. 7 is a graph illustrating the effect of reducing the turn-on loss. FIG. 7 shows that the turn-on loss could be reduced by reducing the Cge as described above.

According to the semiconductor device according to the first embodiment of the present invention, the steady loss (Vce (sat)) can be reduced. That is, the portion of the base layer 22 sandwiched between the dummy trench gates D1 and D2 is not connected to the emitter electrode 46, so that a floating base layer is formed. The floating base layer promotes the Injection Enhancement effect (IE effect). Since holes are accumulated in the floating base layer and conductivity modulation occurs, the specific resistance of the drift layer 12 is lowered and Vce (sat) can be reduced.

The semiconductor device according to the first embodiment of the present invention can be variously modified. For example, the semiconductor element does not form an IGBT, but may form a trench MOSFET or an RC-IGBT. The semiconductor substrate 10 may be formed of silicon, or may be formed of a wide bandgap semiconductor having a larger bandgap than silicon. Wide bandgap semiconductors include, for example, silicon carbide, gallium nitride based materials or diamond. The n-type layer may be replaced with a p-type, and the p-type layer may be replaced with an n-type. That is, each layer of the semiconductor substrate is formed of the first conductive type or the second conductive type. Each of the above-described modifications can be appropriately applied to the semiconductor device according to the following embodiment. Since the semiconductor elements according to the following embodiments have much in common with the first embodiment, the differences from the first embodiment will be mainly described.

Embodiment 2.
FIG. 8 is a partial cross-sectional view of the semiconductor element according to the second embodiment. The portion of the base layer 22 sandwiched between the dummy trench gates D1 is connected to the emitter electrode 46. That is, the emitter contacts 44 are provided on both sides of the dummy trench gate D1, and the dummy trench gate D1 is sandwiched between the emitter contacts 44. A p + type contact layer 20 for reducing contact resistance may be formed below the emitter contact 44. The pattern of the contact layer 20 is not limited to a specific pattern, and may be selectively formed at the lower part of the emitter contact 44, for example. By providing the emitter contact 44 in the portion sandwiched between the dummy trench gates D1, it is possible to promote the discharge of holes from the emitter contact 44 and reduce the turn-off loss.

In particular, when the number of dummy trench gates is large, the increase in turn-off loss becomes a problem rather than the effect of reducing Vce (sat) due to the IE effect due to the formation of the floating base layer. Therefore, by providing the emitter contacts 44 on all the base layers 22 as shown in FIG. 8, the turn-off loss can be reduced.

Here, the emitter contact 44 may be provided only on the right side of a certain dummy trench gate D1, and the emitter contact 44 may not be provided on the left side of the dummy trench gate D1. This makes it possible to adjust the amount of accumulated holes. Alternatively, emitter contacts 44 may be provided on both sides of one dummy trench gate D1, but emitter contacts 44 may be provided on only one side of another dummy trench gate D1. Explaining with reference to FIG. 9, according to the second structure 62, there are two or more base layers 22 sandwiched between the dummy trench gates D1, one of which is connected to the emitter electrode 46, and the other of which is the emitter electrode 46. Not connected to. By doing so, the turn-on loss can be reduced without deteriorating the trade-off characteristics between the turn-off loss and Vce (sat).

Embodiment 3.
FIG. 10 is a partial cross-sectional view of the semiconductor element according to the third embodiment. The emitter electrode 46 (emitter contact 44) is connected only to the portion of the base layer 22 sandwiched between the active trench gates. The Cge generated between the active trench gate and the emitter contact 44 between the active trench gate and the dummy trench gate is reduced by thinning out the emitter contact 44.

Since the potential of the floating base layer 22'adjacent to the active trench gate fluctuates due to the hole flowing in at the time of turn-on to generate a displacement current, the dV / dt increases at the time of low current. Therefore, it is important to reduce the density of the floating base layer 22'by alternately providing the first structure in which three or more active trench gates are lined up and the second structure in which three or more dummy trench gates are lined up as described above. Is.

FIG. 11 is a partial cross-sectional view of the semiconductor element according to the modified example. The emitter electrode 46 (emitter contact 44) is connected only to the portion of the base layer 22 sandwiched between the active trench gates and the portion sandwiched between the dummy trench gates. No emitter contact 44 is provided on the base layer 22 between the active trench gate and the dummy trench gate. As a result, Cge can be reduced and turn-off loss can be reduced while promoting the discharge of holes from the emitter contact 44.

Embodiment 4.
FIG. 12 is a partial cross-sectional view of the semiconductor element according to the fourth embodiment. The base layer 22 is formed so as to avoid the region between the active trench gate and the dummy trench gate. That is, the base layer 22 is not arranged between the active trench gate A1 and the dummy trench gate D1. Thereby, the Cge generated between the active trench gate A1 and the emitter contact between the active trench gate A1 and the dummy trench gate D1 can be reduced.

By alternately providing the first structure in which three or more active trench gates are lined up and the second structure in which three or more dummy trench gates are lined up as described above, the portion where the base layer 22 is omitted (active trench gate and dummy trench). The proportion of the base layer 22 increases as the proportion of the part between the gates decreases. Since the base layer 22 has a function of increasing the pressure resistance by extending the depletion layer at the time of reverse bias, the pressure resistance can be increased by increasing the ratio of the base layer 22 as described above.

Embodiment 5.
FIG. 13 is a plan view of a semiconductor substrate constituting the semiconductor element according to the fifth embodiment. Three active trench gates A1 extend in the lateral direction. The three active trench gates A1 are connected by active trench gates extending in the lateral direction thereof, and the active trench gates have a mesh shape in a plan view. The dummy trench gate D1 is arranged in a striped shape in a plan view. The shape of the dummy trench gate D1 is not limited to the stripe shape and may be a mesh shape.

By forming a mesh-shaped active trench gate, when a voltage is applied between the gate and the emitter, the depletion layer spreads not only in the x positive / negative direction but also in the y positive / negative direction, and the spread depletion layers overlap each other. Therefore, the surface area S of the depletion layer is small, the distance d of the depletion layer is large, and the Cge can be reduced.

The number of active trench gates constituting the first structure is not limited to three. Cge can be reduced by connecting three or more active trench gates constituting the first structure to form a mesh-like first structure in a plan view.

Embodiment 6.
FIG. 14 is a partial cross-sectional perspective view of the semiconductor element according to the sixth embodiment. The source layer 18 has a first source layer 18a and a second source layer 18b intersecting a plurality of active trench gates A1 and A2 extending in parallel and a plurality of dummy trench gates D1. The distance between the first source layer 18a and the second source layer 18b is not constant. In other words, the spacing between the source layers is not constant and is partially long. For example, when the distance L4 between the source layers is 1, the distance L5 between the source layers is 10.

With such a configuration, the electron injection efficiency changes in each cell. In cells with long source layer spacing, the injection efficiency is low and the threshold voltage Vth is high. Therefore, two types of cells, a high Vth cell and a normal Vth cell, are configured in the same chip. FIG. 14 shows a high Vth cell (High Vth cell) and a normal Vth cell (Ref Vth cell). The recovery dV / dt depends on the time change dVge / dt of the gate-emitter voltage, and the dVge / dt depends on the threshold voltage Vth. If dVge / dt increases rapidly at turn-on, dV / dt also increases rapidly. When two types of cells with different Vths are configured, the size of dVge / dt emitted from each cell is different and the phase is out of phase. Therefore, when viewed as a chip, the peak of dVge / dt emitted from each cell is large. The small part and the small part overlap each other. Therefore, the peak of dVge / dt becomes gentle. As a result, the current dependence of recovery dV / dt can be reduced. Further, since the peak of the dVge / dt waveform can be reduced, EMI noise can be reduced.

The effects of the present invention may be enhanced by appropriately combining the characteristics of the semiconductor elements according to the above embodiments.

10 Semiconductor substrate, 18 Source layer, 20 Contact layer, 22 Base layer, 24 Carrier storage layer, 46 Emitter electrode, 50 Gate electrode, 60,64 1st structure, 62,66 2nd structure, 80 Depletion layer, A1, A2 Active trench gate, D1, D2 dummy trench gate

Claims (11)

With a semiconductor substrate
An emitter electrode formed on the semiconductor substrate and
The gate electrode formed on the semiconductor substrate and
A first conductive type source layer formed on the upper surface side of the semiconductor substrate, and
A second conductive type base layer formed on the upper surface side of the semiconductor substrate, and
A collector electrode formed under the semiconductor substrate and
A plurality of active trench gates formed on the upper surface side of the semiconductor substrate and connected to the gate electrode,
A plurality of dummy trench gates formed on the upper surface side of the semiconductor substrate and not connected to the gate electrode are provided.
The first structure in which three or more active trench gates are lined up and the second structure in which three or more dummy trench gates are lined up are alternately provided, and the second structure is larger than the number of active trench gates in the first structure. The number of dummy trench gates in the structure is large
The semiconductor element is characterized in that the base layer is connected to the emitter electrode between the first structure and the second structure. The semiconductor substrate is
A first conductive type carrier storage layer provided under the base layer formed under the source layer, and
A first conductive type drift layer under the carrier storage layer is provided.
The impurity concentration of the carrier accumulation layer is larger than the impurity concentration of the drift layer and smaller than the impurity concentration of the source layer.
The semiconductor device according to claim 1, wherein the plurality of active trench gates and the plurality of dummy trench gates penetrate the source layer, the base layer, and the carrier storage layer. A portion of the base layer adjacent to the active trench gate is connected to the emitter electrode.
The semiconductor element according to claim 1 or 2, wherein a portion of the base layer sandwiched between the dummy trench gates is not connected to the emitter electrode. A portion of the base layer adjacent to the active trench gate is connected to the emitter electrode.
The semiconductor element according to claim 1 or 2, wherein a portion of the base layer sandwiched between the dummy trench gates is connected to the emitter electrode. The second structure is characterized in that there are two or more base layers sandwiched between the dummy trench gates, one of which is connected to the emitter electrode and the other of which is not connected to the emitter electrode. The semiconductor element according to claim 1 or 2. Any of claims 1 to 5, wherein the first structure is formed in a mesh shape in a plan view by connecting three or more active trench gates constituting the first structure. The semiconductor element according to item 1. The source layer has a first source layer and a second source layer that intersect the plurality of active trench gates and the plurality of dummy trench gates.
The semiconductor device according to any one of claims 1 to 6, wherein the distance between the first source layer and the second source layer is not constant. The semiconductor element according to any one of claims 1 to 7, wherein the trench MOSFET is formed. The semiconductor element according to any one of claims 1 to 8, wherein the RC-IGBT is formed. The semiconductor element according to any one of claims 1 to 9, wherein the semiconductor substrate is formed of a wide bandgap semiconductor. The semiconductor device according to claim 10, wherein the wide bandgap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.

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