JP6747247B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and particularly to a technique effectively applied to a semiconductor device having a field effect transistor using a semiconductor film made of a metal oxide as a channel layer.

A thin film transistor (TFT), which is a type of field effect transistor, is a device that plays an important role in electronics technology, and is used for a pixel switch of a liquid crystal display. Currently, amorphous silicon is widely used as a channel layer material of a thin film transistor, but in recent years, a thin film transistor using a semiconductor film made of a metal oxide as a channel layer has been used as an alternative material of these silicon materials. Is attracting attention.

For example, JP 2006-165532 A (Patent Document 1) discloses a semiconductor device using an oxide containing In, Ga, and Zn.

In addition, Japanese Patent Laid-Open No. 2008-243928 (Patent Document 2) discloses a thin film transistor using an amorphous oxide containing indium, tin, zinc and oxygen. Further, Japanese Patent Application Laid-Open No. 2012-033699 (Patent Document 3) discloses a technique of manufacturing a thin film transistor by using an oxide semiconductor target made of an oxide sintered body containing zinc oxide and tin oxide as main materials. ing.

Further, in Japanese Patent No. 5503667 (Patent Document 4), a first semiconductor layer containing indium oxide as a main component, and zinc and tin oxide containing no indium on the first semiconductor layer as a main component are included. An oxide semiconductor TFT having a second semiconductor layer is disclosed.

JP, 2006-165532, A JP, 2008-243928, A JP 2012-033699A Japanese Patent No. 5503667

The present inventor is engaged in research and development of thin film transistors and metal oxide materials suitable for use in the transistors.

However, regarding the metal oxide material used for the thin film transistor, even if the developed material is simply applied to the conventional structure or manufacturing process, the characteristics may be deteriorated. Details will be described later.

For this reason, in addition to improving the characteristics of the developed material, it is desired to find out the optimum structure and manufacturing method by conducting a composite examination of the application site and manufacturing process.

The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

The following is a brief description of the outline of the typical invention disclosed in the present application.

Among the inventions disclosed in the present application, a semiconductor device shown in a typical embodiment includes a gate electrode formed on a substrate, and a first semiconductor film formed on the gate electrode via a gate insulating film. , A second semiconductor film formed on the first semiconductor film, and source and drain electrodes formed on the second semiconductor film. The edge of the first semiconductor film is receded from the edge of the second semiconductor film.

Among the inventions disclosed in the present application, a method for manufacturing a semiconductor device shown in a representative embodiment has a step of etching a laminated film of a first semiconductor film and a second semiconductor film. Then, this etching step includes a step of etching the laminated film with the first etching liquid, and a step of etching the first semiconductor film from the sidewall of the laminated film with the second etching liquid after this step.

Among the inventions disclosed in the present application, the characteristics can be improved according to the semiconductor device shown in the following representative embodiments.

Among the inventions disclosed in the present application, according to the method of manufacturing a semiconductor device shown in the following representative embodiments, it is possible to manufacture a semiconductor device having excellent characteristics.

FIG. 3 is a cross-sectional view showing the configuration of the semiconductor device of the first embodiment. FIG. 3 is a cross-sectional view showing the configuration of the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first embodiment. FIG. 4 is a cross sectional view showing the manufacturing process of the semiconductor device of the first embodiment, which is a cross sectional view showing a step following FIG. 3; FIG. 5 is a cross sectional view showing the manufacturing process of the semiconductor device of the first embodiment, which is a cross sectional view showing a step following FIG. 4. FIG. 6 is a cross sectional view showing the manufacturing process of the semiconductor device of the first embodiment, which is a cross sectional view showing a step following FIG. 5; FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment, which is a cross-sectional view showing a step following FIG. 6; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first embodiment, which is a cross-sectional view showing a process following FIG. 7. FIG. 9 is a cross sectional view showing the manufacturing process of the semiconductor device of the first embodiment, which is a cross sectional view showing a step following FIG. 8. FIG. 10 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment, which is a cross-sectional view showing a process following FIG. 9. FIG. 7 is a cross-sectional view showing the configuration of the semiconductor device of the comparative example of the first embodiment. It is a figure which shows the structure of the semiconductor device of a comparative example. It is a figure which shows the current-voltage characteristic of the semiconductor device of a comparative example. FIG. 3 is a diagram showing a configuration of the semiconductor device of the first embodiment. FIG. 6 is a diagram showing current-voltage characteristics of the semiconductor device of the first embodiment. FIG. 7 is a cross-sectional view showing another configuration of the semiconductor device of the first embodiment. FIG. 11 is a diagram showing current-voltage characteristics of the semiconductor device of the first example of the second embodiment. FIG. 11 is a diagram showing current-voltage characteristics of the semiconductor device of the second example of the second embodiment. It is a circuit diagram which shows the structure of an active matrix substrate. It is a top view which shows the structure of an active matrix substrate.

In the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, amount, range, etc.), unless explicitly stated and in principle limited to a specific number, etc., The number is not limited to the specific number, and may be more than or less than the specific number. Further, in the following embodiments, the notation such as “first”, “second”, “third”, etc. is given to identify the constituent elements, and does not necessarily limit the number or order. Absent.

Further, the position, size, range, etc. of each configuration shown in the drawings and the like do not necessarily correspond to the actual device, and in order to make the description easy to understand, the position, size, range, etc. are appropriately changed and shown. There is.

(Embodiment 1)
Hereinafter, the semiconductor device of the present embodiment will be described in detail with reference to the drawings.

[Structure description]
1 and 2 are cross-sectional views showing the configuration of the semiconductor device according to the present embodiment. FIG. 2 is a partially enlarged view of FIG. The semiconductor device shown in FIG. 1 is a thin film transistor. The thin film transistor is a so-called bottom gate/top contact structure transistor.

The bottom gate structure means that the gate electrode GE is provided in a layer below a semiconductor film (channel layer, here, a stacked film MO of the first metal oxide semiconductor film MO1 and the second metal oxide semiconductor film MO2) forming a channel. Refers to the structure that is arranged. Further, the top contact means a structure in which the source and drain electrodes SD are arranged in a layer above the semiconductor film (here, the laminated film MO).

That is, as shown in FIG. 1, the thin film transistor of the present embodiment is arranged on the main surface of the substrate SUB. Specifically, the thin film transistor of the present embodiment includes a gate electrode GE arranged on the substrate SUB, and the laminated film MO which is a semiconductor film arranged on the gate electrode GE via a gate insulating film GI, The source and drain electrodes SD are arranged on the laminated film MO.

The source/drain electrodes SD are arranged at a predetermined interval on the overlapping region of the gate electrode GE and the laminated film MO. The portion of this predetermined interval becomes the channel region.

Here, the laminated film MO has a first metal oxide semiconductor film (first semiconductor film) MO1 and a second metal oxide semiconductor film (second semiconductor film) MO2 arranged thereabove. The first metal oxide semiconductor film (first semiconductor film) MO1 is a metal oxide containing at least In element and O element as main components. The second metal oxide semiconductor film (second semiconductor film) MO2 is a metal oxide containing at least Zn element and O element as main components and not containing In element as main components. Here, the main component in the present application means an element having a content rate of 10 atomic% or more, not contained as an impurity. For example, the carrier density of the first metal oxide semiconductor film (first semiconductor film) MO1 is 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less, and the second metal oxide semiconductor film (second (Semiconductor film) MO2 has a carrier density of 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁷ cm ⁻³ or less.

The first metal oxide semiconductor film (first semiconductor film) MO1 is, for example, an ITO film. The film thickness of the ITO film is, for example, about 5 nm. The ITO (indium tin oxide, In-Sn-O, indium tin oxide, indium tin composite oxide) film is a metal oxide composed of tin, indium, and oxygen. Therefore, the ITO film contains tin, indium, and oxygen as main components.

The second metal oxide semiconductor film (second semiconductor film) MO2 is, for example, a ZTO film. The film thickness of the ZTO film is, for example, about 50 nm. The ZTO (zinc-tin oxide, zinc tin oxide, zinc tin composite oxide) film is a metal oxide containing tin, zinc and oxygen as main components. This ZTO film does not contain a rare metal as a main component and is a material advantageous in terms of cost. The ZTO film has a carrier density of about 2×10 ¹⁶ cm ⁻³ , and the ITO film has a carrier density of about 2×10 ¹⁹ cm ⁻³ .

By using the metal oxide (MO) channel layer having such a stacked structure, on-state characteristics (carrier mobility and on-state) can be obtained as compared with the case where a single-layer oxide semiconductor layer such as a single-layer IGZO is used as a channel layer. Current) can be improved, and the operation (driving) can be speeded up. In addition, the low leakage current at the time of off maintains the characteristics of oxide semiconductors such as single-layer IGZO, and power saving can be achieved.

Since the laminated structure channel including the ITO layer and the ZTO layer shown as an example here has high on-characteristics as described above, even if the thin film transistor is miniaturized as the pixel size is miniaturized, a good on-current can be obtained. Can be secured. In other words, sufficient transistor characteristics can be maintained even when miniaturized, and when applied to ultra-high-definition displays such as 4K and 8K, a high aperture ratio can be achieved, resulting in high brightness of ultra-high-definition displays. Higher contrast and wider dynamic range can be achieved.

Further, in the above-mentioned laminated structure, it is possible to apply a low-cost back channel etching process by using the ZTO film having high resistance to electrode processing as the upper layer. Furthermore, since ZTO has resistance to process damage due to the passivation film formation process, it is possible to realize a reduction in manufacturing cost as compared with a general oxide semiconductor process such as single-layer IGZO.

Then, the end portion of the lower first metal oxide semiconductor film MO1 is set back from the end portion of the upper second metal oxide semiconductor film MO2. In other words, the formation region of the lower first metal oxide semiconductor film MO1 is slightly smaller than the formation region of the upper second metal oxide semiconductor film MO2. The distance between the end of the lower first metal oxide semiconductor film MO1 and the end of the upper second metal oxide semiconductor film MO2 is set to "L1" (see FIG. 2).

Therefore, a gap (gap SP) is formed between the lower first metal oxide semiconductor film MO1 and the source/drain electrode SD. In other words, an “undercut portion” in which the lower first metal oxide semiconductor film MO1 is not formed is arranged near the end portion of the upper second metal oxide semiconductor film MO2.

In this way, by retracting the end portion of the lower first metal oxide semiconductor film MO1, it is possible to secure the distance L2 between the lower first metal oxide semiconductor film MO1 and the source/drain electrodes SD, A short circuit between the source/drain electrode SD and the underlying first metal oxide semiconductor film MO1 can be prevented. As a result, transistor characteristics, particularly off characteristics, can be improved. Details will be described later.

[Description of manufacturing method]
Next, the manufacturing process of the semiconductor device of the present embodiment will be described and the structure of the semiconductor device of the present embodiment will be clarified.

3 to 10 are cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment.

First, as shown in FIG. 3, the gate electrode GE is formed on the substrate SUB. As the substrate SUB, for example, a substrate made of glass, quartz, sapphire, or the like can be used. Also, a substrate made of a plastic film or the like, a so-called flexible substrate may be used.

Then, on the substrate SUB, as a gate electrode material (conductive material), for example, a molybdenum (Mo) film is deposited with a film thickness of about 100 nm by using a DC magnetron sputtering method or the like. As the gate electrode material, in addition to molybdenum (Mo), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), silver (Ag), gold ( A metal material such as Au), platinum (Pt), tantalum (Ta), or zinc (Zn) can be used. These may be used alone, or some of these metals may be used as an alloy. Alternatively, a conductive metal nitride such as titanium nitride (TiN) may be used. Alternatively, a semiconductor containing impurities and having many carriers (electrons, holes) may be used. Alternatively, a stacked body of the above metal compound (metal oxide, metal nitride) or semiconductor and a metal (including an alloy) may be used. In addition to the sputtering method, a vapor deposition method, a CVD (Chemical Vapor Deposition) method, or the like can be used for forming the gate electrode material.

Next, a photoresist film (not shown) is formed on the gate electrode material (Mo film), and the photoresist film is left only in the formation region of the gate electrode GE by exposure/development processing. Next, by using this photoresist film as a mask, the gate electrode material (Mo film) is etched by reactive ion etching (RIE (Reactive Ion Etching)) or the like to form the gate electrode GE. Dry etching such as reactive ion etching may be performed, or wet etching may be performed. The shape of the gate electrode GE (planar shape when viewed from the upper surface) is, for example, a substantially rectangular shape having long sides in the direction intersecting the plane of the drawing.

Next, as shown in FIG. 4, a gate insulating film GI is formed on the gate electrode GE. As the gate insulating film GI, for example, a silicon oxide film (SiOx) is deposited to a thickness of about 100 nm by the PE-CVD method or the like. Other than the silicon oxide film, another oxide film such as an aluminum oxide film may be used. In addition to the oxide film, an inorganic insulating film such as a silicon nitride film or an aluminum nitride film can be used. Alternatively, an organic insulating film such as parylene may be used. In addition to the above CVD method, a sputtering method, a coating method, or the like may be used as the film forming method.

Next, as shown in FIG. 5, a semiconductor film (MO) is formed on the gate insulating film GI. Specifically, the first metal oxide semiconductor film MO1 is formed on the gate insulating film GI, and the second metal oxide semiconductor film MO2 is further formed on the first metal oxide semiconductor film MO1. The first metal oxide semiconductor film MO1 is a film forming a main channel region of a thin film transistor and has a semiconductor property. Here, as the first metal oxide semiconductor film MO1, an ITO film is deposited with a film thickness of about 5 nm by using, for example, a DC magnetron sputtering method. For example, using a target material having a tin composition of 10 at% and an indium composition of 90 at%, film forming conditions, room temperature, film forming pressure of 0.5 Pa, sputtering gas Ar/O ₂ mixed gas (oxygen addition ratio of about 30%), DC power of 50 W At, an ITO film can be formed. As the first metal oxide semiconductor film MO1, an IZO film or an IGZO film may be used in addition to the ITO film. An application example of these films will be described in detail in Embodiment 2.

Then, the second metal oxide semiconductor film MO2 is continuously formed on the first metal oxide semiconductor film MO1. This second metal oxide semiconductor film MO2 is also a film having semiconductor properties. Here, as the second metal oxide semiconductor film MO2, a ZTO film is deposited with a film thickness of about 50 nm by using, for example, a DC magnetron sputtering method. For example, using a target material having a tin composition of 30 at% and a zinc composition of 70 at% (adding 500 ppm of Al), film forming conditions, room temperature, film forming pressure of 0.5 Pa, sputtering gas Ar/O ₂ mixed gas (oxygen addition ratio of about 10% ), the ZTO film can be formed. In addition to the above-mentioned sputtering method, a CVD method, a PLD method, a coating method, a printing method, or the like can be used as a film forming method. It is possible. Further, compared with the chemical vapor deposition method or the like, there is an advantage that a material having low heat resistance (for example, a resin substrate material) can be selected because the film can be formed at a relatively low temperature.

In this way, a laminated film MO of the first metal oxide semiconductor film (ITO film) MO1 and the second metal oxide semiconductor film (ZTO film) MO2 arranged thereover can be formed.

Next, a photoresist film PR1 is formed on the stacked film MO, and the photoresist film PR1 is left only in a substantially rectangular region which is slightly larger than the region where the gate electrode GE is formed by exposure/development processing. Next, by using the photoresist film PR1 as a mask, the laminated film MO is wet-etched (first etching) to form the laminated film MO having the above-described shape. An oxalic acid-based etching liquid can be used as the etching liquid. The etching time is about 3 to 4 minutes. The oxalic acid-based etching solution is an etching solution generally used in etching the ITO film. Further, the oxalic acid-based etching solution can etch the ZTO film.

Here, in etching (so-called patterning process) using the photoresist film PR1 as a mask, the side surface of the film to be etched tends to have a tapered shape. This is because the upper part of the film to be etched is more likely to be exposed to the etching agent and the etching is more likely to proceed than the lower part. Further, regarding the etching rate (nm/min) by the oxalic acid-based etching solution, the ITO film is 120, while the ZTO film is 215, and the etching rate of the ITO film is smaller than that of the ZTO film. Therefore, the lower ITO film is less likely to be etched, and the taper angle becomes smaller. The taper angle mentioned here is an angle formed between the substrate surface and the side surface of the ITO film.

In this way, the etching end surface is tapered at the end of the stacked film MO. In other words, the end portion of the first metal oxide semiconductor film (ITO film) MO1 protrudes outside the end portion of the second metal oxide semiconductor film (ZTO film) MO2 (FIG. 6). ).

Then, the photoresist film PR1 is removed. Next, as shown in FIG. 7, the lower first metal oxide semiconductor film (ITO film) MO1 is wet-etched (second etching). As a result, an undercut is formed under the edge of the upper second metal oxide semiconductor film (ZTO film) MO2. Dilute nitric acid (about 0.7%) can be used as the etching liquid. The etching time is about 2 minutes. Regarding the etching rate of dilute nitric acid (about 0.7%), the ITO film is 5.0, while the ZTO film is 0.2, and the etching rate of the ZTO film is smaller than that of the ITO film. Only are selectively etched. Therefore, an undercut (side etching) of about 10 to 15 nm is formed from the end of the ZTO film. In other words, the ITO film recedes from the end of the ZTO film by about 10 to 15 nm. As a result, a space SP is formed below the end of the ZTO film. The degree of the undercut has an appropriate numerical value in terms of device design, process such as film forming technology, and can be appropriately adjusted.

Next, as shown in FIG. 8, a metal film MF is formed as a conductive film on the second metal oxide semiconductor film (ZTO film) MO2. The metal film MF becomes the source/drain electrodes SD. On the second metal oxide semiconductor film (ZTO film) MO2, as the metal film MF, for example, a Mo film is deposited with a film thickness of about 100 nm by using a DC magnetron sputtering method or the like. As the metal film MF, in addition to molybdenum (Mo), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), tantalum (Ta), silver ( A single layer film of a metal such as Ag) or zinc (Zn) can be used. In addition, an alloy film containing two or more kinds of metals among the plurality of metals can be used. In addition, a laminated film of two or more kinds of films among the films made of the above metals and the alloy films can be used. For example, a laminated film of Mo film/Al film/Mo film may be used. For forming the metal film MF, a vapor deposition method, a CVD method, or the like can be used in addition to the sputtering method. Here, it is possible to use a film forming method having high anisotropy (directivity) so that the voids (spaces) SP are not filled below the end portion of the second metal oxide semiconductor film (ZTO film) MO2. preferable. For example, according to the sputtering method or the vapor deposition method, the void (space) SP below the end portion of the ZTO film is hard to fill, which is preferable as a method for forming the metal film MF.

By forming the metal film MF, the side surface (side wall) of the stacked film MO is covered with the metal film MF. At this time, a space SP remains below the end of the ZTO film.

Next, a photoresist film PR2 is formed on the metal film MF, and the photoresist film PR2 above the gate electrode GE is removed by exposure/development processing. Next, by using the photoresist film PR2 as a mask, the metal film MF is wet-etched to form the source/drain electrodes SD (FIG. 9). A PAN-based etching solution or the like can be used as the etching solution. Here, when the metal film MF is etched, the upper layer of the laminated film MO is the second metal oxide semiconductor film (ZTO film) MO2 having a high resistance to the etching solution (here, PAN-based etching solution) for the metal film MF. Therefore, etching damage to the laminated film MO can be reduced. Therefore, the characteristics of the laminated film MO serving as the channel are improved, and the transistor characteristics can be improved. Such an etching process of the metal film MF is called a BCE (Back-Channel-Etch, back channel etch) process.

Next, as shown in FIG. 10, a protective film PRO is formed on the stacked film MO and the source/drain electrodes SD. As the protective film, for example, a laminated film (SiNx/SiOx) of a silicon oxide film and a silicon nitride film can be used. For example, a silicon oxide film is formed on the laminated film MO and the source/drain electrodes SD by the PE-CVD method or the like, and a silicon nitride film is formed on the silicon oxide film by the PE-CVD method or the like.

Through the above steps, the thin film transistor of this embodiment is almost completed.

As described above, according to the present embodiment, the laminated film MO of the first and second metal oxide semiconductor films (MO1 and MO2) is used as the channel layer, and the lower first metal oxide semiconductor film MO1 is formed. Since the second metal oxide semiconductor film MO2 in the upper layer is made to recede, a short circuit between the source/drain electrodes SD and the first metal oxide semiconductor film MO1 in the lower layer can be prevented. Thereby, a thin film transistor having favorable characteristics can be obtained.

On the other hand, in the case of the comparative example in which the source/drain electrodes SD are formed without receding the lower first metal oxide semiconductor film MO1 from the upper second metal oxide semiconductor film MO2, the source/drain The electrode SD and the underlying first metal oxide semiconductor film MO1 are short-circuited and have no transistor characteristics.

FIG. 11 is a cross-sectional view showing the configuration of the semiconductor device (thin film transistor) of the comparative example of the present embodiment. In the semiconductor device of the comparative example, the source/drain electrodes SD are formed on the laminated film MO in which the end portion of the ITO film protrudes outside the end portion of the ZTO film described with reference to FIG. It is a thing. FIG. 12 is a diagram showing a configuration of a semiconductor device of a comparative example. (A) is a cross-sectional SEM photograph, and (B) is a schematic representation of the photograph of (A). As shown in FIG. 12, when the laminated film (ZTO, ITO) MO is etched using the photoresist film PR as a mask, the end surface of the laminated film MO has a tapered shape (see the area surrounded by a broken line).

In such a case, as shown in FIG. 11, the source/drain electrode SD and the underlying first metal oxide semiconductor film MO1 come into contact with each other, so that a short circuit occurs therebetween. Such a short-circuited thin film transistor can no longer operate as a transistor. FIG. 13 is a diagram showing current-voltage characteristics of the semiconductor device of the comparative example. In FIG. 13, the horizontal axis represents the gate voltage (Vg, [V]), the vertical axis represents the drain current [A], and the three graphs show that the drain voltage (Vd, [V]) is 0.1V. 1V, 10V. As is clear from FIG. 13, the rise of the drain current cannot be confirmed, and it can be seen that the transistor cannot operate.

FIG. 14 is a diagram showing the configuration of the semiconductor device of this embodiment. (A) is a cross-sectional SEM photograph, and (B) is a schematic representation of the photograph of (A). As shown in FIG. 14, the laminated film (ZTO, ITO) MO is etched using the photoresist film PR as a mask, and further the second etching is performed, whereby the lower layer is formed on the end surface of the laminated film (ZTO, ITO) MO. It can be seen that the ITO of #1 recedes. In this manner, when the lower layer ITO is made to recede and the space SP is provided, the source/drain electrodes SD and the lower layer first metal oxide semiconductor film MO1 do not come into contact with each other, so that good transistor operation can be confirmed. .. FIG. 15 is a diagram showing current-voltage characteristics of the semiconductor device of this embodiment. That is, the current-voltage characteristics when ZTO/ITO is used as the laminated film MO are shown. As is clear from FIG. 15, the rise of the drain current can be confirmed, and it can be seen that the transistor can operate. In FIG. 15, the horizontal axis represents the gate voltage (Vg, [V]), the vertical axis represents the drain current [A], and the three graphs from the top show that the drain voltage (Vd, [V]) is 0. 1V, 1V, 10V. Further, the bottom graph shows carrier mobility (cm ² /Vs). As is clear from this graph, good transistor characteristics with a mobility of 39.5 cm ² /Vs could be confirmed.

By adopting the structure of the channel end portion of the present application, it becomes possible to practically manufacture and use a laminated channel structure TFT having good on-characteristics, and achieve high brightness and high contrast of an ultra-high-definition display such as 8K, A high dynamic range can be realized.

Further, according to the manufacturing process described in the present embodiment, the first metal oxide semiconductor film MO1 as the lower layer of the stacked film MO is made to recede using the second metal oxide semiconductor film MO2 as the upper layer as a mask. That is, it is possible to manufacture a thin film transistor having excellent characteristics with a minimum increase in the number of steps without increasing the number of masks. That is, a low cost process can be realized. Further, it is possible to avoid complication of the manufacturing process and improve the manufacturing yield.

Further, according to the manufacturing process described in the present embodiment, unlike the low temperature polysilicon process using laser annealing, it can be applied to a large screen display. The laser annealing process is not suitable for processing a large area, but the manufacturing process described in this embodiment can easily deal with increasing the area of a substrate. That is, a display can be manufactured at a lower cost than low temperature polysilicon using laser annealing.

In the present embodiment, the distance L1 between the end of the lower first metal oxide semiconductor film MO1 and the end of the upper second metal oxide semiconductor film MO2 is defined as Although the distance L2 between the oxide semiconductor film MO1 and the source/drain electrodes SD is shown to be approximately the same (FIG. 2), L1>L2 may be satisfied. FIG. 16 is a cross-sectional view showing another structure of the semiconductor device of this embodiment.

In FIG. 16, the distance L2 between the lower first metal oxide semiconductor film MO1 and the source/drain electrodes SD is equal to the end portion of the lower first metal oxide semiconductor film MO1 and the upper second metal oxide semiconductor. It is smaller than the distance L1 between the edge of the film MO2 (L1>L2). For example, even when the metal film is a little under the edge of the upper second metal oxide semiconductor film MO2 at the time of forming the metal film to be the source/drain electrodes SD (see FIG. 8), If the distance L2 between the first metal oxide semiconductor film MO1 and the source/drain electrode SD is secured, a short circuit between them can be prevented.

(About etching liquid)
In the above manufacturing process, oxalic acid is used as the first etching liquid for etching the laminated film MO of the first metal oxide semiconductor film (ITO film) MO1 and the second metal oxide semiconductor film (ZTO film) MO2. A dilute nitric acid (about 0.7%) was used as a second etching solution for etching the lower first metal oxide semiconductor film (ITO film) MO1 using a system-based etching solution. You may use.

The first etching solution is an etching solution capable of etching the second metal oxide semiconductor film (ZTO film) MO2 and the metal oxide semiconductor film (ITO film) MO1. The respective etching rates are preferably close to each other, for example, as compared with the case of the second etching liquid. In particular, the oxalic acid-based etching solution has high versatility and is suitable for use as the first etching solution. The oxalic acid-based etching solution is an etching solution containing at least oxalic acid.

In the second etching liquid, the etching rate R1 of the first metal oxide semiconductor film (ITO film) MO1 is higher than the etching rate R2 of the second metal oxide semiconductor film (ZTO film) MO2 (R1>R2). The lower first metal oxide semiconductor film (ITO film) MO1 is an etching solution that is more easily etched. As such a second etching solution, sulfuric acid, hydrochloric acid, hydrofluoric acid or the like can be used in addition to dilute nitric acid. The concentration of sulfuric acid may be about 1.0%, the concentration of hydrochloric acid may be about 0.4%, and the concentration of hydrofluoric acid may be about 0.03%. The concentration here is% by weight. Moreover, the above-mentioned concentration is an example, and can be appropriately adjusted including the treatment time. In addition, a PAN-based etching solution or a phosphoric acid-nitric acid-based etching solution may be used. The PAN-based etching solution contains phosphoric acid, nitric acid and acetic acid. The phosphoric acid-nitric acid-based etching solution contains phosphoric acid and nitric acid.

Table 1 is a table showing the relationship between the metal oxide semiconductor film and the etching rate of the etching solution. For example, the etching rates of the ZTO film and the ITO film at room temperature (25° C.) when the above etching solution is used are shown. In Table 1, the value in parentheses is the etching rate at 40°C. Further, Table 1 also shows the etching rates for the IZO film and the IGZO film in addition to the ITO film.

In this embodiment, the ITO film is used as the first metal oxide semiconductor film having a high carrier density, but an IZO film or an IGZO film may be used. An application example of these films will be described in Embodiment 2.

(Embodiment 2)
In this embodiment, a case where an IZO film is used as the first metal oxide semiconductor film MO1 (first example) and a case where an IGZO film is used (second example) will be described.

(First example)
Although the ITO film is used as the first metal oxide semiconductor film MO1 in the first embodiment, an IZO film may be used. The first metal oxide semiconductor film MO1 is the same as the first embodiment except for the specific film type. That is, the structure is the same as that described with reference to FIG. 1 and the like, and it can be formed by the same process as the manufacturing process described with reference to FIGS.

The semiconductor device of the first example is a thin film transistor having a bottom gate/top contact structure, as in the case of the first embodiment (see FIGS. 1 and 2).

Also in the semiconductor device of the present first example, the laminated film MO includes the first metal oxide semiconductor film (first semiconductor film) MO1 and the second metal oxide semiconductor film (second semiconductor) arranged thereabove. Membrane) MO2. The first metal oxide semiconductor film (first semiconductor film) MO1 is an IZO film. The film thickness of the IZO film is, for example, about 4 nm. The IZO (In-Zn-O, indium zinc oxide, indium zinc composite oxide) film is a metal oxide containing zinc, indium, and oxygen as main components. In other words, it is a metal oxide containing zinc oxide (ZnO) and indium oxide (InO ₂ ).

The second metal oxide semiconductor film (second semiconductor film) MO2 is a ZTO film. The film thickness of the ZTO film is, for example, about 50 nm. A ZTO (zinc-tin oxide, zinc tin oxide) film is a metal oxide containing tin, zinc and oxygen as main components. In other words, it is a metal oxide containing tin oxide and zinc oxide.

The carrier density of the ZTO film is about 1.2×10 ¹⁶ cm ⁻³ , and the carrier density of the IZO film is about 1×10 ¹⁹ cm ⁻³ . As described above, by using the IZO film, the carrier density is improved, and as in the case of the first embodiment, it is possible to achieve the effects of improving the on-characteristics, speeding up the operation, and reducing the off-leakage. Furthermore, sufficient transistor characteristics can be maintained even with miniaturization, and high brightness and high contrast of an ultra-high-definition display can be achieved.

Then, the end portion of the lower first metal oxide semiconductor film MO1 is set back from the end portion of the upper second metal oxide semiconductor film MO2 (see FIGS. 1 and 2). Therefore, a gap (gap SP) is formed between the lower first metal oxide semiconductor film MO1 and the source/drain electrode SD.

In this way, by retracting the end portion of the lower first metal oxide semiconductor film MO1, it is possible to secure the distance L2 between the lower first metal oxide semiconductor film MO1 and the source/drain electrodes SD, A short circuit between the source/drain electrode SD and the underlying first metal oxide semiconductor film MO1 can be prevented. This can improve the transistor characteristics.

The manufacturing process of the semiconductor device of the first example is similar to that of the first embodiment (FIGS. 3 to 10). That is, the gate electrode GE is formed on the substrate SUB, and the gate insulating film GI is formed thereon. Then, the first metal oxide semiconductor film MO1 is formed over the gate insulating film GI, and further, the second metal oxide semiconductor film MO2 is formed over the first metal oxide semiconductor film MO1. Here, as the first metal oxide semiconductor film MO1, an IZO film is deposited with a film thickness of about 4 nm by using, for example, a DC magnetron sputtering method. For example, using a target material having a zinc composition of 10 at% and an indium composition of 90 at%, film forming conditions, room temperature, film forming pressure of 0.5 Pa, sputtering gas Ar/O ₂ mixed gas (oxygen addition ratio of about 50%), DC power of 50 W Then, the IZO film can be formed.

Then, the second metal oxide semiconductor film MO2 is continuously formed on the first metal oxide semiconductor film MO1. As the second metal oxide semiconductor film MO2, a ZTO film is deposited with a film thickness of about 50 nm by using, for example, a DC magnetron sputtering method. For example, using a target material having a tin composition of 30 at% and a zinc composition of 70 at% (adding 500 ppm of Al), film forming conditions, room temperature, film forming pressure of 0.5 Pa, sputtering gas Ar/O ₂ mixed gas (oxygen addition ratio of about 10% ), the ZTO film can be formed.

In this way, the laminated film MO of the first metal oxide semiconductor film (IZO film) MO1 and the second metal oxide semiconductor film (ZTO film) MO2 arranged thereabove can be formed.

Next, the laminated film MO is first etched to form the laminated film MO having the above-described shape. An oxalic acid-based etching liquid can be used as the etching liquid. The etching time is about 3 to 4 minutes. The oxalic acid-based etching solution is an etching solution that is generally used in etching a metal oxide such as an ITO film. The oxalic acid-based etching solution can etch the ZTO film, but the etching rate (nm/min) of the IZO film is 290, whereas that of the ZTO film is 215, and the etching rate is about the same. Therefore, at this time, the etching end surface can be tapered at the end of the stacked film MO (see FIG. 6 ). However, since the etching rates are about the same, the taper angle is larger than that in the first embodiment (FIG. 6).

Then, the lower first metal oxide semiconductor film (ITO film) MO1 is secondly etched to form an undercut below the end portion of the upper second metal oxide semiconductor film (ZTO film) MO2. Dilute sulfuric acid (about 0.1%) can be used as the etching liquid. The etching time is about 2 to 3 minutes. The etching rate of dilute sulfuric acid (about 0.1%) is 43 for the IZO film, whereas it is 0.8 for the ZTO film, and the etching rate of the ZTO film is smaller than that of the IZO film. It is selectively etched. Therefore, an undercut (side etching) of about 10 to 20 nm is formed from the end of the ZTO film. In other words, the IZO film of about 10 to 20 nm recedes from the end of the ZTO film. As a result, a void (space, SP) is formed below the end of the ZTO film (see FIG. 7).

Although dilute sulfuric acid (about 0.1%) is used as the etching solution here, a phosphoric acid-sulfuric acid-based etching solution may be used. The phosphoric acid-sulfuric acid-based etching solution is generally used as an etching solution for Mo and Cu. When a phosphoric acid-sulfuric acid-based etching solution is used, the etching time may be about 20 seconds. The ZTO film has sufficient resistance to this phosphoric acid-sulfuric acid-based etching solution and is difficult to be etched. Therefore, the IZO film recedes from the end of the ZTO film.

Then, a metal film (MF) is formed as a conductive film on the second metal oxide semiconductor film (ZTO film) MO2, and wet etching is performed to form the source/drain electrodes SD. Next, the protective film PRO is formed on the stacked film MO and the source/drain electrodes SD. Through the above steps, the thin film transistor of the first example is almost completed.

As described above, also in the first example, the laminated film MO of the first and second metal oxide semiconductor films (MO1, MO2) is used as the channel layer, and the lower first metal oxide semiconductor film MO1 is used as the upper layer. Since the second metal oxide semiconductor film MO2 is retracted, it is possible to prevent a short circuit between the source/drain electrode SD and the underlying first metal oxide semiconductor film MO1. As a result, good transistor characteristics can be obtained. FIG. 17 is a diagram showing current-voltage characteristics of the semiconductor device of the first example of the present embodiment. That is, the current-voltage characteristics when ZTO/IZO is used as the laminated film MO are shown. In FIG. 17, the horizontal axis is the gate voltage (Vg, [V]), the vertical axis is the drain current [A], and the three graphs from the top show that the drain voltage (Vd, [V]) is 0. 1V, 1V, 10V. Further, the bottom graph shows carrier mobility (cm ² /Vs). As is clear from FIG. 17, the rise of the drain current can be confirmed, and it can be seen that the transistor can operate. Also, as is clear from the bottom graph, good transistor characteristics with a mobility of 30.7 cm ² /Vs could be confirmed.

Also in the present first example, an oxalic acid-based etching liquid can be used as the first etching liquid, and dilute sulfuric acid or phosphoric acid-nitric acid-based etching liquids as well as nitric acid, hydrochloric acid, Hydrofluoric acid, a PAN-based etching solution or the like can be used (see Table 1).

(Second example)
Although the ITO film is used as the first metal oxide semiconductor film MO1 in the first embodiment, an IGZO film may be used. The first metal oxide semiconductor film MO1 is the same as the first embodiment except for the specific film type. That is, the structure is the same as that described with reference to FIG. 1 and the like, and it can be formed by the same process as the manufacturing process described with reference to FIGS.

The semiconductor device of the second example is a bottom-gate/top-contact thin film transistor as in the case of the first embodiment (see FIGS. 1 and 2).

Also in the semiconductor device of the present second example, the laminated film MO includes the first metal oxide semiconductor film (first semiconductor film) MO1 and the second metal oxide semiconductor film (second semiconductor) arranged thereabove. Membrane) MO2. The first metal oxide semiconductor film (first semiconductor film) MO1 is an IGZO film. The film thickness of the IGZO film is, for example, about 25 nm. The IGZO (In-Ga-Zn-O, indium gallium zinc oxide, indium gallium zinc composite oxide) film is a metal oxide containing zinc, indium, gallium, and oxygen.

The second metal oxide semiconductor film (second semiconductor film) MO2 is a ZTO film. The film thickness of the ZTO film is, for example, about 5 nm. The ZTO (zinc-tin oxide, zinc tin oxide) film is a metal oxide containing tin, zinc and oxygen. In other words, it is a metal oxide containing tin oxide and zinc oxide. For example, it may be represented as Zn ₂ SnO ₄ , but the composition ratio may change.

The carrier density of the ZTO film is about 7×10 ¹⁶ cm ⁻³ , and the carrier density of the IGZO film is about 5×10 ¹⁸ cm ⁻³ . As described above, by using the IGZO film, the carrier density is improved, and as in the case of the first embodiment, it is possible to achieve the effects of improving the ON characteristics, speeding up the operation, and reducing the off leak. Furthermore, sufficient transistor characteristics can be maintained even with miniaturization, and high brightness and high contrast of the display can be achieved.

Then, the end portion of the lower first metal oxide semiconductor film MO1 is set back from the end portion of the upper second metal oxide semiconductor film MO2 (see FIGS. 1 and 2). Therefore, a gap (gap SP) is formed between the lower first metal oxide semiconductor film MO1 and the source/drain electrode SD.

In this way, by retracting the end portion of the lower first metal oxide semiconductor film MO1, it is possible to secure the distance L2 between the lower first metal oxide semiconductor film MO1 and the source/drain electrodes SD, A short circuit between the source/drain electrode SD and the underlying first metal oxide semiconductor film MO1 can be prevented. This can improve the transistor characteristics.

The manufacturing process of the semiconductor device of the second example is similar to that of the first embodiment (FIGS. 3 to 10). That is, the gate electrode GE is formed on the substrate SUB, and the gate insulating film GI is formed thereon. Then, the first metal oxide semiconductor film MO1 is formed over the gate insulating film GI, and further, the second metal oxide semiconductor film MO2 is formed over the first metal oxide semiconductor film MO1. Here, as the first metal oxide semiconductor film MO1, an IGZO film is deposited with a film thickness of about 5 nm by using, for example, a DC magnetron sputtering method. For example, using a target material having an In:Ga:Zn composition of 4:1:1, 2:2:1, or 1:1:1, film forming conditions, room temperature, film forming pressure 0.5 Pa, sputtering gas Ar/ The IGZO film can be formed with an O ₂ mixed gas (oxygen addition ratio of about 10%) and a DC power of 50W.

Then, the second metal oxide semiconductor film MO2 is continuously formed on the first metal oxide semiconductor film MO1. As the second metal oxide semiconductor film MO2, a ZTO film is deposited with a film thickness of about 25 nm by using, for example, a DC magnetron sputtering method. For example, using a target material having a tin composition of 30 at% and a zinc composition of 70 at% (Al: 300 ppm added, Si: 100 ppm added), film forming conditions, room temperature, film forming pressure 0.5 Pa, sputtering gas Ar/O ₂ mixed gas ( The ZTO film can be formed at an oxygen addition ratio of about 10%).

In this way, a laminated film MO of the first metal oxide semiconductor film (IGZO film) MO1 and the second metal oxide semiconductor film (ZTO film) MO2 arranged thereabove can be formed.

Next, the laminated film MO is first etched to form the laminated film MO having the above-described shape. An oxalic acid-based etching liquid can be used as the etching liquid. The etching time is about 3 to 4 minutes. The oxalic acid-based etching solution is an etching solution that is generally used in etching a metal oxide such as an ITO film. The oxalic acid-based etching solution can etch the ZTO film, but the etching rate (nm/min) of the IGZO film is 220 to 290, whereas that of the ZTO film is 215, and the etching rate is similar. .. Therefore, at this time, the etching end surface can be tapered at the end of the stacked film MO (see FIG. 6 ). However, since the etching rates are the same, the taper angle becomes larger than that in the embodiment (FIG. 6).

Then, the lower first metal oxide semiconductor film (IGZO film) MO1 is secondly etched to form an undercut below the end portion of the upper second metal oxide semiconductor film (ZTO film) MO2. Dilute sulfuric acid (about 0.1%) can be used as the etching liquid. The etching rate of dilute sulfuric acid (about 0.1%) is 43 to 52 for the IGZO film, while it is 0.8 for the ZTO film, and the etching rate of the ZTO film is smaller than that of the IGZO film. Only are selectively etched. Therefore, an undercut (side etching) is formed below the end of the ZTO film, and a void (space, SP) is formed below the end of the ZTO film (see FIG. 7).

Next, the metal film MF is formed as a conductive film on the second metal oxide semiconductor film (ZTO film) MO2, and the source/drain electrodes SD are formed by wet etching. Next, the protective film PRO is formed on the stacked film MO and the source/drain electrodes SD. Through the above steps, the thin film transistor of the second embodiment is substantially completed.

Thus, also in the second example, the laminated film MO of the first and second metal oxide semiconductor films (MO1, MO2) is used as the channel layer, and the lower first metal oxide semiconductor film MO1 is used as the upper layer. Since the second metal oxide semiconductor film MO2 is retracted, it is possible to prevent a short circuit between the source/drain electrode SD and the underlying first metal oxide semiconductor film MO1. As a result, good transistor characteristics can be obtained. FIG. 18 is a diagram showing current-voltage characteristics of the semiconductor device of the second example of the present embodiment. That is, the current-voltage characteristics when ZTO/IGZO is used as the laminated film MO are shown. (A) shows the current-voltage characteristics of a semiconductor device having an In:Ga:Zn composition of 4:1:1, and (b) shows the current of a semiconductor device having an In:Ga:Zn composition of 2:2:1. -Voltage characteristics are shown, and (c) shows current-voltage characteristics of a semiconductor device having an In:Ga:Zn composition of 1:1:1. 18, the horizontal axis represents the gate voltage (Vg, [V]), the vertical axis represents the drain current [A], and the three graphs from the top show that the drain voltage (Vd, [V]) is 0. 1V, 1V, 10V. Further, the bottom graph shows carrier mobility (cm ² /Vs). As is apparent from the graphs of (a) to (c) of FIG. 18, it can be seen that the rise of the drain current can be confirmed and the transistor can operate even when IGZO having any composition is used. In addition, as is clear from the bottom graphs of the graphs (a) to (c) of FIG. 18, it is necessary to confirm the transistor characteristics with good mobility in any of the compositions using IGZO. I was able to. Specifically, the mobility of the semiconductor device having an In:Ga:Zn composition of 4:1:1 shown in (a) is 20 cm ² /Vs. The mobility of the semiconductor device having an In:Ga:Zn composition of 2:2:1 shown in (b) is 17.8 cm ² /Vs, and the In:Ga:Zn composition shown in (c) is The mobility of a 1:1:1 semiconductor device is 12.5 cm ² /Vs. When IGZO was used, its mobility was proportional to the In composition, and in the above case, the In composition of 4 (In:Ga:Zn composition of 4:1:1) showed the highest mobility.

The IGZO film has insufficient resistance to a PAN-based etching solution and is easily etched. Therefore, when the IGZO film is used as the semiconductor film (MO) in a single layer, it cannot withstand the etching when forming the source/drain electrodes SD. Therefore, it is impossible to adopt a low-cost BCE process. However, when ZTO/IGZO is used as the laminated film MO as in the second example, since the ZTO film having a large resistance to the PAN-based etching solution serves as an etching stopper, the IGZO film is used as the semiconductor film (MO). Can be adopted.

Also in the second example, an oxalic acid-based etching solution can be used as the first etching solution, and nitric acid, hydrochloric acid, hydrofluoric acid, etc. can be used as the second etching solution in addition to dilute sulfuric acid ( See Table 1). In addition, a PAN-based etching solution or a phosphoric acid-nitric acid-based etching solution may be used.

(Embodiment 3)
Although there is no limitation on application examples of the thin film transistor described in Embodiment Modes 1 and 2, application to an active matrix substrate (array substrate) used for an electro-optical device such as a display (a liquid crystal display device or a semiconductor device) is not limited. You can

FIG. 19 is a circuit diagram showing the configuration of the active matrix substrate. 20 is a plan view showing the structure of the active matrix substrate.

As shown in FIG. 19, the array substrate has a plurality of data lines DL (source lines) arranged in the Y direction and a plurality of gate lines GL arranged in the X direction in the display section (display region). .. A plurality of pixels are arranged in a matrix at the intersections of the data lines DL and the gate lines GL. This pixel has a pixel electrode PE and a thin film transistor T. For example, the data line DL is driven by the data line drive circuit DDC, and the gate line GL is driven by the gate line drive circuit GDC.

As shown in FIG. 20, for example, the gate electrode GE of the thin film transistor T is connected to the gate line GL extending in the X direction. Here, the gate electrode GE and the gate line GL are integrated. A semiconductor film (MO) is arranged above the gate electrode GE via a gate insulating film, and source and drain electrodes SD are arranged on both sides of the semiconductor film (MO). Of the source and drain electrodes SD, for example, the source electrode (left side in FIG. 20) is connected to the data line DL extending in the Y direction, and the drain electrode (right side in FIG. 20) is connected to the pixel electrode PE. Has been done.

A display is formed by sealing the liquid crystal between the array substrate and the counter substrate on which the counter electrode is formed.

In the display, when the scanning signal is supplied to the gate line GL, the thin film transistor T is turned on, and the video signal from the data line DL extending in the Y direction in the drawing is supplied to the pixel electrode PE through the turned on thin film transistor T. Supplied. Therefore, the pixel portion selected by the gate line GL and the data line DL enters the display state.

As described above, by using the thin film transistor described in Embodiment Modes 1 and 2 as the thin film transistor of the display, the characteristics of the display can be improved. Specifically, as described above, it can be applied to high-definition displays called 4K and 8K, and a current value per unit area can be secured even if the thin film transistor is miniaturized with the miniaturization of the pixel size. .. In other words, sufficient transistor characteristics can be maintained even with miniaturization, and high brightness and high contrast of an ultra-high-definition display can be achieved.

In the above description, the thin film transistor of the above-described first and second embodiments is applied to the thin film transistor T that constitutes a pixel. One or two thin film transistors may be used.

Further, the thin film transistor of Embodiment Modes 1 and 2 may be used as a thin film transistor for an organic EL (electroluminescence) backplane. The organic EL requires a large current drive, and is suitable for using the thin film transistor according to the first or second embodiment.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the film thickness of each film, the film forming method, the processing (etching) method, and the like shown in the above embodiment can be variously changed according to the characteristics required for the device to be manufactured. Further, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment without departing from the spirit of the invention, and to add the configuration of another embodiment to the configuration of one embodiment. It is possible. Further, it is possible to add/delete/replace other configurations with respect to a part of the configurations of the respective embodiments.

DDC data line driving circuit DL data line GDC gate line driving circuit GE gate electrode GI gate insulating film GL gate line L1 distance L2 distance MF metal film MO laminated film MO1 first metal oxide semiconductor film MO2 second metal oxide semiconductor film PE Pixel electrode PR1 Photoresist film PR2 Photoresist film PRO Protective film SD Source/drain electrode SP Void SUB Substrate T Thin film transistor

Claims (7)

A gate electrode formed on the substrate,
A first semiconductor film made of a semiconductor containing a first metal oxide formed on the gate electrode via a gate insulating film;
A second semiconductor film made of a semiconductor containing a second metal oxide formed on the first semiconductor film;
Source and drain electrodes formed on the second semiconductor film,
Have
The first metal oxide contains at least one of ITO (indium tin composite oxide), IZO (indium zinc composite oxide) and IGZO (indium gallium zinc composite oxide) ,
The second metal oxide contains at least ZTO (zinc tin composite oxide) , does not contain In element,
The edge of the first semiconductor film is receded from the edge of the second semiconductor film,
Under the second semiconductor film, there is a gap between the end of the first semiconductor film and the end of the second semiconductor film,
The distance L1 between the end of said the end portion of the first semiconductor layer a second semiconductor layer, said first semiconductor film and the source, the distance L2 between the drain electrode is L1> Ri L2 Der,
A semiconductor device in which the mobility of carriers is 30.7 cm ² /Vs or higher . The semiconductor device according to claim 1,
The carrier density of the first semiconductor film is 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less, and the carrier density of the second semiconductor film is 1×10 ¹⁵ cm ⁻³ or more 1×10. ^A semiconductor device having a ^{density of 17} cm ⁻³ or less. A gate electrode formed on the substrate,
A first semiconductor film made of a semiconductor containing a first metal oxide formed on the gate electrode via a gate insulating film;
A second semiconductor film made of a semiconductor containing a second metal oxide formed on the first semiconductor film;
Source and drain electrodes formed on the second semiconductor film and covering sidewalls of the second semiconductor film;
Have
The first metal oxide contains at least one of ITO (indium tin composite oxide), IZO (indium zinc composite oxide) and IGZO (indium gallium zinc composite oxide) ,
The second metal oxide contains at least ZTO (zinc tin composite oxide) , does not contain In element,
The end portion of the first semiconductor film is separated from the source and drain electrodes,
Under the second semiconductor film, there is a gap between the end of the first semiconductor film and the source and drain electrodes,
The distance L1 between the end of said the end portion of the first semiconductor layer a second semiconductor layer, said first semiconductor film and the source, the distance L2 between the drain electrode is L1> Ri L2 Der,
A semiconductor device in which the mobility of carriers is 30.7 cm ² /Vs or higher . The semiconductor device according to claim 3 ,
The carrier density of the first semiconductor film is 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less, and the carrier density of the second semiconductor film is 1×10 ¹⁵ cm ⁻³ or more 1×10. ^A semiconductor device having a ^{density of 17} cm ⁻³ or less. (A) a step of forming a gate electrode on the substrate,
(B) a step of forming a first semiconductor film made of a semiconductor containing a first metal oxide on the gate electrode via a gate insulating film,
(C) forming a second semiconductor film made of a semiconductor containing a second metal oxide on the first semiconductor film;
(D) a step of etching a laminated film of the first semiconductor film and the second semiconductor film,
(D1) a step of etching the laminated film with a first etching liquid,
(D2) After the step (d1), the first semiconductor film is second-etched from the side wall of the stacked film so that the end of the first semiconductor film recedes from the end of the second semiconductor film. Liquid etching process,
(E) After the step (d), a source film and a drain electrode are formed by forming a conductive film on the second semiconductor film and patterning the conductive film. Under the second semiconductor film, 1 a step of forming a gap between the end portion of the semiconductor film and the source and drain electrodes,
Have
The first metal oxide contains at least one of ITO (indium tin composite oxide), IZO (indium zinc composite oxide) and IGZO (indium gallium zinc composite oxide) ,
The second metal oxide contains at least ZTO (zinc tin composite oxide) , does not contain In element,
The distance L1 between the end of said the end portion of the first semiconductor layer a second semiconductor layer, said first semiconductor film and the source, the distance L2 between the drain electrode is L1> Ri L2 Der,
A method for manufacturing a semiconductor device , wherein the mobility of carriers is 30.7 cm ² /Vs or more . The method of manufacturing a semiconductor device according to claim 5 ,
The method for manufacturing a semiconductor device, wherein the first etching liquid is a liquid containing oxalic acid. The method of manufacturing a semiconductor device according to claim 5 ,
The method for manufacturing a semiconductor device, wherein the second etching liquid is a liquid containing an acid selected from nitric acid, sulfuric acid, hydrochloric acid and hydrofluoric acid.