JP6592948B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  Nitride semiconductors have been studied for application to high breakdown voltage and high output semiconductor devices utilizing characteristics such as high saturation electron velocity and wide band gap. For example, the band gap of GaN that is a nitride semiconductor is 3.4 eV, which is larger than the band gap of Si (1.1 eV) and the band gap of GaAs (1.4 eV), and has a high breakdown electric field strength. Therefore, a nitride semiconductor such as GaN is extremely promising as a material for a semiconductor device for power supply that obtains high voltage operation and high output.

  As semiconductor devices using nitride semiconductors, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs). For example, in a GaN-based HEMT (GaN-HEMT), an HEMT made of AlGaN / GaN using GaN as an electron transit layer and AlGaN as an electron supply layer has attracted attention. In the HEMT composed of AlGaN / GaN, strain caused by the difference in lattice constant between GaN and AlGaN occurs in AlGaN. High-density 2DEG (Two-Dimensional Electron Gas) is obtained by the piezoelectric polarization generated thereby and the spontaneous polarization difference of AlGaN.

  As a device using GaN-HEMT, there is a GaN-HEMT monolithic microwave integrated circuit (MMIC), which is expected to be applied to millimeter wave radio communication systems, microwave radar systems, and the like. . Generally, a GaN-HEMT-MMIC is formed by a GaN-HEMT-HPA (high power amplifier) formed on the same SiC substrate or the like and an input / output matching circuit.

JP 2001-332866 A JP 2006-270037 A JP2012-216601A JP2013-167553A JP 2013-98373 A

  However, since the SiC substrate is more expensive than a Si substrate or the like and it is difficult to form a large substrate, the GaN-HEMT-MMIC becomes expensive. Therefore, in order to reduce the cost of the GaN-HEMT-MMIC, for example, by using a GaN-HEMT-HPA chip and an input / output matching circuit chip manufactured using an inexpensive Si substrate, It is very effective to convert to MMIC by a rewiring process.

  In the case of GaN-HEMT-MMIC, metal is attached to the back of each chip for heat dissipation of the GaN-HEMT-HPA chip and grounding via TSV (Through Substrate Via) of the input / output matching circuit chip. A film is formed. For this reason, after integrating and rewiring each chip, a step of back grinding (grinding) the mold resin or the like is performed until the back surface of each chip is exposed. However, since the GaN-HEMT-HPA chip and the input / output matching circuit chip are formed of different materials for the substrate, a decrease in yield and reliability is caused by the difference in substrate thickness accuracy and grinding rate. It was.

  For this reason, in the case of forming an IC with a plurality of chips using substrates made of different materials, there is a demand for a low-cost and highly reliable method for manufacturing a semiconductor device.

According to one aspect of the present embodiment, a first semiconductor chip having an electrode formed on the front surface side and a through electrode penetrating from the front surface side to the back surface side, and an electrode formed on the front surface side and from the front surface side A step of fixing a second semiconductor chip having a penetrating electrode penetrating on the back side with a resin on the back side of the first semiconductor chip and the second semiconductor chip, and removing the resin by etching A step of exposing the back surface side of the first semiconductor chip and the back surface side of the second semiconductor chip; and a common electrode on the back surface side of the first semiconductor chip and the back surface side of the second semiconductor chip. A semiconductor element is formed of a nitride semiconductor layer on the surface side of the SiC substrate, and the second semiconductor chip is on the surface side of the Si substrate. Resistors, capacitors, one or more of the inductance are formed, exposing the back side of the first semiconductor chip on the back surface side and the second semiconductor chip, said first semiconductor chip and the A step of grinding the resin from the back surface side of the second semiconductor chip to a predetermined thickness, a resist pattern formed on the ground surface, and a resin in a region where the resist pattern is not formed the is removed by etching, characterized Rukoto to have a, thereby exposing the back surface side of the first semiconductor chip on the back side and the second semiconductor chip.

  According to the disclosed method for manufacturing a semiconductor device, an IC formed by a plurality of chips using substrates made of different materials can be manufactured at low cost and with high reliability.

Structure diagram of a semiconductor device formed by multiple chips with different substrate materials Explanatory drawing of a semiconductor device formed by a plurality of chips made of different substrate materials Process drawing (1) of the manufacturing method of the semiconductor device in 1st Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in the first embodiment Illustration of pseudo wafer Process drawing (3) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (4) of the manufacturing method of the semiconductor device in the first embodiment Process drawing of the manufacturing method of the semiconductor device in the first embodiment (5) Process drawing (6) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (7) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (8) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (9) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (10) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (11) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (12) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (13) of the manufacturing method of the semiconductor device in the first embodiment Explanatory drawing of the semiconductor device in 1st Embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (3) Process drawing (4) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (5) Process drawing (6) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing (7) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (8) Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (9) Process drawing (10) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing (11) of the manufacturing method of the semiconductor device in 2nd Embodiment Structure diagram of high frequency width device in the third embodiment

  The form for implementing is demonstrated below. In addition, about the same member etc., the same code | symbol is attached | subjected and description is abbreviate | omitted.

[First Embodiment]
First, an MMIC formed by a plurality of chips using substrates made of different materials will be described. As shown in FIG. 1, the MMIC includes, for example, three chips, that is, a first semiconductor chip 10 using an SiC substrate 11, a second semiconductor chip 20 using an Si substrate 21, and an Si substrate 31. It is formed by the third semiconductor chip 30 used. A rewiring layer 50 is formed on the surface side of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 by an interlayer insulating film 51 and a wiring 52 formed of metal. The semiconductor layers are electrically connected by the wiring layer 50. On the back side of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30, a metal film 60 serving as a common electrode is formed for heat dissipation and grounding. The thicknesses of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are about 100 μm, and the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor. The chip 30 is joined by a mold resin 40.

  The first semiconductor chip 10 is a GaN-HEMT-HPA chip. Specifically, a semiconductor circuit is formed on a nitride semiconductor layer 12 such as GaN formed on the surface of the first semiconductor chip 10, and a gate electrode (G) is formed on the nitride semiconductor layer 12. The surface side electrodes 13 such as the source electrode (S) and the drain electrode (D) are formed. The second semiconductor chip 20 is an input side matching circuit chip, and silicon oxide films 22 a and 22 b are formed on the front and back surfaces of the Si substrate 21. On the surface-side silicon oxide film 22a, electronic elements such as a surface-side electrode 23, a capacitor 24, and a resistor 25 are formed. The third semiconductor chip 30 is an output side matching circuit chip, and silicon oxide films 32 a and 32 b are formed on the front and back surfaces of the Si substrate 31. On the surface-side silicon oxide film 32a, electronic elements such as a surface-side electrode 33, a capacitor 34, and an inductance 35 are formed.

  Further, the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are connected with a part of the front surface side electrodes 13, 23, and 33 and the metal film 60 formed on the back surface side. TSV wirings 17, 27, and 37 that serve as through electrodes for this purpose are formed of copper or the like.

  When manufacturing the MMIC as shown in FIG. 1, first, as shown in FIG. 2A, the surface side of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 is used. Are aligned and hardened with mold resin 40 from the back side of the semiconductor chip. Thereafter, the rewiring layer 50 is formed on the surface side of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 that are solidified by the mold resin 40. The rewiring layer 50 is formed of an interlayer insulating film 51 and wirings 52. Specifically, the rewiring layer 50 is formed by forming the insulating film to be the interlayer insulating film 51, etching the insulating film for forming the through electrode, the region where the insulating film has been removed, and the wiring 52 in the surface of the insulating film. It is formed by forming a metal film for forming.

  Next, as shown in FIG. 2B, in order to form the metal film 60 on the back surface side of each semiconductor chip, the mold resin 40 on the back surface side of each semiconductor chip is removed by grinding, and the first semiconductor The back surfaces of the chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are exposed. However, the thickness of the SiC substrate 11 forming the first semiconductor chip 10 and the thicknesses of the Si substrates 21 and 31 forming the second semiconductor chip 20 and the third semiconductor chip 30 are acceptable accuracy. There may be a slight deviation within the range. Further, the grinding rate varies depending on the material of the substrate on which each semiconductor chip is formed.

  For this reason, as shown in FIG. 2B, even the silicon oxide films 22b and 32b on the back surfaces of the second semiconductor chip 20 and the third semiconductor chip 30 may be removed by grinding. Thus, when the silicon oxide films 22b and 32b on the back surfaces of the second semiconductor chip 20 and the third semiconductor chip 30 are removed, the metal film 60 serving as a common electrode is formed on the back surfaces of the Si substrates 21 and 31. Since the film is formed directly, Si and the metal come into contact with each other. For this reason, the reliability of the manufactured semiconductor device will fall. In addition, since Si forming the Si substrates 21 and 31 and SiC forming the SiC substrate 11 have different grinding rates, irregularities may be formed by the semiconductor chip on the back surface side. As described above, when unevenness is formed by the semiconductor chip on the back surface side, voids are formed when the metal film 60 is formed on the back surface side, which may adversely affect heat radiation characteristics, ground potential, and the like.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described. The method for manufacturing a semiconductor device according to the present embodiment is a method for manufacturing a semiconductor device capable of manufacturing the MMIC having the structure shown in FIG. 1 with high reliability.

  First, as shown in FIG. 3, the adhesive layer 71 is formed on the support substrate 70. A glass substrate or the like can be used as the support substrate 70, and the adhesive layer 71 has an adhesive force at room temperature, the adhesive force is weakened by applying heat, and the attached adhesive sheet can be easily peeled off. Can be used.

  Next, as shown in FIG. 4, the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are adhered by a flip chip bonder or a chip mounter so that the surface sides of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are in contact with the adhesive layer 71. It is mounted on the layer 71 and temporarily fixed.

  The first semiconductor chip 10 has a GaN-HEMT-HPA formed on a SiC substrate 11. Specifically, it is a GaN-HEMT-HPA chip formed by separating the GaN-HEMT-HPA formed on the SiC wafer 81 as shown in FIG. 5A for each chip by dicing or the like. Specifically, a semiconductor circuit is formed of a nitride semiconductor layer 12 on the surface of the first semiconductor chip 10, and a surface of a gate electrode, a source electrode, a drain electrode or the like is formed on the nitride semiconductor layer 12. A side electrode 13 is formed. Further, a back surface side electrode 16 is formed on the back surface side of the first semiconductor chip 10, and a part of the front surface side electrode 13 and the back surface side electrode 16 are formed by connecting the first semiconductor chip 10 as necessary. They are connected by TSV wiring 17 formed of penetrating copper or the like.

  In addition, the second semiconductor chip 20 and the third semiconductor chip 30 have a matching circuit formed on the Si substrate, and each formed on the Si wafer 82 as shown in FIG. 5B. The matching circuit is formed by separating each chip by dicing or the like. In FIG. 5C, the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 separated from the SiC wafer 81 and the Si wafer 82 are hardened with a mold resin 40. A state of the formed pseudo wafer 83 described later is shown.

  The second semiconductor chip 20 is an input side matching circuit chip, and silicon oxide films 22 a and 22 b are formed on the front and back surfaces of the Si substrate 21. On the surface-side silicon oxide film 22a, electronic elements such as a surface-side electrode 23, a capacitor 24, and a resistor 25 are formed. Further, a back-side electrode 26 is formed on the silicon oxide film 22b on the back side of the second semiconductor chip 20, and a part of the front-side electrode 23 and the back-side electrode 26 are connected to the second semiconductor chip. The TSV wiring 27 formed of copper or the like penetrating through 20 is connected.

  The third semiconductor chip 30 is an output side matching circuit chip, and silicon oxide films 32 a and 32 b are formed on the front and back surfaces of the Si substrate 31. On the surface-side silicon oxide film 32a, electronic elements such as a surface-side electrode 33 and a capacitor 34 are formed. Further, a back surface side electrode 36 is formed on the silicon oxide film 32b on the back surface side of the third semiconductor chip 30, and a part of the front surface side electrode 33 and the back surface side electrode 36 are composed of the third semiconductor chip. These are connected by TSV wiring 37 formed of copper or the like that penetrates 30.

  Next, as shown in FIG. 6, a liquid mold resin is formed on the back side of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 that are temporarily fixed on the adhesive layer 71. 40 is applied, and the mold resin 40 is cured and hardened in a state flattened by pressing. Thereby, the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are fixed by the cured mold resin 40. The shape of the hardened mold resin 40 is formed in a wafer shape so as to be a pseudo wafer 83 as shown in FIG.

  Next, as shown in FIG. 7, the support substrate 70 and the adhesive layer 71 are heated, and the support substrate 70 and the adhesive layer 71 are peeled off. As a result, a pseudo wafer 83 in which the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are hardened with the mold resin 40 as shown in FIG. 5C is formed. In the pseudo wafer 83, the surface sides of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are exposed.

  Next, as illustrated in FIG. 8, an interlayer insulating film 51 is formed on the surface side of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 in the pseudo wafer 83. The interlayer insulating film 51 is formed by applying a liquid polyimide solution or the like to the surface side of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 of the pseudo wafer 83, and then curing it. Form.

  Next, as shown in FIG. 9, a via opening 51 a for forming a via electrode is formed in the interlayer insulating film 51. Specifically, a photoresist is applied on the interlayer insulating film 51, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern 72 having an opening in a region where the via opening 51a is formed. Thereafter, the interlayer insulating film 51 in the region where the resist pattern 72 is not formed is removed by dry etching, thereby forming a via opening 51 a in the interlayer insulating film 51. The interlayer insulating film 51 in which the via openings 51a are formed is obtained by applying a photosensitive resin such as a liquid photosensitive polyimide to the pseudo wafer 83, and exposing the photosensitive resin in an unexposed region by performing exposure using an exposure apparatus. It may be formed by removing and curing. Thereafter, the resist pattern 72 is removed with an organic solvent or the like.

  Next, as shown in FIG. 10, the wiring 52 is formed by forming the via electrode 52 a and the surface electrode 52 b. The wiring 52 formed by the via electrode 52a and the surface electrode 52b is also called rewiring. Specifically, a seed metal (not shown) formed of Ti / Cu is formed by sputtering, a resist pattern (not shown) or the like is formed on the seed metal, and then copper (Cu) plating is performed. Thus, a via electrode 52 a is formed in the via opening 51 a in the interlayer insulating film 51, and a surface electrode 52 b is formed on the surface of the interlayer insulating film 51. Thereafter, the resist pattern is removed with an organic solvent or the like, and the exposed seed metal is removed by milling or the like. As a result, the rewiring layer 50 is formed by the interlayer insulating film 51 and the wiring 52. At this time, the inductance 35 is simultaneously formed by the via electrode 52a. The via electrode 52a and the surface electrode 52b may be formed by depositing Al by sputtering.

  Next, as shown in FIG. 11, in order to grind the mold resin 40 on the back side of the pseudo wafer 83, the side on which the rewiring layer 50 to be the front side of the pseudo wafer 83 is formed on the support substrate 73. Affixed with a thermoplastic adhesive 74. As the support substrate 73, for example, a glass substrate or the like is used.

  Next, as shown in FIG. 12, the mold resin 40 on the back surface side of the pseudo wafer 83 is ground until the back surface side of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 is exposed. Remove with. That is, on the back surface side of the pseudo wafer 83, the back surfaces of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are thinly covered with the mold resin 40, for example, the thickness is 10 μm. Remove by grinding until

  Next, as shown in FIG. 13, the opening 40 a is formed on the back side of the first semiconductor chip 10, the opening 40 b is formed on the back side of the second semiconductor chip 20, and the opening is formed on the back side of the third semiconductor chip 30. 40c is formed. Specifically, a photoresist is applied to the surface of the ground mold resin 40, and exposure and development are performed by an exposure device, so that the openings 40a, 40b, and 40c are not formed in the regions where the openings are formed. The illustrated resist pattern is formed. Thereafter, the mold resin 40 in the region where the resist pattern is not formed is removed by dry etching or the like to form openings 40a, 40b, 40c, and the first semiconductor chip 10, the second semiconductor chip 20, The back surface of the third semiconductor chip 30 is exposed. As a result, the back surface side electrode 16 on the back surface side of the first semiconductor chip 10, the back surface side electrode 26 on the back surface side of the second semiconductor chip 20, and the back surface side electrode 36 on the back surface side of the third semiconductor chip 30 are exposed. . The opening 40 a thus formed is formed in a region narrower than the back surface side electrode 16, the opening 40 b is formed in a region narrower than the back surface side electrode 26, and the opening 40 c is a region narrower than the back surface side electrode 36. Formed. Thereafter, the resist pattern (not shown) is removed with an organic solvent or the like.

  Next, as shown in FIG. 14, the back side electrode 16 on the back side of the first semiconductor chip 10, the back side electrode 26 on the back side of the second semiconductor chip 20, and the back side of the third semiconductor chip 30. First metal films 61, 62, and 63 are formed on the back surface side electrode 36. As the first metal films 61, 62, 63, a single layer film or a multilayer film containing Cu, Au, Ag, Pt, In, Sn, Ni or the like is formed by electroless plating. The first metal film 61 is formed in a region narrower than the first semiconductor chip 10, and the first metal film 62 is formed in a region narrower than the second semiconductor chip 20, The first metal film 63 is formed in a region narrower than the third semiconductor chip 30. In this way, the first metal films 61 and 62 formed in the mold resin 40 and the openings 40a, 40b, and 40c by embedding the openings 40a, 40b, and 40c with the first metal films 61, 62, and 63, respectively. , 63 can be made substantially the same height.

  Next, as shown in FIG. 15, after depositing a seed metal on the back surface side of the pseudo wafer 83 on which the first metal films 61, 62, 63 are formed, the second metal film 64 is formed by Au plating. Form. The seed metal is formed by forming a Ti / Au (20 nm / 0.2 μm) film by sputtering, and the Au plating film is formed by performing Au plating with a film thickness of 3 μm. As a result, a metal film 60 serving as a common electrode including the first metal films 61, 62, 63 and the second metal film 64 is formed on the back surface side of the pseudo wafer 83.

  Next, as shown in FIG. 16, after the support substrate 73 is peeled from the pseudo wafer 83, the thermoplastic adhesive 74 is removed. Thus, a GaN-HEMT-MMIC that is a semiconductor device in this embodiment can be manufactured. FIG. 17 is a top view of a part of the mold resin of the GaN-HEMT-MMIC.

  In the present embodiment, when the mold resin 40 on the back side of the second semiconductor chip 20 and the third semiconductor chip 30 is removed, the silicon oxide films 22b and 32b on the back side are not removed. It can suppress that reliability falls. Further, since the back surfaces of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are not removed by grinding, unevenness due to the difference in grinding rate does not occur between the semiconductor chips. In addition, the mold resin 40 is formed on part of the front side and back side edges of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30. Since they are joined, the semiconductor chips are not separated by thermal expansion or the like.

[Second Embodiment]
(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the second embodiment will be described. The method for manufacturing a semiconductor device according to the present embodiment is a method for manufacturing a semiconductor device capable of manufacturing the MMIC having the structure shown in FIG. 1 with high reliability.

  First, as shown in FIG. 18, the adhesive layer 71 is formed on the support substrate 70. A glass substrate or the like can be used as the support substrate 70, and the adhesive layer 71 has an adhesive force at room temperature, the adhesive force is weakened by applying heat, and the attached adhesive sheet can be easily peeled off. Can be used.

  Next, as shown in FIG. 19, the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are adhered by a flip chip bonder or a chip mounter so that the surface side is in contact with the adhesive layer 71. It is mounted on the layer 71 and temporarily fixed.

  The first semiconductor chip 10 is a GaN-HEMT-HPA chip in which a GaN-HEMT-HPA is formed on a SiC substrate 11. Specifically, a semiconductor circuit is formed of a nitride semiconductor layer 12 on the surface of the first semiconductor chip 10, and a surface of a gate electrode, a source electrode, a drain electrode or the like is formed on the nitride semiconductor layer 12. A side electrode 13 is formed. Further, a back side electrode 16 is formed on the back side of the first semiconductor chip 10, and part of the front side electrode 13 and the back side electrode 16 penetrate the first semiconductor chip 10 as necessary. Are connected by TSV wiring 17 formed of copper or the like. A first metal film 61 is formed on the back side electrode 16 by plating.

  The second semiconductor chip 20 is an input side matching circuit chip, and silicon oxide films 22a and 22b serving as insulating films are formed on the front and back surfaces of the Si substrate 21. On the surface-side silicon oxide film 22a, electronic elements such as a surface-side electrode 23, a capacitor 24, and a resistor 25 are formed. Further, a back-side electrode 26 is formed on the silicon oxide film 22b on the back side of the second semiconductor chip 20, and a part of the front-side electrode 23 and the back-side electrode 26 are connected to the second semiconductor chip. The TSV wiring 27 formed of copper or the like penetrating through 20 is connected. A first metal film 62 is formed on the back-side electrode 26 by plating.

  The third semiconductor chip 30 is an output side matching circuit chip, and silicon oxide films 32 a and 32 b serving as insulating films are formed on the front and back surfaces of the Si substrate 31. On the surface-side silicon oxide film 32a, electronic elements such as a surface-side electrode 33 and a capacitor 34 are formed. Further, a back surface side electrode 36 is formed on the silicon oxide film 32b on the back surface side of the third semiconductor chip 30, and a part of the front surface side electrode 33 and the back surface side electrode 36 are composed of the third semiconductor chip. These are connected by TSV wiring 37 formed of copper or the like that penetrates 30. A first metal film 63 is formed on the back side electrode 36 by plating.

  In the present embodiment, the first metal films 61, 62, and 63 are made of a single layer film or multilayer film containing Cu, Au, Ag, Pt, In, Sn, Ni, etc. with a film thickness of 10 μm or more. It is formed by forming a film. Further, the first metal film 61 is formed in a region narrower than the first semiconductor chip 10, and the first metal film 62 is formed in a region narrower than the second semiconductor chip 20, The first metal film 63 is formed in a region narrower than the third semiconductor chip 30.

  Next, as shown in FIG. 20, liquid mold resin is formed from the back side of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 that are temporarily fixed on the adhesive layer 71. 40 is applied, and the mold resin 40 is hardened in a state flattened by pressing. Thereby, the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are fixed by the cured mold resin 40. The shape of the hardened mold resin 40 is formed in a wafer shape so as to be a pseudo wafer 83 as shown in FIG.

  Next, as shown in FIG. 21, the support substrate 70 and the adhesive layer 71 are heated, and the support substrate 70 and the adhesive layer 71 are peeled off. As a result, a pseudo wafer 83 in which the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are hardened with the mold resin 40 as shown in FIG. 5C is formed. In the pseudo wafer 83, the surface side of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 is exposed.

  Next, as shown in FIG. 22, an interlayer insulating film 51 is formed on the surface side of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 in the pseudo wafer 83. The interlayer insulating film 51 is formed by applying a liquid polyimide solution or the like to the surface side of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 of the pseudo wafer 83, and then curing it. Form.

  Next, as shown in FIG. 23, a via opening 51a for forming a via electrode in the interlayer insulating film 51 is formed. Specifically, a photoresist is applied on the interlayer insulating film 51, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern 72 having an opening in a region where the via opening 51a is formed. Thereafter, the interlayer insulating film 51 in the region where the resist pattern 72 is not formed is removed by dry etching, thereby forming a via opening 51 a in the interlayer insulating film 51. The interlayer insulating film 51 in which the via openings 51a are formed is obtained by applying a photosensitive resin such as a liquid photosensitive polyimide to the pseudo wafer 83, and exposing the photosensitive resin in an unexposed region by performing exposure using an exposure apparatus. It may be formed by removing and curing. Thereafter, the resist pattern 72 is removed with an organic solvent or the like.

  Next, as shown in FIG. 24, the wiring 52 is formed by forming the via electrode 52a and the surface electrode 52b. The wiring 52 formed by the via electrode 52a and the surface electrode 52b is also called rewiring. Specifically, a seed metal (not shown) formed of Ti / Cu is formed by sputtering, a resist pattern (not shown) or the like is formed on the seed metal, and then copper (Cu) plating is performed. Thus, a via electrode 52 a is formed in the via opening 51 a in the interlayer insulating film 51, and a surface electrode 52 b is formed on the surface of the interlayer insulating film 51. Thereafter, the resist pattern is removed with an organic solvent or the like, and the exposed seed metal is removed by milling or the like. As a result, the rewiring layer 50 is formed by the interlayer insulating film 51 and the wiring 52. At this time, the inductance 35 is simultaneously formed by the via electrode 52a. The via electrode 52a and the surface electrode 52b may be formed by depositing Al by sputtering.

  Next, as shown in FIG. 25, in order to grind the mold resin 40 on the back surface side of the pseudo wafer 83, the side on which the rewiring layer 50 to be the front surface side of the pseudo wafer 83 is formed on the support substrate 73. Affixed with a thermoplastic adhesive 74. As the support substrate 73, for example, a glass substrate or the like is used.

  Next, as shown in FIG. 26, the mold resin 40 on the back surface side of the pseudo wafer 83 is replaced with the first metal film on the back surface side of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30. Remove by grinding until 61, 62, 63 is exposed. At this time, even if the difference in height of the semiconductor chips is about ± 2 μm, the thickness of the first metal films 61, 62, 63 is 10 μm or more. Therefore, when the mold resin 40 on the back surface side of the pseudo wafer 83 is removed, even if the first metal films 61, 62, 63 are somewhat removed, they are not completely removed.

  Next, as shown in FIG. 27, after depositing a seed metal on the back surface side of the pseudo wafer 83 on which the first metal films 61, 62, 63 are formed, the second metal film 64 is formed by Au plating. Form. The seed metal is formed by forming a Ti / Au (20 nm / 0.2 μm) film by sputtering, and the Au plating film is formed by performing Au plating with a film thickness of 3 μm. As a result, a metal film 60 serving as a common electrode including the first metal films 61, 62, 63 and the second metal film 64 is formed on the back surface side of the pseudo wafer 83.

  Next, as shown in FIG. 28, after the support substrate 73 is peeled from the pseudo wafer 83, the thermoplastic adhesive 74 is removed. Thus, a GaN-HEMT-MMIC that is a semiconductor device in this embodiment can be manufactured.

  In the present embodiment, when the mold resin 40 on the back side of the second semiconductor chip 20 and the third semiconductor chip 30 is removed, the silicon oxide films 22b and 32b on the back side are not removed. It can suppress that reliability falls. Further, since the back surfaces of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are not removed by grinding, unevenness due to the difference in grinding rate does not occur between the semiconductor chips. In addition, the mold resin 40 is formed on part of the front side and back side edges of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30. Since they are joined, the semiconductor chips are not separated by thermal expansion or the like.

  The contents other than the above are the same as in the first embodiment.

[Third Embodiment]
Next, the high frequency amplifier in 3rd Embodiment is demonstrated based on FIG. The high-frequency amplifier in the present embodiment is a high-frequency amplifier using the semiconductor device in the first or second embodiment. The high frequency amplifier 470 in the present embodiment may be applied to, for example, a power amplifier for a base station of a mobile phone. The high-frequency amplifier 470 includes a digital predistortion circuit 471, mixers 472a and 472b, a power amplifier 473, and a directional coupler 474. The digital predistortion circuit 471 compensates for nonlinear distortion of the input signal. The mixers 472a and 472b mix the input signal compensated for nonlinear distortion and the AC signal. The power amplifier 473 amplifies the input signal mixed with the AC signal. In the present embodiment, the power amplifier 473 includes the semiconductor device in the first or second embodiment. The directional coupler 474 performs monitoring of input signals and output signals. Further, the high-frequency amplifier according to the present embodiment can mix the output signal with the AC signal by the mixer 472 and send it to the digital predistortion circuit 471 by switching the switch, for example.

  Since the high-frequency amplifier in this embodiment includes the semiconductor device in the first or second embodiment, a highly reliable high-frequency high-power amplifier can be obtained. In addition, in the transmission / reception module using such a high-frequency, high-power amplifier, it is possible to provide system equipment such as highly reliable communication, radar, sensors, and radio wave jammers.

  Although the embodiment has been described in detail above, it is not limited to the specific embodiment, and various modifications and changes can be made within the scope described in the claims.

In addition to the above description, the following additional notes are disclosed.
(Appendix 1)
A first semiconductor chip having an electrode formed on the front surface side and a through electrode penetrating from the front surface side to the back surface side; and an electrode formed on the front surface side and a through electrode penetrating from the front surface side to the back surface side. Fixing the two semiconductor chips with a resin on the back side of the first semiconductor chip and the second semiconductor chip;
Exposing the back side of the first semiconductor chip and the back side of the second semiconductor chip by removing the resin by etching; and
Forming a common electrode on the back side of the first semiconductor chip and the back side of the second semiconductor chip;
A method for manufacturing a semiconductor device, comprising:
(Appendix 2)
After the step of fixing with the resin,
The wiring on the surface side of the first semiconductor chip and the second semiconductor chip is connected to connect the electrode on the surface side of the first semiconductor chip and the electrode on the surface side of the second semiconductor chip. The method for manufacturing a semiconductor device according to appendix 1, further comprising a step of forming a rewiring to be performed.
(Appendix 3)
Exposing the back side of the first semiconductor chip and the back side of the second semiconductor chip,
Forming a resist pattern on the resin;
Removing the resin in a region where the resist pattern is not formed by etching, exposing the back surface side of the first semiconductor chip and the back surface side of the second semiconductor chip;
The method for manufacturing a semiconductor device according to appendix 1 or 2, characterized by comprising:
(Appendix 4)
Exposing the back side of the first semiconductor chip and the back side of the second semiconductor chip,
Grinding the resin from the back side of the first semiconductor chip and the second semiconductor chip to a predetermined thickness;
A resist pattern is formed on the ground surface, and the resin in the region where the resist pattern is not formed is removed by etching, whereby the back surface side of the first semiconductor chip and the back surface of the second semiconductor chip Exposing the side;
The method for manufacturing a semiconductor device according to any one of appendices 1 to 3, wherein:
(Appendix 5)
The step of forming the common electrode includes:
Forming a first metal film on the back side of the first semiconductor chip and the back side of the second semiconductor chip;
Forming a second metal film on the first metal film by plating;
The method for manufacturing a semiconductor device according to any one of appendices 1 to 4, wherein:
(Appendix 6)
A first semiconductor chip having an electrode formed on the front surface side and the back surface side, a through electrode connecting the electrode on the front surface side and the electrode on the back surface side; an electrode formed on the front surface side and the back surface side; Fixing a second semiconductor chip having a through electrode connecting the electrode and the electrode on the back surface side with a resin on the back surface side of the first semiconductor chip and the second semiconductor chip;
Removing the resin by grinding, exposing a back side electrode of the first semiconductor chip and a back side electrode of the second semiconductor chip; and
Forming a common electrode connecting the electrode on the back surface side of the first semiconductor chip and the electrode on the back surface side of the second semiconductor chip;
A method for manufacturing a semiconductor device, comprising:
(Appendix 7)
After the step of fixing with the resin,
The wiring on the surface side of the first semiconductor chip and the second semiconductor chip is connected to connect the electrode on the surface side of the first semiconductor chip and the electrode on the surface side of the second semiconductor chip. The method for manufacturing a semiconductor device according to appendix 6, further comprising a step of forming a rewiring to be performed.
(Appendix 8)
The thickness of the electrode on the back surface side of the first semiconductor chip and the electrode on the back surface side of the second semiconductor chip before the grinding is 10 μm or more. Production method.
(Appendix 9)
The step of fixing the first semiconductor chip and the second semiconductor chip with the resin,
Bonding the surface side of the first semiconductor chip and the second semiconductor chip to the adhesive layer on the support substrate;
Supplying resin to the back side of the first semiconductor chip and the second semiconductor chip attached to the adhesive layer of the support substrate, and then curing the resin;
A step of peeling the adhesive layer and the support substrate from the one in which the first semiconductor chip and the second semiconductor chip are fixed by the resin;
The method for manufacturing a semiconductor device according to any one of appendices 1 to 8, wherein the method includes:
(Appendix 10)
In the first semiconductor chip, a semiconductor element is formed of a nitride semiconductor layer on the surface side of the SiC substrate,
10. The semiconductor device according to any one of appendices 1 to 9, wherein the second semiconductor chip has one or more of a resistor, a capacitor, and an inductance formed on a surface side of a Si substrate. Production method.
(Appendix 11)
11. The method of manufacturing a semiconductor device according to any one of appendices 1 to 10, wherein a plurality of the second semiconductor chips are provided.
(Appendix 12)
A first semiconductor chip having an electrode formed on the front surface side and a through electrode penetrating from the front surface side to the back surface side;
A second semiconductor chip having an electrode formed on the front surface side and a through electrode penetrating from the front surface side to the back surface side;
Resin for fixing the first semiconductor chip and the second semiconductor chip;
A common electrode connecting the back surface of the first semiconductor chip and the back surface of the second semiconductor chip;
Have
The first semiconductor chip is formed on a SiC substrate,
A semiconductor device, wherein the semiconductor substrate on which the second semiconductor chip is formed is formed of a material different from that of the semiconductor substrate on which the first semiconductor chip is formed.
(Appendix 13)
The first semiconductor chip has a semiconductor element formed of a semiconductor layer containing GaN on a SiC substrate,
13. The semiconductor device according to appendix 12, wherein the second semiconductor chip is an Si element on which an electronic element is formed.
(Appendix 14)
14. The semiconductor device according to appendix 12 or 13, wherein a plurality of the second semiconductor chips are provided.
(Appendix 15)
15. An amplifier comprising the semiconductor device according to any one of appendices 12 to 14.

DESCRIPTION OF SYMBOLS 10 1st semiconductor chip 11 SiC substrate 12 Nitride semiconductor layer 13 Front surface side electrode 16 Back surface side electrode 17 TSV wiring 20 2nd semiconductor chip 21 Si substrate 22a, 22b Silicon oxide film 23 Front surface side electrode 24 Capacitor 25 Resistance 26 Back surface Side electrode 27 TSV wiring 30 Third semiconductor chip 31 Si substrate 32a, 32b Silicon oxide film 33 Front side electrode 34 Capacitor 35 Inductance 36 Back side electrode 37 TSV wiring 40 Mold resin 50 Rewiring layer 51 Interlayer insulating film 52 Wiring 60 Metal Film 70 Support substrate 71 Adhesive layer 72 Resist pattern 73 Support substrate 74 Thermoplastic adhesive 81 SiC wafer 82 Si wafer 83 Pseudo wafer

Claims (5)

A first semiconductor chip having an electrode formed on the front surface side and a through electrode penetrating from the front surface side to the back surface side; and an electrode formed on the front surface side and a through electrode penetrating from the front surface side to the back surface side. Fixing the two semiconductor chips with a resin on the back side of the first semiconductor chip and the second semiconductor chip;
Exposing the back side of the first semiconductor chip and the back side of the second semiconductor chip by removing the resin by etching; and
Forming a common electrode on the back side of the first semiconductor chip and the back side of the second semiconductor chip;
Have
In the first semiconductor chip, a semiconductor element is formed of a nitride semiconductor layer on the surface side of the SiC substrate,
The second semiconductor chip has one or more of a resistor, a capacitor, and an inductance formed on the surface side of the Si substrate ,
Exposing the back side of the first semiconductor chip and the back side of the second semiconductor chip,
Grinding the resin from the back side of the first semiconductor chip and the second semiconductor chip to a predetermined thickness;
A resist pattern is formed on the ground surface, and a resin in a region where the resist pattern is not formed is removed by etching, whereby the back surface side of the first semiconductor chip and the second semiconductor chip Exposing the back side;
The method of manufacturing a semiconductor device according to claim Rukoto to have a. The method of manufacturing a semiconductor device according to claim 1 , wherein the predetermined thickness is 10 μm or less. After the step of fixing with the resin,
The wiring on the surface side of the first semiconductor chip and the second semiconductor chip is connected to connect the electrode on the surface side of the first semiconductor chip and the electrode on the surface side of the second semiconductor chip. the method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that it comprises a step of forming a re-wiring. The step of forming the common electrode includes:
Forming a first metal film on the back side of the first semiconductor chip and the back side of the second semiconductor chip;
Forming a second metal film on the first metal film by plating;
The method of manufacturing a semiconductor device according to any of claims 1 to 3, characterized in that those comprising a. The step of fixing the first semiconductor chip and the second semiconductor chip with the resin,
Bonding the surface side of the first semiconductor chip and the second semiconductor chip to the adhesive layer on the support substrate;
Supplying resin to the back side of the first semiconductor chip and the second semiconductor chip attached to the adhesive layer of the support substrate, and then curing the resin;
A step of peeling the adhesive layer and the support substrate from the one in which the first semiconductor chip and the second semiconductor chip are fixed by the resin;
The method of manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that those comprising a.

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