JP6420551B2 - Lead frame and manufacturing method of semiconductor device - Google Patents

Lead frame and manufacturing method of semiconductor device Download PDF

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JP6420551B2
JP6420551B2 JP2014025802A JP2014025802A JP6420551B2 JP 6420551 B2 JP6420551 B2 JP 6420551B2 JP 2014025802 A JP2014025802 A JP 2014025802A JP 2014025802 A JP2014025802 A JP 2014025802A JP 6420551 B2 JP6420551 B2 JP 6420551B2
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semiconductor chip
recess
lead frame
die
region
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JP2015153877A (en
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祐一 宮島
祐一 宮島
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Ablic Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

本発明は、リードフレームおよびそれを用いた半導体装置の製造方法に関する。   The present invention relates to a lead frame and a method for manufacturing a semiconductor device using the lead frame.

一般的に、半導体チップをリードフレームに搭載する工程、すなわち、ダイボンド工程では、図８に示すように、ダイパッド４上に銀ペースト１２が滴下され、その上にコレット８によって運ばれた半導体チップ３をスクラブして接着する。その後、１５０℃以上の高温雰囲気（高温槽や高温炉）内で銀ペーストをキュアさせて半導体チップを固着させるという方法がとられている。（例えば、特許文献１参照）   In general, in a process of mounting a semiconductor chip on a lead frame, that is, a die bonding process, as shown in FIG. 8, a silver paste 12 is dropped on a die pad 4 and carried by a collet 8 thereon. Scrub and glue. Thereafter, a method is employed in which the semiconductor chip is fixed by curing the silver paste in a high temperature atmosphere (high temperature tank or high temperature furnace) of 150 ° C. or higher. (For example, see Patent Document 1)

特開昭６２−４５１３３号公報JP-A-62-45133

しかしながら、高温雰囲気内でのキュアには数時間を要することから、その分、半導体のパッケージング工程が長くなるという問題がある。また、高温雰囲気内に数時間もの間、リードフレームを放置することにより、リードフレーム表面が酸化し、モールド樹脂とリードフレームの密着性が低下するという問題がある。   However, since curing in a high temperature atmosphere requires several hours, there is a problem that the semiconductor packaging process becomes longer. In addition, if the lead frame is left in a high temperature atmosphere for several hours, the lead frame surface is oxidized, and the adhesion between the mold resin and the lead frame is lowered.

また、ダイボンディング材が銀ペーストの場合は、ノズルからディスペンスすることでダイパッドに塗布しているため、ダイボンディング材の塗布量がばらついて、半導体チップとダイパッドとの間から銀ペーストが漏出し、ダイパッドの側面や裏面に回りこんでリードとのショートや樹脂封止不良などの問題を引き起こすという懸念もある。   In addition, when the die bonding material is a silver paste, since it is applied to the die pad by dispensing from the nozzle, the amount of application of the die bonding material varies, and the silver paste leaks from between the semiconductor chip and the die pad, There is also a concern that the side surface or back surface of the die pad may wrap around and cause problems such as a short circuit with the lead or defective resin sealing.

発明はかかる事情に鑑みてなされたものであり、パッケージング工程の時間短縮、リードフレームの変質防止、ダイボンド材の漏出防止を目的とする。   The present invention has been made in view of such circumstances, and aims at shortening the packaging process time, preventing lead frame deterioration, and preventing die bond material leakage.

上記課題の解決のために、本発明では以下の手段を用いた。
まず、半導体チップを搭載するダイパッドを有するリードフレームであって、前記ダイパッドの半導体チップ搭載領域内には、凹部を有することを特徴とするリードフレームとした。
また、前記凹部は球面であり、球面の曲率半径が、前記凹部に載置する球状のダイボンド材の曲率半径よりも大きいことを特徴とするリードフレームとした。 In order to solve the above problems, the present invention uses the following means.
First, a lead frame having a die pad for mounting a semiconductor chip, wherein the lead pad has a recess in the semiconductor chip mounting region of the die pad.
Further, the lead frame is characterized in that the concave portion is a spherical surface, and the radius of curvature of the spherical surface is larger than the radius of curvature of the spherical die-bonding material placed in the concave portion.

また、前記凹部が平面視的に円もしくは楕円であって、前記半導体チップ搭載領域を成す４辺のうち、少なくとも２辺に内接することを特徴とするリードフレームとした。
また、前記凹部が内接する２辺が、前記半導体チップ搭載領域の隅を成す２辺であることを特徴とするリードフレームとした。
また、前記凹部の球面の最深部が、平面視的な円もしくは楕円の中心から偏心していることを特徴とするリードフレームとした。 Further, the lead frame is characterized in that the concave portion is a circle or an ellipse in a plan view and is inscribed in at least two sides among the four sides forming the semiconductor chip mounting region.
The lead frame is characterized in that two sides inscribed by the recess are two sides forming a corner of the semiconductor chip mounting region.
Further, the lead frame is characterized in that the deepest portion of the spherical surface of the concave portion is decentered from the center of a circle or ellipse in plan view.

また、前記凹部が内接する２辺が、前記半導体チップ搭載領域を成す対向する２辺であることを特徴とするリードフレームとした。
また、前記凹部から前記半導体チップ搭載領域の外周に向かう凹状誘導路を設けることを特徴とするリードフレームとした。
また、前記凹部が半導体チップを搭載する領域６と相似形であって、半導体チップを搭載する領域６よりも小さいことを特徴とする請求項２記載のリードフレームとした。 The lead frame is characterized in that two sides inscribed by the recess are two opposite sides forming the semiconductor chip mounting region.
The lead frame is characterized in that a concave guiding path is provided from the recess toward the outer periphery of the semiconductor chip mounting region.
3. The lead frame according to claim 2, wherein the recess is similar to the region 6 for mounting a semiconductor chip and is smaller than the region 6 for mounting a semiconductor chip.

また、前記半導体チップを前記リードフレームに接着する半導体装置の製造方法において、前記リードフレームをヒータープレートの上に搭載する工程と、前記リードフレームの前記凹部に前記球体のダイボンド材を供給する工程と、前記ダイボンド材を加熱溶融する工程と、前記半導体チップ搭載領域に半導体チップを置いて半導体チップをダイパッドに固着させる工程と、からなることを特徴とする半導体装置の製造方法を用いた。   In the method of manufacturing a semiconductor device in which the semiconductor chip is bonded to the lead frame, the step of mounting the lead frame on a heater plate, and the step of supplying the spherical die bond material to the concave portion of the lead frame; A method of manufacturing a semiconductor device comprising: a step of heating and melting the die bond material; and a step of placing a semiconductor chip in the semiconductor chip mounting region and fixing the semiconductor chip to a die pad.

また、前記球体のダイボンド材は、熱硬化性のエポキシ樹脂であることを特徴とする半導体装置の製造方法を用いた。
また、前記球体のダイボンド材は、フィラー材料を含有することを特徴とする半導体装置の製造方法を用いた。
また、前記球体のダイボンド材は、導電性材料を含有することを特徴とする半導体装置の製造方法を用いた。 In addition, the semiconductor device manufacturing method is characterized in that the spherical die-bonding material is a thermosetting epoxy resin.
In addition, the semiconductor device manufacturing method is characterized in that the spherical die-bonding material contains a filler material.
In addition, the semiconductor device manufacturing method is characterized in that the spherical die-bonding material contains a conductive material.

上記手段を用いることで、半導体パッケージング工程の時間短縮、リードフレームの変質防止、ダイボンド材の漏出防止を図ることができる。   By using the above-mentioned means, it is possible to shorten the time of the semiconductor packaging process, prevent lead frame deterioration, and prevent die bond material leakage.

本発明のダイボンド工程を説明する断面図である。It is sectional drawing explaining the die-bonding process of this invention. 本発明のリードフレームの第１の実施形態を説明する平面図である。1 is a plan view illustrating a first embodiment of a lead frame of the present invention. 本発明のリードフレームの第２の実施形態を説明する平面図である。It is a top view explaining 2nd Embodiment of the lead frame of this invention. 本発明のリードフレームの第３の実施形態を説明する平面図である。It is a top view explaining a 3rd embodiment of a lead frame of the present invention. 本発明のリードフレームの第４の実施形態を説明する平面図である。It is a top view explaining a 4th embodiment of a lead frame of the present invention. 本発明のリードフレームの第５の実施形態を説明する平面図である。It is a top view explaining a 5th embodiment of a lead frame of the present invention. 本発明のリードフレームの第６の実施形態を説明する平面図である。It is a top view explaining a 6th embodiment of a lead frame of the present invention. 従来のダイボンド工程を説明する断面図である。It is sectional drawing explaining the conventional die-bonding process.

本発明のリードフレームおよび半導体装置の製造方法について図を用いて説明する。
図１は、本発明のダイボンド工程を説明する断面図である。加熱機能を有するヒータープレート５の上に、凹部２を設けたダイパッド４が搭載されている。次いで、底面がゆるやかな球面状の凹部２の上にエポキシなどの熱硬化性樹脂からなる球体のダイボンド材１を供給すると、凹部２の球面の曲率半径よりも小さい曲率半径を有する球体のダイボンド材１は転がって、凹部２の球面の最深部に載置されることになる。その後、ヒータープレート５を１５０〜２００℃に加熱し、ダイボンド材１をゲル状に溶融させる。このとき、溶融したダイボンド材は凹部２に溜まり、その表面が凹部２から僅かに盛り上がった状態である。このためにはダイボンド材の体積は凹部の容積よりもわずかに大きいことが必要である。次いで、コレット８で真空吸着した半導体チップ３を、凹部２を覆うように置き、ダイボンド材の硬化により半導体チップ３をダイパッド４に固着させる。 The lead frame and semiconductor device manufacturing method of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view illustrating the die bonding process of the present invention. A die pad 4 provided with a recess 2 is mounted on a heater plate 5 having a heating function. Next, when the spherical die-bonding material 1 made of a thermosetting resin such as epoxy is supplied on the spherical concave portion 2 having a gentle bottom surface, the spherical die-bonding material having a curvature radius smaller than the curvature radius of the spherical surface of the concave portion 2. 1 rolls and is placed at the deepest part of the spherical surface of the recess 2. Thereafter, the heater plate 5 is heated to 150 to 200 ° C., and the die bond material 1 is melted in a gel form. At this time, the melted die bond material is accumulated in the recess 2, and the surface is slightly raised from the recess 2. For this purpose, the volume of the die bond material needs to be slightly larger than the volume of the recess. Next, the semiconductor chip 3 vacuum-adsorbed by the collet 8 is placed so as to cover the recess 2, and the semiconductor chip 3 is fixed to the die pad 4 by curing the die bonding material.

なお、ダイボンド材１は、フィラーを含有する樹脂であるほうが固着時の収縮が少なく好適である。さらに、必要に応じて、金属粒などの導電性粒子を含有するものであっても良い。   Note that the die bond material 1 is preferably a resin containing a filler with less shrinkage during fixation. Furthermore, you may contain electroconductive particles, such as a metal grain, as needed.

図２は、本発明のリードフレームの第１の実施形態を説明する平面図である。両側に複数のリード７を備えたダイパッド４は矩形の半導体チップを搭載する領域６を有し、その領域６の中心には凹部２が設けられ、凹部２の中には凹部の直径よりも小さい球状のダイボンド材１が置かれている。加熱されると、このダイボンド材１がゲル状に溶融して半導体チップとダイパッド４との接着剤として働くが、半導体チップに押さえつけられてもダイボンド材１は、区画された凹部２から外に漏出することはない。なお、図２では凹部２を真円で図示したが、半導体チップが長方形であれば、それに合わせて楕円としても構わない。   FIG. 2 is a plan view for explaining the first embodiment of the lead frame of the present invention. The die pad 4 having a plurality of leads 7 on both sides has a region 6 on which a rectangular semiconductor chip is mounted, and a recess 2 is provided at the center of the region 6, and the recess 2 has a diameter smaller than the diameter of the recess. A spherical die bond material 1 is placed. When heated, the die bond material 1 melts into a gel and acts as an adhesive between the semiconductor chip and the die pad 4, but the die bond material 1 leaks out from the partitioned recess 2 even when pressed against the semiconductor chip. Never do. In FIG. 2, the recess 2 is illustrated as a perfect circle. However, if the semiconductor chip is rectangular, it may be oval according to the shape.

図３は、本発明のリードフレームの第２の実施形態を説明する平面図である。図２との違いは、半導体チップを搭載する領域６と凹部２との位置関係であり、凹部２は半導体チップを搭載する領域６のうち、少なくとも平行に対向する２辺に内接するように形成されている。図のように、２組の対向する２辺、すなわち、４辺に内接する凹部２とすることで、半導体チップとダイパッド４との接着性がさらに向上することは明らかである。   FIG. 3 is a plan view for explaining a second embodiment of the lead frame of the present invention. The difference from FIG. 2 is the positional relationship between the semiconductor chip mounting region 6 and the recess 2, and the recess 2 is formed so as to be inscribed in at least two parallel opposing sides of the semiconductor chip mounting region 6. Has been. As shown in the figure, it is apparent that the adhesiveness between the semiconductor chip and the die pad 4 is further improved by forming the recesses 2 inscribed in two opposing two sides, that is, the four sides.

図４は、本発明のリードフレームの第３の実施形態を説明する平面図である。図２との違いは、凹部２が半導体チップを搭載する領域６と相似であって、半導体チップを搭載する領域６よりも幾分小さくなっている点である。この場合、矩形の凹部２と半導体チップを搭載する領域６で画定される領域に半導体チップの端部が固定されることになる。なお、凹部が矩形であってもその底面は球面からなり、その最深部は平面視的に矩形の中心に位置し、そこにダイボンド材１が載置されることになる。   FIG. 4 is a plan view for explaining a third embodiment of the lead frame of the present invention. The difference from FIG. 2 is that the recess 2 is similar to the region 6 on which the semiconductor chip is mounted, and is somewhat smaller than the region 6 on which the semiconductor chip is mounted. In this case, the end of the semiconductor chip is fixed to a region defined by the rectangular recess 2 and the region 6 on which the semiconductor chip is mounted. Even if the concave portion is rectangular, the bottom surface is a spherical surface, and the deepest portion is located at the center of the rectangle in plan view, and the die bond material 1 is placed there.

図５は、本発明のリードフレームの第４の実施形態を説明する平面図である。図２との違いは、ダイパッド４の中央に設けた凹部２に加えて、半導体チップを搭載する領域６の４隅に凹部９を設けた点である。４隅に設けた凹部９の各々は半導体チップを搭載する領域６の隅を成す２辺に内接し、ダイパッド４の中央に設けた凹部２に外接するように設けられている。半導体チップを搭載する領域６の中央部に設けた凹部２および隅部に設けた凹部９の底面は球面であり、中央部に設けた凹部２の最深部は平面視的に円の中心に位置するが、隅部に設けた凹部９の最深部は平面視的に円の中心ではなく、中心よりも半導体チップを搭載する領域６の４隅の頂点方向に偏心しており、この偏心した最深部に小径のダイボンド材１１を載置する。このような形状にすることで、半導体チップを搭載する領域６の４隅までの接着が良好なものとなる。   FIG. 5 is a plan view for explaining a fourth embodiment of the lead frame of the present invention. The difference from FIG. 2 is that, in addition to the recess 2 provided at the center of the die pad 4, recesses 9 are provided at the four corners of the region 6 on which the semiconductor chip is mounted. Each of the recesses 9 provided at the four corners is provided so as to be inscribed in the two sides forming the corner of the region 6 on which the semiconductor chip is mounted and so as to be circumscribed by the recess 2 provided in the center of the die pad 4. The bottom surface of the recess 2 provided at the center of the region 6 on which the semiconductor chip is mounted and the recess 9 provided at the corner are spherical, and the deepest portion of the recess 2 provided at the center is located at the center of the circle in plan view. However, the deepest portion of the recess 9 provided at the corner is not centered on the circle in plan view, but is decentered from the center toward the apex of the four corners of the region 6 where the semiconductor chip is mounted. The die bond material 11 having a small diameter is placed on By adopting such a shape, adhesion to the four corners of the region 6 on which the semiconductor chip is mounted is good.

以上の説明では、中心部の凹部２が大きく、隅部の凹部９が小さいというように異なる大きさで表現したが、外寸が同じ大きさとし、載置するダイボンド材の大きさも同じにしても良い。また、ダイパッド４の中央の凹部２を省いて４隅のみに凹部９を配置し、各々の凹部９が隣接する凹部９と外接するという配置でも構わない。   In the above description, the concave portion 2 at the center is large and the concave portion 9 at the corner is small. However, the outer dimensions are the same, and the size of the die bond material to be placed is the same. good. Alternatively, the concave portion 2 at the center of the die pad 4 may be omitted, and the concave portions 9 may be disposed only at the four corners, and each concave portion 9 may circumscribe the adjacent concave portion 9.

図６は、本発明のリードフレームの第５の実施形態を説明する平面図である。図２との違いは、ダイパッド４の中央に設けた凹部２に加えて、凹部２から半導体チップを搭載する領域６の４隅にかけて凹状誘導路１０を設けた点である。凹部２にダイボンド材１を置き、加熱することでダイボンド材１は溶融するが、そこに半導体チップを載置すると、ゲル状に溶融したダイボンド材は凹部２からオーバーフローして凹状誘導路１０を４隅に向けて流れ、半導体チップとダイパッド４との良好な接着が可能となる。図では、４隅に向けた４本の凹状誘導路１０が示されているが、さらに、４辺に向けた複数の凹状誘導路など、半導体チップを搭載する領域６の外周に向けた凹状誘導路を設けても良い。   FIG. 6 is a plan view for explaining a fifth embodiment of the lead frame of the present invention. The difference from FIG. 2 is that, in addition to the concave portion 2 provided at the center of the die pad 4, concave guide paths 10 are provided from the concave portion 2 to the four corners of the region 6 on which the semiconductor chip is mounted. The die-bonding material 1 is melted by placing the die-bonding material 1 in the recess 2 and heating. However, when the semiconductor chip is placed there, the die-bonding material melted in a gel state overflows from the recess 2 and passes through the concave guiding path 10. The semiconductor chip and the die pad 4 can be bonded well by flowing toward the corner. In the figure, four concave guiding paths 10 toward four corners are shown, but a concave guiding toward the outer periphery of the region 6 on which the semiconductor chip is mounted, such as a plurality of concave guiding paths toward four sides. A road may be provided.

図７は、本発明のリードフレームの第６の実施形態を説明する平面図である。図２との違いは、凹部２が平面視的に矩形であって、半導体チップを搭載する領域６よりも幾分小さくなっている点である。この場合、矩形の凹部２と半導体チップを搭載する領域６で画定される領域に半導体チップの端部が固定されることになる。なお、凹部が矩形であってもその底面はゆるやかな球面からなり、その最深部は平面視的に矩形の中心に位置する。そこに、複数の小径のダイボンド材１１を供給すると、凹部２の球面上を転がって、複数の小径のダイボンド材１１が凹部２の全面に、密に並べられることになる。これを加熱して溶融した後、半導体チップを領域６に載置すると、半導体チップとダイパッド４との良好な接着が可能となる。小径のダイボンド材１１は凹部２の形状に合わせて、その全面に密に敷きつめられるので、半導体チップの形状に合った凹部とすることでダイボンド材の漏出がなく、半導体チップとダイパッドとの良好な接着が可能となる。なお、密に並べられるダイボンド材が極めて小さければ、単層ではなく複数層となるように載置しても構わない。   FIG. 7 is a plan view for explaining a sixth embodiment of the lead frame of the present invention. The difference from FIG. 2 is that the recess 2 is rectangular in plan view and is somewhat smaller than the region 6 on which the semiconductor chip is mounted. In this case, the end of the semiconductor chip is fixed to a region defined by the rectangular recess 2 and the region 6 on which the semiconductor chip is mounted. Even if the concave portion is rectangular, the bottom surface has a gentle spherical surface, and the deepest portion is located at the center of the rectangle in plan view. When a plurality of small-diameter die bond materials 11 are supplied thereto, the rolls roll on the spherical surface of the recess 2, and the plurality of small-diameter die bond materials 11 are densely arranged on the entire surface of the recess 2. When the semiconductor chip is placed on the region 6 after being heated and melted, good bonding between the semiconductor chip and the die pad 4 becomes possible. The small-diameter die-bonding material 11 is densely laid on the entire surface in accordance with the shape of the recess 2, so that the die-bonding material does not leak by making the recess suitable for the shape of the semiconductor chip, and the semiconductor chip and the die pad are excellent. Adhesion becomes possible. In addition, if the die-bonding material arranged densely is very small, you may mount so that it may become multiple layers instead of a single layer.

以上のようなリードフレームおよび半導体装置の製造方法を用いることで、数時間を要していたキュア工程を削減できるため工程時間の削減が可能となる。また、リードフレームが高温雰囲気に長時間にわたり放置されることが無いため、リードフレーム表面が酸化し、モールド樹脂とリードフレームとの密着性が低下するという問題も解消できる。また、ダイパッドには区画された凹部や凹状誘導路があるため、溶融したダイボンド材が半導体チップを搭載する領域から漏出する懸念もない。さらには、凹部の形状の工夫や凹状誘導路の配置によって半導体チップとダイパッドとの良好な接着も可能となる。   By using the lead frame and semiconductor device manufacturing method as described above, it is possible to reduce the curing process, which has required several hours, thereby reducing the process time. Further, since the lead frame is not left in a high temperature atmosphere for a long time, the problem that the lead frame surface is oxidized and the adhesion between the mold resin and the lead frame is reduced can be solved. In addition, since the die pad has a partitioned concave portion and a concave guide path, there is no fear that the melted die bond material leaks from the region where the semiconductor chip is mounted. Furthermore, good bonding between the semiconductor chip and the die pad is also possible by devising the shape of the recess and arranging the concave guide path.

１ ダイボンド材
２ ダイパッド上の凹部（中央部）
３ 半導体チップ
４ ダイパッド
５ ヒータープレート
６ 半導体チップ搭載領域
７ リード
８ コレット
９ ダイパッド上の凹部（隅部）
１０ 凹状誘導路
１１ 小径のダイボンド材
１２ 銀ペースト 1 Die bond material 2 Recess on the die pad (center part)
3 Semiconductor chip 4 Die pad 5 Heater plate 6 Semiconductor chip mounting area 7 Lead 8 Collet 9 Recess (corner) on the die pad
10 concave guideway 11 small diameter die bond material 12 silver paste

Claims (1)

半導体チップを搭載する矩形の領域を有するダイパッドと、
前記ダイパッドの両側に設けられたリードと、
前記領域の中心に設けられた第１の凹部と、
前記第１の凹部に外接し、前記領域の４隅に設けられた平面視的に円形状の第２の凹部と、を備え、
前記第２の凹部の底面は球面であって、前記底面の最深部が平面視的に前記円形状の中心よりも前記領域の４隅の頂点方向に偏心していることを特徴とするリードフレーム。 A die pad having a rectangular region for mounting a semiconductor chip;
Leads provided on both sides of the die pad;
A first recess provided in the center of the region;
A second recess that circumscribes the first recess and is circular in plan view provided at the four corners of the region ;
The bottom surface of the second recess is a spherical surface, a lead frame deepest portion of the bottom surface is characterized that you have eccentric than the circular center of a plan view of the four corners of the vertex direction of the region .
JP2014025802A 2014-02-13 2014-02-13 Lead frame and manufacturing method of semiconductor device Expired - Fee Related JP6420551B2 (en)

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JPS53145570A (en) * 1977-05-25 1978-12-18 Mitsubishi Electric Corp Die bonding method of semiconductor device
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JPH05166856A (en) * 1991-12-19 1993-07-02 Fuji Electric Co Ltd Metal-base bonding method of semiconductor device and metal base
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US8779565B2 (en) * 2010-12-14 2014-07-15 Stats Chippac Ltd. Integrated circuit mounting system with paddle interlock and method of manufacture thereof

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