JP6280601B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachislot machine or a pachinko machine.

  Conventionally, it is detected that a plurality of reels having a plurality of symbols arranged on each surface, a game medal, a coin, etc. (hereinafter referred to as a “medal, etc.”) and a start lever is operated by a player, A start switch that requests the start of rotation of a plurality of reels and a stop button provided corresponding to each of the plurality of reels are detected by the player, and the stop of rotation of the corresponding reel is requested. A stop switch that outputs a signal, a stepping motor that is provided corresponding to each of the plurality of reels, and that transmits each driving force to each reel, and a stepping motor based on the signals output by the start switch and the stop switch The reel control unit controls the operation of each reel and rotates and stops each reel. When it is detected, lottery is performed based on the random number value, and the rotation of the reel is determined based on the result of the lottery (hereinafter referred to as “internal winning combination”) and the timing at which the stop button is detected. A so-called pachislot machine that stops is known.

  This type of gaming machine includes a cabinet that houses reels and the like, and a front door that is attached to the cabinet so as to be opened and closed. The reel accommodated in the cabinet is visually recognized by the player through a display window provided in the front door. A main control board (main board) constituting a main control circuit is disposed in the cabinet. The main control circuit, for example, determines the internal winning combination performed using a random number in the program, rotates and stops a plurality of reels, and whether or not a prize is awarded based on the symbols displayed on the display window when the plurality of reels are stopped The main flow of the game in the gaming machine such as determination of the game is controlled. On the other hand, a sub control board (sub board) constituting a sub control circuit is disposed on the front door. The sub-control circuit controls execution of effects by displaying sound or video. This effect is determined by the sub control circuit based on, for example, the operation of the start lever by the player or the internal winning combination determined by the main control circuit. Among the effects executed in this manner, for example, there are those that inform the player of information relating to AT (assist time) or ART (privilege that combines assist time and replay time).

  As such a gaming machine, for example, Patent Document 1 discloses that a command transmission from a main board (main control circuit) to a sub board (sub control circuit) is encrypted to prevent illegal actions such as so-called communication goto. Is presented.

  By the way, serial data is generally exchanged between a main board and a sub board in this type of gaming machine via an interface circuit such as UART (Universal Asynchronous Receiver Transmitter) or SPI (Serial Peripheral Interface).

Japanese Patent Laid-Open No. 2005-21660

  However, in the conventional gaming machine described above, in communication via UART or SPI, data errors are likely to occur due to noise, fluctuations in the transmission level, etc., and there is a possibility that data cannot be received correctly.

  In addition, since an interface circuit that performs serial bus communication such as SPI requires a clock signal line for synchronizing data, there is also a problem that it is difficult to simplify the connection form between the main board and the sub board.

  The present invention has been created under the circumstances described above, and provides a gaming machine that can transmit and receive data correctly and stably and can easily simplify the connection form related to communication. For the purpose.

The present invention
First control means for performing predetermined control processing relating to the game;
In accordance with a command from the first control means, performs a specific control different from the first control means, a second control means having a higher specification than the first control means,
A gaming machine equipped with
First communication means for receiving the command from the first control means at a first communication speed and transmitting communication data including the command at a second communication speed higher than the first communication speed; ,
Second communication means for receiving the communication data from the first communication means at the second communication speed and transmitting the communication data to the second control means at the second communication speed;
With
The first communication means has modulation means for modulating the communication data by a two-phase phase shift keying method and transmitting the communication data to the second communication means,
The second communication means has demodulation means for demodulating the communication data modulated by the modulation means by the two-phase phase shift keying method and transmitting the communication data to the second control means. ,
The modulation means generates the communication data modulated by exclusive OR of a clock signal for synchronization and the communication data, and outputs the communication data to the second communication means,
The demodulation unit generates the communication data demodulated by exclusive OR of the synchronization clock signal and the modulated communication data, the communication data output from the first communication unit, To the second control means,
The second control means includes
A communication error detected according to the reception time set based on the first communication speed and the second communication speed when the first communication means and the second communication means perform reception. Communication error detecting means for detecting upon reception of the communication data;
The communication data received by the second control means from the second communication means includes the command transmitted from the first control means, the first control means, and the first communication means. Communication error information generated between the first communication unit and the second communication unit, and communication error information generated between the first communication unit and the second communication unit.
In the present invention, the second communication means receives communication data having the same configuration as the communication data received by the second control means from the first communication means,
A predetermined fixed value is assigned to communication error information generated between the first communication means and the second communication means included in the communication data received from the first communication means. It is good.
The present invention also provides:
First control processing means for performing predetermined control processing relating to a game;
Second control processing means for performing specific control processing different from the first control processing means in response to a command from the first control processing means;
A gaming machine equipped with
First communication means for receiving the command from the first control processing means and transmitting communication data including the command;
Second communication means for receiving the communication data from the first communication means and transmitting the communication data to the second control processing means;
With
The first communication means has modulation means for modulating the communication data by a two-phase phase shift keying method and transmitting the communication data to the second communication means,
The second communication means has demodulation means for demodulating the communication data modulated by the modulation means by the two-phase phase shift keying method and transmitting the communication data to the second control processing means. It is characterized by that.

  According to such a configuration, the command is transmitted from the first control processing unit to the first communication unit, and the communication data including the command is transmitted from the first communication unit to the second communication unit. The signal is transmitted after being modulated by the shift keying method. In the second communication means, the communication data received from the first communication means is demodulated by the two-phase phase shift keying and then transmitted to the second control processing means. Thereby, in the gaming machine according to the present invention, data can be transmitted and received correctly and stably by the two-phase phase shift keying method. Further, since the clock rate can be embedded in the communication data exchanged by the two-phase phase shift keying method, it is necessary to provide a clock signal line between the first control processing means and the second control processing means. Therefore, the connection form for communication can be easily simplified.

As a preferred embodiment of the present invention,
The first communication unit and the second communication unit communicate with each other via an optical transmission path.

  According to such a configuration, it is possible to transmit and receive data via the optical transmission path without optically generating a clock signal between the first communication unit and the second communication unit, which is inexpensive. The first communication means and the second communication means can be connected using an optical transmission line.

  ADVANTAGE OF THE INVENTION According to this invention, while being able to transmit / receive data correctly and stably, the game machine which can simplify the connection form which concerns on communication easily can be provided.

It is a perspective view which shows the external appearance of the game machine which concerns on one Embodiment of this invention. It is a perspective view which shows the internal structure of the game machine which concerns on one Embodiment of this invention. It is a block diagram which shows the structure of the main control circuit of the game machine which concerns on one Embodiment of this invention. It is a block diagram which shows the structure of the sub control circuit of the game machine which concerns on one Embodiment of this invention. It is a block diagram which shows the structure of the communication LSI of the game machine which concerns on one Embodiment of this invention. It is a schematic diagram which shows the connection form of the main board | substrate and subboard | substrate of a gaming machine which concerns on one Embodiment of this invention. It is a schematic diagram showing an AES circuit in a communication LSI of a gaming machine according to an embodiment of the present invention. It is explanatory drawing which shows the data flow of the game machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the data flow of the game machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the symbol arrangement | positioning table and symbol code of the gaming machine which concern on one Embodiment of this invention. It is explanatory drawing which shows the symbol combination table of the game machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the bonus operation time table of the game machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the internal lottery table for general game states of the gaming machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the internal lottery table for RB operation | movement of the gaming machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the internal winning combination determination table for a small combination and replay of the gaming machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the internal winning combination determination table for bonus of the gaming machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the internal winning combination storing area | region of the gaming machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the carryover combination storage area | region of the game machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the operating flag storage area | region of the game machine which concerns on one Embodiment of this invention. It is a figure which shows the main flowchart by control of main CPU of the game machine which concerns on one Embodiment of this invention. 4 is a flowchart showing medal acceptance / start check processing by the main CPU of the gaming machine according to the embodiment of the present invention; It is a flowchart which shows the internal lottery process by main CPU of the gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows the reel stop control processing by main CPU of the gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows the bonus operation | movement check process by main CPU of the gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows the bonus completion | finish check process by main CPU of the gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows the interruption process by control of main CPU of the gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows the reception interruption process by sub CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the main board | substrate communication process by sub CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the communication LSI reception data analysis process by sub CPU of the gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows the production | presentation registration task performed by sub CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the production content determination process by sub CPU of the game machine which concerns on one Embodiment of this invention. It is the schematic which shows the menu screen of the game machine which concerns on one Embodiment of this invention. It is the schematic which shows the error information log | history screen of the gaming machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the code number of the received command used for the game machine which concerns on one Embodiment of this invention, a classification | category, and a parameter. It is explanatory drawing which shows the communication log collection area | region in subRAM of the game machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the communication error preservation | save area | region in subRAM of the game machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the frame of the communication data used for the game machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the frame of the communication data used for the game machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the reception status in the communication data of the gaming machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the packet classification in the communication data of the game machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the flow of the communication data of the game machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the area | region image in subRAM of the gaming machine which concerns on one Embodiment of this invention. It is explanatory drawing which shows the error information log | history storage area and error code in sub-RAM of the gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows the main control sequence by the main board | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the reception interruption process by the main board | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the initial setting process by the main board | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the reception process by the main board | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the transmission process by the main board | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the main control sequence by the sub board | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the reception interruption process by the subboard | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the initial setting process by sub board | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the reception process by the subboard | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the transmission process by the subboard | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a schematic diagram which shows the connection form of the main board | substrate and sub board | substrate of the game machine which concerns on other embodiment of this invention. It is a schematic diagram which shows the connection form of the main board | substrate and sub board | substrate of the game machine which concerns on other embodiment of this invention. It is explanatory drawing which shows the data flow of the game machine which concerns on other embodiment of this invention. It is a schematic diagram which shows the connection form of the main board | substrate and sub board | substrate of the game machine which concerns on other embodiment of this invention. It is explanatory drawing which shows the data flow of the game machine which concerns on other embodiment of this invention. It is a perspective view which shows the external appearance of the game machine which concerns on other embodiment of this invention. It is a block diagram which shows the structure of the main control circuit and sub control circuit of the game machine which concern on other embodiment of this invention.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.

[Appearance structure of gaming machine]
FIG. 1 is a perspective view showing an appearance of a gaming machine according to an embodiment of the present invention. As shown in the figure, in this embodiment, a pachislot 1 is applied as a gaming machine. The exterior body 2 of the pachi-slot 1 includes a cabinet 2a that houses a reel, a circuit board, and the like, and a front door 2b that is attached to the cabinet 2a so as to be opened and closed. Handles 7 are provided on both side surfaces of the cabinet 2a. The handle 7 is a recess that is put on when carrying the pachi-slot 1.

  Inside the cabinet 2a, three reels 3L, 3C, 3R are provided side by side. The reels 3L, 3C, and 3R are referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively, when individually described. Each reel 3L, 3C, 3R has a reel body formed in a cylindrical shape and a translucent sheet material mounted on the peripheral surface of the reel body. A plurality of (for example, 21) symbols are drawn on the surface of the sheet material at predetermined intervals along the circumferential direction.

  A liquid crystal display device 10 is provided at the center of the front door 2b. The liquid crystal display device 10 includes a display screen including a liquid crystal display area 10A and symbol display areas 4L, 4C, and 4R, and is positioned on the near side as superimposed on the three reels 3L, 3C, and 3R when viewed from the front. Is provided. In the present embodiment, the entire display screen including the liquid crystal display area 10A and the symbol display areas 4L, 4C, and 4R is used to display an image and execute an effect.

  The symbol display areas 4L, 4C, 4R are provided corresponding to the three reels 3L, 3C, 3R, respectively. The symbol display areas 4L, 4C, and 4R serve as display windows, and are configured to be able to pass through the reels 3L, 3C, and 3R provided behind the symbol display areas 4L, 4C, and 4R. The symbol display areas 4L, 4C, and 4R are referred to as a left display window 4L, a middle display window 4C, and a right display window 4R, respectively, when individually described.

  When the rotation of the reels 3L, 3C, 3R provided behind the display windows 4L, 4C, 4R is stopped, among the plural types of symbols of the reels 3L, 3C, 3R, One symbol (three in total) is displayed in each of the middle and lower regions. Each of the display windows 4L, 4C, 4R is a target for determining whether or not to win a pseudo line that is a combination of any one of the three areas consisting of the upper, middle, and lower stages. It is defined as a line (winning determination line).

  In the present embodiment, a center line 8 is provided as a winning determination line. The center line 8 includes a combination of the middle stage of the left display window 4L, the middle stage of the middle display window 4C, and the middle stage of the right display window 4R.

  Below the display screen of the liquid crystal display device 10, a 7-segment display 6 composed of 7-segment LEDs is provided. The 7-segment display 6 digitally stores information such as the number of medals to be paid out to the player as a privilege (hereinafter referred to as the number of payouts) and the number of medals deposited in the pachislot 1 (hereinafter referred to as the number of credits). indicate.

  The front door 2b is provided with various devices to be operated by the player. The medal slot 11 is provided for receiving a medal dropped from the outside by the player. The medals accepted by the medal slot 11 are inserted into one game with a predetermined number as the upper limit, and the amount exceeding the specified number can be deposited inside the pachislot 1. (So-called credit function).

  On the left side of the medal slot 11, a selection button 11A and a determination button 11B are provided. A player or a staff member can input to the menu screen or the like displayed in the liquid crystal display area 10A by using the selection button 11A and the determination button 11B.

  The maximum BET button 12 is provided to determine the maximum number of coins that can be put into one game from medals deposited inside the pachislot 1. The checkout button 14 is provided to pull out medals deposited inside the pachislot 1 to the outside.

  The start lever 16 is provided for starting the rotation of all the reels 3L, 3C, 3R. The stop buttons 17L, 17C, and 17R are associated with the three reels 3L, 3C, and 3R, respectively, and are provided to stop the rotation of the corresponding reels. The stop buttons 17L, 17C, and 17R are referred to as a left stop button 17L, a middle stop button 17C, and a right stop button 17R, respectively, when individually described.

  The medal payout port 18 guides medals discharged by driving a medal payout device 34 described later to the outside. The medals discharged from the medal payout opening 18 are stored in the medal tray 19. The lamp (LED or the like) 20 outputs light in a turn-on / off pattern according to the content of the effect. The speaker holes 48, 49, 22L, and 22R are provided for outputting sound such as sound effects and music corresponding to the contents of the performance.

  The pachi-slot 1 includes a lock mechanism that switches the front door 2b to a locked state or an unlocked state with the front door 2b closed. This locking mechanism is operated by inserting the door key 110 into the door key hole 11C and rotating the door key 110.

  When the door key 110 is inserted into the door key hole 11C and rotated to the right, for example, the front door 2b can be opened and closed, and when rotated to the left, a main control circuit 60 (see FIG. 3) and the like described later are electrically connected. It is supposed to be reset. That is, the door key 110 has a reset function for electrically resetting the pachi-slot 1 in addition to the operation of the lock mechanism.

[Internal structure of gaming machine]
FIG. 2 is a perspective view showing the internal structure of the gaming machine according to one embodiment of the present invention. On the upper side inside the cabinet 2a, a main control board 6A (a main board 6A to be described later, see FIG. 6 not shown in FIG. 2) constituting the main control circuit 60 (see FIG. 3) is disposed. The main control circuit 60 is a circuit that controls the main flow of the game in the pachislot 1 such as determination of an internal winning combination, rotation and stop of the reels 3L, 3C, 3R, and determination of the presence or absence of winning. A specific configuration of the main control circuit 60 will be described later.

  Three reels 3L, 3C, and 3R are provided at the center inside the cabinet 2a. Note that FIG. 2 shows a state in which the reel body is exposed by removing the sheet material from the reels 3L, 3C, 3R. Stepping motors 50L, 50C, and 50R (see FIG. 3) are connected to the three reels 3L, 3C, and 3R through gears having a predetermined reduction ratio.

  When the inside of the cabinet 2a is viewed from the front, a setting key type switch and an external concentration terminal board (not shown) are arranged on the right side of the right reel 3R. The setting key type switch is used by using a setting key when changing or confirming the setting of the pachislot 1. The external concentrated terminal plate is attached to the side plate of the cabinet 2a. The external concentration terminal board is provided for outputting signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachislot machine 1.

  Below the inside of the cabinet 2a, there is provided a medal payout device (hereinafter referred to as a hopper device) 34 having a structure capable of storing a large amount of medals and discharging them one by one. The hopper device 34 pays out medals when the number of stored medals exceeds 50, for example, or when the settlement button is pressed and the medals are settled. The medals paid out by the hopper device 34 are discharged from the medal payout outlet 18 (see FIG. 2).

  When the inside of the cabinet 2a is viewed from the front, a medal auxiliary store 35 for storing medals overflowing from the hopper device 34 is disposed on the right side of the hopper device 34. Further, when the inside of the cabinet 2a is viewed from the front, a power supply device 36 is provided on the left side of the hopper device 34 for supplying necessary power to each device included in the pachislot machine 1. Further, a sub speaker 37 is disposed between the hopper device 34 and the three reels 3L, 3C, 3R.

  A sub-control board case 42 that accommodates a sub-control board 7A (sub-board 7A to be described later, see FIG. 6 not shown in FIG. 2) is disposed on the upper surface of the rear surface of the front door 2b. The sub control board 7A faces the main control board 6A inside the cabinet 2a via the sub control board case 42. The sub control board 7A constitutes a sub control circuit 70 (see FIGS. 3 and 4). The sub control board 7A is connected to the main control board 6A via an optical fiber cable (not shown). The sub-control circuit 70 is a circuit that controls the execution of effects by displaying images. A specific configuration of the sub control circuit 70 will be described later.

  LED boards 45A, 45B, and 45C and a sound I / O board 46 are disposed at appropriate portions on the back side of the front door 2b. The LED boards 45 </ b> A, 45 </ b> B, and 45 </ b> C display-control the blinking pattern by the lamp (LED etc.) 20 according to the effect executed by the control of the sub control circuit 70. The sound I / O board 46 outputs sound to speakers 48L, 48R, 49L, 49R (48, 49) described later.

  A gaming operation display board (not shown) is disposed below the sound I / O board 46. This game operation display board displays the number of inserted medals on the 7-segment display 6 when accepting insertion of medals, when the three reels 3L, 3C, 3R are rotatable and when replaying. It is a substrate for making it.

  Upper speakers 48L and 48R (48) are arranged on the left and right sides of the sound I / O board 46. And lower speaker 49L, 49R (49) is arrange | positioned by the lower side in the back surface of the front door 2b. The upper speakers 48L and 48R face the speaker holes 48 and 49, respectively, and the lower speakers 49L and 49R face the speaker holes 22L and 22R, respectively.

  A selector 51 and a door open / close monitoring switch 52 are arranged between the upper speaker 48R and the lower speaker 49R. The selector 51 is a device for selecting whether or not the medal material or shape is appropriate, and guides the appropriate medal received in the medal insertion slot 11 to the hopper device 34. A medal sensor (not shown) for detecting that an appropriate medal has passed is provided on the path through which the medal passes in the selector 51.

  The door open / close monitoring switch 52 is disposed on the left side of the selector 51 when the front door 2b is viewed from the back side. The door open / close monitoring switch 52 outputs a security signal for notifying the opening / closing of the front door 2b to the outside of the pachi-slot 1.

  A door relay board 53 is disposed on the right side of the selector 51 when the front door 2b is viewed from the back side. The door relay board 53 is a board that relays wiring between the main control board 6A, various buttons and switches, the sub control board 7A, the game operation display board, and the selector 51. Examples of the various buttons and switches include a maximum BET button 12, a settlement button (C / P button) 14, a door open / close monitoring switch 52, a maximum BET switch 13S and a start switch 6S described later.

  A 24h door open / close monitoring unit (not shown) is disposed below the door relay board 53. This 24h door opening / closing monitoring unit stores a history of opening / closing of the front door 2b. When the front door 2b is opened or the selector 51 is removed, a signal for displaying an error on the liquid crystal display device 10 is output to the sub control board 7A (sub control circuit 70).

  Next, with reference to FIGS. 3 to 9, the electrical configuration of the pachislot machine 1 and the configuration related to the communication function will be described. FIG. 3 is a block diagram showing the configuration of the main control circuit. FIG. 4 is a block diagram showing a configuration of the sub control circuit. FIG. 5 is a block diagram showing the configuration of the communication LSI. FIG. 6 is a schematic diagram showing a connection form between the main board and the sub board. FIG. 7 is a schematic diagram showing an AES circuit in a communication LSI. 8 and 9 are explanatory diagrams showing the data flow.

[Configuration of main control circuit]
The main control circuit 60 controls the progress of a series of games such as determination of an internal winning combination and reel rotation control. The main control circuit 60 includes a microcomputer 600 arranged on the main board 6 (see FIG. 6) as a main component, and is added to a circuit for random number sampling. The microcomputer 600 includes a main CPU 601, a main ROM 602, and a main RAM 603.

  Connected to the main CPU 601 are a clock pulse generation circuit 604, a frequency divider 605, a random number generator 606, and a sampling circuit 607.

  The main CPU 601 determines an internal winning combination based on a random number value and an internal lottery table which will be described later, and stops the rotation of the reels 3L, 3C, 3R based on the internal winning combination and the timing when the stop operation is detected. Let When the main CPU 601 stops the rotation of the reels 3L, 3C, 3R, the main CPU 601 determines whether a winning combination has been established based on the combination of symbols displayed in the symbol display areas 4L, 4C, 4R. Is established (winning), the player is given a profit such as paying out medals according to the established combination.

  The clock pulse generation circuit 604 and the frequency divider 605 generate a reference clock pulse. The random number generator 606 generates a random number in the range of “0” to “65535”. The sampling circuit 607 extracts (samples) one random number value from the random number generated by the random number generator 606.

  The main CPU 601 stores the extracted random number value in a random value storage area of the main RAM 603 described later. The main CPU 601 determines an internal winning combination in an internal lottery process, which will be described later, based on the random value stored in the random value storage area of the main RAM 603 for each game.

  As a means for random number sampling, random number sampling may be executed in the microcomputer 600, that is, on the operation program of the main CPU 601. In that case, the random number generator 606 and the sampling circuit 607 can be omitted. Alternatively, it can be left as a backup for the random number sampling operation.

  The main ROM 602 stores programs related to processing of the main CPU 601, various tables, and the like.

  Various information obtained by processing of the main CPU 601 is set in the main RAM 603. For example, information for specifying the extracted random number value, gaming state, internal winning combination, number of payouts, bonus carryover status, setting value, etc., various counters and flags are set. Some of these pieces of information are transmitted to the sub control circuit 70 as commands.

  Examples of main peripheral devices whose operation is controlled by a control signal from the microcomputer 600 include a medal payout device (hopper device) 34, stepping motors 50L, 50C, and 50R. Transfer of signals between these actuators and the main CPU 601 is performed via the bus 60A.

  Each circuit for controlling the operation of each peripheral device described above is connected to the bus 60A in response to a control signal output from the main CPU 601. The circuits include a motor drive circuit 39, a display unit drive circuit 340, and a hopper drive circuit 341.

  The motor drive circuit 39 drives and controls the stepping motors 50L, 50C, and 50R. As a result, the reels 3L, 3C, 3R are rotated or stopped.

  The display unit drive circuit 340 controls the display of the 7-segment display 6. As a result, the 7-segment display 6 displays the number of payouts and the number of credits.

  The hopper driving circuit 341 controls driving of the hopper device 34. Thereby, the medals accommodated in the hopper device 34 are paid out.

  The bus 60A is connected to switches and circuits that generate input signals that trigger the output of control signals to the circuits and peripheral devices described above. The switches and circuits include a start switch 6S, stop switches 7LS, 7CS, and 7RS, a maximum BET switch 13S, a settlement switch (C / P switch) 14S, a medal sensor 22S, a reel position detection circuit 50, and a payout completion signal circuit 342. There is. The stop switches 7LS, 7CS, and 7RS are collectively referred to as a stop switch 7S.

  The start switch 6S detects a player's start operation on the start lever 16, and outputs a start signal instructing the start of the game to the microcomputer 600.

  The stop switches 7LS, 7CS, 7RS detect the player's stop operation on the stop buttons 7L, 7C, 7R, respectively, and stop the rotation of the reels 3L, 3C, 3R corresponding to the detected stop buttons 7L, 7C, 7R. A stop signal to be commanded is output to the microcomputer 600.

  The maximum BET switch 13S detects a player's insertion operation (pressing operation) on the maximum BET button 12, and outputs a signal for instructing insertion of a medal from a credited medal to the microcomputer 600.

  The settlement switch 14 </ b> S detects a player's switching operation on the settlement button 14 and outputs a signal for switching the credit mode or the payout mode to the microcomputer 600. When the credit mode is switched to the payout mode, a signal for instructing payout of medals credited to the pachislot 1 is output to the microcomputer 600.

  The medal sensor 22S detects medals inserted into the medal insertion slot 11 by the player's insertion operation, and outputs a signal indicating that a medal has been inserted to the microcomputer 600.

  The reel position detection circuit 50 detects a pulse signal from a reel rotation sensor (not shown), and generates a signal for detecting the position of the symbol on each reel 3L, 3C, 3R.

  The payout completion signal circuit 342 indicates that the payout of medals has been completed when the number of medals detected by the medal detection unit 34S (that is, the number of medals paid out from the hopper device 34) reaches the designated number. A signal is generated to indicate

  Further, a main board communication LSI 610 for transmitting information such as commands to the sub control circuit 70 is connected to the main control circuit 60. The main board communication LSI 610 is mounted on the main board 6A (see FIG. 6) as an element constituting the main control circuit 60 together with the microcomputer 600. The output port of the main board communication LSI 610 is connected to the sub control circuit 70 via an optical fiber cable (not shown) as an optical transmission path. The microcomputer 600 (main CPU 601) transmits various commands to the sub-control circuit 70 through the main board communication LSI 610. Note that the main CPU 601 of the present embodiment incorporates a UART 601A, and the main CPU 601 can transmit information to the main board communication LSI 610 through the UART 601A (see FIG. 6). Details of such main board communication LSI 610 and UART 601A will be described later.

  The sub control circuit 70 performs various processes such as determination and execution of effect data based on various commands transmitted from the main control circuit 60 including a start command and the like which will be described later. The sub control circuit 70 does not transmit commands or information to the main control circuit 60, and communication is performed in one direction (one direction) from the main control circuit 60 to the sub control circuit 70.

  Examples of main peripheral devices whose operation is controlled by a control signal from the sub-control circuit 70 include a liquid crystal display device 10 as display means for displaying an image on the liquid crystal display area 10A, speakers 48 and 49, a lamp 20, and the like. is there. The sub-control circuit 70 determines and displays an image displayed on the liquid crystal display device 10 based on the determined effect data, determines and outputs the light emission patterns of the various lamps 20, and effects sound output from the speakers 48 and 49. And control of sound effects and output. Details of the sub control circuit 70 will be described later.

  In the pachislot 1, when a signal for starting a game is output from the start switch 6S by a player's operation on the start lever 16 on condition that a medal is inserted, a control signal is output to the motor drive circuit 39, and the stepping motor 50L , 50C, 50R drive control (for example, excitation to each phase, etc.), the reels 3L, 3C, 3R start to rotate. At this time, the number of pulses output to the stepping motors 50L, 50C, 50R is counted, and the counted value is set in a predetermined area of the main RAM 603 as a pulse counter. In the pachi-slot 1, when the pulse “16” is output, the reels 3L, 3C, 3R move by one symbol. The number of symbols moved is counted, and the counted value is set in a predetermined area of the main RAM 603 as a symbol counter. In other words, every time the pulse counter counts “16” pulses, the symbol counter is updated by “1”. The symbol at the symbol position (see FIG. 10) indicated by the symbol counter value corresponds to the symbol positioned on the center line 8. For example, when the symbol counter of the left reel 3L is “0”, the bell at the symbol position “0” in the symbol arrangement table shown in FIG.

  Further, a reel index is obtained from each reel 3L, 3C, 3R, and the reel index is output to the main CPU 601 via the reel position detection circuit 50. With the output of the reel index, the pulse counter and the symbol counter set in the main RAM 603 are cleared to “0”. In this way, the symbol position within one rotation range is specified for each reel 3L, 3C, 3R. The distance that each symbol moves by one symbol by the rotation of the reel is called one frame. That is, moving the symbol by one frame corresponds to updating the symbol counter by “1”.

  In order to associate the rotational positions of the reels 3L, 3C, and 3R with the symbols drawn on the outer peripheral surface of the reel, the main ROM 602 stores a symbol arrangement table (see FIG. 10A). The symbol arrangement table is provided with code numbers from “00” to “20” that are sequentially given at fixed rotation pitches of the reels 3L, 3C, 3R with reference to the position where the reel index is output. A symbol code for identifying the type of symbol provided corresponding to each code number is associated with each other.

  When a start signal is output from the start switch 6S, a random number value is extracted by the random number generator 606 and the sampling circuit 607. In the pachi-slot 1, when a random value is extracted, it is stored in a random value storage area of the main RAM 603. Then, an internal winning combination is determined based on the random value stored in the random value storage area.

  After the reels 3L, 3C, 3R reach constant speed rotation, when a stop signal is output from the stop switches 7LS, 7CS, 7RS by the stop operation, based on the output stop signal and the determined internal winning combination, A control signal for stopping and controlling the reels 3L, 3C, 3R is output to the motor drive circuit 39. The motor drive circuit 39 drives and controls the stepping motors 50L, 50C, and 50R, and stops the rotation of the reels 3L, 3C, and 3R.

  The main CPU 601 stops the rotation of the reels 3L, 3C, and 3R by drawing in the symbols related to the establishment of the internal winning combination for the maximum number of sliding frames, that is, four frames from the time when the stop operation is performed. Specifically, the main CPU 601 determines whether or not there is a symbol related to the establishment of the internal winning combination within 4 frames after the stop operation is detected by the stop switches 7LS, 7CS, and 7RS, and 4 frames. If there is a symbol related to the establishment of the internal winning combination within, the number of sliding symbols is determined so that the symbol is stopped and displayed on the active line, and the corresponding reel is stopped. Further, when the main CPU 601 determines a plurality of winning combinations as internal winning combinations and there are a plurality of symbols related to the establishment of the internal winning combination within 4 frames, the symbols related to the internal winning combination having a higher priority. The number of sliding frames is determined so that is stopped on the active line.

  Basically, the first priority (highest priority) is a symbol combination related to replay, and the second priority is a symbol combination related to a small role. Next, the 3rd priority rank is a combination of symbols related to the bonus. When the stop operation is detected by the stop switches 7LS, 7CS, 7RS, the symbol positions corresponding to the symbol counters of the corresponding reels 3L, 3C, 3R, that is, the rotation of the reels L, 3C, 3R is stopped. The symbol position is called “stop start position”, and the symbol position obtained by adding the determined number of sliding frames (numerical range “0” to “4”) to the stop start position, that is, the rotation of the reels 3L, 3C, 3R The symbol position to be stopped is called “scheduled stop position”. The number of sliding frames is the amount of rotation of the reels 3L, 3C, 3R from when the stop operation is detected by the stop switches 7LS, 7CS, 7RS until the corresponding reels 3L, 3C, 3R stop rotating. For example, the maximum number of sliding frames is defined as “4”.

  When the rotation of all the reels 3L, 3C, 3R is stopped, the main CPU 601 searches the display combination based on the combination of symbols displayed on the effective line including the center line 8, that is, the determination of whether the combination is established or not established. Process. The display combination search is performed based on a symbol combination table (see FIG. 11) described later stored in the main ROM 602. In this symbol combination table, a symbol combination related to a display combination and a corresponding payout are set.

  When it is determined by the display combination search that a combination of symbols related to winning is displayed, a control signal is output to the hopper driving circuit 341 and the hopper device 34 is driven to pay out medals. At this time, the medal detection unit 34S counts the number of medals paid out from the hopper device 34, and when the count value reaches a designated number, a signal indicating completion of the medal payout is output from the payout completion signal circuit 342. The Thereby, a control signal is output to the hopper drive circuit 341, and the drive of the hopper apparatus 34 is stopped.

  When the payment mode is switched to the credit mode by the settlement switch 14S, if it is determined that the winning symbol combination is displayed, the payout number corresponding to the winning symbol combination is displayed in the credit counter of the main RAM 603. Add to. Further, information regarding the number of medals paid out is transmitted to the sub-control circuit 70, and based on this information, the number of medals paid out and the updated number of credits are displayed in the liquid crystal display area 10A of the liquid crystal display device 10. Is done. Here, there is a case where a medal payout or a credit performed when a symbol combination related to winning is displayed is simply referred to as “payout”.

[Sub-control circuit configuration]
The sub-control circuit 70 performs control for performing effects related to games using video, sound, light, and the like. The sub control circuit 70 determines effect data based on various commands transmitted from the main control circuit 60 and performs various effect processes. The sub control circuit 70 includes a sub CPU 701 as a processing means, a sub ROM 702, a sub RAM 703 as a storage means, a rendering processor 704, a drawing RAM 705 (including a frame buffer 706), a driver 707, a DSP 708, an A / D converter 709A, It has an amplifier 709B, an audio RAM 709C, and a sub-board communication LSI 710 as communication means.

  The sub CPU 701 performs display control of the liquid crystal display device 10, output control of the speakers 48 and 49, light emission control of the lamp 20, and the like based on a program stored in the sub ROM 702. Specifically, the sub CPU 701 receives various commands from the main control circuit 60 and stores various information included in the received commands in the sub RAM 703. All information is transmitted from the main control circuit 60 by a command, and the sub control circuit 70 can determine the state of the main control circuit 60 one by one based on the received command. The sub CPU 701 executes the program while referring to the game state information, internal winning combination information, and the like stored in the sub RAM 703, thereby performing the effects on the rendering devices such as the liquid crystal display device 10, the speakers 48 and 49, and the lamp 20. Determine the content of the production to be performed. The sub CPU 701 controls the liquid crystal display device 10 via the rendering processor 704 based on the determined effect data, and controls the sound output from the speakers 48 and 49 and the light emission of the various lamps 20.

  Further, the sub CPU 701 executes a random number acquisition program stored in the sub ROM 702 to acquire a random number value used when determining effect data and the like. However, when the random number generator and the sampling circuit are provided in the sub-control circuit 70 as in the main control circuit 60, this processing is not necessary.

  The sub ROM 702 has a program storage area for storing programs executed by the sub CPU 701 and a data storage area for storing various tables. The program storage area stores various processes related to communication with the operating system, device driver, main control circuit 60, production registration tasks for determining the contents of production, and the like. On the other hand, the data storage area is a table storage area for storing an effect lottery table, a drawing control data storage area for storing animation data such as character object data, and a voice control data storage area for storing sound data such as BGM and sound effects. And an LED control data storage area for storing a lighting pattern and the like.

  As shown in FIG. 42, the sub RAM 703 has a sub control game data area 703a, a sub control game data sum value area 703b, a work area 703c, an error information history storage area 703d, a communication log collection area 703e, a communication And an error storage area 703f.

  The sub control game data area 703a stores data stored in the sub RAM 703 among the game data relating to the progress of the game. The sub-control game data sum value area 703b stores a check-sum value for the checksum of the game data stored in the sub-control game data area 703a. The work area 703c stores work data in various processes.

  The sub control game data area 703a and the work area 703c are used as work temporary storage means when the sub CPU 701 executes each program. The sub-control game data area 703a stores, for example, information transmitted from the main control circuit 60, such as command, effect data information, game state information, internal winning combination information, display combination information, various counters and various flags. It is like that.

  As shown in FIG. 43A, the error information history storage area 703d contains all error information detected by a main board communication process (see FIG. 28), a communication LSI received data analysis process (see FIG. 29), etc., which will be described later. Is to be remembered. In the error information history storage area 703d, an error information history is created by sequentially storing error codes. In the error information history storage area 703d, the detected error is stored as a COM error.

  Specifically, as shown in FIG. 43A, the error information history storage area 703d includes an error code (ERROR CODE in the figure), an error occurrence date and time (“occurrence” in the figure), and an error release date and time. (“Release” in the figure) is one set of error information, and 128 sets of error information can be stored. As described above, the error information history is created in the error information history storage area 703d by sequentially storing the error codes.

  The error code is 1-byte data. As shown in FIG. 43B, the error code includes a data destruction error (“Sum Abnormal” in the figure) and various errors related to communication (“Main” in the figure). "Substrate communication LSI physical layer error", "Main board communication LSI size shortage", "Subboard communication LSI physical layer error", "Subboard communication LSI size shortage", "Subboard communication LSI CRC error", "Sub CPU CRC error" "," Sub CPU size is insufficient ") and other errors. The error occurrence date and time and the error release date and time are both composed of a 2-byte data year, 1-byte data month, 1-byte data day, 1-byte data hour, 1-byte data minute, and 1-byte data second. Yes.

  In the present embodiment, the following procedure is employed as an example in order to display the error information history stored in the error information history storage area 703d on the liquid crystal display device 10. For example, when the clerk rotates the door key 110 to the right, the lock mechanism of the front door 2b is released, and when the setting key is inserted into the setting key type switch and turned on, the menu shown in FIG. A screen is displayed. Then, when the clerk operates the operation keys on the screen and selects the “error information history” item 100a, an error information history screen as shown in FIG. 33 is displayed in the liquid crystal display area 10A. Further, when the clerk turns the door key to the left, the error is reset, and the error information history screen as shown in FIG. 33 is also displayed in the liquid crystal display area 10A by holding the state for a predetermined time, for example, 5 seconds or more. Is displayed.

  As shown in FIG. 35, in the communication log collection area 703e, an appropriate number of data groups consisting of 256 command and parameter data sets and one corresponding buffer index are stored so that they function as a ring buffer. It has become. As shown in FIG. 36, the communication error storage area 703f stores 1024 data groups including 256 command and parameter data sets and one corresponding buffer index. The communication error storage area 703f is provided with one buffer selection index indicating which buffer index of 1024 buffer indexes is selected. In the communication log collection area 703e shown in FIG. 35 and the communication error storage area 703f shown in FIG. 36, the command consists of one character data and the parameter consists of two character data.

  The sub CPU 701 collects information regarding a reception log (hereinafter also referred to as a communication log) and temporarily stores the communication log in the communication log collection area 703e. Further, when detecting an error related to communication, the sub CPU 701 stores up to 1024 communication logs related to communication errors (hereinafter referred to as communication error logs) in the communication error storage area 703f.

  FIG. 34 shows examples of command types and parameters. The numerical value in the figure is the number of characters of data, 1-character data indicates the command type, and 2-character data indicates the parameter for the immediately preceding command. In the present embodiment, the numerical range of the received command is 01H to 10H as shown in FIG.

  As shown in FIG. 4, the sub CPU 701 is connected to a sub board communication LSI 710 for receiving data such as a command transmitted from the main control circuit 60. The sub board communication LSI 710 is mounted on the sub board 7A (see FIG. 6) as an element constituting the sub control circuit 70. The sub board communication LSI 710 is connected to the main board communication LSI 610 in the main control circuit 60 via an optical fiber cable (not shown) as an optical transmission path. The sub CPU 701 receives various commands and the like transmitted from the main control circuit 60 through the sub board communication LSI 710. Note that the sub CPU 701 of this embodiment has a built-in UART 701A, and the sub CPU 701 can transmit and receive data to and from the sub board communication LSI 710 through the UART 701A (see FIG. 6). Details of such sub-board communication LSI 710 and UART 701A will be described later.

  The rendering processor 704 performs processing for displaying an image on the liquid crystal display device 10 based on an image display command or the like from the sub CPU 701. Data necessary for processing performed by the rendering processor 704 is expanded in the drawing RAM 705 at the time of activation. The rendering processor 704 generates image data by sequentially superimposing the image data developed in the drawing RAM 705 from the background image located at the rear to the image located at the front, and supplies the image data to the liquid crystal display device 10 via the driver 707. To do. As a result, an image corresponding to the effect data determined by the sub CPU 701 is displayed on the liquid crystal display area 10 </ b> A by the liquid crystal display device 10.

  The drawing RAM 705 has two frame buffers 706 for a writing image data area and a display image data area. The write image data area stores image data generated by the rendering processor 704 to generate a display image, and the display image data area stores image data to be displayed on the liquid crystal display device 10. The rendering processor 704 sequentially displays the image data on the liquid crystal display device 10 by alternately switching these frame buffers (that is, switching the banks).

  The DSP 708 generates sound data based on the digital sound data selected by the sub CPU 701 based on the effect data. The audio RAM 709C temporarily stores sound data and is used as an audio buffer. The A / D converter 709A converts the sound data from the DSP 708 into analog sound data and outputs it to the amplifier 709B. The amplifier 709B amplifies the analog sound data from the A / D converter 709A based on the volume adjusted by a volume adjustment knob (not shown), and outputs the amplified data to the speakers 48 and 49. As a result, a sound corresponding to the effect data determined by the sub CPU 701 is output from the speakers 48 and 49.

[Configuration of communication LSI]
FIG. 5 shows the configuration of the main board communication LSI 610 and the sub board communication LSI 710. The main board communication LSI 610 and the sub board communication LSI 710 have the same components. Hereinafter, the function of each component common to the main board communication LSI 610 and the sub board communication LSI 710 will be mainly described, and the function of each component in the main board communication LSI 610 and the sub board communication LSI 710 will be mainly described. The communication LSI 610 and the sub-board communication LSI 710 will be appropriately distinguished for explanation.

  As shown in FIG. 5, the main board communication LSI 610 and the sub board communication LSI 710 include dedicated controllers 611 and 711, setting registers 612 and 712, cache memories 613 and 713, AES (Advanced Encryption Standard) circuits 614 and 714, and a first UART ( Universal Asynchronous Receiver Transmitter (615, 715), 2nd UART 616, 716, 1st SPI (Serial Peripheral Interface) 617, 717, 2nd SPI (not shown), 1st to 4th Manchester circuits 618-621, 7th to 18th clocks 618-7 The reset control circuits 622 and 722 are included as components. These components are connected to each other via internal buses 623 and 723. The first UART 615, 715 and the first Manchester circuit 618, 718 are connected to each other, and the second UART 616, 716 and the second Manchester circuit 619, 719 are also connected to each other. Such main board communication LSI 610 and sub board communication LSI 710 are configured by, for example, an ASIC.

  The dedicated controllers 611 and 711 perform general control related to transmission and reception. For example, the dedicated controllers 611 and 711 function as a hardware timer, for example, and perform timeout processing during transmission / reception. The setting registers 612 and 712 are storage circuits having functions equivalent to those of the nonvolatile memory. The setting registers 612 and 712 store encryption keys used in AES circuits 614 and 714, which will be described later, setting data related to communication specifications, and the like. For example, data can be written into the setting registers 612 and 712 through a second SPI described later only once when the board is mounted. The cache memories 613 and 713 are mainly used as buffers. For example, data related to transmission / reception is temporarily stored in the cache memories 613 and 713. The clock / reset control circuits 622 and 722 generate a clock signal and a reset signal based on an input signal by an oscillator (OSC: Oscillator) or an external reset, and control transmission / reception timing and a reset operation.

  The AES circuits 614 and 714 perform data encryption and decryption by a common key block encryption method. The AES circuits 614 and 714 have a hardware configuration including a functional block based on an AES encryption algorithm and a functional block based on an AES decryption algorithm that is an inverse function of the AES encryption algorithm. The AES encryption algorithm encrypts plaintext data using a common key, and the AES decryption algorithm returns data encrypted using the same common key to the original plaintext data.

  Here, the AES encryption algorithm is a typical encryption algorithm of the common key encryption method, and the key length can be selected from 128 bits, 192 bits, and 256 bits, and the block length is, for example, 128 bits SPN ( This is a block cipher having a Substitution Permutation Network Structure) structure. Most block ciphers are repetitive ciphers that repeat the same round function in order to increase the implementation cost, and the SPN structure is a typical configuration method of repetitive ciphers. The block cipher is a kind of common key cipher and is a general term for ciphers that process fixed length data as a unit. Incidentally, ciphers that perform processing in bit units or byte units are called stream ciphers.

  FIG. 7 is a schematic diagram showing the configuration of the AES circuits 614 and 714. As shown in the figure, the AES circuits 614 and 714 are configured by functional blocks that repeatedly execute a matrix operation of a predetermined number of rounds in units of steps. Steps repeatedly executed by the AES circuits 614 and 714 include byte sub-steps 614A and 714A, row shift steps 614B and 714B, column mixing steps 614C and 714C, and round key addition steps 614D and 714D as final steps. The number of times that these steps are repeatedly executed (number of rounds) depends on the key length. The key length is 128 bits, the number of rounds is 11, the key length is 192 bits, the number of rounds is 13, the key length is 256 bits, and the number of rounds is 15. It has become. However, in any case, the column mixing steps 614C and 714C are not executed in the final round.

  In the byte sub-steps 614A and 714A, first, the input data having a fixed length is divided into, for example, 16 bytes having 4 rows and 4 columns, and each byte is replaced by an S box. The S box is a hardware-implemented basic function of the common key block cryptosystem, and provides a mechanism for breaking the correlation (linearity) between plaintext and ciphertext. The S box is excellent in resistance to differential cryptanalysis, and is excellent in preventing approximation by linear cryptanalysis.

  Next, in the row shift steps 614B and 714B, each row of the bytes composed of rows and columns is shifted in the row direction based on a predetermined algorithm. Such row shift steps 614B, 714B provide a mechanism to prevent different bytes in each row from interacting with corresponding bytes in other rows.

  Next, in the column mixing steps 614C and 714C, the byte of each column that has passed through the row shift steps 614B and 714B is multiplied by a matrix based on the Galois field operation. Such column mixing steps 614C, 714C provide a mechanism that allows each byte in each column to affect other bytes.

  Next, in round key addition steps 614D and 714D, the encryption key (public key) stored in the setting registers 612 and 712 is converted based on a predetermined algorithm, and the converted data is passed to the next round as a round key. It is. Then, in round key addition steps 614D and 714D, an exclusive OR is performed between the round key that is different for each round and each byte that has undergone column mixing steps 614C and 714C or row shift steps 614B and 714B. Note that the encryption key (public key) that is the original key with respect to the round key, the setting data related to the AES circuits 614 and 714, etc., for example, only once at the time of board mounting, are set registers 612 and 712 through the second SPI described later. Is written to.

  According to the AES circuits 614 and 714, the byte sub-steps 614A and 714A, the row shift steps 614B and 714B, the column mixing steps 614C and 714C, and the round key addition steps 614D and 714D are repeatedly executed for a predetermined number of rounds. As a result, encrypted data is output. The encrypted data is converted into the original plaintext data by an AES decryption algorithm opposite to the AES encryption algorithm by the AES circuits 614 and 714. As a result, data transmitted from the main board communication LSI 610 to the sub board communication LSI 710 becomes AES encrypted data and is difficult to be decrypted. That is, in the communication section between the main board communication LSI 610 and the sub board communication LSI 710, communication gotten can be sufficiently prevented by AES encryption.

  The first UARTs 615 and 715 are circuits that convert a serial signal based on the start-stop synchronization method into a parallel signal, or perform conversion in the opposite direction. In the first UARTs 615 and 715, a synchronous clock signal line for measuring transmission / reception timing is unnecessary. The first UARTs 615 and 715 have a function of detecting errors during transmission / reception (physical layer errors). The first UARTs 615 and 715 inform the dedicated controllers 611 and 711 that an error has occurred.

  As shown in FIG. 39, the error types include a parity error, an overrun error, and a framing error. A parity error occurs when there is an error in the parity bit of the received data. The overrun error occurs when the next data is received before the dedicated controllers 611 and 711 take out the data stored in the reception data buffer (cache memories 613 and 713). A framing error occurs when the stop bit is not received and is not a logical value of the stop bit.

  The second UARTs 616 and 716 have functions similar to those of the first UARTs 615 and 715, and description of common functions is omitted. The UART 601A and the UART 701A (see FIG. 6) built in the main CPU 601 and the sub CPU 701 also have the same functions as the first UARTs 615 and 715, and a description of the common functions is omitted.

  The first SPIs 617 and 717 are serial communication interface circuits based on a synchronous method. The first SPIs 617 and 717 can transmit and receive data at a higher speed than the asynchronous serial communication. A plurality of devices can be connected to the first SPIs 617 and 717. In the present embodiment, the first SPIs 617 and 717 are preliminarily provided as extended functions of the main board communication LSI 610 and the sub board communication LSI 710. Note that the second SPI (not shown) has the same function as the first SPIs 617 and 717, and a description of common functions is omitted. The second SPI of this embodiment is provided with a dedicated terminal used when writing an encryption key, setting data, and the like to the setting registers 612 and 712. That is, the second SPI is used as a connection circuit dedicated to a writing device such as an encryption key and setting data.

  The first Manchester circuits 618 and 718 are circuits that modulate (encode) and demodulate (decode) digital serial data in accordance with a binary phase-shift keying (BPSK) method. The first Manchester circuits 618 and 718 modulate serial data including an arbitrary bit string that does not include a relatively long string including “0” or “1” in succession, and the original bit string from the modulated serial data. Demodulate digital data consisting of The first Manchester circuits 618 and 718 can embed a clock rate used for modulation in the serial data. Basically, in the Manchester modulation system, a binary state composed of digital input values “1” and “0” is defined as a transition, and as a digital output value with respect to a rising edge and a falling edge of a signal input as serial data. Modulated serial data is generated by assigning logic levels of “0” and “1” or vice versa. At the time of demodulation, demodulation is performed in the reverse procedure of the modulation, and the logic level “0” and “1” as the digital input value, the rising edge and falling edge or the reverse of the signal to be output. The demodulated serial data is generated by forming the signal waveform.

  In this embodiment, as specifically shown in FIGS. 5 and 6, the first Manchester circuits 618 and 718 are paired with the first UARTs 615 and 715 and can transmit and receive data through the first UARTs 615 and 715. It is configured as follows. The second Manchester circuits 619 and 719, the third Manchester circuits 620 and 720, and the fourth Manchester circuits 621 and 721 have the same functions as the first Manchester circuits 618 and 718. Omitted. In this embodiment, the first Manchester circuits 618 and 718 are provided in the wired optical communication system (the main board communication LSI 610 and the sub board communication LSI 710). However, the Manchester circuit is generally suitable for wireless transmission. Therefore, a wireless communication system including a Manchester circuit may be constructed.

  The second Manchester circuits 619 and 719 are paired with the second UART 616 and 716, and are configured to transmit and receive data through the second UART 616 and 716. The third Manchester circuits 620 and 720 are provided for transmission / reception via the first SPIs 617 and 717, and are configured to transmit and receive data via the first SPIs 617 and 717. The fourth Manchester circuits 621 and 721 are provided as independent ones without being combined with other circuits, and are configured so that data can be transmitted and received by the fourth Manchester circuits 621 and 721 alone.

  In the present embodiment, as specifically shown in FIG. 8, the second Manchester circuit 619 of the main board communication LSI 610 mainly functions as a Manchester modulation circuit, while the second Manchester circuit 719 of the sub board communication LSI 710 is Mainly functions as a Manchester demodulation circuit. The second Manchester circuit 619 as a modulation circuit takes an exclusive OR of the synchronization clock signal 800c and the input serial data 800d, and as a result, generates and outputs the modulated serial data 800d '. The second Manchester circuit 719 as a demodulating circuit inputs an exclusive OR of the synchronization clock signal 800c and the modulated serial data 800d 'as an input, and as a result, the demodulated original serial data 800d is obtained. Generate and output. Such second Manchester circuits 619 and 719 can transmit and receive digital data at a relatively low cost.

  As schematically shown in FIG. 6, in the main board 6 </ b> A of the present embodiment, data (packet data) including a command from the main CPU 601 is supplied from the UART 601 </ b> A to the first UART 615, and a physical layer described later in the first UART 615. After error detection or the like is performed, the data is encrypted by AES 614, further supplied to second Manchester circuit 619 through second UART 616, and modulated by second Manchester circuit 619. The data modulated in this way is converted into serial data including a command, and is transmitted to the sub-board 7A through the optical link 630 and the optical fiber cable corresponding to the terminal portion of the optical fiber cable.

  In the sub board 7A, the serial data including the command transmitted from the main board 6A is supplied to the second Manchester circuit 719 through the optical link 730 corresponding to the optical fiber cable and its terminal part, and demodulated by the second Manchester circuit 719. Then, the sub CPU 701 can receive a command from the main CPU 601 by being supplied to the AES 714 through the second UART 716, further decrypted by the AES 714, and then supplied to the UART 701 A through the first UART 715.

  Also, as shown in FIG. 9, the data transmitted from the main CPU 601 to the main board communication LSI 610 is packet data composed of 8 bytes of plain text, and the communication speed (baud rate) at that time is 19200 bps. This conforms to the communication specifications between the main CPU 601 and the main board communication LSI 610, specifically, the communication specifications designed according to the processing specifications of the main CPU 601. Data transmitted from the main board communication LSI 610 to the sub board communication LSI 710 is 16-byte data that is Manchester-modulated and encrypted, and the communication speed at that time is 115200 bps. This conforms to the communication specifications between the main board communication LSI 610 and the sub board communication LSI 710, specifically, the communication specifications designed according to the processing specifications of the main board communication LSI 610 and the sub board communication LSI 710 and the sub CPU 701. It is. Data transmitted from the sub-board communication LSI 710 to the sub CPU 701 is 16-byte plaintext data subjected to Manchester demodulation and AES decoding, and the communication speed at that time is 115200 bps. This is based on communication specifications between the sub-board communication LSI 710 and the sub CPU 701, specifically, communication specifications designed according to the specifications of the sub CPU 701.

[Contents of communication data]
37 to 41 are explanatory diagrams showing the contents of communication data related to transmission / reception. Hereinafter, communication data will be described with reference to FIGS.

  As shown in FIG. 37, the external communication data transmitted from the main board communication LSI 610 to the sub board communication LSI 710 is composed of a 16-byte fixed-length data frame divided by D0 to D15 byte numbers (byte numbers). .

  A packet reception number is assigned to byte numbers D0 and D1 of the external communication data. The packet reception number can be assigned a value from 0 to 65535, and is added (incremented) when one packet is received or during timeout during reception. One packet reception means that data transmitted from the main CPU 601 in, for example, a 1-byte packet unit (transmission unit) is received. The time-out during reception means that a time-out has occurred in a situation in which only data less than 1 byte is received when one piece of data in a packet unit is 1 byte, for example.

  Packet data transmitted from the main CPU 601 is assigned to byte numbers D2 to D9 of the external communication data. The packet data corresponds to a command transmitted from the main CPU 601 to the sub CPU 701. The packet data is determined to have a fixed length of 8 bytes based on the communication specification.

  Communication information related to the main board communication LSI 610 is assigned to the byte numbers D10 and D11 of the external communication data. Specifically, a data size of packet data transmitted from the main board communication LSI 610 is assigned to the byte number D10. A main board communication LSI physical layer error or the like is assigned to the byte number D11 as a reception status (see FIG. 39). The main board communication LSI physical layer error is a hardware communication error that can be detected by the first UART 615 when the main board communication LSI 610 receives data supplied from the main CPU 601. For example, an overrun error shown in FIG. Framing error, parity error, etc. Since the data size of the packet data is a fixed length of 8 bytes based on the communication specification, a fixed value indicating 8 bytes is always assigned to the byte number D10.

  Communication information related to the sub-board communication LSI 710 is assigned to the byte numbers D12 and D13 of the external communication data. The byte numbers D12 and D13 are assigned a reception status or the like generated when data is received by the sub board communication LSI 710, as will be described later. Therefore, the byte numbers D12 and D13 in the external communication data are simply reserved as reserved areas, and a fixed value “0000H” is assigned as dummy data, for example.

  CRC data by cyclic redundancy check is assigned to byte numbers D14 and D15 of external communication data. The cyclic redundancy check is performed on the byte numbers D0 to D13.

  As shown in FIG. 38, the internal communication data transmitted from the sub-board communication LSI 710 to the sub CPU 701 basically consists of frames having the same structure as the communication data shown in FIG.

  The contents of the byte numbers D0 to D11 of the external communication data described above are copied and assigned as they are to the byte numbers D0 to D11 of the internal communication data.

  Communication information related to the sub-board communication LSI 710 is assigned to the byte numbers D12 and D13 of the internal communication data. More specifically, a sub board communication LSI physical layer error or the like is assigned to the byte number D12 as a reception status. The sub-board communication LSI physical layer error is a hardware communication error that can be detected by the second UART 716 when the sub-board communication LSI 710 receives data supplied from the main board communication LSI 610. For example, the over board shown in FIG. Run errors, framing errors, parity errors, etc. A logical error (to be described later) that can be detected when the sub board communication LSI 710 receives data supplied from the main board communication LSI 610 is assigned to the byte number D13 as a packet type.

  CRC data based on cyclic redundancy check is assigned to byte numbers D14 and D15 of internal communication data in the same manner as external communication data. The cyclic redundancy check is performed on the byte numbers D0 to D13.

  As shown in FIG. 39, the reception status has a format divided by numbers (bit numbers) in bit units of B0 to B7.

  An error count is assigned to the bit numbers B0 to B3 of the reception status. The error count indicates the total number of error occurrences related to parity, framing, and overrun, which is the total number of reception errors, and a value from 0 to 15 can be assigned.

  The bit number B4 of the reception status is assigned presence / absence of an overrun error as a physical layer error. For example, when there is an overrun error, “1” is assigned to the bit number B4, and when there is no overrun error, “0” is assigned to the bit number B4.

  The presence or absence of a framing error is assigned to the bit number B5 of the reception status as a physical layer error. For example, when there is a framing error, “1” is assigned to the bit number B5, and when there is no framing error, “0” is assigned to the bit number B5.

  The presence or absence of a parity error is assigned to the bit number B6 of the reception status as a physical layer error. For example, when there is a parity error, “1” is assigned to the bit number B6, and when there is no parity error, “0” is assigned to the bit number B6.

  The bit number B7 of the reception status is assigned presence / absence of timeout. For example, when timeout occurs, “1” is assigned to the bit number B7, and when timeout does not occur, “0” is assigned to the bit number B7.

  As shown in FIG. 40, the packet type is composed of a format divided by numbers (bit numbers) in bit units of B0 to B7.

  The type of logic error is assigned to the bit numbers B0 to B4 of the packet type. For example, bit numbers B0 to B4 are assigned a bit string of “00000” when there is no logic error, and are assigned a bit string of “00001” when there is a CRC error, and the main board communication LSI 610 receives from the main CPU 601. If the data is insufficient in size, a bit string “00010” is assigned, and if the data received by the sub board communication LSI 710 from the main board communication LSI 610 is insufficient in size, a bit string “00100” is assigned, and other logic errors occur. If there is, a bit string associated with the logic error is assigned. The CRC error assigned to the packet type bit numbers B0 to B4 can occur when the sub board communication LSI 710 receives data from the main board communication LSI 610. The lack of size when the main board communication LSI 610 receives data from the main CPU 601 occurs when a timeout occurs as the reception status of the main board communication LSI 610. Insufficient size when the sub board communication LSI 710 receives data from the main board communication LSI 610 occurs when a timeout occurs as the reception status of the sub board communication LSI 710.

  Communication classification is assigned to bit numbers B5 to B7 of the packet type. For example, the bit numbers B5 to B7 are assigned a bit string of “000” when corresponding to communication with the main control circuit 60 (main control communication), and are associated with the communication when corresponding to other communication. A bit string is assigned.

  As shown in FIG. 41A, the main CPU 601 transmits 8-byte fixed-length packet data P0 to P7 including a command to the main board communication LSI 610 as serial data. For example, the packet data P0 indicates data related to the command, the packet data P1 to P6 indicate parameter data corresponding to the command, and the packet data P7 is, for example, BCC (Block Check Character) as a checksum of the packet data P0 to P6. ). The main board communication LSI 610 checks the received packet data P0 to P7 for a physical layer error and the like, and further performs AES encryption on the data to which the reception result is added.

  As shown in FIG. 41B, when the main board communication LSI 610 receives the packet data P0 to P7 from the main CPU 601, the 16-byte fixed length external communication data D0 to D15 including the packet data P0 to P7 are used as serial data. Transmit to the sub-board communication LSI 710. At this time, the serial data transmitted from the main board communication LSI 610 carries external communication data D0 to D15 encrypted by the AES 614 and modulated by the second Manchester circuit 619 as a modulation circuit. The packet data P0 to P7 are arranged in, for example, D2 to D9 among the external communication data D0 to D15 (see FIG. 37).

  As shown in FIG. 41 (c), when the sub-board communication LSI 710 receives external communication data D0 to D15 as serial data from the main sub-board communication LSI 610, internal communication with variable length according to the external communication data D0 to D15. Data STX (Start of TeXt), DLE (Data Link Escape), and D0 to D15 are transmitted to the sub CPU 701 as serial data. At this time, the serial data transmitted from the sub-board communication LSI 710 carries the internal communication data D0 to D15 decoded by the AES 714 and demodulated by the second Manchester circuit 719 as a demodulation circuit. The packet data P0 to P7 from the main CPU 601 are arranged in, for example, D2 to D9 among the internal communication data D0 to D15 (see FIG. 38). D0 to D15 are transmitted as binary data in serial format, while STX and DLE are transmitted as control characters as described later.

  For example, if the data transmitted from the sub-board communication LSI 710 does not correspond to the control data (data corresponding to the received command, see FIG. 34) described later, only the control character “STX” indicating the start of the communication message is used. Are transmitted as internal communication data STX, D0 to D15. At this time, the minimum number of transmission bytes as the data transmission size is 17 bytes obtained by adding 1 byte of STX to 16 bytes of D0 to D15. On the other hand, when there is data corresponding to the control data in the data transmitted from the sub-board communication LSI 710, “STX” is added to the head and the block including the control data (in FIG. 41 (c), for example, byte number D12). Internal communication data STX, DLE, D0 to D15, to which “DLE” of the control character indicating that is added, are transmitted. As a result, assuming that the control data is included in all the blocks D0 to D15, the maximum number of transmission bytes as the data transmission size is theoretically 16 bytes of D0 to D15 and a maximum of 16 bytes of DLE corresponding thereto. And 1 byte of STX is 33 bytes. When the sub-board communication LSI 710 detects the control data in the data to be transmitted, the sub-board communication LSI 710 escapes the block with the corresponding byte number and adds DLE before the block. The escape process is executed by calculating an exclusive OR of the data of the corresponding block (byte number) and a predetermined value.

  As described above, the main CPU 601 realizes the first control processing means for performing a predetermined control process related to the game. The sub CPU 701 realizes a second control processing unit that performs specific control processing different from the first control processing unit in response to a command from the first control processing unit.

  The main board communication LSI 610 receives a command from the first control processing unit at the first communication speed, and transmits communication data including the command at a second communication speed different from the first communication speed. The first communication means is realized. The sub-board communication LSI 710 realizes a second communication unit that receives communication data from the first communication unit at the second communication speed and transmits the communication data to the second control processing unit.

  The dedicated controller 611 of the main board communication LSI 610 includes first reception wait time calculating means for calculating a first reception wait time for detecting a command for each predetermined transmission unit based on the first communication speed. The first receiving means for receiving the command while detecting the command based on the first reception waiting time for each predetermined transmission unit is realized. The dedicated controller 711 of the sub-board communication LSI 710 includes second reception waiting time calculating means for calculating a second reception waiting time for detecting communication data for each predetermined transmission unit based on the second communication speed, And a second receiving means for receiving communication data while detecting the communication data for each predetermined transmission unit based on the second reception waiting time.

  In addition, the dedicated controller 611 and the first UART 615 of the main board communication LSI 610 realize a first communication error detection unit that detects a first communication error when receiving a command. When the first communication error is detected, the dedicated controller 611 communicates the first error information generating means for generating the first error information related to the first communication error and the generated first error information together with the command. And a first transmission means for transmitting the communication data included in the data. The dedicated controller 711 and the second UART 716 of the sub-board communication LSI 710 realize second communication error detection means for detecting a second communication error when receiving communication data. The dedicated controller 711, when a second communication error is detected, a second error information generating unit that generates second error information related to the second communication error, and the generated second error information with the command and the second error information. And second transmission means for transmitting the communication data included in the communication data including 1 error information.

  Further, the sub CPU 701 and the UART 701A realize third communication error detection means for detecting a third communication error when receiving communication data. The sub CPU 701 executes a received data analysis process (see FIG. 29) described later, and generates a third error information for generating third error information related to the third communication error when a third communication error is detected. An information generating means and a communication error analyzing means for analyzing a communication error based on the communication data received from the second transmitting means and the third error information are realized.

  In the main board communication LSI 610, the AES circuit 614 realizes an encryption means for encrypting communication data by a predetermined encryption method, and the second Manchester circuit 619 is a communication data encrypted by the encryption means. Modulating means for modulating the signal by a two-phase phase shift keying method is realized. In the sub-board communication LSI 710, the second Manchester circuit 719 realizes demodulation means for demodulating the communication data modulated by the modulation means by the two-phase phase shift keying method, and the AES circuit 714 is demodulated by the demodulation means. Decrypting means for decrypting the communication data using a predetermined encryption method is realized.

  Next, the configuration of various tables and the like stored in the main ROM 602 will be described with reference to FIGS. The main ROM 602 stores a symbol arrangement table, a symbol code, a symbol combination table, a bonus operating table, an internal lottery table, and an internal winning combination determination table.

[Design arrangement table and design code]
As shown in FIG. 10 (a), the symbol arrangement table includes data (hereinafter referred to as symbol code (FIG. 10 (b)) that specifies the position of each symbol in the rotation direction of each reel and the type of symbol arranged at each position. ))).

  In the symbol arrangement table, when the reel index is detected, the symbol position existing in the middle stage (on the center line 8) in the display windows 4L, 4C, 4R is set to “0”, and the symbols are arranged in the order of advance in the reel rotation direction. “0” to “20” are assigned to the positions of symbols, respectively. Therefore, by managing how many symbols have been rotated since the reel index was detected and referring to the symbol arrangement table, the positions of symbols existing mainly in the middle of the display windows 4L, 4C, 4R and It is possible to always manage the type of the symbol.

[Design combination table]
In the present embodiment, when the symbol combination displayed by the reels 3L, 3C, 3R along the center line 8 serving as a winning determination line matches the symbol combination defined by the symbol combination table, The main CPU 601 determines that a prize has been won, and a privilege such as payout of medals, re-game operation, or bonus game operation is given to the player.

  As shown in FIG. 11, the symbol combination table defines a symbol combination, a display combination, and a payout number predetermined according to the type of privilege. The display combination is data for identifying a combination of symbols displayed along the winning determination line (center line 8).

  The display combination is represented as 1-byte data in which a unique symbol combination is assigned to each bit. For example, when the symbol “bell” of each reel 3L, 3C, 3R is displayed along the winning determination line (center line 8), “bell (00000010)” is determined as the display combination.

  Further, when a numerical value of 1 or more is determined as the payout number, medals are paid out. In this embodiment, when a cherry, bell, or watermelon is determined as a display combination, medals are paid out. The number of payouts is defined according to the number of inserted sheets. Basically, a larger number of paid-out sheets is determined when the number of inserted sheets is small.

  In addition, when replay is determined as the display combination, replaying is performed. When BB is determined as the display combination, the bonus is activated. In addition, when the symbol combination displayed along the winning determination line (center line 8) does not match any of the symbol combinations defined by the symbol combination table, it is a so-called “losing”.

[Bonus operating table]
As shown in FIG. 12, the bonus operation time table defines data to be stored in various storage areas provided in the main RAM 603 when the bonus operation is performed.

  The in-operation flag is data for identifying the type of bonus that is activated. In the present embodiment, BB (a combination continuous action device related to a first type special combination) and RB (a first type special combination) are provided as bonus types. The operation of RB is continuously performed while the operation of BB is performed.

  The operation of BB is ended when the medals that have reached the prescribed number are paid out. The operation of the RB is ended by either a game that reaches the specified number of times, a winning that reaches the specified number of times, or a case where the operation of the BB ends. The bonus end number counter, the possible game number counter, and the possible winning number counter are data for managing whether or not the specified number of times or the specified number of times as a trigger end timing of the bonus has been reached.

  More specifically, numerical values defined by the bonus operation time table are stored in the respective counters, and the subtraction is performed through the operation of the bonus. As a result, the operation of the corresponding bonus is completed on condition that the value of each counter is updated to “0”.

[Internal lottery table]
As shown in FIGS. 13 and 14, as the internal lottery table, an internal lottery table for a general gaming state and an internal lottery table for RB operation are provided. The internal lottery table defines a data pointer and a lottery value according to the winning number. The data pointer is data acquired as a result of lottery performed with reference to the internal lottery table, and is data for designating an internal winning combination defined by an internal winning combination determination table described later. The data pointer is provided with a small role / replay data pointer and a bonus data pointer.

  In the present embodiment, random numbers extracted from a predetermined numerical range “0 to 65535” are sequentially subtracted by lottery values corresponding to each winning number, and whether or not the result of subtraction has become negative (so-called An internal lottery is performed by determining whether or not a “digit” has occurred. Thereby, the larger the numerical value defined as the lottery value, the higher the probability that the data (that is, the data pointer) to which it is assigned will be determined. The winning probability of each winning number can be represented by “the lottery value corresponding to each winning number / the number of all random numbers that may be extracted (65536)”.

  In the present embodiment, a plurality of types of internal lottery tables (the internal lottery table for the general gaming state in FIG. 13 and the internal for RB operation in FIG. 14) according to the situation such as whether or not the bonus is being operated. By properly using the lottery table), the type of internal winning combination to be determined and the winning probability are changed, and as a result, the expectation held by the player is undulated.

[Internal winning combination determination table]
As shown in FIGS. 15 and 16, as the internal winning combination determination table, an internal winning combination determination table for bonus combination / replay and an internal winning combination determination table for bonus are provided. The internal winning combination determination table defines an internal winning combination in accordance with the data pointer. When the data pointer is determined, the internal winning combination is uniquely acquired.

  The internal winning combination is data for identifying a combination of symbols of each reel 3L, 3C, 3R that is permitted to be displayed along the winning determination line (center line 8). Like the display combination, the internal winning combination is represented as 1-byte data in which a unique symbol combination is assigned to each bit. When the data pointer is “0”, the content of the internal winning combination is “losing”, which indicates that display of any combination of symbols defined by the above-described symbol combination table is not permitted.

  As shown in FIG. 15, the internal winning combination determination table for a small combination / replay defines an internal winning combination relating to the payout of medals or an internal winning combination relating to the operation of replay. As shown in FIG. 16, the bonus internal winning combination determination table defines internal winning combinations related to the operation of the bonus.

  Next, the configuration of various storage areas provided in the main RAM 603 will be described with reference to FIGS. The main RAM 603 is provided with an internal winning combination storage area, a display combination storage area, a carryover combination storage area, and an operating flag storage area.

[Internal winning combination storage area]
As shown in FIG. 17, the internal winning combination storing area stores the internal winning combination represented by the above-mentioned 1-byte data. When the bit is set to “1”, display of the corresponding symbol combination is permitted. When all bits are “0”, the contents are lost. The main RAM 603 is provided with a display combination storage area in which the display combination described above is stored. The configuration of the display combination storing area is the same as the configuration of the internal winning combination storing area. When “1” is set in the bit, the corresponding symbol combination is displayed along the winning determination line (center line 8).

[Coverage storage area]
As shown in FIG. 18, the carryover combination storage area stores an internal winning combination related to the operation of the bonus as a result of the lottery described above. The internal winning combination (hereinafter referred to as the carryover combination) related to the operation of the bonus stored in the carryover combination storage area is not cleared until the corresponding symbol combination is displayed on the winning determination line (center line 8). It is the structure held by. And while the carryover combination is stored in the carryover combination storage area, it is stored in the internal winning combination storage area regardless of the result of the lottery described above.

[Operation flag storage area]

  As shown in FIG. 19, the operating flag storage area stores an operating flag consisting of 1 byte. The operating flag has a unique bonus assigned to each bit. When “1” is set in the bit, the corresponding bonus is activated. In the present embodiment, the state when all bits are “0” is defined as the general gaming state.

  Next, the contents of a program executed by the main CPU 601 of the main control circuit 60 will be described with reference to FIGS.

[Main flowchart by control of main CPU]
FIG. 20 shows a main flowchart under the control of the main CPU 601. As shown in FIG. 20, when the pachislot 1 is powered on, first, the main CPU 601 performs an initialization process (S1).

  Next, the main CPU 601 clears the designated storage area in the main RAM 603 (S2). For example, data stored in a storage area that needs to be erased for each game, such as an internal winning combination storage area or a display combination storage area, is cleared.

  Next, the main CPU 601 performs a medal acceptance / start check process described with reference to FIG. 21 (S3). In this process, the medal sensor and start switch input are checked.

  Next, the main CPU 601 extracts a random value and stores it in a random value storage area provided in the main RAM 603 (S4).

  Next, the main CPU 601 performs an internal lottery process described with reference to FIG. 22 (S5). In this process, the internal winning combination is determined by lottery based on a random value.

  Next, the main CPU 601 transmits a start command to the sub-control circuit 70 (S6). The start command includes a parameter for specifying an internal winning combination. The start command is supplied from the UART 601A in the main CPU 601 to the sub CPU 701 through the main board communication LSI 610 and the sub board communication LSI 710.

  Next, the main CPU 601 requests the start of rotation of all the reels 3L, 3C, 3R (S7). When the start of rotation of all the reels 3L, 3C, 3R is requested, the driving of the stepping motors 50L, 50C, 50R is controlled by an interrupt process (see FIG. 26) executed at a constant cycle (1.1173 msec). Then, rotation of each reel 3L, 3C, 3R is started.

  Next, the main CPU 601 performs a reel stop control process described with reference to FIG. 23 (S8). In this process, the input of the stop switches 7LS, 7CS, 7RS is checked, and the rotation of the reels 3L, 3C, 3R is stopped based on the timing when the stop buttons 17L, 17C, 17R are pressed and the internal winning combination. Is done.

  Next, the main CPU 601 searches for a combination of symbols displayed along the winning determination line (center line 8), and determines a payout number and the like based on the result (S9). As a result of the search, when the symbol combination displayed along the winning determination line (center line 8) matches the symbol combination defined by the symbol combination table, the corresponding display combination and the number of payouts are determined.

  Next, the main CPU 601 transmits a display command to the sub control circuit 70 (S10). The display command includes parameters that specify the display combination, the number of payouts, and the like. The display command is supplied from the UART 601A in the main CPU 601 to the sub CPU 701 through the main board communication LSI 610 and the sub board communication LSI 710.

  Next, the main CPU 601 performs medal payout processing (S11). Based on the determined payout number, the hopper device 34 is driven and the credit number is updated.

  Next, the main CPU 601 updates the bonus end number counter based on the payout number (S12). The numerical value determined as the payout number is subtracted from the bonus end number counter.

  Next, the main CPU 601 determines whether or not the bonus operating flag is on (S13). When determining that the bonus operating flag is on, the main CPU 601 performs a bonus end check process described with reference to FIG. 25 (S14). In the bonus end check process, it is checked whether or not to end the bonus operation with reference to various counters for managing the bonus end timing.

  The main CPU 601 performs a bonus operation check process described with reference to FIG. 24 after S14 or when it is determined in S13 that the bonus operating flag is not on (S15). In the bonus operation check process, it is checked whether or not the bonus operation is started. When this process ends, the main CPU 601 proceeds to S2.

[Medal reception / start check processing]
FIG. 21 shows medal acceptance / start check processing by the main CPU 601. As shown in FIG. 21, the main CPU 601 determines whether or not the automatic insertion counter is 0 (S31). When determining that the automatic insertion counter is 0, the main CPU 601 permits medal passage (S32). Thereby, the solenoid of the selector 51 is driven, and the passage of medals in the selector is prompted.

  When determining that the automatic insertion counter is not 0, the main CPU 601 copies the automatic insertion counter to the insertion number counter (S33). Next, the main CPU 601 clears the automatic insertion counter (S34). S33 and S34 are processes for replaying.

  After S32 or S34, the main CPU 601 sets 3 as the maximum value of the insertion number counter (S35). Next, the main CPU 601 determines whether or not the bonus operating flag is on (S36). When determining that the bonus operating flag is on, the main CPU 601 changes the maximum value of the insertion number counter (S37). For example, the maximum value is changed to 2.

  The main CPU 601 determines whether or not the passage of medals has been detected after S37 or when it is determined in S36 that the bonus operating flag is not on (S38). When determining that the passage of medals has been detected, the main CPU 601 determines whether or not the insertion number counter has reached the maximum value (S39). When determining that the inserted number counter has not reached the maximum value, the main CPU 601 increments the inserted number counter by 1 (S40).

  Next, the main CPU 601 stores 5 in the effective line counter (S41). Next, the main CPU 601 transmits a medal insertion command to the sub control circuit 70 (S42). The medal insertion command includes a parameter for specifying the number of inserted coins. The medal insertion command is supplied from the UART 601A in the main CPU 601 to the sub CPU 701 through the main board communication LSI 610 and the sub board communication LSI 710.

  When the main CPU 601 determines in S39 that the inserted number counter is the maximum value, the main CPU 601 adds 1 to the credit counter (S43). The main CPU 601 checks the bet switch 13S after S43, after S42, or when it is determined that the passage of medals is not detected in S38 (S44). As a result, the numerical value corresponding to the bet button 12 is added to the inserted number counter while being subtracted from the credit counter.

  Next, the main CPU 601 determines whether or not the insertion number counter has reached the maximum value (S45). When the main CPU 601 determines that the insertion number counter has not reached the maximum value, the main CPU 601 proceeds to S38, whereas when it determines that the insertion number counter has reached the maximum value, the main CPU 601 determines whether the start switch 6S is on. A determination is made (S46).

  When determining that the start switch 6S is not on, the main CPU 601 proceeds to S38, while when determining that the start switch 6S is on, the main CPU 601 prohibits medal passage (S47). The solenoid of the selector 51 is not driven, and medals are urged to be ejected. When this process ends, the main CPU 601 ends the medal acceptance / start check process.

[Internal lottery processing]
FIG. 22 shows an internal lottery process by the main CPU 601. As shown in FIG. 22, the main CPU 601 determines the internal lottery table and the number of lotteries (S61). Thus, the operating flag storage area is referred to, and the internal lottery table and the number of lotteries are determined according to whether or not the bonus is activated. The number of lotteries indicates the number of times of lottery value subtraction and determination of whether or not a digit has occurred for each winning number defined by the internal lottery table.

  Next, the main CPU 601 obtains a random value stored in the random value storage area and sets it as a determination random value (S62). Next, the main CPU 601 sets 1 as the initial value of the winning number (S63).

  Next, the main CPU 601 refers to the internal lottery table and acquires a lottery value corresponding to the winning number (S64). Next, the main CPU 601 subtracts the lottery value from the determination random number value (S65). Next, the main CPU 601 determines whether or not a digit has been made (S66). When the main CPU 601 determines that the digit is not set, the main CPU 601 subtracts 1 from the number of lotteries and adds 1 to the winning number (S67).

  Next, the main CPU 601 determines whether or not the number of lotteries is 0 (S68). When the main CPU 601 determines that the number of lotteries is not 0, the process proceeds to S64. On the other hand, when the number of lotteries is determined to be 0, the main CPU 601 sets 0 as a small role / replay data pointer and serves as a bonus data pointer. 0 is set (S69).

  When the main CPU 601 determines in S66 that a digit has been made, the main CPU 601 obtains the small role / replay data pointer and the bonus data pointer according to the current winning number (S70). After S70 or S69, the main CPU 601 refers to the small winning combination / replay internal winning combination determination table and acquires the internal winning combination based on the small winning combination / replay data pointer (S71).

  Next, the main CPU 601 stores the acquired internal winning combination in the internal winning combination storing area (S72). Next, the main CPU 601 determines whether or not the data stored in the carryover combination storage area is 0 (S73). When the main CPU 601 determines that the data stored in the carryover combination storage area is 0, the main CPU 601 refers to the bonus internal winning combination determination table and acquires the internal winning combination based on the bonus data pointer (S74). ). Next, the main CPU 601 stores the acquired internal winning combination in the carryover combination storing area (S75).

  After determining whether the data stored in the carryover combination storage area is not 0 after S75, the main CPU 601 takes a logical sum of the carryover combination storage area and the internal winning combination storage area, and the result Is stored in the internal winning combination storing area (S76). Thereby, the internal winning combination relating to the operation of the bonus is carried over. When this process ends, the main CPU 601 ends the internal lottery process.

[Reel stop control process]
FIG. 23 shows a reel stop control process by the main CPU 601. As shown in FIG. 23, the main CPU 601 determines whether or not an effective stop button 17L, 17C, or 17R has been pressed (S101). When the main CPU 601 determines that the effective stop buttons 17L, 17C, and 17R are not pressed, the main CPU 601 waits until it is pressed.

  When the main CPU 601 determines that the valid stop buttons 17L, 17C, and 17R are pressed, the main CPU 601 invalidates the operation of the corresponding stop buttons 17L, 17C, and 17R (S102). The valid and invalid states of the stop buttons 17L, 17C, and 17R are managed in a predetermined storage area provided in the main RAM 603.

  Next, the main CPU 601 sets 5 as the number of checks (S103). In this embodiment, since the maximum number of sliding frames is “4”, the position of the symbol in the middle of the corresponding display window 4L, 4C, 4R is included when the stop button 17L, 17C, 17R is pressed. From there, the check is performed up to the position of the symbol 4 frames ahead. That is, any of the five numerical values “0”, “1”, “2”, “3”, and “4” is determined as the number of sliding frames.

  Next, based on the internal winning combination, the main CPU 601 positions the symbols in the middle of the display windows 4L, 4C, 4R when the stop buttons 17L, 17C, 17R are pressed (hereinafter referred to as stop start positions). The position of the symbol with the highest priority is searched for among the positions of each symbol within the range of the number of checks including “S” (S104). In this process, the symbol position where the symbol combination that is permitted to be displayed by the internal winning combination can be displayed along the winning determination line (center line 8) is the symbol position with the highest priority. As determined.

  Next, the main CPU 601 determines the number of sliding frames based on the search result (S105). The number of symbols from the stop start position to the highest priority symbol position is determined as the number of sliding symbols. Next, the main CPU 601 proceeds to wait for a scheduled stop position (S106). When a transition is made to waiting for the scheduled stop position, the driving of the stepping motors 50L, 50C, 50R is controlled by an interrupt process described later, and the position of the symbol with the highest priority reaches the middle stage of the corresponding display window 4L, 4C, 4R. The rotation of the reels 3L, 3C, 3R is stopped after waiting.

  Next, the main CPU 601 transmits a reel stop command to the sub control circuit 70 (S107). The reel stop command includes a parameter for specifying the type of the stopped reel. The reel stop command is supplied from the UART 601A in the main CPU 601 to the sub CPU 701 through the main board communication LSI 610 and the sub board communication LSI 710.

  Next, the main CPU 601 determines whether or not there are stop buttons 17L, 17C, and 17R whose operations are valid (S108). That is, it is determined whether or not there are reels 3L, 3C, and 3R that are still rotating. When the main CPU 601 determines that there are stop buttons 17L, 17C, and 17R that are effective in operation, the main CPU 601 proceeds to S101, while when it determines that there are no stop buttons 17L, 17C, and 17R that are effective in operation, the reel stop control process. Exit.

[Bonus activation check process]
FIG. 24 shows a bonus operation check process by the main CPU 601. As shown in FIG. 24, the main CPU 601 determines whether or not the display combination is BB (S121). When the main CPU 601 determines that the display combination is BB, the main CPU 601 refers to the bonus operation time table and performs the BB operation processing (S122). In this process, the BB operating flag is turned on, and a predetermined value is set in the bonus end number counter.

  Next, the main CPU 601 clears the carryover combination storage area (S123). Next, the main CPU 601 transmits a bonus start command to the sub-control circuit (S124). The bonus start command is supplied from the UART 601A in the main CPU 601 to the sub CPU 701 through the main board communication LSI 610 and the sub board communication LSI 710. When this process ends, the main CPU 601 ends the bonus operation check process.

  When determining that the display combination is not BB in S121, the main CPU 601 determines whether or not the display combination is replay (S125). When determining that the display combination is replay, the main CPU 601 copies the value of the insertion number counter to the automatic insertion counter (S126).

  When determining that the display combination is not replay in S125, the main CPU 601 determines whether or not the BB operating flag is on (S127). When the main CPU 601 determines that the BB operating flag is not on, the main CPU 601 ends the bonus operation check process, whereas when the main CPU 601 determines that the BB operating flag is on, whether or not the RB operating flag is on. Is determined (S128).

  When the main CPU 601 determines that the RB operating flag is on, the main CPU 601 ends the bonus operation check process. On the other hand, if the main CPU 601 determines that the RB operating flag is not on, the main CPU 601 refers to the bonus operating time table. Time processing is performed (S129). In this process, the RB operating flag is turned on, and predetermined values are set in the winning possible number counter and the possible gaming number counter. When this process ends, the main CPU 601 ends the bonus operation check process.

[Bonus end check process]
FIG. 25 shows a bonus end check process by the main CPU 601. As shown in FIG. 25, the main CPU 601 determines whether or not the bonus end number counter is 0 (S141). When determining that the bonus end number counter is 0, the main CPU 601 performs BB end time processing (S142). In this process, the BB operating flag and the RB operating flag are turned off, and various counters for managing the end timing of the bonus are cleared. Next, the main CPU 601 transmits a bonus end command to the sub-control circuit 70 (S143). The bonus end command is supplied from the UART 601A in the main CPU 601 to the sub CPU 701 through the main board communication LSI 610 and the sub board communication LSI 710. When this process ends, the main CPU 601 ends the bonus end check process.

  When the main CPU 601 determines that the bonus end number counter is not 0 in S141, the main CPU 601 updates the winning possible number counter or the possible gaming number counter (S144). As a result, the game possible number counter is decremented by one, and when a prize has been won, the prize winning number counter is decremented by one. Next, the main CPU 601 determines whether or not the winning possible number counter or the possible gaming number counter is 0 (S145).

  When the main CPU 601 determines that the winning count counter or the possible gaming count counter is not 0, the main CPU 601 ends the bonus end check process, whereas when determining that the winning count counter or the possible gaming count counter is 0, Processing at the end of RB is performed (S146). In this process, the RB operating flag is turned off, and the winning possible number counter and the possible gaming number counter are cleared. When this process ends, the main CPU 601 ends the bonus end check process.

  Next, with reference to the flow charts shown in FIGS.

[Reception interrupt processing]
FIG. 27 shows reception interrupt processing by the sub CPU 701. As shown in FIG. 27, the sub CPU 701 obtains reception data supplied from the main control circuit 60 (main CPU 601) via the main board communication LSI 610 and the sub board communication LSI 710 (S181). At this time, the received data is received as serial data through the UART 701A in the sub CPU 701.

  Next, the sub CPU 701 determines whether or not the received data is “STX” (S182). When the sub CPU 701 determines that the received data is “STX”, the sub CPU 701 clears the received data buffer and the reception counter, sets the reception error flag to OFF (S183), and proceeds to S196 described later. The reception data buffer, reception counter, and reception error flag are secured in a predetermined area of the sub RAM 703. The reception data buffer is used for temporarily storing reception data. The reception counter is used, for example, for counting received data by 1 byte in units of blocks indicated by byte numbers. The reception error flag is used to identify whether there is an error during data reception.

  If it is determined in S182 that the received data is not “STX”, the sub CPU 701 determines whether or not the received data is “DLE” (S184). When the sub CPU 701 determines that the received data is “DLE”, the sub CPU 701 sets the escape processing flag to ON (S185), and proceeds to S196 described later. The escape process flag is secured in a predetermined area of the sub RAM 703. The escape processing flag is used to identify whether or not the escape processing needs to be executed.

  If it is determined in S184 that the received data is not “DLE”, the sub CPU 701 determines whether or not the escape processing flag is on (S186). If the sub CPU 701 determines that the escape process flag is on, the sub CPU 701 executes the escape process on the received data (S187), and then sets the escape process flag to off (S188).

  The sub CPU 701 stores the reception data and the reception status in a predetermined area of the sub RAM 703 after S188 or when it is determined that the escape processing flag is not on in S186 (S189). Next, the sub CPU 701 updates the reception counter by adding 1 (S190).

  Next, the sub CPU 701 sets a timeout timer (S191). The timeout timer is for determining the presence or absence of a communication error at the time of data reception based on the reception waiting time. In this embodiment, the timeout timer of the sub CPU 701 has a waiting time for receiving data of, for example, about 8 bytes that is longer than the waiting time of reception measured by timeout timers of the main board communication LSI 610 and the sub board communication LSI 710 described later. It is configured to be timed.

  Next, the sub CPU 701 determines whether or not the reception counter has counted 16 bytes (S192). When determining that the reception counter has counted 16 bytes, the sub CPU 701 clears the timeout timer (S193), and then proceeds to S194. If the sub CPU 701 determines that the reception counter has not counted 16 bytes, it proceeds to S196 described later.

  Next, the sub CPU 701 extracts data corresponding to the command portion and reception status data from the received data, and registers these data in the received data registration queue (S194). The reception data registration queue is secured in a predetermined area of the sub RAM 703.

  Next, the sub CPU 701 performs communication LSI reception data analysis processing described with reference to FIG. 29 (S195). According to this communication LSI received data analysis processing, a communication error between the main CPU 601 and the main board communication LSI 610, a communication error between the main board communication LSI 610 and the sub board communication LSI 710, and the sub board communication LSI 710 and the sub CPU 701 Various communication errors on all communication paths, such as communication errors between them, are specified. This communication LSI received data analysis processing will be described later.

  Next, the sub CPU 701 determines whether or not there is a physical layer error in the reception data supplied from the sub board communication LSI 710 (S196). The process of determining whether or not there is a physical layer error is mainly performed by the UART 701A built in the sub CPU 701. The physical layer error that can be detected at this time is not the reception status in the received data (the reception status relating to the main board communication LSI 610 and the sub board communication LSI 710 indicated by the byte numbers D11 and D12), but the sub CPU 701 has received the data. An overrun error, a framing error, a parity error, etc. detected by the UART 701A.

  If it is determined in S196 that there is a physical layer error in the received data, the sub CPU 701 sets a reception error flag to ON (S197). Thereafter, the sub CPU 701 ends the reception interrupt process. If it is determined that there is no physical layer error in the received data, the sub CPU 701 ends the reception interrupt process.

[Main board communication processing]
FIG. 28 shows main board communication processing by the sub CPU 701. As shown in FIG. 28, the sub CPU 701 determines whether a timeout has occurred (S201). A timeout occurs when 16 bytes of data are not received even after the waiting time counted by the timeout timer has elapsed.

  If it is determined in S201 that a timeout has occurred, the sub CPU 701 registers 'COM3 ERR2' in the error information history storage area 703d of the sub RAM 703 as corresponding error information (S202). On the other hand, if it is determined that a timeout has not occurred, the sub CPU 701 proceeds to S204 described later. Next, the sub CPU 701 clears the reception data buffer and the reception counter (S203), and proceeds to S201.

  Next, the sub CPU 701 acquires reception data (command data and reception status data) from the reception data registration queue (S204). Then, the sub CPU 701 determines whether there is received data in the received data registration queue (S205).

  If it is determined in S205 that there is received data in the received data registration queue, the sub CPU 701 proceeds to the next S206. On the other hand, if it is determined that there is no received data in the received data registration queue, the sub CPU 701 proceeds to S201.

  Next, the sub CPU 701 determines whether or not there is an error in the received data based on the content of the acquired reception status (S206). If it is determined that there is no error in the received data, the sub CPU 701 checks the range of command data (S207). That is, the sub CPU 701 confirms the data type of the command data. On the other hand, if it is determined that there is an error in the received data, the sub CPU 701 proceeds to S201.

  Next, the sub CPU 701 determines whether the command data is within a predetermined range (predetermined data type) (S208). If it is determined that the command data is within the predetermined range, the sub CPU 701 performs BCC check processing on the received data (S209). This BCC check process is performed based on whether or not the BCC recalculated as the checksum of the packet data P0 to P6 matches the BCC stored in the packet data P7. On the other hand, when determining that the command data is not within the predetermined range, the sub CPU 701 proceeds to S201.

  Next, the sub CPU 701 determines whether or not the BCC is normal as a result of the BCC check process (S210). When it is determined that the BCC is normal, the sub CPU 701 extracts the command type from the command data (S211). Examples of the command type include a start command, a display command, a medal insertion command, a reel stop command, a bonus start command, a bonus end command, and the like, as well as a non-operation command indicating a non-operation state. On the other hand, if it is determined that the BCC is not normal, the sub CPU 701 proceeds to S201.

  Next, the sub CPU 701 determines whether or not the command type is a no-operation command (S212). If it is determined that the command is other than the no-operation command, the sub CPU 701 determines whether a command different from the previous command is received as the current command (S213). On the other hand, if it is determined that the command is a no-operation command, the sub CPU 701 proceeds to S201.

  If it is determined in S213 that a command different from the previous command has been received as the current command, the sub CPU 701 registers the received command in the message queue (S214), and proceeds to S201. On the other hand, if it is determined that the same command as the previous command is received as the current command, the sub CPU 701 proceeds to S201 as it is.

[Communication LSI received data analysis processing]
FIG. 29 shows communication LSI received data analysis processing by the sub CPU 701. As shown in FIG. 29, the sub CPU 701 calculates a CRC by cyclic redundancy check for the data of the byte numbers D0 to D13 in the received data (S221).

  Next, the sub CPU 701 determines whether or not the calculated CRC is abnormal (S222). If it is determined that the CRC is abnormal, the sub CPU 701 registers 'COM3 ERR1' as the corresponding error information in the error information history storage area 703d of the sub RAM 703 and sets the reception error flag to ON (S223). On the other hand, if the CRC is determined to be normal, the sub CPU 701 proceeds to the next S224.

  Next, the sub CPU 701 acquires the main board communication LSI reception status from the received data (S224). Then, the sub CPU 701 determines whether or not there is a physical layer error in the main board communication LSI reception status (S225).

  If it is determined in S225 that there is a physical layer error in the main board communication LSI reception status, the sub CPU 701 registers 'COM1 ERR1' as the corresponding error information in the error information history storage area 703d of the sub RAM 703 and receives a reception error. The flag is set on (S226). On the other hand, if it is determined that there is no physical layer error, the sub CPU 701 proceeds to the next S227.

  Next, the sub CPU 701 acquires the sub board communication LSI reception status from the received data (S227). Then, the sub CPU 701 determines whether or not there is a physical layer error in the sub board communication LSI reception status (S228).

  If it is determined in S228 that there is a physical layer error in the sub-board communication LSI reception status, the sub CPU 701 registers 'COM2 ERR1' as the corresponding error information in the error information history storage area 703d of the sub RAM 703 and receives a reception error. The flag is set on (S229). On the other hand, if it is determined that there is no physical layer error, the sub CPU 701 proceeds to the next S230.

  Next, the sub CPU 701 acquires the sub board communication LSI packet type from the received data (S230). Then, the sub CPU 701 determines whether or not the main board communication LSI size is insufficient as the logic error type from the obtained sub board communication LSI packet type (S231).

  In S231, when it is determined that the main board communication LSI size is insufficient as the logic error type in the sub board communication LSI packet type, the sub CPU 701 uses the error information history storage area 703d of the sub RAM 703 as 'COM1 ERR2' as the corresponding error information. And the reception error flag is set to ON (S232). On the other hand, if it is determined that there is no shortage of the main board communication LSI size, the sub CPU 701 proceeds to the next S233.

  Next, the sub CPU 701 determines whether or not the sub board communication LSI size is insufficient as the logic error type from the obtained sub board communication LSI packet type (S233).

  If it is determined in S233 that the sub-board communication LSI packet type has a shortage of the sub-board communication LSI size as the logical error type, the sub CPU 701 uses the error information history storage area 703d of the sub RAM 703 as 'COM2 ERR2' as the corresponding error information. And the reception error flag is set to ON (S234). On the other hand, if it is determined that there is no shortage of the sub board communication LSI size, the sub CPU 701 proceeds to the next S235.

  Next, the sub CPU 701 determines whether there is a CRC error of the sub board communication LSI as a logic error type from the acquired sub board communication LSI packet type (S235).

  In S235, when it is determined that there is a CRC error of the sub board communication LSI as the logic error type in the sub board communication LSI packet type, the sub CPU 701 uses the error information history storage area of the sub RAM 703 as 'COM2 ERR3' as the corresponding error information. In addition, the reception error flag is set to ON (S236). Thereafter, the sub CPU 701 ends the communication LSI received data analysis process. On the other hand, when determining that there is no CRC error in the sub-board communication LSI, the sub CPU 701 ends the communication LSI reception data analysis processing.

[Production registration task performed by sub CPU]
FIG. 30 shows an effect registration task performed by the sub CPU 701. As shown in FIG. 30, the sub CPU 701 extracts a message from the message queue (S241). Next, the sub CPU 701 determines whether or not there is a message (S242). When the sub CPU 701 determines that there is a message, it copies the game information from the message (S243). For example, various data such as an internal winning combination, a type of reel that has stopped rotating, a display combination, an operating flag, and the like specified by the parameters are copied to a predetermined storage area provided in the sub RAM 703.

  Next, the sub CPU 701 performs an effect content determination process described with reference to FIG. 31 (S244). In this process, depending on the type of the received command, the contents of the effect are determined and the effect data is registered.

  The sub CPU 701 registers animation data after S244 or when it is determined that there is no message in S242 (S245). Next, the sub CPU 701 registers sound data (S246). Next, the sub CPU 701 registers lamp data (S247). The registration of the animation data, the registration of the sound data, and the registration of the ramp data are performed based on the effect data registered in the effect content determination process. When this process ends, the process proceeds to S241.

[Production content decision processing]
FIG. 31 shows effect content determination processing by the sub CPU 701. As shown in FIG. 31, the sub CPU 701 determines whether or not it is a start command reception (S261). When determining that the start command is received, the sub CPU 701 extracts the effect random number, determines the effect number by lottery based on the internal winning combination, etc., and registers it (S262). The production number is data for designating production contents to be executed this time.

  Next, the sub CPU 701 registers the start effect data based on the registered effect number (S263). The effect data is data specifying animation data, sound data, and lamp data. When the effect data is registered, corresponding animation data and the like are determined, and effects such as video display are executed. When this process ends, the sub CPU 701 ends the effect content determination process.

  Next, when determining that the start command is not received, the sub CPU 701 determines whether or not the reel stop command is received (S264). When the sub CPU 701 determines that it is time to receive the reel stop command, the sub CPU 701 registers the stop effect data based on the registered effect number and the type of the stop button (S265). When this process ends, the sub CPU 701 ends the effect content determination process.

  Next, when determining that the reel stop command is not received, the sub CPU 701 determines whether or not the display command is received (S266). When the sub CPU 701 determines that the display command is received, the sub CPU 701 registers the display effect data based on the registered effect number (S267). When this process ends, the sub CPU 701 ends the effect content determination process.

  Next, when determining that the display command is not received, the sub CPU sub CPU 701 determines whether or not the bonus start command is received (S268). When the sub CPU 701 determines that the bonus start command is received, the sub CPU 701 registers the bonus start effect data (S269). When this process ends, the sub CPU 701 ends the effect content determination process.

  Next, when determining that the bonus start command is not received, the sub CPU 701 determines whether or not the bonus end command is received (S270). When the sub CPU 701 determines that it is not at the time of receiving the bonus end command, the effect content determination process ends. On the other hand, if it is determined that the bonus end command has been received, the sub CPU 701 registers the bonus end effect data (S261). When this process ends, the sub CPU 701 ends the effect content determination process.

  As described above, according to the reception interrupt processing, main board communication processing, and communication LSI reception data analysis processing by the sub CPU 701, error information related to various types of communication is registered in the error information history storage area 703d of the sub RAM 703. The error information registered in the sub RAM 703 can be transmitted to a remote data management server such as a hall computer, and the cause of the error can be analyzed not only by a single pachislot machine but also by a hall computer.

  Next, the pachislot 1 when the staff uses the error information history will be described. The sub CPU 701 of the pachi-slot 1 employs two types of operation methods, a normal operation by a staff member and a simple operation, in order to display the error information history shown in FIG. 33 on the liquid crystal display device 10. When executing the normal operation, the clerk turns the door key 110 clockwise to release the lock mechanism of the front door 2b, turns on the setting key to turn on the setting key type switch, and the liquid crystal display area 10A. The menu screen shown in FIG. 32 is displayed. Then, when the clerk operates the operation key and selects the “error information history” item 100a, the error information history screen shown in FIG. 33 is displayed in the liquid crystal display area 10A. On the other hand, when executing a simple operation, the attendant resets the error by rotating the door key 110 counterclockwise when an error occurs or not playing, and holds the state for a predetermined time, for example, 5 seconds or more. As a result, the error information history screen shown in FIG. 33 is displayed in the liquid crystal display area 10A.

  When the sub CPU 701 detects an operation of selecting the “error information history” item 100a using the selection button 11A and the determination button 11B, the sub CPU 701 displays the error information history in the liquid crystal display area 10A as shown in FIG. . In the error information history, for example, as shown by hatching in the figure, as the COM error related to communication, the above-mentioned “COM1 ERR1 (COM1 error 1)”, “COM3 ERR2 (COM3 error 2)”, “COM2 ERR1 (COM2) Error 1) ”,“ COM2 ERR3 (COM2 error 3) ”, and the like may be included.

  When the sub CPU 701 detects an operation for selecting, for example, the “COM2 ERR3 (COM2 error 3)” item 100b using the selection button 11A and the determination button 11B, the sub CPU 701 generates transmission information based on the error information history. In addition, the transmission information can be transmitted to a hall computer or the like.

  Next, operations related to communication of the main board communication LSI 610 and the sub board communication LSI 710 will be described with reference to the flowcharts shown in FIGS.

[Main control sequence (Main board communication LSI)]
FIG. 44 shows a main control sequence by the main board communication LSI. As shown in FIG. 44, the dedicated controller 611 of the main board communication LSI 610 performs an initial setting process described with reference to FIG. 46 (S401). According to this initial setting process, various setting information relating to communication is set based on a predetermined communication specification. The initial setting process will be described later.

  Next, the dedicated controller 611 performs reception processing described with reference to FIG. 47 (S402). According to this reception process, data such as a command supplied from the main CPU 601 is received based on the communication specifications. This reception process will be described later.

  Next, the dedicated controller 611 determines whether there is a transmission request (S403). The presence / absence of such a transmission request is determined based on a transmission request flag described later. When it is determined that there is a transmission request, the dedicated controller 611 performs a transmission process described with reference to FIG. 48 (S404). Thereafter, the dedicated controller 611 proceeds to S402. On the other hand, when it is determined that there is no transmission request, the dedicated controller 611 proceeds to S402 without performing transmission processing. The transmission process will be described later.

[Reception interrupt processing (main board communication LSI)]
FIG. 45 shows reception interrupt processing by the main board communication LSI. As shown in FIG. 45, the dedicated controller 611 of the main board communication LSI 610 acquires the reception data supplied from the main CPU 601 via the UART 601A and the first UART 615 (S421).

  Next, the dedicated controller 611 determines whether or not the received data supplied from the main CPU 601 has a physical layer error (S422). The processing for determining whether or not there is a physical layer error is mainly performed by the first UART 615 built in the main board communication LSI 610. The physical layer error that can be detected at this time is an overrun error, a framing error, a parity error, or the like detected by the first UART 615.

  If it is determined in S422 that there is a physical layer error in the received data, the dedicated controller 611 sets the detected physical layer error in the main board communication LSI reception status (S423), and then proceeds to S424. As shown in FIG. 37, the main board communication LSI reception status is set in a block of byte number D11 of serial data transmitted from the main board communication LSI 610 to the sub board communication LSI 710. On the other hand, if it is determined that there is no physical layer error in the received data, the dedicated controller 611 moves to the subsequent S425.

  Next, the dedicated controller 611 updates the error count by adding 1 (S424). Such an error count is set in bit numbers B0 to B3 in the main board communication LSI reception status, and the total number of reception errors generated is indicated by the error count (see FIG. 39).

  Next, the dedicated controller 611 sequentially stores the reception data from the main CPU 601 in the transmission buffer (cache memory 613) (S425), and then updates the reception counter by adding 1 (S426). The reception counter is used to count data sent from the main CPU 601 with a data size of 8 bytes fixed length.

  Next, the dedicated controller 611 sets a timeout timer (S427), and ends this reception interrupt process. The timeout timer is for determining the presence or absence of a communication error at the time of data reception based on the reception waiting time. In the present embodiment, the timeout timer at the time of reception in the main board communication LSI 610 measures the waiting time during which at least 1 byte of data can be received in order to detect a communication error in packet units (transmission units). It is like that. Specifically, the timeout timer of the main board communication LSI 610 measures 2.5 msec based on a communication speed of 19,200 bps as a waiting time during which, for example, 48 bits (6 bytes) of data can be received. It is configured.

[Initial setting processing (main board communication LSI)]
FIG. 46 shows an initial setting process by the main board communication LSI. As shown in FIG. 46, the dedicated controller 611 of the main board communication LSI 610 performs initial setting for the first UART 615 (S441). Specifically, the dedicated controller 611 refers to the setting data based on the communication specifications and the like stored in advance in the setting register 612, sets the baud rate (communication speed related to transmission / reception) in the control register of the first UART 615, and data at the time of transmission / reception. Set length, parity, stop bit, etc. In this embodiment, for example, the communication speed with the main CPU 601 is set to 19200 bps, the data length is 8 bits, the parity is even parity, and the stop bit is 1 bit.

  Next, the dedicated controller 611 calculates a timeout value at the time of reception of the first UART 615 from the baud rate setting value of the communication speed related to reception (S442). Specifically, for example, when the baud rate setting value is 19200 bps and data for at least 48 bits is received, the dedicated controller 611 obtains 2.5 msec as a timeout value by 1 / baud rate × 48. The timeout value thus obtained is set in the timeout timer.

  Next, the dedicated controller 611 performs initial setting for the second UART 616 (S442), and ends this initial setting processing. Specifically, the dedicated controller 611 refers to the setting data based on the communication specifications and the like stored in advance in the setting register 612, sets the baud rate (communication speed related to reception), and data at the time of transmission / reception in the control register of the second UART 616. Set length, parity, stop bit, etc. In this embodiment, for example, the communication speed with the sub-board communication LSI 710 is set to 115200 bps, the data length is 8 bits, the parity is even parity, and the stop bit is 1 bit.

[Reception processing (main board communication LSI)]
FIG. 47 shows reception processing by the main board communication LSI. As shown in FIG. 47, the dedicated controller 611 of the main board communication LSI 610 determines whether a timeout has occurred using a timeout timer when acquiring received data from the main CPU 601 (S461).

  If it is determined in S461 that a timeout has not occurred, the dedicated controller 611 ends this reception process. On the other hand, when it is determined that a timeout has occurred, the dedicated controller 611 updates the packet reception number by adding 1 (S462).

  Next, the dedicated controller 611 determines whether or not the received data is less than 8 bytes (S463). When it is determined that the received data is less than 8 bytes, the dedicated controller 611 sets a timeout as error information in the main board communication LSI reception status (S464). As shown in FIG. 39, the time-out as error information is set with the bit of bit number B7 in the main board communication LSI reception status being “1”. On the other hand, when it is determined that the received data is not less than 8 bytes, that is, the received data is at least 8 bytes, the dedicated controller 611 proceeds to the next S465.

  Next, the dedicated controller 611 sets a transmission request flag (S465), and ends this reception process. The transmission request flag is secured in a predetermined area of the cache memory 613 and is used for identifying the presence / absence of data to be transmitted by the main board communication LSI 610.

[Transmission processing (main board communication LSI)]
FIG. 48 shows transmission processing by the main board communication LSI. As shown in FIG. 48, the dedicated controller 611 of the main board communication LSI 610 determines whether or not there is a data transmission request based on the transmission request flag, that is, whether or not there is received data including a command from the main CPU 601. A determination is made (S481).

  If it is determined in S481 that there is a data transmission request, the dedicated controller 611 sets the packet reception number in the transmission buffer (S482). The transmission buffer is secured in a predetermined area of the cache memory 613, and is used for temporarily storing communication data including commands supplied from the main CPU 601 to the sub CPU 701. On the other hand, when it is determined that there is no data transmission request, the dedicated controller 611 ends this transmission processing.

  Next, the dedicated controller 611 sets the reception data (packet data: data fixed length 8 bytes) from the main CPU 601 in the transmission buffer (S483). Subsequently, the dedicated controller 611 sets the main board communication LSI reception status in the transmission buffer (S484). The dedicated controller 611 sets dummy data in the transmission buffer (S485). Further, the dedicated controller 611 calculates the CRC by the cyclic redundancy check, and sets the CRC data as the calculation result in the transmission buffer (S486). As a result, external communication data (see FIG. 37) consisting of 16 bytes of byte numbers D0 to D15 is sequentially output from the transmission buffer 1 byte at a time as serial transmission data. The data transmitted from the main board communication LSI 610 to the sub board communication LSI 710 in this way is data having a fixed data length of 16 bytes, which is Manchester-modulated and AES encrypted in the main board communication LSI 610, and is based on the communication specifications. It is transmitted at 115200 bps.

  Next, the dedicated controller 611 determines whether or not 16 bytes of data have been transmitted (S487). When it is determined that 16 bytes of data are not transmitted, the dedicated controller 611 transmits the transmission data from the transmission port of the second UART 616 (S488), and then returns to S487 again. On the other hand, if it is determined that 16 bytes of data have been transmitted, the dedicated controller 611 clears the received data, the reception counter, and the transmission request flag (S489), and ends this transmission processing.

[Main control sequence (Sub-board communication LSI)]
FIG. 49 shows a main control sequence by the sub-board communication LSI. As shown in FIG. 49, the dedicated controller 711 of the sub-board communication LSI 710 performs an initial setting process described with reference to FIG. 51 (S501). According to this initial setting process, various setting information relating to communication is set based on a predetermined communication specification. The initial setting process will be described later.

  Next, the dedicated controller 711 performs a reception process described with reference to FIG. 52 (S502). According to this reception process, external communication data including a command and the like supplied from the main CPU 601 through the main board communication LSI 610 is received based on the communication specification. This reception process will be described later.

  Next, the dedicated controller 711 determines whether or not there is a transmission request (S503). The presence / absence of such a transmission request is determined based on a transmission request flag described later. When it is determined that there is a transmission request, the dedicated controller 711 performs a transmission process described with reference to FIG. 53 (S504). Thereafter, the dedicated controller 711 proceeds to S502. On the other hand, when it is determined that there is no transmission request, the dedicated controller 711 proceeds to S502 without performing transmission processing. The transmission process will be described later.

[Reception interrupt processing (sub-board communication LSI)]
FIG. 50 shows reception interrupt processing by the sub-board communication LSI. As shown in FIG. 50, the dedicated controller 711 of the sub-board communication LSI 710 acquires the reception data supplied from the main board communication LSI 610 via the second UART 716 (S521).

  Next, the dedicated controller 711 determines whether or not there is a physical layer error in the received data supplied from the main board communication LSI 610 (S522). The processing for determining whether or not there is a physical layer error is mainly performed by the second UART 716 built in the sub-board communication LSI 710. The physical layer error that can be detected at this time is an overrun error, a framing error, a parity error, or the like detected by the second UART 716.

  If it is determined in S522 that there is a physical layer error in the received data, the dedicated controller 711 sets the detected physical layer error to the sub-board communication LSI reception status (S523), and then proceeds to S524. As shown in FIG. 38, the sub-board communication LSI reception status is set in the block of the byte number D12 of serial data transmitted from the sub-board communication LSI 710 to the sub CPU 701. On the other hand, if it is determined that there is no physical layer error in the received data, the dedicated controller 711 moves to the subsequent S525.

  Next, the dedicated controller 711 updates the error count by adding 1 (S524). Such an error count is set to bit numbers B0 to B3 in the sub-board communication LSI reception status, and the total number of reception errors generated is indicated by the error count (see FIG. 39).

  Next, the dedicated controller 711 sequentially stores the received data from the main board communication LSI 610 in the transmission buffer (cache memory 713) (S525), and then updates the reception counter by adding 1 (S526). The reception counter is used to count data transmitted from the main board communication LSI 610 with a data size of 16 bytes fixed length.

  Next, the dedicated controller 711 sets a timeout timer (S527), and ends this reception interrupt process. Such a timeout timer of the sub-board communication LSI 710 also measures a waiting time during which at least 1 byte of data can be received in order to detect a communication error in packet units (transmission units). . Specifically, the timeout timer of the sub-board communication LSI 710 measures about 0.4 msec based on a communication speed of 115200 bps as a waiting time during which, for example, 48 bits (6 bytes) of data can be received. It is configured.

[Initial setting processing (sub-board communication LSI)]
FIG. 51 shows an initial setting process by the sub-board communication LSI. As shown in FIG. 51, the dedicated controller 711 of the sub-board communication LSI 710 performs initial setting for the first UART 715 (S541). Specifically, the dedicated controller 711 refers to the setting data based on the communication specifications and the like stored in advance in the setting register 712, sets the baud rate (communication speed related to transmission / reception) in the control register of the first UART 715, and data at the time of transmission / reception. Set length, parity, stop bit, etc. In this embodiment, for example, the communication speed with the sub CPU 701 is set to 115200 bps, the data length is 8 bits, the parity is even parity, and the stop bit is 1 bit.

  Next, the dedicated controller 711 performs initial setting for the second UART 716 (S542). Specifically, the dedicated controller 711 refers to the setting data based on the communication specifications and the like stored in advance in the setting register 712, sets the baud rate (communication speed related to reception) in the control register of the second UART 716, and data at the time of transmission / reception Set length, parity, stop bit, etc. In the present embodiment, for example, the communication speed with the main board communication LSI 610 is set to 115200 bps, the data length is 8 bits, the parity is even parity, and the stop bit is 1 bit.

  Next, the dedicated controller 711 calculates a timeout value at the time of reception of the second UART 716 from the baud rate setting value of the communication speed related to reception (S543), and ends this initial setting process. Specifically, for example, when the baud rate setting value is 115200 bps and data for at least 48 bits is received, the dedicated controller 711 obtains about 0.4 msec as a timeout value by 1 / baud rate × 48. The timeout value thus obtained is set in the timeout timer.

[Reception processing (sub-board communication LSI)]
FIG. 52 shows reception processing by the sub-board communication LSI. As shown in FIG. 52, the dedicated controller 711 of the sub-board communication LSI 710 determines whether a time-out has occurred using a time-out timer when acquiring the received data from the main board communication LSI 610 (S561).

  If it is determined in S561 that a timeout has not occurred, the dedicated controller 711 ends this reception process. On the other hand, when it is determined that a timeout has occurred, the dedicated controller 711 determines whether or not the received data is 16 bytes (S562).

  If it is determined in S562 that the received data is not 16 bytes, for example, less than 16 bytes, the dedicated controller 711 sets a timeout as error information in the sub-board communication LSI reception status (S563). As shown in FIG. 39, the time-out as error information is set with the bit of bit number B7 in the sub-board communication LSI reception status as “1”. On the other hand, if it is determined that the received data is 16 bytes, the dedicated controller 711 moves to the next S564.

  Next, the dedicated controller 711 calculates a CRC by cyclic redundancy check for the data of byte numbers D0 to D13 in the received data (S564).

  Next, the dedicated controller 711 determines whether or not the calculated CRC is normal (S565). If it is determined that the CRC is normal, the dedicated controller 711 proceeds to the subsequent S567. On the other hand, when it is determined that the CRC is abnormal, the dedicated controller 711 sets a CRC error as the logic error type in the sub-board communication LSI packet type (S566). As shown in FIG. 38, the sub board communication LSI packet type is set in a block of byte number D13 of serial data transmitted from the sub board communication LSI 710 to the sub CPU 701.

  Next, the dedicated controller 711 sets a transmission request flag (S567) and ends this reception process. The transmission request flag is secured in a predetermined area of the cache memory 713, and is used for identifying the presence / absence of data to be transmitted by the sub-board communication LSI 710.

[Transmission processing (sub-board communication LSI)]
FIG. 53 shows transmission processing by the sub-board communication LSI. As shown in FIG. 53, the dedicated controller 711 of the sub-board communication LSI 710 includes a command sent from the main CPU 601 through the main board communication LSI 610 based on a transmission request flag. It is determined whether there is received data (S581).

  If it is determined in S581 that there is a data transmission request, the dedicated controller 711 transmits the block of the byte numbers D0 to D11 in the received data (external communication data: data fixed length 16 bytes) from the main board communication LSI 610 to the transmission buffer. (S582). Subsequently, the dedicated controller 711 sets an error count in the sub-board communication LSI reception status (S583), and sets the sub-board communication LSI reception status as a block of the byte number D12 in the transmission buffer (S584).

  Also, the dedicated controller 711 sets the sub-board communication LSI packet type as a block of the byte number D13 in the transmission buffer (S585). Further, the dedicated controller 711 calculates CRC for the blocks of byte numbers D0 to D13 of the transmission buffer by cyclic redundancy check, and sets the CRC data as the calculation result in the transmission buffer (S586). As a result, internal communication data (see FIG. 38) consisting of 16 bytes of byte numbers D0 to D15 is temporarily stored in the transmission buffer as serial format transmission data.

  When the data (D0 to D15) to be transmitted to the transmission buffer is temporarily stored (standby) in this way, the dedicated controller 711 firstly corresponds to “STX” indicating the start of the communication message from the transmission port of the first UART 715. Is transmitted (S587).

  Then, the dedicated controller 711 determines whether 16-byte data (D0 to D15) has been transmitted (S588). When it is determined that 16 bytes of data (D0 to D15) have been transmitted, the dedicated controller 711 clears the reception data, the reception counter, and the transmission request flag (S593), and ends this transmission processing.

  On the other hand, if it is determined in S588 that 16-byte data (D0 to D15) has not been transmitted, the dedicated controller 711 indicates that the transmission data output from the transmission buffer at the current timing is “STX” or “DLE”. It is determined whether or not the same value is satisfied (S589).

  In S589, when it is determined that the transmission data corresponds to the same value as “STX” or “DLE”, the dedicated controller 711 corresponds to “DLE” indicating that the block includes control data from the transmission port of the first UART 715. Data is transmitted (S590), and the corresponding transmission data is escaped (S591). In the escape process, the data transmission order of the corresponding block and the next and subsequent blocks is decremented one by one. On the other hand, when it is determined that the transmission data does not correspond to the same value as “STX” or “DLE”, the dedicated controller 711 proceeds to the next S592 without performing transmission or escape processing of “DLE”.

  Next, the dedicated controller 711 transmits the transmission data (D0 to D15) set in the transmission buffer from the transmission port of the first UART 715 (S592), and then returns to S588 again. As a result, the internal communication data (see FIG. 38) including the byte numbers D0 to D15 is sequentially output from the transmission buffer 1 byte at a time as serial transmission data. The data transmitted from the sub-board communication LSI 710 to the sub CPU 701 in this way is the data demodulated by Manchester demodulation and AES decoding in the sub-board communication LSI 710, and further the blocks with byte numbers D0 to D15 in the sub-board communication LSI 710. The data is variable length 17 to 33 bytes including “STX” and “DLE”, and is transmitted at a communication speed of 115200 bps based on the communication specification.

  As described above, according to the pachislo 1 of the present embodiment, the following effects can be obtained.

  In this embodiment, various commands are transmitted as a fixed data length of 8 bytes from the main CPU 601 to the main board communication LSI 610, and external communication including commands as a larger fixed data length of 16 bytes from the main board communication LSI 610 to the sub board communication LSI 710. Data is transmitted, and further, internal communication data including a command as a variable data length of 17 to 33 bytes is transmitted from the sub-board communication LSI 710 to the sub CPU 701.

  As a result, the sub CPU 701 can receive internal communication data including information related to other communication errors as well as commands. That is, since the sub CPU 701 receives internal communication data having a larger reception data size than the case where only the command is received from the main CPU 601, it is possible to prevent the reception waiting time from being wasted, and as a result, from the main CPU 601. A bottleneck in communication with the sub CPU 701 can be eliminated.

  In addition, since the internal communication data received by the sub CPU 701 includes various types of information related to communication errors as information other than commands, the sub CPU 701 may execute processing related to the information based on information on communication errors. Can be operated efficiently.

  Further, the main board communication LSI 610 and the sub board communication LSI 710 can receive commands and communication data while detecting them in units of 1 byte transmission units, for example, while the sub CPU 701 is limited to such transmission units. The communication data can be received while being detected collectively for each larger amount of data such as 16 bytes. Thus, the main board communication LSI 610 and the sub board communication LSI 710 can periodically transmit and receive data efficiently, and the sub CPU 701 can efficiently receive communication data as a certain amount of data.

  In this embodiment, a command is transmitted from the main CPU 601 to the main board communication LSI 610 at a communication speed of 19200 bps (first communication speed), and a higher communication speed of 115200 bps (from the main board communication LSI 610 to the sub board communication LSI 710). Communication data including a command is transmitted at the second communication speed. Further, communication data including a command is transmitted from the sub board communication LSI 710 to the sub CPU 701 at a communication speed of 115200 bps (second communication speed).

  At this time, in main board communication LSI 610, the reception waiting time (first reception waiting time) for detecting the command for each 1 byte as a predetermined transmission unit is calculated as 2.5 msec based on the first communication speed. The command is received by detecting a command for each predetermined transmission unit based on the calculated first reception waiting time (2.5 msec). On the other hand, in the sub-board communication LSI 710, a reception waiting time (second reception waiting time) for detecting communication data including a command for each 1 byte as a predetermined transmission unit is about 0. 0 based on the second communication speed. It is calculated as 4 msec, and is received by detecting communication data for each predetermined transmission unit based on the calculated second reception waiting time (about 0.4 msec).

  That is, based on the first communication speed at which the main board communication LSI 610 receives a command based on the communication specification according to the relatively low-spec main CPU 601 and the communication specification according to the relatively high-spec sub CPU 701. Even if the second communication speed at which the sub-board communication LSI 710 receives communication data is set at a different speed, the first reception waiting time (2.5 msec) and the second reception suitable for each communication speed are set. A waiting time (about 0.4 msec) can be used.

  Thereby, in the sub CPU 701 that receives the communication data lastly, it is possible to eliminate as much as possible the dead time related to the reception waiting time when receiving the communication data, and to eliminate the communication bottleneck. The CPU 701 can be operated efficiently.

  Further, since the second reception waiting time (about 0.4 msec) in the sub board communication LSI 710 immediately before the communication data reaches the sub CPU 701 is shorter than the first reception waiting time (2.5 msec) in the main board communication LSI 610, Accordingly, the reception processing of communication data in the sub CPU 701 can be reduced.

  In addition, according to the present embodiment, the pachislot machine 1 includes the main CPU 601 that has a relatively low specification and a low communication speed, and the sub CPU 701 that has a relatively high specification and a high communication speed. A communication system can be realized.

  In this embodiment, a command is transmitted from the main CPU 601 to the main board communication LSI 610, communication data including the command is transmitted from the main board communication LSI 610 to the sub board communication LSI 710, and the sub board communication LSI 710 further transmits the sub CPU 701. Communication data including a command is transmitted to

  At this time, when the main board communication LSI 610 detects a shortage of size or a physical layer error (first communication error) upon reception of the command, the main board communication LSI reception status (first error information) indicating the data size or the main board communication LSI reception command is displayed. It is included in the communication data and transmitted together with the packet data corresponding to. Further, when the sub-board communication LSI 710 detects a logic error (second communication error) including a physical layer error or insufficient size when receiving the communication data from the main board communication LSI 610, the sub-board communication LSI reception status or The sub board communication LSI packet type (second error information) is included in the communication data together with the command (packet data) and the first error information and transmitted.

  Further, when the sub CPU 701 detects a CRC error or an error relating to timeout occurrence (third communication error) upon reception of communication data, error information indicating them is “COM3 ERR1”, “COM3 ERR2” (third error information). ). Also, the sub CPU 701 registers “COM1 ERR1” and “COM1 ERR2” (first error information) as error information related to the main board communication LSI 610 based on the communication data received from the sub board communication LSI 710, and the sub board communication LSI 710. 'COM2 ERR1', 'COM2 ERR2', and 'COM2 ERR3' (second error information) are registered as the error information related to.

  Thereby, the sub CPU 701 is based on 'COM1 ERR1', 'COM1 ERR2', 'COM2 ERR1', 'COM2 ERR2', 'COM2 ERR3', COM3 ERR1 ', and' COM3 ERR2 'which are registered as communication errors. The cause and location of communication errors can be identified and analyzed in detail.

  Further, the sub-board communication LSI 710 includes a command or the like as binary data in the communication data, and control characters such as STX indicating the start of transmission of the binary data and DLE indicating control data in the binary data are also included in the communication data. Then, the communication data is transmitted to the sub CPU 701. That is, commands are transmitted and received between the sub-board communication LSI 710 and the sub CPU 701 using binary data having a relatively small data size compared to text data that requires code conversion.

  Thereby, the sub CPU 701 can receive binary data having a relatively small size by detecting whether or not a predetermined amount of data has been acquired while detecting based on control characters such as STX and DLE. Therefore, the reception waiting time can be prevented from occurring as much as possible, and data communication can be efficiently performed between the sub board communication LSI 710 and the sub CPU 701. In this embodiment, the control character is included in the communication data and transmitted together with the binary data between the sub board communication LSI 710 and the sub CPU 701. For example, between the main board communication LSI 610 and the sub board communication LSI 710, A control character may be included in the communication data and transmitted together with the binary data.

  In the present embodiment, a command is transmitted from the main CPU 601 to the main board communication LSI 610, and communication data including the command is encrypted from the main board communication LSI 610 to the sub board communication LSI 710 by the AES encryption method. It is transmitted after being modulated by the modulation method. In the sub board communication LSI 710, the communication data received from the main board communication LSI 610 is demodulated by the Manchester modulation method, and the demodulated communication data is decrypted by the AES encryption method, and then transmitted to the sub CPU 701. Thereby, in this embodiment, communication data can be transmitted and received correctly and stably by the Manchester modulation method.

  In addition, since the clock rate can be embedded in the communication data exchanged by the Manchester modulation method, it is not necessary to separately provide a device or the like for generating a clock signal between the main board 6A and the sub board 7A. Therefore, it is possible to easily simplify the transmission path for communication as an optical fiber cable.

  Further, communication data can be transmitted and received as it is via the optical fiber cable without optically generating a clock signal between the main board 6A and the sub board 7A, and an inexpensive Manchester circuit is used as a digital data modulation circuit. Therefore, the main board 6A and the sub board 7A can be connected by an inexpensive device and transmission path.

  As other embodiment of this invention, a structure as shown to FIGS. 54-60 may be sufficient. In the following description, the same or similar components as those according to the above-described embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 54 shows a connection form between a main board and a sub board of a gaming machine according to another embodiment of the present invention. As shown in FIG. 54, in this embodiment, the third Manchester circuits 620 and 720 are used in combination with the first SPIs 617 and 717, and are configured to be able to transmit and receive data through the first SPIs 617 and 717. In the present embodiment, the third Manchester circuit 620 and the third Manchester circuit 720 are electrically connected to each other via a communication cable.

  In the main board 6A of the present embodiment, data (packet data) including a command from the main CPU 601 is supplied from the UART 601A to the first UART 615, and after the physical layer error is detected by the first UART 615, the AES 614 The encrypted data is further supplied to the third Manchester circuit 620 through the first SPI 617 serving as a master, and is modulated by the third Manchester circuit 620. The data modulated in this way is converted into serial data including a command, and is transmitted to the sub board 7A through the communication cable.

  In the sub board 7A, the serial data including the command transmitted from the main board 6A is supplied to the third Manchester circuit 720 through the communication cable, demodulated by the third Manchester circuit 720, and then the first SPI 717 serving as a slave. The sub CPU 701 can receive a command from the main CPU 601 by being supplied to the AES 714 through the first UART 715 and then being decrypted in the AES 714 and then supplied to the UART 701A.

  FIG. 55 shows a connection form between a main board and a sub board of a gaming machine according to another embodiment of the present invention. FIG. 56 is an explanatory diagram showing the flow of data in the connection form shown in FIG. In this embodiment, as shown in FIG. 55, the Manchester modulation and demodulation are not performed. More specifically, the second UARTs 616 and 716 are configured not to be used in combination with a Manchester circuit or the like but to be able to transmit and receive data independently.

  In the main board 6A of the present embodiment, data (packet data) including a command from the main CPU 601 is supplied from the UART 601A to the first UART 615, and after the physical layer error is detected by the first UART 615, the AES 614 The encrypted serial data including the command is transmitted to the sub-board 7A through the second UART 616.

  In the sub-board 7A, the serial data including the command transmitted from the main board 6A is supplied to the AES 714 through the sixth UART 716, and further decrypted in the AES 714, and then supplied to the UART 701A through the first UART 715. Can receive a command from the main CPU 601.

  Also, as shown in FIG. 56, the data transmitted from the main CPU 601 to the main board communication LSI 610 is packet data composed of 8 bytes of plain text, and the communication speed (baud rate) at that time is 19200 bps. Data transmitted from the main board communication LSI 610 to the sub board communication LSI 710 is encrypted 16-byte data, and the communication speed at that time is 115200 bps. Data transmitted from the sub-board communication LSI 710 to the sub CPU 701 is 16-byte plaintext data that has been AES-decrypted, and the communication speed at that time is 115200 bps.

  FIG. 57 shows a connection form between a main board and a sub board of a gaming machine according to another embodiment of the present invention. FIG. 58 is an explanatory diagram showing a data flow in the connection form shown in FIG. In the present embodiment, as shown in FIG. 57, AES encryption and decryption are not performed. Specifically, the main board communication LSI 610 and the sub board communication LSI 710 mainly use the fourth Manchester circuits 621 and 721, and are configured such that the fourth Manchester circuits 621 and 721 can transmit and receive data independently. ing.

  In the main board 6A of the present embodiment, data (packet data) including a command from the main CPU 601 is supplied from the UART 601A to the fourth Manchester circuit 621 and transmitted directly from the fourth Manchester circuit 621 to the sub board 7A. The

  In the sub board 7A, the data including the command transmitted from the main board 6A is directly taken in through the fourth Manchester circuit 721, and is supplied from the fourth Manchester circuit 721 to the UART 701A, whereby the sub CPU 701 has the main CPU 601. You can receive commands from.

  As shown in FIG. 58, the data transmitted from the main CPU 601 to the main board communication LSI 610 is packet data composed of 8 bytes of plain text, and the communication speed (baud rate) at that time is 19200 bps. Data transmitted from the main board communication LSI 610 to the sub board communication LSI 710 is 8 bytes of plaintext data modulated by Manchester modulation, and the communication speed at that time is 19200 bps. Data transmitted from the sub-board communication LSI 710 to the sub CPU 701 is 8-byte plaintext data demodulated by Manchester, and the communication speed at that time is 19200 bps.

  In the embodiment shown in FIGS. 57 and 58, a command is transmitted from the main CPU 601 to the main board communication LSI 610, and communication data including the command is modulated from the main board communication LSI 610 to the sub board communication LSI 710 by the Manchester modulation method. Sent directly above. In the sub board communication LSI 710, the communication data received from the main board communication LSI 610 is demodulated by the Manchester modulation method and then transmitted to the sub CPU 701 as it is. With such a configuration, communication data can be transmitted and received correctly and stably while quickly modulating and demodulating the data by the Manchester modulation method.

  FIG. 59 is a perspective view showing an appearance of a gaming machine (pachinko) according to another embodiment of the present invention. FIG. 60 is a block diagram showing a configuration of a main control circuit and a sub control circuit of the gaming machine shown in FIG. The present invention is also applicable to a pachinko 1 'as shown in FIG. As shown in FIG. 60, the pachinko machine 1 'includes special symbol display device 80, normal symbol display device 81, special symbol hold display device 82, and normal symbol hold display device as specific components connected to the main control circuit 60. 83, a count sensor 84, a general winning ball sensor 85, a passing ball sensor 86, a starting winning ball sensor 87, a normal electric accessory solenoid 88, a large winning opening solenoid 89, a backup clear switch 90, a payout / launch control circuit 350, a payout device 34A, a launching device 35B, a card unit 34C, a lending operation unit 34D, and the like. Also in such a pachinko machine 1 ′, the liquid crystal display device 10, the speakers 48 and 49, the lamp 20, and the like are connected to the sub control circuit 70. The main control circuit 60 and the sub control circuit 70 include a main board communication LSI 610 and a sub board communication LSI 710, and are connected to each other via the main board communication LSI 610 and the sub board communication LSI 710.

  In addition, this invention is not limited to each embodiment mentioned above.

  The numerical values related to the communication speed, the reception waiting time as the timeout value, the transmission unit, etc. exemplified in each embodiment are only given as an example, and these numerical values are according to the specifications of the CPU and the communication LSI. It can be changed as appropriate.

  The communication means is not limited to the communication LSI, and may be constituted by, for example, an IC according to the scale of the integrated circuit.

  The communication means is not limited to communication between the main control circuit and the sub control circuit, and may be provided as a unit that performs communication between the hall computer and the sub control circuit, for example.

1 pachislot machine
1 'Pachinko machine
6A Main control board (main board)
7A Sub control board (sub board)
60 Main control circuit 70 Sub control circuit 600 Microcomputer 601 Main CPU (first control processing means)
610 Main board communication LSI (first communication means)
611 dedicated controller (first reception waiting time calculating means, first receiving means, first communication error detecting means, first error information generating means, first transmitting means)
614 AES circuit (encryption means)
615 First UART (first communication error detecting means)
616 2nd UART
618 First Manchester circuit 619 Second Manchester circuit (modulation means)
620 Third Manchester circuit (modulation means)
621 Fourth Manchester circuit (modulation means)
701 Sub CPU (second control processing means, third communication error detection means, third error information generation means, communication error analysis means)
701A UART (third communication error detection means)
710 Sub-board communication LSI (second communication means)
711 Dedicated controller (second reception waiting time calculation means, second reception means, second communication error detection means, second error information generation means, second transmission means)
714 AES circuit (decoding means)
715 1st UART
716 Second UART (second communication error detecting means)
718 First Manchester circuit 719 Second Manchester circuit (demodulation means)
720 Third Manchester circuit (demodulation means)
721 Fourth Manchester circuit (demodulation means)

Claims (2)

First control means for performing predetermined control processing relating to the game;
In accordance with a command from the first control means, performs a specific control different from the first control means, a second control means having a higher specification than the first control means,
A gaming machine equipped with
First communication means for receiving the command from the first control means at a first communication speed and transmitting communication data including the command at a second communication speed higher than the first communication speed; ,
Second communication means for receiving the communication data from the first communication means at the second communication speed and transmitting the communication data to the second control means at the second communication speed;
With
The first communication means has modulation means for modulating the communication data by a two-phase phase shift keying method and transmitting the communication data to the second communication means,
The second communication means has demodulation means for demodulating the communication data modulated by the modulation means by the two-phase phase shift keying method and transmitting the communication data to the second control means. ,
The modulation means generates the communication data modulated by exclusive OR of a clock signal for synchronization and the communication data, and outputs the communication data to the second communication means,
The demodulator generates the communication data obtained by demodulating the communication data output from the first communication unit by exclusive OR of the synchronization clock signal and the modulated communication data. To the second control means,
The second control means includes
A communication error detected according to the reception time set based on the first communication speed and the second communication speed when the first communication means and the second communication means perform reception. Communication error detecting means for detecting upon reception of the communication data;
The communication data received by the second control means from the second communication means includes the command transmitted from the first control means, the first control means, and the first communication means. A game machine comprising communication error information generated between the first communication means and communication error information generated between the first communication means and the second communication means. The second communication means receives communication data having the same configuration as the communication data received by the second control means from the first communication means,
A predetermined fixed value is assigned to communication error information generated between the first communication means and the second communication means included in the communication data received from the first communication means. The gaming machine according to claim 1.

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