JP6159296B2 - Hall sensor and hall electromotive force detection method - Google Patents

Description

  The present invention relates to a Hall sensor and a Hall electromotive force detection method that constitute a magnetic sensor or the like that detects a magnetic variable using a Hall element.

  Conventionally, as a magnetic sensor semiconductor integrated circuit incorporating a Hall element, a current sensor that detects a magnetic field generated from a current, a rotation angle sensor that detects rotation of a magnet, a position sensor that detects the position of a magnet, and the like are known. (For example, Patent Document 1 and Non-Patent Documents 1 and 2). In the use of such a Hall element, the magnetic sensitivity of the Hall electromotive force signal output from the Hall element (Hole electromotive force output per unit magnetic field) or an offset error, or the amplification factor or offset of an amplifier that amplifies the Hall electromotive force signal. The error due to the above deteriorates the detection accuracy of the current amount, the magnet position, etc., and causes various problems.

For example, a current sensor is used to detect the amount of power charged / discharged from a battery, and the amount of power is calculated by integrating the current value read by the current sensor. However, when a magnetic sensitivity shift or an error due to an offset occurs in the current sensor, an accurate current value cannot be detected, and a large shift occurs in the calculation result of the electric energy.
For this reason, in the signal processing of the Hall element, many techniques for improving the magnetic field detection accuracy have been proposed. However, a magnetic field detection device with higher accuracy and higher resolution is required.

US Pat. No. 7,432,840

R S Popovic HALL EFFECT DEVICES Second Edition p.285-286 (ISBN-10: 0750308559 Inst of Physics Pub Inc (2003/12)) Mario Motz. ISSCC 2006 / SESSION 16 / MEMS AND SENSORS / 16.6

The above-described conventional technology cannot detect a magnetic field with high accuracy and high resolution.
An object of the present invention is to provide a Hall sensor and a Hall electromotive force detection method capable of detecting a magnetic field with high accuracy and high resolution.

  In order to achieve the above object, a Hall sensor according to an aspect of the present invention includes a Hall element, a drive unit that switches the energization direction of the Hall element to drive the Hall element, and a Hall electromotive force of the Hall element. A sampling non-execution period during which the first analog signal is not sampled and a sampling execution period during which the first analog signal is sampled, and the first analog signal sampled during the sampling execution period is converted into a digital signal. A discrete time AD converter; and a dynamic element matching unit that is provided in an analog signal path of the discrete time AD converter and performs dynamic element matching of the analog signal path during the sampling non-execution period.

The discrete time AD converter may be a discrete time ΔΣ modulator.
The discrete time AD converter may include a discrete time integrator, and the dynamic element matching unit may be provided at an input / output terminal of the discrete time integrator.
The discrete time AD converter includes a DA converter that converts the digital signal into a second analog signal, a buffer that buffers the second analog signal, and the buffered first analog signal. A subtracting section that performs subtraction with the second analog signal, and the dynamic element matching section may be provided at an input / output terminal of the buffer section.

The discrete time AD converter may be a discrete time integral AD converter.
The discrete time AD converter may include a discrete time integrator, and the dynamic element matching unit may be provided at an input / output terminal of the discrete time integrator.
The discrete time AD converter includes: a buffer unit that buffers a reference signal and outputs a second analog signal; a selection unit that selects one of the first analog signal and the second analog signal; A discrete-time integrator that integrates the signal selected by the selection unit, and the dynamic element matching unit may be provided at an input / output terminal of the buffer unit.

The dynamic element matching unit may be provided at an input / output terminal of the discrete-time integrator.
The analog signal path may be a differential signal path.
The sampling non-execution period may start in synchronization with the switching of the energization direction.
The sampling execution period may end in synchronization with the switching of the energization direction.

In order to achieve the above object, the Hall electromotive force detection method according to one aspect of the present invention switches the energization direction of the Hall element, and after switching the energization direction, the analog signal path of the discrete-time AD converter The dynamic element matching is performed in a sampling non-execution period in which the analog signal transmitted to the analog signal path is not sampled, and after performing the dynamic element matching, the analog signal corresponding to the Hall electromotive force of the Hall element is converted to the discrete time. A digital signal is converted by a type AD converter .

  According to the present invention, magnetic field detection with high accuracy and high resolution can be performed.

1 is a block diagram showing a schematic configuration of a hall sensor 1 according to a first embodiment of the present invention. It is a block diagram which shows schematic structure of the discrete time type AD converter 6 with which the Hall sensor 1 by the 1st Embodiment of this invention was equipped. It is a block diagram which shows schematic structure of SC integrator 62b with which the discrete time type AD converter 6 of the Hall sensor 1 by the 1st Embodiment of this invention was equipped. It is a figure which shows Hall element 2 with which Hall sensor 1 by a 1st embodiment of the present invention was equipped is modeled by bridge resistance. It is a figure explaining the Hall sensor 1 by the 1st Embodiment of this invention, Comprising: It is a figure which shows an example of the voltage signal waveform of Hall electromotive force at the time of switching the direction of the drive current sent through the Hall element. It is a figure which shows the signal waveform etc. inside the discrete time type AD converter 6 with which the Hall sensor 1 by the 1st Embodiment of this invention was equipped. It is a figure which shows a part of component provided in the discrete time type AD converter 6 of the Hall sensor 1 by the 1st Embodiment of this invention. It is a figure explaining the related technique of the Hall sensor 1 by the 1st Embodiment of this invention. It is a figure explaining the related technique of the Hall sensor 1 by the 1st Embodiment of this invention. It is a figure explaining the problem of the related technique of the Hall sensor 1 by the 1st Embodiment of this invention (the 1). It is a figure explaining the problem of the related technique of the Hall sensor 1 by the 1st Embodiment of this invention (the 2). It is a block diagram which shows schematic structure of the Hall sensor 1 by the modification of the 1st Embodiment of this invention. It is a block diagram which shows schematic structure of the discrete time type AD converter 6 with which the Hall sensor by the 2nd Embodiment of this invention was equipped. It is a figure which shows the internal structure of the 1-bit quantizer 62c with which the discrete time type AD converter 6 of the Hall sensor by the 2nd Embodiment of this invention was equipped. It is a block diagram which shows schematic structure of the discrete time type AD converter 6 with which the Hall sensor by the 3rd Embodiment of this invention was equipped. It is a figure which shows the signal waveform of each part of the discrete time type AD converter 6 with which the Hall sensor by the 3rd Embodiment of this invention was equipped.

[First Embodiment]
A Hall sensor and Hall electromotive force detection method according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a schematic configuration of the hall sensor 1 according to the present embodiment.
As shown in FIG. 1, the Hall sensor 1 includes a Hall element 2, a drive unit 3 that drives the Hall element 2 by switching the energization direction of the Hall element 2, and an amplifier that amplifies an analog signal output from the drive unit 3. 4. The Hall sensor 1 also includes a discrete-time analog-to-digital converter 6 (hereinafter referred to as “analog-to-digital conversion”) that converts analog input signals VIN (+) and VIN (−) input from the amplifier 4 into digital output signals. It may be referred to as “AD conversion”). Furthermore, the Hall sensor 1 includes a dynamic element matching unit 61 (hereinafter, dynamic element matching may be abbreviated as “DEM”) provided in the discrete time AD converter 6, a drive unit 3, and a discrete time AD. And a control signal generation unit 5 that generates various control signals to be input to the converter 6.

  The Hall element 2 is a semiconductor element that generates a potential gradient (Hall electromotive force) by the Hall effect in a direction orthogonal to the direction of the current flowing through the Hall element 2. The hall element 2 has first to fourth terminals 2a, 2b, 2c, and 2d. The first terminal 2a and the second terminal 2b output Hall electromotive force when the driving direction of the Hall element 2 is 0 °, and driving current input from the driving unit 3 when the driving direction of the Hall element 2 is 90 °. It is a terminal which supplies electricity. The third terminal 2c and the fourth terminal 2d pass a driving current input from the driving unit 3 when the driving direction of the Hall element 2 is 0 °, and the Hall electromotive force when the driving direction of the Hall element 2 is 90 °. Is a terminal that outputs.

  The drive unit 3 includes a power supply input terminal 33 to which a power supply voltage output from a drive power supply 35 (not shown in FIG. 1) is applied, and a reference potential input terminal 34 to which a reference potential (for example, a ground potential) is applied. doing. The drive unit 3 includes a drive current source 32 that generates a drive current to be passed through the Hall element 2 and a current direction changeover switch 31 that switches the direction of the drive current that is passed through the Hall element 2. The positive terminal of the drive current source 32 is connected to the negative terminal of the current direction changeover switch 31, and the negative terminal of the drive current source 32 is connected to the reference potential input terminal 34. The positive terminal of the current direction changeover switch 31 is connected to the power input terminal 33. The current direction changeover switch 31 has four input terminals, and the first to fourth terminals 2a, 2b, 2c, 2d of the Hall element 2 are connected to each input terminal. The current direction changeover switch 31 has two output terminals, and the non-inverting input terminal (+) and the inverting input terminal (−) of the amplifier 4 are connected to each output terminal.

  A current direction changeover switch 31 disposed immediately after the Hall element 2 is a circuit that performs spinning current (details will be described later). The current direction change-over switch 31 switches the energization direction of the drive current supplied between the first and terminals 2a and 2b and between the third and fourth terminals 2c and 2d of the Hall element 2 to offset from the Hall electromotive force signal. The components are separated. When the driving direction of the Hall element 2 is 0 °, the current direction changeover switch 31 connects the first terminal 2 a to the non-inverting input terminal (+) of the amplifier 4 and the second terminal 2 b to the inverting input terminal of the amplifier 4, for example. The third terminal 2 c is connected to the power input terminal 33 and the fourth terminal is connected to the drive current source 32. On the other hand, when the driving direction of the Hall element 2 is 90 °, the current direction changeover switch 31 connects the first terminal 2a to the driving current source 32, connects the second terminal 2b to the power input terminal 33, and The terminal 2 c is connected to the non-inverting input terminal (+) of the amplifier 4, and the fourth terminal is connected to the inverting input terminal (−) of the amplifier 4.

  A current direction switching signal Scs generated by the control signal generation unit 5 is input to the current direction switching switch 31. The current direction changeover switch 31 is, for example, one of the first terminals 2a and 2b and the second terminals 2c and 2d between the power input terminal 33 and the drive current source 32 based on the polarity of the input current direction change signal Scs. One is connected, and the other of the first terminals 2a, 2b and the second terminals 2c, 2d is connected to the non-inverting input terminal (+) and the inverting input terminal (−) of the amplifier 4.

  The amplifier 4 is connected to the current direction changeover switch 31. The amplifier 4 amplifies the Hall electromotive force signal output from the Hall element 2. Further, the amplifier 4 has a high-frequency cutoff characteristic with a cutoff frequency fc, and prevents aliasing noise that occurs when the discrete time AD converter 6 samples the first analog signal corresponding to the Hall electromotive force signal. It also functions as an anti-folding filter. In other words, the amplifier 4 is not only an amplification of the Hall electromotive force signal but also an anti-aliasing filter and amplifier that can also function as an anti-aliasing filter. The amplifier 4 is a differential amplifier, which receives a differential signal and outputs a differential signal. The differential signal output from the amplifier 4 is input to the discrete time AD converter 6 as input signals VIN (+) and VIN (−).

  The discrete time AD converter 6 is a circuit that samples an analog signal from the amplifier 4 according to the sample signal Ssp and outputs a digital signal. The discrete-time AD converter 6 performs a sampling pause period (an example of a sampling non-execution period) in which the first analog signal corresponding to the Hall electromotive force of the Hall element 2 is not sampled and a sampling execution for sampling the first analog signal. And a period. The discrete time AD converter 6 converts the first analog signal sampled during the sampling execution period into a digital signal. Although the details will be described later, the first analog signal corresponds to a signal obtained by subtracting the reference voltage signals Vref (+) and Vref (−) from the input signals VIN + and VIN−. The discrete time AD converter 6 includes an AD conversion unit 62 and a dynamic element matching unit 61.

A schematic configuration of the AD conversion unit 62 and the DEM unit 61 will be described with reference to FIG. FIG. 2 is a block diagram illustrating a schematic configuration of the AD conversion unit 62 and the DEM unit 61.
As shown in FIG. 2, the AD conversion unit 62 outputs the output signal from the subtractor 62a according to the polarity of the subtractor 62a and the sample signal Ssp input from the control signal generation unit 5 (not shown in FIG. 2). Based on the magnitude of the voltage value of the output signal from the SC integrator 62b in accordance with the switched capacitor (hereinafter sometimes abbreviated as “SC”) integrator 62b that performs the integration operation to integrate, and the sample signal Ssp. 1-bit quantizer (clocked comparator) 62c for updating the output of -1. The AD converter 62 integrates the digital output signals output from the 1-bit quantizer 62c and outputs a digital filter 62d that outputs an N-bit digital output signal and the digital output signal output from the 1-bit quantizer 62c. And a reference voltage signal Vref (+), Vref (−) (output from the DA conversion element 62e), and a digital-analog conversion (hereinafter, digital-analog conversion may be referred to as “DA conversion”) element 62e. The buffer amplifier 62f and the buffer amplifier 62g hold each voltage signal of an example of the second analog signal. The DA converter 62e corresponds to a DA converter that converts the digital output signal output from the 1-bit quantizer 62c into a second analog signal.

  The DEM unit 61 includes a DEM switch 61 a and a DEM switch 61 b that switch input / output connections according to the polarity of the DEM signal Sde input from the control signal generation unit 5. The DEM unit 61 is provided at the input / output terminals of the buffer amplifiers 62f and 62g. The DEM switch 61a is provided on the input side of the buffer amplifiers 62f and 62g, and the DEM switch 61b is provided on the output side of the buffer amplifiers 62f and 62g. The DEM switch 61a includes two input terminals to which the reference voltage signals Vref (+) and Vref (−) output from the DA conversion element 62e are input, and the input reference voltage signals Vref (+) and Vref (−) to a buffer amplifier. And two output terminals for outputting to 62f and 62g. The buffer amplifiers 62f and 62g correspond to a buffer unit that buffers the second analog signal. The DEM switch 61b subtracts two input terminals to which the reference voltage signals Vref (+) and Vref (−) output from the buffer amplifiers 62f and 62g are input, and the input reference voltage signals Vref (+) and Vref (−). And two output terminals for outputting to the device 62a. The DEM unit 61 is provided in an analog signal path 63 to which reference voltage signals Vref (+) and Vref (−) that are analog signals are transmitted. The analog signal path 63 includes a DA conversion element 62e, buffer amplifiers 62f and 62g, and a subtractor 62a.

  The subtractor 62a receives input signals VIN (+) and VIN (−) input from the amplifier 4, and a reference voltage signal Vref input from the DA conversion element 62e via the DEM switch 61a, buffer amplifiers 62f and 62g, and the DEM switch 61b. Subtraction with (+) and Vref (-) is performed. The subtractor 62a corresponds to a subtracting unit that performs subtraction between the first analog signal and the buffered second analog signal. More specifically, the subtractor 62a subtracts the difference signal between the reference voltage signal Vref (+) and the reference voltage signal Vref (−) from the difference signal between the input signal VIN (+) and the input signal VIN (−). The signal obtained in this manner is output to the SC integrator 62b.

  Each of the DEM switches 61a and 61b connects one input terminal and one output terminal and connects the other input terminal and the other output terminal in accordance with the polarity of the DEM signal Sde. And the other output terminal and the other input terminal and one output terminal are connected to each other. The DEM unit 61 performs dynamic element matching of the analog signal path 63 by switching the connection relationship between the input / output terminals of the DEM switches 61a and 61b. Dynamic element matching means that various elements constituting a circuit are sequentially replaced and used. The DEM unit 61 sequentially switches which of the buffer amplifiers 62f and 62g inputs the reference voltage signal Vref (+) to the subtractor 62a by switching the connection relationship between the input / output terminals of the DEM switches 61a and 61b. . Thus, the DEM unit 61 performs dynamic element matching of the analog signal path 63. Although details will be described later, the DEM unit 61 performs the dynamic element matching of the analog signal path 63 during the sampling pause time of the AD conversion unit 62.

Next, a schematic configuration of the SC integrator 62b will be described with reference to FIG. FIG. 3 is a circuit diagram showing a schematic configuration of the SC integrator 62b. 3 also shows a subtractor 62a connected to the SC integrator 62b, buffer amplifiers 62f and 62g, and a DEM unit 61 for easy understanding.
As shown in FIG. 3, the SC integrator 62b includes an SC circuit 601 to which the first analog signal output from the subtractor 62a is input, an operational amplifier 602 to which an output signal output from the SC circuit 601 is input, and an operational amplifier. And capacitive elements 603 and 604 connected between input and output terminals 602.

  The SC circuit 601 has a switch 601a to which the first analog signal output from one output terminal of the subtractor 62a is input, and a switch to which the first analog signal output from the other output terminal of the arithmetic unit 62a is input. 601a. The SC circuit 601 includes a capacitive element 601i that accumulates charges based on an output signal output from the switch 601a, and a capacitive element 601j that accumulates charges based on an output signal output from the switch 601c. doing. The SC circuit 601 has a switch 601f in which one terminal is connected between the output terminal of the switch 601a and one electrode of the capacitive element 601i, and the other terminal is connected to the reference potential input terminal. doing. Further, the SC circuit 601 includes a switch 601h in which one terminal is connected between the output terminal of the switch 601c and one electrode of the electrostatic capacitance element 601j, and the other terminal is connected to a reference potential. .

  In addition, the SC circuit 601 includes switches 601b and 601e each having one terminal connected to the other electrode of the capacitive element 601i, and each electrode connected to the other electrode of the capacitive element 601j. A switch 601d and a switch 601g. The other terminal of each of the switch 601b and the switch 601d is connected to an input terminal for a reference potential. The first analog signal output from the other electrode of the switch 601e is input to the non-inverting input terminal (+) of the operational amplifier 602. The first analog signal output from the other terminal of the switch 601g is input to the inverting input terminal (−) of the operational amplifier 602.

  The capacitance element 603 has one electrode connected to the non-inverting input terminal (+) of the operational amplifier 602 and the other electrode connected to the output terminal of the operational amplifier 602. The electrostatic capacitance element 604 has one electrode connected to the inverting input terminal (−) of the operational amplifier 602 and the other electrode connected to the output terminal of the operational amplifier 602. Capacitance elements 603 and 604 function as feedback capacitance elements.

  When the polarity of the sample signal Ssp is low, the switches 601a, 601b, 601c, 601d are closed, and the switches 601e, 601f, 601g, 601h are opened. As a result, charges corresponding to the voltage value of the input first analog signal are accumulated in the capacitive elements 601i and 601j. When the polarity of the sample signal Ssp is high, the switches 601a, 601b, 601c, and 601d are opened, and the switches 601e, 601f, 601g, and 601h are closed. Thereby, the charge accumulated in the capacitive element 601i is transferred to the non-inverting input terminal (+) of the operational amplifier 602, and the charge accumulated in the capacitive element 601j is transferred to the inverting input terminal ( -). The voltage value of the output signal output from the operational amplifier 602 is proportional to the amount of charge accumulated in the capacitive elements 603 and 603, and the switches 601a, 601b, 601c, 601d, 601e, 601f, 601g, and 601h are opened and closed. The integration operation is performed by repeating the operation.

  Returning to FIG. 1, the control signal generation unit 5 provided in the hall sensor 1 includes a current direction switching signal Scs for switching the direction in which the drive current flows in the drive unit 3, and an analog signal path 63 in the DEM unit 61. A DEM signal Sde for performing dynamic element matching and a sample signal Ssp for sampling the first analog signal in the AD converter 62 are generated. The control signal generation unit 5 generates these signals based on a command from a control unit (not shown), outputs the current direction switching signal Scs to the current direction switching switch 31 provided in the driving unit 3, and outputs the DEM signal Sde. The sample signal Ssp is output to the DEM unit 61, and the sample signal Ssp is output to the SC integrator 62b and the 1-bit quantizer 62c (see FIG. 2) provided in the AD conversion unit 62.

  The discrete time AD converter 6 includes a difference signal “VIN (+) − VIN (−)” of input signals VIN (+) and VIN (−) input from the amplifier 4, DEM switches 61a and 61b, and a buffer amplifier 62f. , 62g is compared with a difference signal “Vref (+) − Vref (−)” between the reference voltage signals Vref (+) and Vref (−) input from the DA conversion element 62e, and the analog voltage signal is converted into a digital output signal. It is a circuit to convert to. When the resolution of the discrete time AD converter 6 is N bits, the digital output signal after AD conversion is expressed by the following equation (1).

  When an offset voltage is generated in the buffer amplifiers 62f and 62g that hold the reference voltage signals Vref (+) and Vref (−), the digital output signal of the discrete-time AD converter 6 is a digital signal expressed by Expression (1). An error occurs with respect to the output signal. For example, assume that an offset voltage Voff occurs in the output signal of the buffer amplifier 62f. In FIG. 2, the offset voltage Voff is schematically indicated by a circle. The digital output signal after AD conversion when the offset voltage Voff occurs in the output signal of the buffer amplifier 62f is expressed by the following equation (2).

  As shown in Expression (2), when the offset voltage signal Voff occurs in the output signal of the buffer amplifier 62f, compared to the case where no offset voltage occurs in the output signal of the buffer amplifier 62f (see Expression (1)), An error is generated in the digital output signal after AD conversion by the offset voltage Voff. Therefore, the Hall sensor 1 according to the present embodiment includes DEM switches 61a and 61b as circuits for performing dynamic element matching of the analog signal path 63 provided with the buffer amplifiers 62f and 62g. Accordingly, the Hall sensor 1 can be used by switching the buffer amplifiers 62f and 62g by controlling the connection state of the input / output units of the buffer amplifiers 62f and 62g according to the polarity of the DEM signal Sde. The digital output signal when the polarity of the DEM signal Sde is high is expressed by the following equation (3).

The digital output signal when the polarity of the DEM signal Sde is at a low level is expressed by the following equation (4).

The digital filter 62d outputs a digital output signal obtained by averaging the digital output signal when the DEM signal Sde is at a high level and the digital output signal when the DEM signal Sde is at a low level. By averaging the digital output signals at the high and low levels of the DEM signal Sde, the term “−Voff / (Vref (+) − Vref (−))” in the second parentheses of equation (3); The term “+ Voff / (Vref (+) − Vref (−))” in the second parenthesis of the equation (4) cancels out. Thereby, the error due to the influence of the offset voltage Voff is removed from the digital output signal output from the digital filter 62d.
Thus, the Hall sensor 1 according to the present embodiment can remove the error due to the offset voltage generated in the Hall element 2 and the buffer amplifiers 62f and 62g from the digital output signal after AD conversion.

Next, the operation of the Hall sensor 1 and the Hall electromotive force detection method according to the present embodiment will be described with reference to FIGS. 4 to 11 with reference to FIGS. In addition to the operation of the Hall sensor 1 and the description of the Hall electromotive force detection method, problems of the conventional Hall sensor and Hall electromotive force detection method will be described.
As described with reference to FIGS. 1 to 3, the Hall sensor 1 according to the present embodiment is offset from the Hall electromotive force by alternately switching the direction of the drive current of the Hall element 2 between the 0 ° direction and the 90 ° direction. The Hall element 2 is driven by a method called a spinning current method for separating the two. When the drive unit 3 is controlled based on the polarity of the current direction switching signal Scs output from the control signal generation unit 5 to switch the energization direction of the Hall element 2 (an example of an energization direction switching step), the Hall element 2 generates a magnetic field. To detect. Then, the Hall element 2 generates Hall electromotive force in the direction orthogonal to the direction in which the drive current flows in the same plane due to the Hall effect.

  FIG. 4 shows a state in which the Hall element 2 is modeled by a bridge resistor. FIG. 4A shows a state in which a drive current is applied between the third and fourth terminals 2c and 2d, and FIG. 4B shows a drive current applied between the first and second terminals 2a and 2b. It shows a state of being energized. Hereinafter, the direction of the drive current flowing through the Hall element 2 in the state shown in FIG. 4A is referred to as 0 ° direction, and the direction of the drive current flowing through the Hall element 2 in the state shown in FIG. Call.

  As shown in FIG. 4, the Hall element 2 is modeled by, for example, a bridge resistor in which resistors R1 and R2 connected in series and resistors R3 and R4 connected in series are connected in parallel. In this bridge resistor, for example, the connection point between the resistors R2 and R4 is the first terminal 2a, the connection point between the resistors R1 and R3 is the second terminal 2b, and the connection point between the resistors R1 and R2 is the third terminal. 2c, and the connection point between the resistor R3 and the resistor R4 is the fourth terminal 2d.

  The Hall electromotive force is generated on the basis of a potential gradient, which is called the Hall effect, which is generated when electrons are subjected to Lorentz force by applying a magnetic field in a state where current is applied. Therefore, as shown in FIG. 4A, for example, the drive power source 35 is connected to the third terminal, the drive current source 32 is connected to the fourth terminal, and the drive current is directed from the third terminal 2c to the fourth terminal 2d. Is applied to the Hall element 2, a positive voltage Vh (+) is applied to the first terminal 2 a side when a magnetic field H directed from below to above is applied to the Hall element 2. The negative voltage Vh (−) is induced on the second terminal 2b side. On the other hand, as shown in FIG. 4B, for example, the drive power source 35 is connected to the second terminal, the drive current source 32 is connected to the first terminal, and the drive current from the second terminal 2b toward the first terminal 2a is reduced. When a magnetic field H directed from the bottom to the top of the drawing is applied to the Hall element 2 while flowing to the Hall element 2, a positive voltage Vh (+) is induced on the third terminal 2c side, and on the fourth terminal 2d side. A negative voltage Vh (−) is induced. The magnetic field strength can be measured from the potential difference “Vh (+) − Vh (−)” between the positive voltage Vh (+) and the negative voltage Vh (−) induced in the Hall element 2.

In the Hall element 2, an offset voltage is generated due to an imbalance of the bridge resistors R 1, R 2, R 3, and R 4, a change in resistance value due to package stress or mounting stress. For example, when the resistance value of the resistor R1 is different from the resistance values of the other resistors R2, R3, and R4, the Hall electromotive force output from the Hall element 2 is the potential difference “Vh (+) − Vh depending on the magnetic field strength of the magnetic field H. (−) ”Is added to the offset voltage Voff. The Hall sensor 1 according to the present embodiment can remove the offset voltage Voff generated in the Hall element 2 by using the spinning current method. That is, the Hall sensor 1 has a configuration in which the polarity of the offset voltage Voff can be inverted and output by switching the direction of the drive current flowing through the Hall element 2 between the 0 degree direction and the 90 degree direction. The Hall electromotive force obtained when the Hall element 2 is driven with a driving current in the 0 ° direction is Vh (0), and the Hall electromotive force obtained when the Hall element 2 is driven with the driving current in the 90 ° direction is Vh ( 90), and the offset voltage is Voff, the Hall electromotive forces Vh (0) and Vh (90) are expressed by the following equations (5) and (6).
Vh (0) = Vh (+) − Vh (−) − Voff (5)
Vh (90) = Vh (+) − Vh (−) + Voff (6)

  FIG. 5 is a diagram illustrating an example of a voltage signal waveform of the Hall electromotive force output from the drive unit 3 and input to the non-inverting input terminal (+) of the amplifier 4 when the direction of the drive current flowing through the Hall element 2 is switched. is there. The horizontal axis represents time (t), and the vertical axis represents the Hall electromotive force voltage [V]. Periods of the periods T1, T2, T3, and T4 are periods in which the polarity of the current direction switching signal Scs that controls the current direction switching switch 31 is inverted. That is, the period T1, T2, T3, T4 is a period in which the drive direction of the drive current supplied to the Hall element 2 is alternately switched between the 0 ° direction and the 90 ° direction. A period T1 and a period T3 indicate a period in which the Hall element 2 is driven in the direction of 0 °, and a period T2 and a period T4 indicate a period in which the Hall element 2 is driven in the direction of 90 °.

  As described with reference to FIG. 1, the current direction change-over switch 31 disposed immediately after the Hall element 2 is a switch for switching the direction of the drive current to be supplied to the Hall element 2 between the 0 ° direction and the 90 ° direction. . For this reason, the Hall element 2 is controlled so that the direction of the current flowing through the Hall element 2 is switched in synchronization with a certain period in which the polarity of the current direction switching signal Scs is inverted. As a result, as shown in FIG. 5, the voltage value of the Hall electromotive force output from the current direction changeover switch 31 and input to the non-inverting input terminal (+) of the amplifier 4 becomes Vh (0) in the periods T1 and T3. In the periods T2 and T4, Vh (90) is obtained.

  The Hall electromotive force Vh (0) in the periods T1 and T3 is “Vh (+) − Vh (−) − Voff”, and the Hall electromotive force Vh (90) in the periods T2 and T4 is “Vh (+). ) −Vh (−) + Voff ”. At this time, by providing a smoothing circuit (digital filter 62d in FIG. 2) in the subsequent stage of the circuit, the signal waveform is the voltage value of the Hall electromotive force Vh (0) in the periods T1 and T3 and the Hall value in the periods T2 and T4. It becomes an average value with the voltage value of the electromotive force Vh (90). For this reason, the voltage value of the smoothed signal voltage is an average value of the Hall electromotive force Vh (0) and the Hall electromotive force Vh (90), and “Vh (+) − Vh (−)” (= (( Vh (+) − Vh (−) − Voff) + (Vh (+) − Vh (−) + Voff)) / 2). Further, the signal waveform of the smoothed signal voltage is a straight waveform whose voltage value is “Vh (+) − Vh (−)”, as indicated by a broken line in FIG. The switching of the driving current direction of the Hall element 2 is controlled at a constant cycle. Therefore, the signal waveform has a negative offset voltage Voff that is generated when the Hall element 2 is driven in the direction of 0 °, and a positive waveform that is generated when the Hall element 2 is driven in the direction of 90 °. The waveform is offset from the offset voltage Voff. Therefore, only the output voltage value “Vh (+) − Vh (−)” depending on the magnetic field H can be finally obtained from the voltage value of the output signal of the Hall element 2 via the digital filter 62d. .

  The output signal output from the amplifier 4 including the offset voltage generated in the Hall element 2 is input to the discrete time AD converter 6 as input signals VIN (+) and VIN (−). In the discrete time AD converter 6, dynamic element matching is performed on an analog signal path in which the first analog signal based on the input signals VIN (+) and VIN (−) input to the discrete time AD converter 6 is transmitted. (An example of a dynamic element matching step). FIG. 6 is a diagram showing signal waveforms and the like inside the discrete time AD converter 6. In FIG. 6, “Scs” in the first stage indicates a signal waveform of the current direction switching signal, and “Sis” in the second stage indicates an inverting input from the input signal input to the non-inverting input terminal (+) of the amplifier 4. The signal waveform of the input difference signal obtained by subtracting the input signal input to the terminal (−) is shown, and “Sos” in the third stage indicates an output signal output from the positive output terminal (+) of the amplifier 4 (that is, the input signal VIN ( (+)) Shows the signal waveform of the output difference signal obtained by subtracting the output signal (that is, the input signal VIN (−)) output to the negative output terminal (−). In FIG. 6, “Sde” in the fourth stage indicates the signal waveform of the DEM signal Sde that controls the DEM unit 61, and “Ssk” in the fifth stage indicates a spike signal generated when the analog signal path 63 is dynamically elementized. The sixth waveform “Ssp” indicates the signal waveform of the sample signal. In particular, the vertical axis represents voltage and the horizontal axis represents time. Also, in FIG. 6, the passage of time is shown from left to right.

  As shown in the first stage in FIG. 6, the current direction switching signal Scs is a rectangular signal whose polarity is inverted at a predetermined cycle in order to alternately switch the driving current direction of the Hall element 2 between 0 ° and 90 °. It has a waveform. The period from time t0 to time t4 is a period for driving the Hall element 2 in the direction of 90 °, and the period from time t4 to time t7 is a period for driving the Hall element 2 in the direction of 0 °.

  As shown in the second stage in FIG. 6, the input difference signal Sis between the input signal input to the non-inverting input terminal (+) of the amplifier 4 and the input signal input to the inverting input terminal (−) The potential difference “Vh (+) − Vh (−)” depends on the positive offset signal Voff (indicated as “+ Voff” in FIG. 6) and the negative offset voltage Voff (in FIG. Voff ”) is a signal that is alternately superimposed according to the change in polarity of the current direction switching signal Scs. For this reason, as shown in the first and second stages in FIG. 6, when the driving direction of the Hall element 2 is switched from 0 ° to 90 ° at time t0, the input difference signal Sis is superimposed with a negative offset. Due to the change from the voltage Voff to the positive offset voltage Voff, the signal level changes from a relatively low state to a relatively high state. The rising time of the input difference signal Sis is delayed by a certain time with respect to the rising time of the current direction switching signal Scs by the time when the current direction changeover switch 31 is switched. As a result, the rising of the input difference signal Sis is completed at time t1.

  As shown in the third stage in FIG. 6, an output difference signal that is a difference signal between the output signal output from the positive output terminal (+) of the amplifier 4 and the output signal output from the negative output terminal (−). Sos is a signal waveform in which a positive offset voltage Voff and a negative offset voltage Voff are alternately superimposed on a potential difference “Vh (+) − Vh (−)” depending on the magnetic field intensity amplified by the amplifier 4. The output difference signal Sos is delayed from the input difference signal Sis by a fixed time due to the high-frequency cutoff characteristic of the amplifier 4 from the time when the drive current direction of the Hall element 2 is switched. The output difference signal Sos starts from time t0 and changes from a relatively low signal level to a relatively high state from time t3 to time t3.

As shown in the fourth stage in FIG. 6, the DEM signal Sde is set so that the polarity is inverted during the period from time t0 to time t3 until the signal level of the output difference signal Sos is stabilized. . The signal level of the output difference signal Sos changes from a relatively low state to a high state in a period between time t0 and time t3, for example. Further, for example, the signal level of the output difference signal Sos changes from a relatively high state to a low state in a period between time t4 and time t6. The switching operation of the buffer amplifiers 62f and 62g for inputting the reference voltage signals Vref (+) and Vref (−) is controlled according to the polarity of the DEM signal Sde.
Although details will be described later, as shown in the fifth stage in FIG. 6, spike signals Ssk generated at times t2 and t9 in accordance with the polarity inversion of the DEM signal Sde are output to the buffer amplifier 62f or the buffer amplifier 62g, respectively. mixing.

  As shown in the sixth stage in FIG. 6, the sample signal Ssp is output, for example, from time t3 to time t4 and from time t6 to time t7 after the output difference signal Sos converges to a constant value. In the present embodiment, before the output difference signal Sos of the amplifier 4 becomes a constant value, that is, between the time t0 and the time t3 and between the time t4 and the time t6, the DEM signal so that the spike signal Ssk is attenuated to the reference potential Vcom level. Sde input timing is set. Thereby, the Hall sensor 1 can prevent the spike signal Ssk generated by the dynamic element matching of the analog signal path 63 from being mixed into the digital signal after AD conversion (details will be described later). The sample signal Ssp is usually set so as to sample the Hall electromotive force at a period of 1 / fsamp. In order to wait for the offset signal of the Hall element 2 to settle, the sampling signal is adjusted to have a time to stop sampling the first analog signal for a certain time from the switching timing of the driving current direction. The time during which sampling is paused is called a sample pause time (an example of a sampling non-execution period). The time when the sampling of the first analog signal is not paused, that is, the time when the first analog signal is sampled is called a sampling execution period. In the present embodiment, the period from time t0 to time t3, the period from time t4 to time t6, and the period from time t7 to time t10 correspond to the sampling pause time. Further, the period from time t3 to time t4, the period from time t6 to time t7, and the period from time t10 to time t11 correspond to the sampling execution period. The sampling pause time starts in synchronization with switching of the energization direction to the Hall element 2 (for example, time t0, time t4, time t7, and time t11). Further, the sampling execution period ends in synchronization with switching of the energization direction to the Hall element 2 (for example, time t0, time t4, time t7, and time t11). The start timing of the sampling pause time coincides with the end timing of the sampling execution period.

  The Hall sensor 1 according to the present embodiment is in common with the invention disclosed in Patent Document 1 in that dynamic element matching is used. On the other hand, the Hall sensor 1 is different from the invention disclosed in Patent Document 1 in that a continuous-time ΔΣ AD converter is used in that it has a discrete-time AD converter 6 that is a discrete-time method. doing. When dynamic element matching is performed in a continuous-time ΔΣ AD converter, all spike signals associated with replacement of elements such as buffer amplifiers are integrated by an integrator. On the other hand, in the present embodiment, by using the discrete time AD converter 6, the voltage level of the spike signal is converged to a magnitude close to the reference potential (for example, 0 V) at the time of sampling the first analog signal. be able to. For this reason, the Hall sensor 1 can prevent an error due to the influence of the spike signal from occurring in the signal integrated by the SC integrator 62b.

  The sample period Ts (1 / fsamp) of the discrete-time AD converter 6 is an extremely short period of several hundred nanoseconds, and thus is insufficient as a time for completely converging the spike signal to the reference voltage level. Therefore, the Hall sensor 1 according to the present embodiment has a discrete-time AD converter 6 in the signal processing circuit of the Hall element 2, and the discrete-time AD converter 6 uses a buffer amplifier to provide a sample pause time that is a necessary configuration. 62f and 62g are assigned to the execution period of the exchange operation. Thereby, the Hall sensor 1 may have a configuration that can sufficiently ensure the settling time until the spike signal converges to the reference voltage level.

  It will be described that the sample pause time is an essential component when the discrete-time AD converter 6 converts the Hall electromotive force signal into a digital output. Unlike the continuous-time AD converter, the discrete-time AD converter 6 generates aliasing noise accompanying sampling of an analog signal. The aliasing noise becomes more significant as the high frequency noise is included in the analog signal to be sampled. In particular, the Hall element 2 is a sensor that detects a magnetic field, and is affected by high-frequency electromagnetic noise radiated by electronic equipment around the Hall element 2, and thus measures against aliasing noise are required. In order to prevent the aliasing noise, an anti-aliasing filter having a high-frequency cutoff characteristic is arranged in the preceding stage of the sampling circuit to reduce high frequency noise. The Hall sensor 1 according to the present embodiment has a configuration in which the amplifier 4 disposed in front of the discrete time AD converter 6 functions as the anti-folding filter.

  However, when this anti-folding filter is used in the signal processing of the Hall element, the output signal of the Hall element includes an offset signal having a magnitude equal to or larger than that of the Hall electromotive force signal. When the polarity of the offset signal is reversed in accordance with the switching of the drive current direction of the Hall element, a delay caused by the anti-aliasing filter occurs in the output signal of the Hall element. This causes a time during which the discrete time AD converter 6 cannot perform sampling until the offset signal converges to a constant value. The Hall sensor 1 according to the present embodiment performs the replacement operation of the buffer amplifiers 62f and 62g by using this sample pause time when the signal processing of the Hall element 2 is AD-converted by the discrete-time AD converter 6, and spikes are performed. The influence of the signal is reduced.

  In the present embodiment, the anti-aliasing filter, that is, the cutoff frequency fc of the amplifier 4 is preferably set to be equal to or lower than a frequency of 1 / (2 · fsamp) called a Nyquist frequency. The aliasing noise is a phenomenon in which noise is concentrated in a frequency band of ½ · fsamp or less by sampling a high-frequency noise component. If the cutoff frequency fc of the amplifier 4 is set to be equal to or lower than the Nyquist frequency, noise in a frequency band of 1/2 · fsamp or more is reduced before sampling, and the occurrence of aliasing noise can be suppressed to almost zero.

  Further, the settling time of the offset voltage signal required for the offset signal to converge to a constant value after passing through the anti-aliasing filter is generally 2.2τ (τ = 1 / (2πfc)), where fc is the cutoff frequency of the anti-aliasing filter. Defined by For this reason, the sample pause time of the discrete time AD converter 6 is preferably set to a time of 2.2τ (τ = 1 / (2πfc)) or more from the time of switching the drive current direction of the Hall element 2. .

  Here, the reason why the spike signal does not affect the signal integrated by the integrator when the dynamic element matching is performed in the Hall sensor 1 according to the present embodiment will be described with reference to FIG. FIG. 7 shows a switch capacitor circuit 601 provided on the input side of the SC integrator 62b, DEM switches 61a and 61b, buffer amplifiers 62f and 62g, among the components provided in the discrete time AD converter 6. Is shown. FIG. 7 illustrates the open / closed state of the switches 601a to 601h of the SC circuit 601 during the sample pause time of the SC integrator 62b in the discrete time AD converter 6.

  As shown in FIG. 7, the DEM switches 61a and 61b are connected to the signal wiring 65 for transmitting the DEM signal Sde connected to the DEM signal output terminal of the control signal generator 5 (not shown in FIG. 7). ing. A parasitic capacitance 64 is formed between the signal wiring 65 and the signal wiring 66 due to the capacitance of the DEM switches 61a and 61b and the buffer amplifier 62f and the capacitance formed between various signal wirings. The signal wiring 66 is a wiring included in the analog signal path 63. The signal wiring 66 is a wiring that connects the DEM switch 61a and the buffer amplifier 62f, and transmits the reference voltage signal Vref (+) or the reference voltage signal Vref (−). The charge Q is mixed into the buffer amplifier 62f through the parasitic capacitance 64 and the signal wiring 66 at the timing when the polarities of the signal wiring 65 and the DEM signal Sde are inverted. As a result, a spike-like spike signal Ssk is generated in the output signal of the buffer amplifier 62f.

As shown in FIG. 6, the Hall sensor 1 according to the present embodiment is adjusted so that the buffer amplifiers 62f and 62g are replaced during the sample pause time by dynamic element matching. During the sample pause time, the polarity of the sample signal Ssp is always low. For this reason, the switches 601a to 601d of the SC circuit 601 are closed, and the switches 601e to 601h are opened. When the switches 601e to 601h are in the open state, the SC circuit 601, the operational amplifier 602, and the capacitive elements 603 and 604 (see FIG. 3) are electrically disconnected. In addition, the sample pause time is secured for the Hall electromotive force signal to converge to a constant value from the switching of the drive current direction, but the voltage level of the spike signal generated by dynamic element matching is the reference. Sufficient time to converge to the potential level. For this reason, the spike signal generated due to the dynamic element matching is not mixed in the capacitance elements 603 and 604 that determine the voltage value of the output signal of the operational amplifier 602, and the Hall sensor 1 is executed in the analog signal path 63. It is possible to eliminate the influence of the spike signal that occurs with the dynamic element matching.
The Hall sensor 1 performs the dynamic element matching at a timing at which the influence of the spike signal generated when performing the dynamic element matching can be removed, and then performs the discrete time AD conversion of the analog signal corresponding to the Hall electromotive force of the Hall element 2 The digital signal is converted by the device 6 (an example of AD conversion step).

Next, problems of related technologies will be described with reference to FIGS.
When the AD converter is used, there is a problem that the detection accuracy of the signal to be measured is deteriorated due to an error factor of the AD converter itself. Patent Document 1 discloses a circuit technique for reducing an error of an AD converter for a continuous-time ΔΣ AD converter. In general, the ΔΣ AD converter has a configuration in which a plurality of DA conversion elements are provided inside the apparatus. When a mismatch occurs between the DA conversion elements, there is a problem that the linearity is impaired from the output signal of the AD converter. Patent Document 1 discloses using a technique called dynamic element matching (DEM) in which various elements constituting a circuit are sequentially replaced and used. Patent Document 1 discloses a high-accuracy continuous-time method that uses dynamic element matching and sequentially replaces DA conversion elements to eliminate the influence of variation between DA conversion elements and improve linearity. It is disclosed that a ΔΣ AD converter can be realized.

Further, it is known that the magnetic sensitivity of the Hall element changes with temperature and stress. Non-Patent Document 2 discloses a technique in which an analog signal from a hall element is converted into a digital value by a delta-sigma AD converter of a continuous time method, and fluctuations due to temperature and stress are corrected from the hall element signal by a digital unit operation. It is disclosed.
In order to improve the detection accuracy of the magnetic field, it is necessary to use the spinning current method as described above and an AD converter equipped with dynamic element matching. However, when dynamic element matching is performed by an AD converter, the spike signal described above is mixed into the AD converter via a parasitic capacitance, causing a problem of degrading the accuracy of magnetic field detection. Hereinafter, these problems will be described in detail.

  FIG. 8 is a schematic of a transconductance amplifier-capacitance (hereinafter abbreviated as “Gm-C”) integrator 7 of a continuous time ΔΣ AD converter provided in the Hall sensor of the related technology of the Hall sensor 1 according to the present embodiment. It is a block diagram which shows a structure. FIG. 8A shows a schematic configuration of the GM-C integrator 7, and FIG. 8B shows a circuit configuration of the Gm amplifier 71 b provided in the GM-C integrator 7.

  As shown in FIG. 8A, the Gm-C integrator 7 includes a DEM switch 71a that receives a signal output from a hall element (not shown) and a Gm amplifier 71b that receives a signal output from the DEM switch 71a. Have. The Gm-C integrator 7 includes a DEM switch 71c that switches an output signal output from the Gm amplifier 71b, and a Gm amplifier 71d that receives a signal output from the DEM switch 71c. Further, the Gm-C integrator 7 includes a capacitance element 71e connected between one input / output terminal of the Gm amplifier 71d and a capacitance element 71f connected between the other input / output terminal of the Gm amplifier 71d. And have.

  As illustrated in FIG. 8B, the Gm amplifier 71 b includes a transistor pair 710 and a current source 711 that generates a current flowing through the transistor pair 710. The Gm amplifier 71b is a voltage-current conversion element that converts the input signals VIN (+) and VIN (−) input to the Gm amplifier 71b into output currents I (+) and I (−). The Gm amplifier 71b outputs output currents I (+) and I (−) having current values corresponding to the voltage values of the input signals VIN (+) and VIN (−).

The output currents I (+) and I (−) output from the Gm amplifier 71b are charged into the capacitive elements 71e and 71f via the DEM switch 71c. The Gm amplifier 71d outputs output voltages VOUT (+) and −VOUT (−) having voltage values corresponding to the charge amounts charged in the capacitive elements 71e and 71f. The output currents I (+) and I (−) of the Gm amplifier 71b are normally 0 (A) when the input signals VIN (+) and VIN (−) are 0 (V). However, if a mismatch occurs due to factors such as manufacturing variations in the electrical characteristics of the transistors 710a and 710b constituting the transistor pair 710 included in the Gm amplifier 71b, the Gm amplifier 71b receives the input signal VIN (+), Even if VIN (−) is 0 (V), constant output currents I (+) and I (−) are output. This phenomenon is equivalent to the case where the offset voltage Voff1 is input to the input portion of the Gm amplifier 71b. In FIG. 8A, this offset voltage Voff1 is schematically represented by a broken circle mark between the DEM switch 71a and the Gm amplifier 71b.
In consideration of the offset voltage Voff1, the digital output signal output from the continuous-time ΔΣ AD converter is expressed by the following equation (7).

  As shown in the equation (7), the digital output signal considering the offset voltage Voff1 has an error corresponding to the voltage of the offset voltage Voff1 compared to the digital output signal not considering the offset voltage (see equation (1)). Occurs. In order to reduce the influence of the offset voltage Voff1, the continuous-time ΔΣ AD converter shown in FIG. 8 has transistors 710a and 710b for inputting input signals VIN (+) and VIN (−) to the input / output stage of the Gm amplifier 71b. Has an input signal changeover switch 71a. Further, the continuous-time ΔΣ converter has a DEM switch 71c that re-inverts the polarity of the output of the Gm amplifier 71b that is inverted when the transistors 710a and 710b are switched. The input signal changeover switch 71a and the DEM switch 71c are controlled based on the polarity of the DEM signal Sde.

  The input signals VIN (+) and VIN (−) input to the Gm-C integrator 7 are switched twice in total, once each by the DEM switch 71a and the DEM switch 71c before being input to the Gm amplifier 71d. For this reason, the input signals VIN (+) and VIN (−) are demodulated and input to the non-inverting input terminal (+) and the inverting input terminal (−) of the Gm amplifier 71d, respectively. On the other hand, the offset voltage Voff1 is switched only once by the DEM switch 71c before being input to the Gm amplifier 71d. Therefore, the offset voltage Voff1 whose polarity is inverted based on the polarity inversion of the DEM signal Sde is alternately input to the non-inverting input terminal (+) and the inverting input terminal (−) of the Gm amplifier 71d.

  FIG. 9 is a diagram illustrating a signal waveform of the Gm-C integrator 7. “Sde” shown in the upper part of FIG. 9 indicates the signal waveform of the DEM signal, and “Sis” shown in the lower part indicates the signal waveform of the input signal input to the non-inverting input terminal (+) of the Gm amplifier 71d. Yes. In FIG. 9, the upper vertical axis indicates voltage, the lower vertical axis indicates current, and the horizontal axis indicates time. The passage of time is shown from left to right in FIG.

式（８）に示すように、連続時間型ΔΣＡＤ変換器が出力するデジタル出力信号からオフセット電圧Ｖｏｆｆ１に起因する誤差は除去される。
連続時間型ΔΣＡＤ変換器がダイナミックエレメントマッチング機能を備えていてもＧｍアンプに生じるオフセット電圧の影響が完全に除去されるのは寄生容量などが生じていない理想的な場合である。ここで、ダイナミックエレメントマッチング機能を備えたＧｍ−Ｃ積分器の出力信号の誤差の要因となる寄生容量を考慮した場合について説明する。図１０は、寄生容量を考慮した場合の連続時間型ΔΣＡＤ変換器のＧｍ−Ｃ積分器７の概略構成を示すブロック図である。 As shown in FIG. 9, when the polarity of the DEM signal Sde is inverted, the polarity of the input signal input to the Gm amplifier 71d is also inverted. When the polarity of the DEM signal Sde is high, the current level of the input signal is high. When the polarity of the DEM signal Sde is low, the current level of the input signal is low. The current value when the input signal is high is Voff1 · Gm, and the current value when the input signal is low is −Voff1 · Gm. Here, “Voff1” represents the voltage value of the offset voltage Voff1, and “Gm” represents the transconductance of the Gm amplifier 71b. The absolute value of the high-level current value and the low-level current value of the input signal input to the Gm amplifier 71d is the same. When the input signals VIN (+) and VIN (−) input to the transistors 710a and 710b in the Gm amplifier 71b are switched by switching the input / output connection states of the DEM switch 71a and the DEM switch 71c, the output of the Gm 71d A positive offset voltage Voff1 and a negative offset voltage Voff1 are mixed in the signal alternately. A digital output signal of a 1-bit quantizer (not shown) to which the output signal of the Gm amplifier 71d is input is obtained by converting the output signal of the Gm amplifier 71d into a digital output signal. For this reason, the positive offset voltage Voff1 and the negative offset voltage Voff1 are alternately mixed in the digital output signal of the continuous-time ΔΣ AD converter. The digital output signal output from the 1-bit quantizer is averaged by a digital filter (not shown) provided after the 1-bit quantizer. If the reference signals output from the DA conversion element (not shown) are Vref (+) and Vref (−), the digital output signal output from the continuous-time ΔΣ AD converter can be expressed by the following equation (8). .

As shown in Expression (8), the error due to the offset voltage Voff1 is removed from the digital output signal output from the continuous-time ΔΣ AD converter.
Even if the continuous-time ΔΣ AD converter has a dynamic element matching function, the effect of the offset voltage generated in the Gm amplifier is completely removed in an ideal case where no parasitic capacitance is generated. Here, a case where a parasitic capacitance that causes an error in the output signal of the Gm-C integrator having the dynamic element matching function is considered will be described. FIG. 10 is a block diagram showing a schematic configuration of the Gm-C integrator 7 of the continuous time ΔΣ AD converter in consideration of the parasitic capacitance.

  As shown in FIG. 10, there is a parasitic between the signal wiring 72 to which the DEM signal Sde is transmitted and the signal wiring 73 at the input portion of the Gm amplifier 71b due to the capacitance of the DEM switch 71b and the capacitance generated between the signal wirings 72 and 73. A capacity 75 exists. For this reason, charges + Q and -Q are mixed into the Gm-C integrator 7 via the parasitic capacitance 75 at the timing when the polarity of the DEM signal Sde is inverted, and spike noise is generated.

  FIG. 11 is a diagram illustrating a signal waveform of the Gm-C integrator 7 when the parasitic capacitance 75 is considered. “Sde” shown in the upper part of FIG. 11 shows the signal waveform of the DEM signal, “Ssk1” shown in the middle part shows the signal waveform of the spike signal input to the Gm amplifier 71b, and “Ssk2” shown in the lower part shows the Gm amplifier. The signal waveform of the spike signal input to 71d is shown. The vertical axis represents voltage, and the horizontal axis represents time. The passage of time is shown from left to right in FIG.

As shown in FIG. 11, a spike-like spike signal Ssk1 is generated at the timing when the polarity of the DEM signal Sde is inverted. The spike signal Ssk1 rises or falls steeply and then converges to the original voltage level. When the voltage level of the DEM signal Sde is switched from a low level to a high level, a spike signal that rises sharply is generated. On the other hand, when the voltage level of the DEM signal Sde is switched from a high level to a low level, a spike signal that falls sharply is generated. The spike signal that rises sharply on the positive electrode side and the spike signal that falls sharply on the negative electrode side are alternately generated at the input portion of the Gm amplifier 71b. When the output signal of the Gm amplifier 71b is inverted by the DEM switch 71e, the spike signal Ssk2 generated on the input side of the Gm amplifier 71b is a Gm amplifier as a spike signal having the same polarity as shown in the lower part of FIG. 71d. The spike signal Ssk2 is averaged by the digital filter, but since it has the same polarity, it remains as the offset voltage Voff2 even after averaging. In this case, the digital output signal output from the continuous time ΔΣ AD converter can be expressed by the following equation (9).

  Even if the effect of the offset voltage Voff1 due to the mismatch between the transistors 710a and 710b in the Gm amplifier 71b is reduced by dynamic element matching, a new offset voltage Voff2 due to the spike signal is generated in the continuous-time ΔΣ AD converter. . The Hall electromotive force signal that depends on the magnetic field output from the Hall element is a weak voltage of about several μV to several mV. For this reason, the error of the digital output signal caused by the offset voltage Voff2 caused by the spike signal becomes a magnitude that cannot be ignored.

In recent years, in the technical field of magnetic field detection devices using Hall elements, high-precision and high-resolution magnetic field detection devices have been required. The inventors of the present application discovered that a new offset voltage is generated due to the spike signal described above, and found that this hinders high accuracy of the magnetic field detection device.
Since it is difficult to prevent the spike signal from being generated, as a result of intensive studies, the inventors of the present application employ a discrete time AD converter, and the first analog corresponding to the Hall electromotive force of the Hall element. By performing dynamic element matching of the analog signal path where the first analog signal is transmitted during the sampling non-execution period when the signal is not sampled, the influence of the spike signal is reduced, and a highly accurate and high resolution Hall sensor is produced. Successful.

(Modification)
Next, a hall sensor 1 according to a modification of the present embodiment will be described with reference to FIG. The Hall sensor 1 according to this modification is characterized in that a modulation switch 11 and a demodulation switch 9 are provided between the amplifier 4 and the discrete time AD converter 6. Only the differences from the Hall sensor 1 shown in FIG. 1 will be described below. Moreover, the same code | symbol is attached | subjected to the component which show | plays the same effect | action and function as the Hall sensor 1 shown in FIG. 1, and the description is abbreviate | omitted.

  When the polarity of the offset voltage of the Hall element 2 is inverted by the current direction changeover switch 31, the output of the amplifier 4 is directly input to the discrete time AD converter 6 as shown in FIG. On the other hand, when the polarity of the Hall electromotive force signal is inverted, the Hall sensor 1 includes a modulation switch 11 and a demodulation switch 9 provided in the discrete time AD converter 6 as shown in FIG. The modulation switch 11 is provided before the amplifier 4, and the demodulation switch 9 is provided after the amplifier 4. The modulation switch 11 has a configuration in which the two Hall electromotive force signals output from the current direction changeover switch 31 are switched and input alternately to the non-inverting input terminal (+) and the non-inverting input terminal (−) of the amplifier 4. The demodulating switch 9 is configured to return the Hall electromotive force signal to a DC signal before inputting the Hall electromotive force signal output from the amplifier 4.

The spinning current method is a technique for separating a signal of a potential difference “Vh (+) − Vh (−)” depending on the magnetic field strength and an offset voltage Voff. In the Hall sensor 1 shown in FIG. 1, the offset voltage is inverted in accordance with the switching of the drive current direction of the Hall element 2 (see FIG. 6). In contrast, the Hall sensor 1 according to this modification inverts the Hall electromotive force signal Vh (90) when the drive current is supplied in the 90 ° direction by changing the connection method of the current direction changeover switch 31 and the amplifier 4. Thus, the potential difference “Vh (+) − Vh (−)” depending on the magnetic field is inverted. The modulation switch 11 is a switch that inverts the polarity of Vh (90). The Hall electromotive force signal Vh (0) and the Hall electromotive force signal Vh (90) input to the amplifier 4 are expressed by the following equations (10) and (10). It is represented by (11). That is, the Hall electromotive force signal Vh (90) input to the amplifier 4 is different from the Hall electromotive force signal Vh (0) input to the amplifier 4 by the potential difference “Vh (+) − Vh (−) depending on the magnetic field. "Is an inverted signal.
Vh (0) = Vh (+) − Vh (−) − Voff (10)
Vh (90) = − (Vh (+) − Vh (−)) − Voff (11)

  The Hall electromotive force Vh (90) output from the Hall element 2 is subjected to a polarity inversion operation by the modulation switch 11, and then amplified by the amplifier 4, and the polarity is reinverted by the demodulation switch 9. After passing through the demodulation switch 9, the signal of the potential difference “Vh (+) − Vh (−)” depending on the magnetic field returns to direct current. On the other hand, the polarity of the offset signal Voff is inverted depending on the drive current direction of the Hall element 2. Therefore, the Hall electromotive force signal output from the demodulation switch 9 is equal to the signals expressed by the above-described equations (5) and (6), and is input to the discrete-time AD converter. In this case, the polarity of the offset voltage of the amplifier 4 that is generated due to variations in the manufacturing of the Hall sensor 1 is also reversed in the same manner as the offset voltage Voff of the Hall element 2. Therefore, the offset voltage of the amplifier 4 can be removed by the digital filter 62d simultaneously with the offset voltage Voff of the Hall element 2.

[Second Embodiment]
Next, a Hall sensor and Hall electromotive force detection method according to a second embodiment of the present invention will be described with reference to FIGS. 13 and 14 while referring to FIG. The Hall sensor according to the present embodiment has the same overall configuration as the Hall sensor 1 according to the first embodiment, but is different in the configuration of the discrete-time AD converter. Therefore, only the points of the Hall sensor according to the present embodiment that are different from the Hall sensor 1 according to the first embodiment will be described below.

  FIG. 13 is a block diagram showing a schematic configuration of the discrete-time AD converter 6 provided in the Hall sensor according to the present embodiment. As shown in FIG. 13, the discrete time AD converter 6 in the present embodiment has a sampling non-execution period and a sampling execution period in the same manner as the discrete time AD converter 6 in the first embodiment. The first analog signal sampled during the sampling execution period is converted into a digital signal. Similar to the first embodiment, the first analog signal corresponds to a signal obtained by subtracting the reference voltage signals Vref (+) and Vref (−) from the input signals VIN (+) and VIN (−).

  As illustrated in FIG. 13, the discrete time AD converter 6 includes an AD conversion unit 62 and a DEM unit 61. The AD converter 62 includes a subtractor 62a, an SC integrator 62b that performs an integration operation according to the polarity of the sample signal Ssp output from the control signal generator 5 (see FIG. 1), and a +1 according to the sample signal Ssp. Or a 1-bit quantizer (clocked comparator) 62c for updating the output of -1. The AD conversion unit 62 outputs the digital filter 62d to which the output signal of the 1-bit quantizer 62c is input, the DA conversion element 62e to which the output signal of the 1-bit quantizer 62c is input, and the DA conversion element 62e. A buffer amplifier 62f and a buffer amplifier 62g for holding the voltage signals of the reference voltage signals Vref (+) and Vref (−).

  The DEM unit 61 is provided at the input / output terminal of the SC integrator 62b. The DEM unit 61 includes a DEM switch 61a and a DEM switch 61b that switch input / output connections according to the polarity of the DEM signal Sde. The DEM switch 61a is provided on the input side of the SC integrator 62b, and the DEM switch 61b is provided on the output side of the SC integrator 62b. The DEM switch 61a receives the first analog signal output from the subtractor 62a. The first analog signal is a differential signal. The DEM switch 61a has two input terminals so that the positive side of the differential signal and the negative side of the differential signal can be input, and two output terminals that output the input first analog signal to the SC integrator 62b. have. One of the output terminals outputs the positive side of the differential signal that constitutes the first analog signal, and the other of the output terminals outputs the negative side of the differential signal that constitutes the first analog signal.

  The DEM switch 61b receives the first analog signal integrated by the SC integrator 62b. The SC integrator 62b integrates both the positive side constituting the first analog signal and the negative side of the differential signal. For this reason, the DEM switch 61b has two input terminals so that the positive side and the negative side of the integrated differential signal can be input. The DEM switch 61b has two output terminals for outputting the input first analog signal to the 1-bit quantizer 62c. One of the output terminals outputs the positive side of the differential signal that constitutes the first analog signal, and the other of the output terminals outputs the negative side of the differential signal that constitutes the first analog signal.

The DEM unit 61 is provided in an analog signal path 68 through which the first analog signal is transmitted. The analog signal path 68 includes a subtractor 62a, an SC integrator 62b, and a 1-bit quantizer 62c.
Each of the DEM switches 61a and 61b connects one input terminal and one output terminal and connects the other input terminal and the other output terminal in accordance with the polarity of the DEM signal Sde. And the other output terminal and the other input terminal and one output terminal are connected to each other. The DEM unit 61 performs dynamic element matching of the analog signal path 68 by switching the connection relationship between the input / output terminals of the DEM switches 61a and 61b.

The SC integrator 62b has an operational amplifier 602 (see FIG. 3). The operational amplifier 602 has two transistors (not shown) of a differential pair at the input parts of the non-inverting input terminal (+) and the inverting input terminal (−). Due to a mismatch in the electrical characteristics or the like of the two transistors, an offset voltage Voff3 is generated in the output voltage of the operational amplifier 602. In FIG. 13, this offset voltage Voff3 is schematically represented by a circle between the DEM switch 61a and the SC integrator 62b. The Hall sensor according to the present embodiment has a configuration in which DEM switches 61a and 61b are provided on the input / output side of the SC integrator 62b in order to remove the offset voltage Voff3 from the output voltage of the operational amplifier 602. Accordingly, as described with reference to FIGS. 8 and 9, the Hall sensor according to the present embodiment can be used by replacing two transistors constituting the differential pair of the operational amplifier 602 according to the polarity of the DEM signal Sde. Therefore, the offset voltage Voff3 can be removed from the output voltage of the operational amplifier 602. In the present embodiment, the digital output signal when the polarity of the DEM signal Sde is high is expressed by the following equation (12), and the digital output signal when the polarity of the DEM signal Sde is low is expressed by the following equation: It is represented by (13).

  The digital output signal output by the 1-bit quantizer 62c when the polarity of the DEM signal Sde is high and the digital output signal output by the 1-bit quantizer 62c when the polarity of the DEM signal Sde is low are: It is averaged by the digital filter 62d. For this reason, the offset voltage Voff3 superimposed on the digital output signal is removed. That is, the term “Voff3” in the equations (12) and (13) is canceled.

  The DEM operation in the present embodiment is the same as that in the first embodiment in order not to affect the digital output signal output from the discrete time AD converter 6 by the influence of the spike signal generated by the polarity inversion of the DEM signal Sde. At a sample pause time. Here, the open / close state of the switch of the input unit of the 1-bit quantizer 62c during the sample pause time in the Hall sensor according to the present embodiment will be described with reference to FIG. FIG. 14 is a diagram illustrating an open / close state of the switches 606a and 606b during the sample pause time, together with the internal configuration of the 1-bit quantizer 62c. Further, in FIG. 14, for easy understanding, the DEM switch 61b connected to the 1-bit quantizer 62c, the SC integrator 62b connected to the DEM switch 61b, and the SC integrator 62b are connected. A DEM switch 61a is also illustrated.

  As shown in FIG. 14, the 1-bit quantizer 62c includes a switch 606a to which an output signal output from one output terminal of the DEM switch 61b is input, and an output signal output from the other output terminal of the DEM switch 61b. Switch 606b. The 1-bit quantizer 62c includes a comparator 605 to which output signals output from the switches 606a and 606b are input. Further, the 1-bit quantizer 62c includes a capacitance element 607a in which one electrode is connected to one input terminal of the comparator 605 and the output terminal of the switch 606a, and the other electrode serves as a reference potential, and the comparator 605. One electrode is connected to the other input terminal and the output terminal of the switch 606b, and the other electrode has a capacitance element 607b having a reference potential.

  The 1-bit quantizer 62c is composed of a clocked comparator whose output of +1 or −1 is updated in synchronization with the polarity inversion of the sample signal Ssp output from the control signal generator 5 (see FIG. 1). The 1-bit quantizer 62c accumulates charges according to the signal level of the output signal of the SC integrator 62b in the capacitive elements 607a and 607b while the switches 606a and 606b are closed. The 1-bit quantizer 62c updates the output of the comparator 605 according to the amount of charge accumulated in the capacitance elements 607a and 607b at the timing when the switches 606a and 606b are switched from the closed state to the open state. To do. During the sample pause time, the switches 606a and 606b are always open. The DEM signal Sde is set so as to be inverted during the sample pause time. Further, the sample pause time is set to be a period sufficient for the spike signal Ssk to converge to the reference potential level. Therefore, the spike signal Ssk caused by the parasitic capacitance 66 formed between the signal wiring 65 to which the DEM signal Sde is transmitted and the signal wiring 67 connecting the DEM switch 61a and the SC integrator 62b is converted into the SC integrator. Even if it is input to 62b and input to the 1-bit quantizer 62c via the DEM switch 61b, it is not accumulated in the capacitive elements 607a and 607b. As a result, the charge amount held in the capacitive elements 602b and 602c maintains a constant value. Therefore, the Hall sensor according to the present embodiment can remove the influence of the spike signal from the digital output signal.

[Third Embodiment]
A third embodiment of the present invention will be described with reference to FIGS. 15 and 16 with reference to FIG. The Hall sensor according to the present embodiment has the same overall configuration as the Hall sensor 1 according to the first embodiment, but is different in the configuration of the discrete-time AD converter. The Hall sensor according to the present embodiment is characterized in that it includes a discrete-time double integral AD converter (an example of a discrete-time integral AD converter) as an AD converter that performs dynamic element matching. . Therefore, only the points of the Hall sensor according to the present embodiment that are different from the Hall sensor 1 according to the first embodiment will be described below.

  FIG. 15 is a block diagram showing a schematic configuration of the discrete time AD converter 6 provided in the Hall sensor according to the present embodiment. As shown in FIG. 15, the discrete time AD converter 6 in the present embodiment has a sampling non-execution period and a sampling execution period in the same manner as the discrete time AD converter 6 in the first embodiment. The first analog signal sampled during the sampling execution period is converted into a digital signal. The input signals VIN (+) and VIN (−) correspond to the first analog signal, and the reference voltage signals Vref (+) and Vref (−) correspond to the second analog signal.

  As shown in FIG. 15, the discrete-time AD converter 6 includes an SC integrator 62b that performs an integration operation according to the polarity of the sample signal Ssp output from the control signal generator 5 (see FIG. 1), and a sample signal. A 1-bit quantizer (clocked comparator) 62c that updates the output of +1 or -1 according to Ssp. In addition, the AD converter 62 receives a DA conversion element 62e to which an output signal of the 1-bit quantizer 62c is input, and reference voltage signals Vref (+) and Vref (−) output from the DA conversion element 62e. A buffer amplifier 62f and a buffer amplifier 62g. Further, the AD conversion unit 62 selects one of the input signals VIN (+), VIN (−) and the reference voltage signals Vref (−), Vref (+) as the input unit of the SC integrator 62. 62h and a digital output signal output from the 1-bit quantizer 62c, and a counter unit 62i that counts the number of times that the difference signal obtained by subtracting the reference voltage signal Vref (+) from the reference voltage signal Vref (−) is counted. have.

  The selection unit 62h includes a switch 621a to which the input signal VIN (+) is input, a switch 621b to which the input signal VIN (−) is input, a switch 621c to which the reference voltage signal Vref (+) is input, and a reference voltage signal Vref ( -) Has a switch 621d for input. The switch 621a has an input terminal to which the input signal VIN (+) is input, and an output terminal connected to the non-inverting input terminal (+) of the SC integrator 62b and the output terminal of the switch 621d. The switch 621b has an input terminal for receiving the input signal VIN (−), and an output terminal connected to the inverting input terminal (−) of the SC integrator 62b and the output terminal of the switch 621c. The switch 621c has an input terminal connected to the output terminal of the buffer amplifier 62g via the DEM switch 61b, and an output terminal connected to the inverting input terminal (−) of the SC integrator 62b. The switch 621d has an input terminal connected to the output terminal of the buffer amplifier 62f via the DEM switch 61b, and an output terminal connected to the non-inverting input terminal (+) of the SC integrator 62b. The selector 62h selects a signal to be input to the SC integrator 62b according to the polarity of the selection signal Ss generated and output by the control signal generator 5.

  The SC integrator 62b integrates a voltage value obtained by subtracting the input signal VIN (−) from the input signal VIN (+) input via the selection unit 62h according to the sample signal Ssp, and then integrates the reference voltage signal. A voltage value obtained by subtracting the voltage value of the reference voltage signal Vref (+) from the voltage value of Vref (−) is integrated according to the sample signal Ssp. The SC integrator 62b performs integration until the voltage value obtained by subtracting the reference voltage signal Vref (+) from the reference voltage signal Vref (−) is inverted to a negative value. The SC integrator 62b determines the timing at which the output signal is inverted based on the switching of the digital output signal output from the 1-bit quantizer 62c from the low level to the high level.

  The counter unit 62i counts the number of times of integrating the voltage value obtained by subtracting the voltage value of the reference voltage signal Vref (−) from the voltage value of the reference voltage signal Vref (−) according to the count signal Sct. The count signal Sct is generated by the control signal generation unit 5, and is input from the control signal generation unit 5 to the counter unit 62i. In FIG. 1, the count signal Sct is not shown.

  Here, the operation of the discrete time AD converter 6 will be described using FIG. 16 with reference to FIG. FIG. 16 is a diagram showing signal waveforms at various parts of the discrete time AD converter 6. In FIG. 16, “Ssp” in the first stage indicates the signal waveform of the sample signal, “Ss” in the second stage indicates the signal waveform of the selection signal, and “Sct” in the third stage indicates the signal waveform of the counter signal. Show. In FIG. 16, “CT” in the fourth stage indicates the number of counts of the reference voltage signals Vref (+) and Vref (−) by the counter unit 62i, and “Sde” in the fifth stage indicates the signal waveform of the DEM signal. “SC-OUT” indicates the signal waveform of the output voltage of the SC integrator 62b, and “QT-OUT” indicates the output signal waveform of the 1-bit quantizer 62c.

  As shown in FIG. 16, the count signal Sct has a waveform synchronized with the sample signal Ssp only when the polarity of the selection signal Ss is high and the reference voltage signals Vref (+) and Vref (−) are integrated. At this time, the value N (N is an integer other than a negative number) of the count number “CT” counted by the counter unit 62i is obtained when the polarity of the output signal QT-OUT of the 1-bit quantizer 62c is switched to a high level. Final value.

  In FIG. 16, the period from time t0 to time t1 is a period in which the SC integrator 62b integrates a voltage value obtained by subtracting the voltage value of the input signal VIN (−) from the voltage value of the input signal VIN (+). A period from time t1 to time t2 is a period in which the SC integrator 62b integrates a voltage value obtained by subtracting the voltage value of the reference voltage signal Vref (+) from the voltage value of the reference voltage signal Vref (−). As indicated by the output voltage “SC−OUT” of the SC integrator 62b, the reference voltage increases as the number of integrated voltage values obtained by subtracting the voltage value of the input signal VIN (−) from the voltage value of the input signal VIN (+) increases. The cumulative number of voltage values obtained by subtracting the voltage value of the reference voltage signal Vref (+) from the voltage value of the signal Vref (−) increases. Note that ΔVIN shown in FIG. 16 represents a voltage value obtained by subtracting the voltage value of the input signal VIN (−) from the voltage value of the input signal VIN (+), and ΔVref represents the voltage value of the reference voltage signal Vref (−). This represents a voltage value obtained by adding an offset voltage Voff4 (details will be described later) to a voltage value obtained by subtracting the voltage value of the reference voltage signal Vref (+). The count value “CT” increases as the voltage value obtained by subtracting the voltage value of the input signal VIN (−) from the voltage value of the input signal VIN (+) increases. In the double integral AD converter employed in the discrete time AD converter 6 in this embodiment, the value “N” of the count number “CT” counted by the counter unit 62 i corresponds to the digital output signal.

Returning to FIG. 15, the discrete time AD converter 6 adopting the configuration of the double integral AD converter is also a buffer amplifier in the same manner as the discrete time AD converter 6 in the first and second embodiments. An error occurs in the digital output signal due to the offset voltage Voff4 generated in 62f and 62g and the offset voltage generated in the operational amplifier 602 in the SC integrator 62b. In FIG. 15, for ease of understanding, the offset voltage Voff4 is schematically shown by a circle between the buffer amplifier 62f and the DEM switch 61a. However, the Hall sensor according to the present embodiment includes the DEM switches 62f and 62g in the same manner as the Hall sensors according to the first and second embodiments described above, so that a mismatch between elements such as the buffer amplifiers 62f and 62g is caused. The accompanying error can be reduced. In addition, the Hall sensor according to the present embodiment is adjusted to execute the DEM operation during the sample pause time, similarly to the Hall sensors according to the first and second embodiments. Thereby, the Hall sensor according to the present embodiment can remove the influence of the spike signal generated in association with the DEM operation.
The configurations in the first to third embodiments can be performed simultaneously, and dynamic element matching is performed at a plurality of locations in the AD converter, and the replacement timing of each element is set as the sample pause time. It is also suitable to adjust.

DESCRIPTION OF SYMBOLS 1 Hall sensor 2 Hall element 2a 1st terminal 2b 2nd terminal 2c 3rd terminal 2d 4th terminal 3 Drive part 4 Amplifier 5 Control signal generation part 6 Discrete time type AD converter 31 Current direction changeover switch 33 Power supply input terminal 34 Reference | standard Potential input terminal 35 Drive power supply 61 DEM unit 61a, 61b DEM switch 62 AD converter 62a Subtractor 62b SC integrator 62c 1-bit quantizer 62d Digital filter 62e DA converter 62f, 62g Buffer amplifier 62h Selector 62i Counter unit 601a To 601h switch 602 operational amplifiers 603 and 604 capacitance element

Claims (12)

A Hall element;
A drive unit that drives the Hall element by switching the energization direction of the Hall element;
A sampling non-execution period in which the first analog signal corresponding to the Hall electromotive force of the Hall element is not sampled; and a sampling execution period in which the first analog signal is sampled. A discrete time AD converter that converts the analog signal of
A dynamic element matching unit that is provided in an analog signal path of the discrete-time AD converter and performs dynamic element matching of the analog signal path during the sampling non-execution period;
Hall sensor equipped with. The Hall sensor according to claim 1, wherein the discrete-time AD converter is a discrete-time ΔΣ modulator. The discrete time AD converter has a discrete time integrator,
The Hall sensor according to claim 2, wherein the dynamic element matching unit is provided at an input / output terminal of the discrete-time integrator. The discrete time AD converter includes:
A DA converter that converts the digital signal into a second analog signal;
A buffer unit for buffering the second analog signal;
A subtractor for subtracting the first analog signal from the buffered second analog signal;
Have
The Hall sensor according to claim 2, wherein the dynamic element matching unit is provided at an input / output terminal of the buffer unit. The Hall sensor according to claim 1, wherein the discrete-time AD converter is a discrete-time integral AD converter. The discrete time AD converter has a discrete time integrator,
The Hall sensor according to claim 5, wherein the dynamic element matching unit is provided at an input / output terminal of the discrete-time integrator. The discrete time AD converter includes:
A buffer unit for buffering the reference signal and outputting a second analog signal;
A selection unit that selects one of the first analog signal and the second analog signal;
A discrete-time integrator that integrates the signal selected by the selector;
Have
The hall sensor according to claim 6, wherein the dynamic element matching unit is provided at an input / output terminal of the buffer unit. The hall sensor according to claim 7, wherein the dynamic element matching unit is provided at an input / output terminal of the discrete-time integrator. The hall sensor according to any one of claims 1 to 8, wherein the analog signal path is a differential signal path. The hall sensor according to claim 1, wherein the sampling non-execution period starts in synchronization with switching of the energization direction. The Hall sensor according to any one of claims 1 to 10, wherein the sampling execution period ends in synchronization with the switching of the energization direction. Switch the energization direction of the Hall element,
After switching the energization direction, the dynamic element matching of the analog signal path of the discrete time AD converter is performed in a sampling non-execution period in which the analog signal transmitted to the analog signal path is not sampled .
A Hall electromotive force detection method, wherein after performing the dynamic element matching, an analog signal corresponding to the Hall electromotive force of the Hall element is converted into a digital signal by the discrete time AD converter.

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