JP6092680B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

FIG. 10 is a cross-sectional view of a conventional semiconductor device 800. FIG. 11 is a diagram for explaining a problem of the conventional semiconductor device 800. FIG. 11A is a cross-sectional view of a main part of a conventional semiconductor device 800, and FIG. 11B is an equivalent circuit diagram thereof.
A conventional semiconductor device 800 is a trench gate power MOSFET, and as shown in FIG. 10, an n ⁺ type low resistance semiconductor layer 812, an n ⁻ type drift layer 814 located on the low resistance semiconductor layer 812, a drift A p-type body layer 816 located on the layer 814, a trench 818 formed by opening the body layer 816 and reaching the drift layer 814, and disposed in the body layer 816 and at least a part of the inner periphery of the trench 818 A first conductivity type source region 824 formed exposed on the surface, a gate insulating layer 820 formed on the inner peripheral surface of the trench 818, and a gate electrode layer formed on the inner peripheral surface of the gate insulating layer 820 822 includes a source electrode layer 830 which is insulated from the gate electrode layer 822 and formed in contact with the source region 824. Reference numeral 826 indicates a p ⁺ type body contact region, reference numeral 828 indicates an interlayer insulating layer, reference numeral 832 indicates a drain electrode layer, and reference numeral 840 indicates a MOSFET portion.

In the conventional semiconductor device 800 configured as described above, when the surge voltage generated when the switching operation with the inductive load is turned off exceeds the breakdown voltage of the semiconductor device 800, the avalanche breakdown occurs, and the generated minority carriers It flows into the source electrode 830 through the body layer 816 (see “Iav1” in FIG. 11B). At this time, a potential difference VBE is generated between the source region 824 and the body layer 816, and the parasitic bipolar transistor composed of the source region 824, the body layer 816, and the drift layer 814 is turned on, and is amplified by the parasitic bipolar transistor. A current (refer to “Iav2” in FIG. 11B) flows from the drift layer 814 to the source region 824, and the element is destroyed due to heat generated by the excessive current. In recent years, miniaturization of the cell proceeds, since the resistance component R _B has been increased, easily parasitic bipolar transistor is turned on, the above problem is becoming more serious.

  2. Description of the Related Art Conventionally, in order to solve the above-described problem, a semiconductor device is known that includes a MOSFET portion and a protective diode portion that causes avalanche breakdown at a lower voltage than that in the MOSFET portion on the same semiconductor substrate (for example, (See Patent Document 1). FIG. 12 is a cross-sectional view of a conventional semiconductor device 900.

  As shown in FIG. 12, the conventional semiconductor device 900 includes a MOSFET portion 940 and a protective diode portion 950 that causes avalanche breakdown at a lower voltage than that in the MOSFET portion 940 on the same semiconductor substrate 910. In the protection diode portion 950, a deep p-type diffusion region 934 reaching from the body layer 916 to a deep position of the drift layer 914 is formed.

  According to the conventional trench gate power MOSFET 900, the thickness of the drift layer 914 is thinner in the protection diode part 950 than in the MOSFET part 940, so that an avalanche breakdown occurs at a lower voltage than in the MOSFET part 940. become. As a result, according to the conventional trench gate power MOSFET 900, the avalanche breakdown is not caused in the MOSFET section 940 when the switching operation with the inductive load is turned off, and the avalanche resistance can be increased.

JP-A-11-195788

  However, it is difficult to apply conventional trench gate power MOSFET 900 to a silicon carbide semiconductor device. This is because in a silicon carbide semiconductor device, it is difficult to introduce a p-type impurity to a deep position by ion implantation or the like. The situation described above also exists in the semiconductor device in which the p-type and the n-type are reversed.

  In view of the above, the present invention aims to solve the above-described problems. A MOSFET portion and a protection diode portion that causes avalanche breakdown at a lower voltage than that in the MOSFET portion are formed on the same silicon carbide semiconductor substrate. A trench gate power MOSFET is provided.

[1] A semiconductor device of the present invention is a semiconductor device comprising a MOSFET part and a protective diode part that causes avalanche breakdown at a lower voltage than that in the MOSFET part on the same silicon carbide semiconductor substrate. Is a first conductivity type low resistance semiconductor layer, a first conductivity type drift layer located on the low resistance semiconductor layer and containing a first conductivity type impurity at a lower concentration than the low resistance semiconductor layer, the drift layer A body layer of a second conductivity type opposite to the first conductivity type, a trench formed by opening the body layer and reaching the drift layer, and disposed in the body layer and at least one A source region of a first conductivity type formed by exposing a portion to the inner peripheral surface of the trench, a gate insulating layer formed on the inner peripheral surface of the trench, and the gate insulation A gate electrode layer formed on an inner peripheral surface of the layer; a source electrode layer formed in contact with the source region while being insulated from the gate electrode layer; and a region sandwiched between adjacent trenches A first conductive region of a second conductivity type formed so as to project from the body layer toward the drift layer; and the protection diode portion includes a first resistance type low-resistance semiconductor layer and the low-resistance semiconductor A drift layer of a first conductivity type located on the layer and containing a first conductivity type impurity at a lower concentration than the low-resistance semiconductor layer; a second conductivity located on the drift layer and opposite to the first conductivity type A body layer of the mold, and a plurality of second conductive type second projecting regions formed so as to project from the body layer toward the drift layer, and an interval L2 between the adjacent second projecting regions Is adjacent And wherein the wider than the distance L1 of the first extending region that.

[2] In the semiconductor device of the present invention, it is preferable that the deepest portion of the first overhang region and the deepest portion of the second overhang region are located deeper than the deepest portion of the trench.

[3] In the semiconductor device of the present invention, the deepest portion of the first overhang region and the deepest portion of the second overhang region are only in a range of 0.5 μm to 4.5 μm from the deepest portion of the trench. It is preferable that it exists in a deep position.

[4] In the semiconductor device of the present invention, the interval L2 is preferably in the range of 1.05 to 3.0 times the interval L1.

[5] In the semiconductor device of the present invention, it is preferable that the second overhang region is formed in the same process as the first overhang region.

[6] A manufacturing method of a semiconductor device of the present invention is a manufacturing method of a semiconductor device for manufacturing a semiconductor device of the present invention, on the first resistance type low-resistance semiconductor layer and the low-resistance semiconductor layer. A silicon carbide semiconductor substrate preparing step of preparing a silicon carbide semiconductor substrate provided with a drift layer of a first conductivity type that is located and contains a first conductivity type impurity at a lower concentration than the low resistance semiconductor layer; and on the surface of the drift layer The second conductivity type impurity is introduced into the region corresponding to the first overhang region and the region corresponding to the second overhang region by an ion implantation method, and activation annealing of the second conductivity type impurity is performed to perform the first annealing. An overhang region forming step of forming one overhang region and the second overhang region, and an epitaxial growth method for forming the second conductivity type body layer on the surface of the drift layer A body layer forming step to be formed, a first conductivity type impurity is introduced into the region to be the source region on the surface of the body layer by an ion implantation method, and an activation annealing process of the first conductivity type impurity is performed. A source region forming step for forming the source region; a trench forming step for opening the body layer to reach the drift layer; and a gate for forming the gate insulating layer on an inner peripheral surface of the trench. An insulating layer forming step, a gate electrode layer forming step of forming the gate electrode layer on an inner peripheral surface of the gate insulating layer, an interlayer insulating layer forming step of forming an interlayer insulating layer so as to cover the gate electrode layer, A source electrode layer forming step of forming the source electrode layer so as to cover the body layer and the interlayer insulating layer.

[7] A second method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device according to the present invention, wherein the first conductive type low-resistance semiconductor layer and the low-resistance semiconductor are manufactured. A silicon carbide semiconductor substrate preparing step of preparing a silicon carbide semiconductor substrate provided with a drift layer of a first conductivity type that is located on a layer and contains a first conductivity type impurity having a lower concentration than the low resistance semiconductor layer; and the drift layer Forming a second trench in a region corresponding to the first overhanging region and a region corresponding to the second overhanging region on the surface of the substrate, and filling the second trench with a second conductivity type semiconductor material by an epitaxial growth method. An overhang region forming step of forming the first overhang region and the second overhang region; and epidoping the body layer of the second conductivity type on the surface of the drift layer. A body layer forming step formed by a chiral growth method, a first conductivity type impurity is introduced into the region to be the source region on the surface of the body layer by an ion implantation method, and an activation annealing treatment of the first conductivity type impurity A source region forming step of forming the source region, a trench forming step of opening the body layer to reach the drift layer, and forming the gate insulating layer on the inner peripheral surface of the trench Forming a gate insulating layer; forming a gate electrode layer on the inner peripheral surface of the gate insulating layer; and forming an interlayer insulating layer so as to cover the gate electrode layer And a source electrode layer forming step of forming the source electrode layer so as to cover the body layer and the interlayer insulating layer. And butterflies.

[8] In the method for manufacturing a semiconductor device of the present invention, in the overhang region forming step, the deepest portion of the first overhang region and the deepest portion of the second overhang region are deeper than the deepest portion of the trench. It is preferable to form the deepest portion of the first overhang region and the second overhang region.

[9] In the method for manufacturing a semiconductor device of the present invention, in the overhang region forming step, the deepest portion of the first overhang region and the deepest portion of the second overhang region are 0.5 μm to the deepest portion of the trench. It is preferable that the deepest portion of the first overhang region and the second overhang region be formed so as to be deeper by a value within a range of 4.5 μm.

[10] In the method for manufacturing a semiconductor device of the present invention, in the overhang region forming step, the first interval is set so that the interval L2 is in the range of 1.05 to 3.0 times the interval L1. It is preferable to form the deepest portion of the overhang region and the second overhang region.

  According to the semiconductor device of the present invention, as shown in FIGS. 1 and 2 to be described later, the distance L2 between the second overhang regions in the protection diode portion is wider than the interval L1 between the first overhang regions in the MOSFET portion. In the protective diode portion, the depletion layer is less likely to extend to the drift layer side than in the MOSFET portion (that is, the breakdown voltage is lowered), and avalanche breakdown occurs at a lower voltage than in the MOSFET portion. As a result, according to the semiconductor device of the present invention, the avalanche breakdown is not caused in the MOSFET portion when the switching operation with the inductive load is turned off, and the avalanche resistance can be increased.

  In addition, according to the semiconductor device of the present invention, since the second conductivity type impurity only needs to be introduced to a position shallower than the conventional one, the MOSFET portion and the protection diode that causes avalanche breakdown at a lower voltage than the MOSFET portion. It is possible to easily realize the semiconductor device of the present invention provided with the same part on the same silicon carbide semiconductor substrate.

  In addition, according to the semiconductor device of the present invention, since the first extension region formed so as to extend from the body layer toward the drift layer in the region sandwiched between adjacent trenches, Electric field stress is relieved, and the effect that the breakdown voltage can be increased is also obtained.

  According to the method for manufacturing a semiconductor device of the present invention, the excellent semiconductor device of the present invention can be manufactured as described above.

1 is a cross-sectional view of a semiconductor device 100 according to Embodiment 1. FIG. FIG. 6 is a diagram for explaining the function and effect of the semiconductor device 100 according to the first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view of a conventional semiconductor device 800. It is a figure shown in order to demonstrate the problem of the conventional semiconductor device 800. It is sectional drawing of the conventional semiconductor device 900. FIG.

  Hereinafter, a semiconductor device of the present invention will be described based on embodiments shown in the drawings.

[Embodiment 1]
1. Semiconductor Device According to First Embodiment FIG. 1 is a cross-sectional view of a semiconductor device 100 according to the first embodiment.
As shown in FIG. 1, the semiconductor device 100 according to the first embodiment includes a MOSFET unit 40 and a protective diode unit 50 that causes avalanche breakdown at a lower voltage than that in the MOSFET unit 40. The semiconductor device 100 is provided. The semiconductor device 100 is a power MOSFET having a withstand voltage of 1200V.

The MOSFET section 40 includes an n ⁺ type low resistance semiconductor layer 112, an n ⁻ type drift layer 114 located on the low resistance semiconductor layer 112, a p type body layer 116 located on the drift layer 114, and a body layer 116. A trench 118 formed by opening and reaching the drift layer 114; an n ⁺ -type source region 124 disposed in the body layer 116 and formed by exposing at least a part of the inner peripheral surface of the trench 118; A gate insulating layer 120 formed on the inner peripheral surface of the trench 118, a gate electrode layer 122 formed on the inner peripheral surface of the gate insulating layer 120, and insulated from the gate electrode layer 122 and in contact with the source region 124. The source electrode layer 130 and the region sandwiched between the adjacent trenches 118 are stretched from the body layer 116 toward the drift layer 114. Having a first extending region 134 of p-type formed in the Suyo. Reference numeral 126 denotes a p ⁺ -type body contact region, reference numeral 128 denotes an interlayer insulating layer, and reference numeral 132 denotes a drain electrode layer.

The protection diode unit 50 includes an n ⁺ -type low-resistance semiconductor layer 112, an n ⁻ -type drift layer 114 located on the low-resistance semiconductor layer 112, a p-type body layer 116 located on the drift layer 114, and a body A plurality of p-type second projecting regions 134 a are formed so as to project from the layer 116 toward the drift layer 114.

The thickness of the low resistance semiconductor layer 112 is, for example, 50 μm to 500 μm (eg, 350 μm), and the impurity concentration of the low resistance semiconductor layer 112 is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (eg, 5 × 10 ^18). cm ⁻³ ). The thickness of the drift layer 114 is 6.0 μm to 50 μm (for example, 15 μm), and the impurity concentration of the drift layer 114 is 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ (for example, 7 × 10 ¹⁵ cm ^−3). ). The thickness of the body layer 116 is, for example, 1.0 μm to 3.0 μm (for example, 2.0 μm), and the impurity concentration of the body layer 116 is 1 × 10 ¹⁶ cm ⁻³ to 2 × 10 ¹⁸ cm ⁻³ (for example, 2 × 10 ¹⁷ cm ⁻³ ).

The depth of the trench 118 is 1.5 μm to 5.0 μm (for example, 3.0 μm), and the pitch of the trench 118 is 3.0 μm to 15 μm (for example, 5.0 μm).
The gate insulating layer 120 is made of, for example, a silicon dioxide film formed by a CVD method, and the thickness of the gate insulating layer 120 is 20 nm to 200 nm (for example, 100 nm).
The gate electrode layer 122 is made of low resistance polysilicon.

The depth of the source region 124 is 0.2 μm to 1.0 μm (for example, 0.5 μm), and the impurity concentration of the source region 124 is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (for example, 2 × 10 ¹⁹ cm ⁻³ ).
The depth of the body contact region 126 is 0.2 μm to 2.0 μm (for example, 0.5 μm), and the impurity concentration of the body contact region 126 is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (for example, 2 × 10 ¹⁹ cm ⁻³ ).
The interlayer insulating layer 128 is made of, for example, a silicon dioxide film formed by a CVD method, and the thickness of the interlayer insulating layer 128 is 0.5 μm to 3.0 μm (for example, 1.0 μm).

The source electrode layer 130 is composed of, for example, a laminated film in which Ni, Ti, and Al are laminated in order from the bottom, and the thickness of the source electrode layer 130 is 1.0 μm to 10 μm (for example, 3.0 μm).
The drain electrode layer 132 is a laminated film in which Ni, Ti, and Ag are laminated in order from the bottom, and the thickness of the drain electrode layer 132 is 0.2 μm to 1.5 μm (for example, 1.0 μm).

  In the semiconductor device 100 according to the first embodiment configured as described above, the interval L2 between the adjacent second protruding regions 134a is wider than the interval L1 between the adjacent first protruding regions 134. The interval L2 is in the range of 1.05 to 3.0 times the interval L1 (eg, 1.3 times). Specifically, the interval L1 is 5.0 μm, and the interval L2 is 6.5 μm. The second overhang region 134a is formed in the same process as the first overhang region 134.

The deepest portion of the first overhang region 134 and the deepest portion of the second overhang region 134 a are located deeper than the deepest portion of the trench 118. The deepest portion of the first overhang region 134 and the deepest portion of the second overhang region 134a are deeper than the deepest portion of the trench 118 by a value within a range of 0.5 μm to 4.5 μm (for example, 3.0 μm). . The deepest portion of the trench 118 is deeper than the bottom surface of the body layer 116 by a value (for example, 0.5 μm) within a range of 0.2 μm to 2.5 μm. The impurity concentration of the first overhang region 134 and the second overhang region 134a is 1 × 10 ¹⁶ cm ⁻³ to 2 × 10 ¹⁸ cm ⁻³ (for example, 2 × 10 ¹⁷ cm ⁻³ ).

2. Effect of Semiconductor Device According to First Embodiment FIG. 2 is a diagram for explaining the function and effect of the semiconductor device 100 according to the first embodiment. FIG. 2A is a diagram illustrating a state where a depletion layer expands when a reverse bias voltage is applied to the semiconductor device 100 according to the first embodiment, and FIG. 2B is a diagram opposite to the semiconductor device 100a according to the comparative example. It is a figure which shows a mode that a depletion layer expands when a bias voltage is applied. In the semiconductor device 100a according to the comparative example, “the interval L2 between the adjacent second overhang regions 134a in the protection diode unit 50” is set to the same value as “the interval L1 between the adjacent first overhang regions 134 in the MOSFET unit 40”. Is.

  According to the semiconductor device 100 according to the first embodiment configured as described above, unlike the semiconductor device 100a according to the comparative example, as illustrated in FIG. Since the interval L2 is wider than the interval L1 of the first overhang region 134 in the MOSFET portion 40, the depletion layer is less likely to extend toward the drift layer 114 in the protective diode portion 50 than in the MOSFET portion 40 (that is, withstand voltage is reduced). And avalanche breakdown occurs at a lower voltage than in the MOSFET section 40. As a result, according to the semiconductor device 100 of the present invention, the avalanche breakdown is not caused in the MOSFET section 40 when the switching operation with the inductive load is turned off, and the avalanche resistance can be increased.

  In addition, according to the semiconductor device 100 according to the first embodiment, the p-type impurity may be introduced to a position shallower than the conventional one, so that the avalanche breakdown can be performed at a lower voltage than in the MOSFET unit 40 and the MOSFET unit 40. It is possible to easily realize the semiconductor device according to the first embodiment provided with the protective diode portion 50 that is raised on the same silicon carbide semiconductor substrate 110.

  Further, the semiconductor device 100 according to the first embodiment has the first overhang region 134 formed so as to overhang from the body layer 118 toward the drift layer 114 in a region sandwiched between adjacent trenches 118. Thus, the electric field stress on the gate insulating layer 120 is alleviated and the breakdown voltage can be increased.

  Further, according to the semiconductor device 100 according to the first embodiment, since the deepest portion of the first overhang region 134 and the deepest portion of the second overhang region 134a are located deeper than the deepest portion of the trench 118, the gate insulating layer The electric field stress is relaxed and the breakdown voltage can be increased.

  In addition, according to the semiconductor device 100 according to the first embodiment, since the interval L2 is 1.05 times or more the interval L1, the breakdown voltage of the protection diode unit 50 is more reliably set to the breakdown voltage of the MOSFET unit 40 (with an average value). Several tens of volts or more). On the other hand, since the interval L2 is 4.5 times or less than the interval L1, the area of the protection diode portion is not excessively increased.

  Further, according to the semiconductor device 100 according to the first embodiment, since the second overhang region 134a is formed in the same process as the first overhang region 134, the first overhang region 134 and the second overhang region 134a are formed. Therefore, the manufacturing process as a whole is not complicated.

3. Manufacturing method of semiconductor device according to embodiment 1
The semiconductor device 100 according to the first embodiment can be manufactured by a manufacturing method (a manufacturing method of a semiconductor device according to the first embodiment) having the following manufacturing process. 3 to 8 are views for explaining the method of manufacturing the semiconductor device according to the first embodiment. 3-8 is each process.

(1) Silicon carbide semiconductor substrate preparation step Silicon carbide semiconductor substrate 109 in which a silicon carbide semiconductor layer constituting drift layer 114 is formed on the 4H-silicon carbide semiconductor substrate constituting low resistance semiconductor layer 112 by epitaxial growth is formed. Prepare (see FIG. 3A). The thickness of the low-resistance semiconductor layer 112 is, for example, 50 μm to 500 μm (for example, 350 μm), and the impurity concentration of the low-resistance semiconductor layer 112 is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (for example, 5 × 10 ¹⁸ cm). ^-3 ). The thickness of the drift layer 114 is 6.0 μm to 50 μm (for example, 15 μm), and the impurity concentration of the drift layer 114 is 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ (for example, 7 × 10 ¹⁵ cm ⁻³ ). And

(2) Overhang region forming step Thereafter, a mask M1 having an opening in a region corresponding to the first overhang region 134 and a region corresponding to the second overhang region 134a is formed, and the drift layer is formed by ion implantation through the mask M1. By injecting p-type impurities (for example, aluminum ions) into the surface of 114, p-type impurities are introduced into the region corresponding to the first overhang region 134 and the region corresponding to the second overhang region 134a on the surface of the drift layer 114. (See FIG. 3B). Thereafter, after removing the mask M1, activation annealing of the p-type impurity is performed to form the first overhang region 134 and the second overhang region 134a. The impurity concentration of the first overhang region 134 and the second overhang region 134a is set to 1 × 10 ¹⁶ cm ⁻³ to 2 × 10 ¹⁸ cm ⁻³ (for example, 2 × 10 ¹⁷ cm ⁻³ ) at a portion in contact with the body layer 116. Further, the interval L2 between the adjacent first protruding regions 134 is, for example, 5.0 μm, and the interval L2 between the adjacent second protruding regions is, for example, 6.5 μm.

  For example, the activation annealing treatment is performed at a temperature in the range of 1650 ° C. to 1800 ° C. in an Ar gas atmosphere after the front and back surfaces of the silicon carbide semiconductor substrate are covered with a graphite film. Note that the activation annealing treatment of the p-type impurity in this step may be performed in the same step as the activation annealing treatment of the n-type impurity and the p-type impurity in the source region and body contact region forming step described later.

(3) Body Layer Formation Step Thereafter, a p-type body layer 116 is formed on the surface of the drift layer 114 by an epitaxial growth method (see FIG. 4A). The thickness of the body layer 116 is, for example, 1.0 μm to 3.0 μm (for example, 2.0 μm), and the impurity concentration of the body layer 116 is 1 × 10 ¹⁶ cm ⁻³ to 2 × 10 ¹⁸ cm ⁻³ (for example, 2 × 10 ¹⁷ cm ⁻³ ). Thereby, silicon carbide semiconductor substrate 109 becomes silicon carbide semiconductor substrate 110.

(4) Source region and body contact region formation step Thereafter, a mask M2 having an opening in a region corresponding to the source region 124 is formed, and an n-type impurity (on the surface of the body layer 116 is formed by ion implantation through the mask M2. By implanting, for example, phosphorus ions, an n-type impurity is introduced into a region to be the source region 124 on the surface of the body layer 116 (see FIG. 4B).

  Thereafter, after removing the mask M2, a mask M3 having an opening in a region corresponding to the body contact region 126 is formed, and p-type impurities (for example, aluminum ions) are formed on the surface of the body layer 116 by ion implantation through the mask M3. P-type impurities are introduced into a region to be the body contact region 126 on the surface of the body layer 116 (see FIG. 5A).

  Thereafter, after removing the mask M3, activation annealing of n-type impurities and p-type impurities is performed to form the source region 124 and the body contact region 126. For example, the activation annealing treatment is performed at a temperature in the range of 1650 ° C. to 1800 ° C. in an Ar gas atmosphere after the front and back surfaces of the silicon carbide semiconductor substrate are covered with a graphite film.

The depth of the source region 124 is 0.2 μm to 1.0 μm (for example, 0.5 μm), and the impurity concentration of the source region 124 is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (for example, 2 × 10 ^19). cm ⁻³ ). The depth of the body contact region 126 is 0.2 μm to 2.0 μm (for example, 0.5 μm), and the impurity concentration of the body contact region 126 is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (for example, 2 × 10 ¹⁹ cm ⁻³ ).

(5) Trench formation step Thereafter, a mask M4 having an opening in a region corresponding to the trench 118 is formed, and the body layer 116 is opened by anisotropic dry etching using the mask M4 so as to reach the drift layer 114. A trench 118 is formed (see FIG. 5B). The depth of the trench 118 is 1.5 μm to 5.0 μm (for example, 3.0 μm), and the pitch of the trench 118 is 3.0 μm to 15 μm (for example, 5.0 μm).

(6) Gate Insulating Layer Formation Step Thereafter, after removing the mask M4, a silicon dioxide film is formed on the inner peripheral surface of the trench 118 and the surface of the body layer 116 by, for example, the CVD method. The silicon dioxide film located on the inner peripheral surface of the trench 118 becomes the gate insulating layer 120 (see FIG. 6A). The thickness of the gate insulating layer 120 is 20 nm to 200 nm (for example, 100 nm).

(7) Gate Electrode Layer Formation Step Thereafter, a low resistance polysilicon film is deposited on the upper surface of the silicon dioxide film formed on the inner peripheral surface of the gate insulating layer 120 and the upper surface of the body layer 116 by CVD (FIG. 6). (See (b).) Thereafter, the polysilicon film is etched back by a predetermined dry etching method to form the gate electrode layer 122 on the inner peripheral surface of the gate insulating layer 120 (see FIG. 7A). ).

(8) Interlayer Insulating Layer Forming Step Thereafter, a silicon dioxide film is deposited on the upper surface of the silicon dioxide film formed on the upper surface of the gate electrode layer 120 and the upper surface of the body layer 116 by, eg, CVD, and the gate electrode layer A mask M5 is formed in a predetermined area covering 122. Thereafter, the silicon dioxide film is etched by a predetermined dry etching method to form an interlayer insulating layer 128 in a predetermined region covering the gate electrode layer 122 (see FIGS. 7B and 8A). The thickness of the interlayer insulating layer 128 is 0.5 μm to 3.0 μm (for example, 1.0 μm).

(9) Source electrode layer and drain electrode layer formation step Then, after removing the mask M5, for example, a Ni layer and a Ti layer are sequentially formed so as to cover the source region 124, the body contact region 126, and the interlayer insulating layer 128, and then 1000 A lower layer of the source electrode layer 130 is formed by performing a heat treatment at ° C. Thereafter, for example, Ni and Ti layers are sequentially formed on the surface of the low resistance semiconductor layer 112, and then heat treatment at 1000 ° C. is performed to form a lower layer of the drain electrode layer 132. Thereafter, the source electrode layer 130 is formed by forming an Al layer on the lower layer of the source electrode layer 130. Further, the drain electrode layer 132 is formed by sequentially forming a Ti layer, a Ni layer, and an Ag layer on the lower layer of the drain layer 132 (see FIG. 8B). The source electrode layer 130 has a thickness of 1.0 μm to 10 μm (for example, 3.0 μm), and the drain electrode layer 132 has a thickness of 0.2 μm to 1.5 μm (for example, 1.0 μm).

  By performing the above steps, the semiconductor device 100 according to the first embodiment can be manufactured.

[Embodiment 2]
The manufacturing method of the semiconductor device according to the second embodiment basically includes the same steps as the manufacturing method of the semiconductor device according to the first embodiment, but the content of the overhang region forming step is the manufacturing of the semiconductor device according to the first embodiment. It is different from the method. Therefore, a manufacturing method of the semiconductor device according to the second embodiment will be described focusing on the overhang region forming step.

FIG. 9 is a view for explaining the method for manufacturing the semiconductor device according to the second embodiment.
In the manufacturing method of the semiconductor device according to the second embodiment, the overhang region forming step is performed as follows.

  First, a silicon carbide semiconductor substrate 110 is prepared as in the case of the method for manufacturing a semiconductor device according to the first embodiment.

  Thereafter, a mask M6 having an opening in a region corresponding to the first overhang region 134 and a region corresponding to the second overhang region 134a is formed, and the surface of the drift layer 114 is etched using the mask M6, whereby the drift layer A second trench is formed in a region corresponding to the first projecting region and a region corresponding to the second projecting region on the surface of 114 (see FIG. 9A). Then, after removing the mask 6, the first overhang region 134 and the second overhang region 134a are formed by filling the second trench with a p-type semiconductor material by an epitaxial growth method (see FIG. 9B).

  Thereafter, as in the case of the method of manufacturing a semiconductor device according to the first embodiment, a body layer forming step, a source region forming step, a body contact region forming step, a trench forming step, a gate insulating layer forming step, a gate electrode layer forming step, By performing the interlayer insulating layer forming step and the source electrode layer and drain electrode layer forming step, a semiconductor device (not shown) having the same structure as that of the semiconductor device 100 according to Embodiment 1 can be manufactured.

  As mentioned above, although this invention was demonstrated based on said embodiment, this invention is not limited to said embodiment. The present invention can be implemented in various modes without departing from the spirit thereof, and for example, the following modifications are possible.

(1) In each of the above embodiments, the present invention has been described with the n-type as the first conductivity type and the p-type as the second conductivity type, but the present invention is not limited to this. For example, the present invention can also be applied when the p-type is the first conductivity type and the n-type is the second conductivity type.

40,940 ... MOSFET portion, 50,950 ... protective diode portion, 100,800,900 ... semiconductor device, 110 ... silicon carbide semiconductor substrate, 112,812,912 ... low resistance semiconductor layer, 114,814,914 ... drift layer 116, 816, 916 ... body layer, 118, 818, 918 ... trench, 120, 820, 920 ... gate insulating layer, 122, 822, 922 ... gate electrode layer, 124, 824, 924 ... source region, 126, 926 , 926 ... Body contact region, 128, 828, 928 ... Interlayer insulating layer, 130, 830, 930 ... Source electrode layer, 132, 832, 932 ... Drain electrode layer, 134 ... First overhang region, 134a ... Second overhang region , 810, 910... Semiconductor substrate, L 1... L2 ... interval between the adjacent second projecting region 134a, M1, M2, M3, M4, M5, M6 ... Mask

Claims (10)

A semiconductor device comprising a MOSFET part and a protective diode part that causes avalanche breakdown at a lower voltage than that in the MOSFET part on the same silicon carbide semiconductor substrate,
The MOSFET section includes a first conductivity type low resistance semiconductor layer, a first conductivity type drift layer located on the low resistance semiconductor layer and containing a first conductivity type impurity having a lower concentration than the low resistance semiconductor layer, A body layer of a second conductivity type opposite to the first conductivity type located on the drift layer, a trench formed by opening the body layer and reaching the drift layer, and disposed in the body layer And a first conductivity type source region formed by exposing at least a part of the inner peripheral surface of the trench, a gate insulating layer formed on the inner peripheral surface of the trench, and an inner peripheral surface of the gate insulating layer A gate electrode layer formed between the body layer and the source electrode layer that is insulated from the gate electrode layer and is in contact with the source region, and a region sandwiched between the adjacent trenches. Has a first extending region of the second conductivity type formed so as to protrude toward the shift layer,
The protection diode unit includes a first conductivity type low resistance semiconductor layer, a first conductivity type drift layer located on the low resistance semiconductor layer and containing a first conductivity type impurity having a lower concentration than the low resistance semiconductor layer. A body layer of a second conductivity type located on the drift layer and opposite to the first conductivity type, and a plurality of second conductors formed so as to protrude from the body layer toward the drift layer Having a second overhang region of the mold,
2. A semiconductor device according to claim 1, wherein an interval L2 between the adjacent second extending regions is wider than an interval L1 between the adjacent first extending regions. The semiconductor device according to claim 1,
The deepest portion of the first overhang region and the deepest portion of the second overhang region are located deeper than the deepest portion of the trench. The semiconductor device according to claim 2,
The deepest portion of the first overhang region and the deepest portion of the second overhang region are deeper than the deepest portion of the trench by a value within a range of 0.5 μm to 4.5 μm. . The semiconductor device according to claim 1,
The interval L2 is in the range of 1.05 to 3.0 times the interval L1. In the semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the second overhang region is formed in the same process as the first overhang region. A manufacturing method of a semiconductor device for manufacturing the semiconductor device according to claim 1,
A silicon carbide semiconductor comprising a first conductivity type low-resistance semiconductor layer and a first conductivity type drift layer located on the low-resistance semiconductor layer and containing a first conductivity-type impurity at a concentration lower than that of the low-resistance semiconductor layer A silicon carbide semiconductor substrate preparation step of preparing a substrate;
A second conductivity type impurity is introduced into the region corresponding to the first overhang region and the region corresponding to the second overhang region on the surface of the drift layer by ion implantation, and activation annealing of the second conductivity type impurity is performed. An overhang region forming step of performing processing to form the first overhang region and the second overhang region;
Forming a body layer of the second conductivity type on the surface of the drift layer by an epitaxial growth method;
A source region for forming the source region by introducing a first conductivity type impurity into the region to be the source region on the surface of the body layer by ion implantation, and performing an activation annealing treatment of the first conductivity type impurity Forming process;
Forming a trench so as to open the body layer and reach the drift layer;
A gate insulating layer forming step of forming the gate insulating layer on the inner peripheral surface of the trench;
A gate electrode layer forming step of forming the gate electrode layer on an inner peripheral surface of the gate insulating layer;
An interlayer insulating layer forming step of forming an interlayer insulating layer so as to cover the gate electrode layer;
And a source electrode layer forming step of forming the source electrode layer so as to cover the body layer and the interlayer insulating layer. A manufacturing method of a semiconductor device for manufacturing the semiconductor device according to claim 1,
A silicon carbide semiconductor comprising a first conductivity type low-resistance semiconductor layer and a first conductivity type drift layer located on the low-resistance semiconductor layer and containing a first conductivity-type impurity at a concentration lower than that of the low-resistance semiconductor layer A silicon carbide semiconductor substrate preparation step of preparing a substrate;
A second trench is formed in a region corresponding to the first projecting region and a region corresponding to the second projecting region on the surface of the drift layer, and the second trench is made of a second conductivity type semiconductor material by an epitaxial growth method. A projecting region forming step of forming the first projecting region and the second projecting region by filling;
Forming a body layer of the second conductivity type on the surface of the drift layer by an epitaxial growth method;
A source region for forming the source region by introducing a first conductivity type impurity into the region to be the source region on the surface of the body layer by ion implantation, and performing an activation annealing treatment of the first conductivity type impurity Forming process;
Forming a trench so as to open the body layer and reach the drift layer;
A gate insulating layer forming step of forming the gate insulating layer on the inner peripheral surface of the trench;
A gate electrode layer forming step of forming the gate electrode layer on an inner peripheral surface of the gate insulating layer;
An interlayer insulating layer forming step of forming an interlayer insulating layer so as to cover the gate electrode layer;
And a source electrode layer forming step of forming the source electrode layer so as to cover the body layer and the interlayer insulating layer. In the manufacturing method of the semiconductor device according to claim 7,
In the overhang region forming step, the deepest portion and the second overhang region of the first overhang region so that the deepest portion of the first overhang region and the deepest portion of the second overhang region are deeper than the deepest portion of the trench. Forming a semiconductor device. In the manufacturing method of the semiconductor device according to claim 8,
In the overhang region forming step, the deepest portion of the first overhang region and the deepest portion of the second overhang region are deeper than the deepest portion of the trench by a value within a range of 0.5 μm to 3.0 μm. A method of manufacturing a semiconductor device, comprising forming a deepest portion of the first overhang region and a second overhang region. In the manufacturing method of the semiconductor device in any one of Claims 6-9,
In the overhang region forming step, the deepest portion of the first overhang region and the second overhang region are formed so that the interval L2 is within a range of 1.05 to 3.0 times the interval L1. A method of manufacturing a semiconductor device.

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