JP5732953B2 - Vector processing apparatus, vector processing method, and program - Google Patents

Description

  The present invention relates to a vector processing apparatus, a vector processing method, and a program suitable for improving processing performance by controlling instruction packets.

  As for the write control to the cache by the processor, there are known a write-through control for writing to the cache at the same time as writing data to the memory and a write-back control for writing only to the cache. The write-through control is simpler than the write-back control, but has a high frequency of access to the memory accompanying the store process and takes a long time for the store process. Therefore, the write-through control has a disadvantage that it becomes a restriction for improving the performance of the processor.

  In the vector processing device 9 including the scalar processing unit 91 and the vector processing unit 92 as shown in FIG. 12, the scalar processing unit 91 employs write-through control. For example, when data is written from the register to the memory 95, the data is written to the memory 95 at the same time as the data is written to the L1 cache 91a.

  Assume that the scalar processing unit 91 employs write-back control for writing data only to the L1 cache 91a. In this case, when the scalar processing unit 91 loads the data in the vector processing unit 92, the data stored in the L1 cache 91a is written back to the flash memory and the L1 cache for many address elements. Data transfer from 91a to the vector processing unit 92 is required. That is, when the write back control is employed, the control becomes very complicated, and the execution of the load instruction for the vector processing unit 92 may be stagnant. Therefore, in a vector processing apparatus in which a scalar processing unit and a vector processing unit are provided in parallel, write-through control is employed in order to avoid the above inconvenience. Since the vector processing apparatus employing the write-through control must write data to the memory 95 every time, more instruction packets are issued to the address conversion unit 93 than the processor employing the write-back control. .

  Since the number, format, or timing of instruction packets issued by a processor greatly affects the processing performance of the processor, various methods have been conventionally studied. For example, Patent Document 1 discloses a technique for adjusting the length of an instruction code issued by one processor and the cycle of issuing instructions according to data. However, in a vector processing apparatus having a plurality of processors, there is a limitation on the data writing method as described above, so it is necessary to consider the format of an instruction packet specialized for the vector processing apparatus.

  For example, when a scalar processing unit 91 that employs write-through control executes a scalar store instruction that stores data having a length of 1 to 8 bytes, an instruction packet having an 8-byte data field is used regardless of the data size to be stored. It was issued to the address conversion unit 93 and the like. Further, the scalar processing unit 91 issues one instruction packet when the address range for storing data does not cross a predetermined address boundary, and two instruction packets when the address range crosses a predetermined address boundary. For this reason, for example, when a scalar store instruction of data such as 1 or 2 bytes is executed for consecutive addresses, the entire 8-byte data field is not used, that is, a plurality of instruction packets with inefficient use of instruction packets are issued. Is done. Each time an instruction packet is issued, data must be transferred to the address conversion unit 93 and the memory network 94.

  On the other hand, the instruction packet issued from the scalar processing unit 91 is always issued to the address conversion unit 93 in the order in which the scalar processing unit 91 generates the instruction packet. In order to prioritize the arithmetic processing in the scalar processing unit 91 and the vector processing unit 92, it is often required to execute the load instruction preferentially over the store instruction unless the addresses of the memory to be accessed overlap. However, since the load instruction for the vector processing unit 92 covers a wide range of address areas to be processed, it is difficult in implementation to determine the overlap of the address areas one by one in the pipeline of the scalar processing unit 91 in which many instructions exist. is there. Therefore, in the vector processing device 9 in which the scalar processing unit 91 and the vector processing unit 92 are provided in parallel, the overtaking control between the store instruction for the scalar processing unit 91 and the load instruction for the vector processing unit 92 has conventionally been performed. It wasn't.

JP 2005-267215 A

  The format of the instruction packet as described above has a problem that a plurality of instruction packets are issued despite a small amount of data to be stored, and the load of data transfer is large. Such a data transfer load also causes a load or store process in the vector processing unit to be delayed, causing a reduction in the performance of the entire vector processing apparatus.

  Further, if the address of the store instruction and the address of the load instruction do not overlap, it is required to increase the processing speed of the vector processing device by overtaking the instruction packet of the load instruction and executing it preferentially. .

  An object of the present invention is to solve the above-described problems, and to provide a vector processing apparatus, a vector processing method, and a program suitable for improving processing performance by controlling an instruction packet. And

A vector processing apparatus according to the first aspect of the present invention provides:
A vector processing apparatus comprising a scalar processing unit that performs a scalar operation, a vector processing unit that performs a vector operation, and a storage unit,
The scalar processing unit is
Issuing a first instruction packet and a second instruction packet indicating an instruction to load data from the storage unit or an instruction to store data in the storage unit;
An instruction packet buffer unit for storing a first instruction packet issued by the scalar processing unit;
It determines the type of the second command packet issued after said first command packet and the first instruction packet, the first address of the first instruction packet designated, the second instruction A buffer control unit that compares a second address specified by the packet and outputs an instruction to combine the first instruction packet and the second instruction packet;
A combining processor that combines the first instruction packet and the second instruction packet based on the output instruction;
With
The buffer control unit
The instruction indicated by the first instruction packet is a scalar store instruction, the instruction indicated by the second instruction packet is (a) a scalar store instruction, and the first address matches the second address. The combination processing unit outputs the combination instruction, the combined packet is stored in the instruction packet buffer unit as the first instruction packet , and the first address and the second address do not match , Outputting the first instruction packet, causing the second instruction packet to be stored in the instruction packet buffer unit as the first instruction packet,
(B) a vector load instruction, when said first address and said second address does not overlap, the second outputs an instruction packet, the second address and the first address duplicate If so, the first instruction packet is output, the second instruction packet is stored in the instruction packet buffer unit as the first instruction packet,
(C) In the case of a scalar load instruction, when the first address and the second address do not match, the second instruction packet is output , and the first address and the second address match Output the first instruction packet, store the second instruction packet as the first instruction packet in the instruction packet buffer unit,
(D) In the case of a vector store instruction, when the first address and the second address do not overlap, the second instruction packet is output, and the first address and the second address overlap. In this case, the first instruction packet is output, and the second instruction packet is stored in the instruction packet buffer unit as the first instruction packet .

A vector processing method according to the second aspect of the present invention provides:
A scalar processing unit that performs a scalar operation; a vector processing unit that performs a vector operation; and a storage unit, wherein the scalar processing unit loads data from the storage unit or stores data in the storage unit The first instruction packet and the second instruction packet are issued, and the scalar processing unit includes an instruction packet buffer unit, a buffer control unit, and a combination processing unit. A vector processing method for
The vector processing method is
An instruction packet buffer step in which the instruction packet buffer unit stores a first instruction packet issued by the scalar processing unit;
The buffer control unit determines the type of the second command packet issued after said first command packet and the first instruction packet, the first address of the first instruction packet designated compares the second address the second instruction packet is specified, the buffer control step of outputting an instruction to combine said first instruction packet and said second instruction packet,
A combining processing step in which the combining processing unit combines the first instruction packet and the second instruction packet based on the output instruction;
With
In the buffer control step, the buffer control unit includes:
The instruction indicated by the first instruction packet is a scalar store instruction, the instruction indicated by the second instruction packet is (a) a scalar store instruction, and the first address matches the second address. The combination processing unit outputs the combination instruction, the combined packet is stored in the instruction packet buffer unit as the first instruction packet , and the first address and the second address do not match , Outputting the first instruction packet, causing the second instruction packet to be stored in the instruction packet buffer unit as the first instruction packet,
(B) a vector load instruction, when said first address and said second address does not overlap, the second outputs an instruction packet, the second address and the first address duplicate If so, the first instruction packet is output, the second instruction packet is stored in the instruction packet buffer unit as the first instruction packet,
(C) In the case of a scalar load instruction, when the first address and the second address do not match, the second instruction packet is output , and the first address and the second address match Output the first instruction packet, store the second instruction packet as the first instruction packet in the instruction packet buffer unit,
(D) In the case of a vector store instruction, when the first address and the second address do not overlap, the second instruction packet is output, and the first address and the second address overlap. In this case, the first instruction packet is output, and the second instruction packet is stored in the instruction packet buffer unit as the first instruction packet .

The program according to the third aspect of the present invention is:
Computer
A scalar processing unit that performs a scalar operation; a vector processing unit that performs a vector operation; and a storage unit, wherein the scalar processing unit loads data from the storage unit or stores data in the storage unit A program for functioning as a vector processing device that issues a first instruction packet and a second instruction packet indicating
The program causes the computer to
In the scalar processing unit,
An instruction packet buffer unit for storing a first instruction packet issued by the scalar processing unit;
It determines the type of the second command packet issued after said first command packet and the first instruction packet, the first address of the first instruction packet designated, the second instruction A buffer control unit that compares a second address specified by the packet and outputs an instruction to combine the first instruction packet and the second instruction packet;
A combining processor that combines the first instruction packet and the second instruction packet based on the output instruction;
Function as
The buffer control unit
The instruction indicated by the first instruction packet is a scalar store instruction, the instruction indicated by the second instruction packet is (a) a scalar store instruction, and the first address matches the second address. The combination processing unit outputs the combination instruction, the combined packet is stored in the instruction packet buffer unit as the first instruction packet , and the first address and the second address do not match , Outputting the first instruction packet, causing the second instruction packet to be stored in the instruction packet buffer unit as the first instruction packet,
(B) a vector load instruction, when said first address and said second address does not overlap, the second outputs an instruction packet, the second address and the first address duplicate If so, the first instruction packet is output, the second instruction packet is stored in the instruction packet buffer unit as the first instruction packet,
(C) In the case of a scalar load instruction, when the first address and the second address do not match, the second instruction packet is output , and the first address and the second address match Output the first instruction packet, store the second instruction packet as the first instruction packet in the instruction packet buffer unit,
(D) In the case of a vector store instruction, when the first address and the second address do not overlap, the second instruction packet is output, and the first address and the second address overlap. The first instruction packet is output, and the second instruction packet is stored in the instruction packet buffer unit as the first instruction packet.
It is made to function as follows.

  The above program can be distributed and sold via a computer communication network independently of the computer on which the program is executed. The recording medium storing the program can be distributed and sold independently from the computer.

  According to the present invention, in the vector processing device, by providing a buffer for holding an instruction packet of a store instruction in the scalar processing unit, a combination of a plurality of store instruction packets and an overtaking control between instruction packets can be performed. Thereby, the number of store instruction packets issued from the scalar processing unit can be reduced, vector load / store instructions can be overtaken, and the processing performance can be improved.

It is a figure for demonstrating the vector processing apparatus by which the vector processing apparatus which concerns on embodiment of this invention is implement | achieved. It is a figure for demonstrating the format of an instruction packet. 3 is a diagram for explaining a scalar processing unit according to the first embodiment. FIG. It is a figure for demonstrating the combination process of an instruction packet. FIG. 5 is a flowchart for explaining instruction packet control processing performed by each unit of the instruction buffer unit according to the first embodiment. It is a flowchart for demonstrating a scalar store instruction packet control process. It is a flowchart for demonstrating a vector load / store instruction packet control process. It is a flowchart for demonstrating a scalar load instruction packet control process. It is a flowchart figure for demonstrating other command packet control processing. It is a flowchart for demonstrating control processing of the command packet which is not effective. FIG. 10 is a flowchart for explaining instruction packet control processing performed by each unit of an instruction buffer unit according to the second embodiment. It is a figure for demonstrating the conventional vector processing apparatus.

(1. Outline Configuration of Vector Processing Device of Embodiment 1)
The vector processing apparatus according to the embodiment of the present invention is typically realized by the vector processing apparatus 1 shown in FIG. Hereinafter, a schematic configuration of the vector processing device 1 will be described.

  As shown in FIG. 1, the vector processing device 1 includes a scalar processing unit 11, a vector processing unit 12, an address conversion unit 13, a memory network 14, and a memory 15.

  The vector processing apparatus 1 includes a “scalar store instruction” for storing data stored in the scalar register in the scalar processing unit 11 in the memory 15, a “scalar load instruction” for reading data from the memory 15 into the scalar register, and vector processing. A “vector store instruction” for storing data stored in the vector register in the unit 12 in the memory 15 and a “vector load instruction” for reading data from the memory 15 into the vector register are handled. Hereinafter, the function of each unit will be described by taking as an example the case where the vector processing apparatus 1 handles these instructions.

  The scalar processing unit 11 includes, for example, an L1 cache 11a, an instruction buffer unit 11b, a scalar register that stores scalar data (not shown), and various arithmetic units (not shown). The scalar processing unit 11 fetches, decodes, schedules, and executes various instructions according to a predetermined program. The scalar processing unit 11 sends “instruction packets” indicating various control instructions including load / store instructions and vector operations to the components in the vector processing device 1 such as the vector processing unit 12 and the address conversion unit 13. Issue.

  Hereinafter, an instruction packet indicating a scalar store instruction issued by the scalar processing unit 11 is a “scalar store instruction packet”, an instruction packet indicating a scalar load instruction is “scalar load instruction packet”, and an instruction packet indicating a vector store instruction is “vector load” An instruction packet ”and a packet indicating a vector load instruction are referred to as a“ vector load instruction packet ”. In addition, an instruction packet indicating all instructions issued by the scalar processing unit 11 (for example, a page switching instruction and an instruction for performing communication between processors) other than the scalar load / store instruction and the vector load / store instruction. “Other instruction packets”. The format of each instruction packet is shown in FIG. Other command packet formats are arbitrary and will be omitted below.

  As shown in FIG. 2A, the scalar store instruction packet 200 includes an instruction code 201, an address 202, a byte enable 203, and store data 204.

  The instruction code 201 indicates the instruction type or packet format.

  The address 202 indicates an address on the memory 15 where the store data 204 is stored. It is assumed that the address 202 can only take a value that is a multiple of 8.

  The byte enable 203 is 8-bit width information indicating which byte contains the store data 204 (valid) by dividing the 64-bit width store data 204 in units of 1 byte.

  The store data 204 is 64-bit width data stored in the memory 15.

  That is, the scalar store instruction packet 200 indicates an instruction for storing the store data 204 at the designated address 202.

  As shown in FIG. 2B, the scalar load instruction packet 300 includes an instruction code 301 and an address 302.

  Similar to the instruction code 201, the instruction code 301 indicates the type of instruction or the packet format.

  An address 302 indicates an address on the memory 15 of data read by the scalar processing unit 11.

  That is, the scalar load instruction packet 300 indicates an instruction for reading data on the memory 15 designated by the address 302.

  As shown in FIG. 2C, the vector load / store instruction packet 400 includes an instruction code 401, a base address 402, a distance 403, and an element number 404.

  As with the instruction code 201, the instruction code 401 indicates the type of instruction or packet format.

  The base address 402 indicates an address on the memory 15.

  A distance 403 indicates a distance from the base address 402.

  The element number 404 indicates the number of addresses.

  Here, if the base address 402 is “X”, the distance 403 is “Y”, and the number of elements 404 is “N”, the addresses specified by the vector load / store instruction packet are X, X + Y, X + 2 * Y,. X + (N-1) * Y.

  That is, the vector load / store instruction packet 400 is an address that is separated from the base address 402 and the base address 402 by an integer multiple of the distance 403, and commands for reading or writing data are simultaneously sent to several addresses. It is shown.

  When executing the scalar store instruction, the scalar processing unit 11 determines the address 202 and the store data 204, shapes them into an instruction packet having the format shown in FIG. Further, when executing the scalar load instruction, the scalar processing unit 11 determines the address 302, shapes it into an instruction packet having the format shown in FIG. 2B, and sends it to the address conversion unit 13.

  On the other hand, when executing the vector load / store instruction, the scalar processing unit 11 determines the base address 402, the distance 403, and the number of elements 404, and shapes them into an instruction packet having the format shown in FIG. Then, the scalar processing unit 11 sends the instruction packet to the address conversion unit 13 and delivers it to the vector processing unit 12 via the address conversion unit 13.

  The vector processing unit 12 includes a vector register for storing vector data and various arithmetic units (not shown). The vector processing unit 12 performs various arithmetic processes based on instructions from the scalar processing unit 11 or transmits / receives load / store data to / from the address conversion unit 13. For example, when the vector processing unit 12 receives a vector store instruction packet from the scalar processing unit 11, it sends the data stored in the vector register to the address conversion unit 13.

  The address conversion unit 13 performs conversion from a logical address to a physical address, if necessary, when performing data load / store performed by the scalar processing unit 11 or the vector processing unit 12, and schedules data transfer to the memory 15. Do.

  When the address conversion unit 13 receives the scalar store instruction packet from the scalar processing unit 11, the address conversion unit 13 interprets the content of the instruction packet and performs conversion processing to a physical address. Then, the address conversion unit 13 transfers the converted address and the store data 204 to the memory 15 via the memory network 14.

  When the address conversion unit 13 receives the scalar load instruction packet from the scalar processing unit 11, the address conversion unit 13 interprets the content of the instruction packet and performs conversion processing to a physical address. Then, the address conversion unit 13 transfers the converted address to the memory 15 via the memory network 14.

  When the address conversion unit 13 receives the vector store instruction packet from the scalar processing unit 11 and receives data from the vector processing unit 12, the address conversion unit 13 expands the physical address to the address specified by the base address, the distance, and the number of elements. Convert to. Then, the address conversion unit 13 transfers the converted address or store data to the memory 15 via the memory network 14.

  When receiving the instruction packet of the vector load instruction from the scalar processing unit 11, the address conversion unit 13 performs expansion to a real address and conversion to a physical address. Then, the address conversion unit 13 transfers the converted address to the memory 15 via the memory network 14.

  The memory network 14 performs data transfer between the address conversion unit 13 and the memory 15.

  The memory 15 stores data that the scalar processing unit 11 or the vector processing unit 12 reads or writes.

(2. Outline configuration of scalar processing unit of embodiment 1)
Hereinafter, a schematic configuration of the scalar processing unit of the present embodiment included in the vector processing device 1 will be specifically described.
The scalar processing unit of Embodiment 1 combines and overtakes instruction packets.

  The scalar processing unit 11 includes an L1 cache 11a and an instruction buffer unit 11b.

  The L1 cache 11a stores data frequently used in the scalar processing unit 11. The scalar processing unit 11 updates the contents of the L1 cache 11a and simultaneously writes data to the memory 15 when executing the scalar store instruction.

  The instruction buffer unit 11b is for combining or overtaking an instruction packet issued by the scalar processing unit 11. The instruction buffer unit 11 b receives an instruction packet before the scalar processing unit 11 sends the instruction packet to the address conversion unit 13. As shown in FIG. 3, the instruction buffer unit 11b includes an address comparison / buffer control unit 11b1, an instruction packet buffer unit 11b2, and a combination processing unit 11b3, and is configured as follows.

  The address comparison / buffer control unit 11b1 includes an instruction packet received by the instruction buffer unit 11b (hereinafter referred to as “accepted instruction packet”) and an instruction packet stored in the instruction packet buffer unit 11b2 (hereinafter referred to as “held instruction packet”). )). Then, the address of the holding instruction packet is compared with the address of the reception instruction packet. Here, the holding instruction packet is an instruction packet received prior to the reception instruction packet. That is, the address comparison / buffer control unit 11b1 determines the type of the preceding instruction packet (holding instruction packet) and the subsequent instruction packet (acceptance instruction packet), and compares the addresses of both instruction packets. Then, the address comparison / buffer control unit 11b1 instructs to combine the preceding instruction packet and the subsequent instruction packet or overtake between instructions based on the types of the reception instruction packet and the holding instruction packet and the comparison result.

  The instruction packet buffer unit 11b2 is a buffer that holds one instruction packet received by the instruction buffer unit 11b.

  The combination processing unit 11b3 combines instruction packets into one based on an instruction from the address comparison / buffer control unit 11b1.

  Hereinafter, specific functions of the address comparison / buffer control unit 11b1 will be described.

  When the instruction packet of the format of FIG. 2 is generated from the scalar processing unit 11, the instruction packet is first sent to the instruction buffer unit 11b. When the instruction buffer unit 11b receives the instruction packet, the address comparison / buffer control unit 11b1 determines that the received instruction packet includes (A) a scalar store instruction packet, (B) a vector load / store instruction packet, and (C) a scalar load instruction packet. , (D) any other instruction packet, and (E) an invalid instruction packet.

  The scalar processing unit 11 always generates and outputs an “instruction packet” including some signal, and the signal included in the instruction packet is ignored when it indicates an instruction to be actually executed. Sometimes it should be. Therefore, the address comparison / buffer control unit 11b1 also determines whether or not the reception instruction packet is “valid”. Here, the instruction packet is “valid” means that the instruction packet includes information on an instruction to be actually executed with an effective bit “1”. That is, valid instruction packets include (A) scalar store instructions, (B) vector load / store instructions, (C) scalar load instructions, or (D) instruction packets of other instructions. On the other hand, “invalid” packet means that the instruction packet has a valid bit “0” and does not include information on an instruction to be executed.

  Next, the address comparison / buffer control unit 11b1 determines whether or not the retained instruction packet is “valid”.

  When the received instruction packet is (A) a scalar store instruction packet and the hold instruction packet is valid, the address comparison / buffer control unit 11b1 determines whether the hold instruction packet is a scalar store instruction packet or a scalar store instruction packet. For example, it is determined whether the addresses of the reception instruction packet and the holding instruction packet match. If the holding instruction packet is a scalar store instruction packet and the addresses match, the address comparison / buffer control unit 11b1 combines the holding instruction packet and the reception instruction packet. The address comparison / buffer control unit 11b1 holds the combined packet (hereinafter referred to as “combined instruction packet”) in the instruction packet buffer unit 11b2.

An example of the combination of the hold command packet and the reception command packet will be described with reference to FIG.
4A is a holding instruction packet, FIG. 4B is a reception instruction packet, and FIG. 4C is a combination of a holding instruction packet (FIG. 4A) and a reception instruction packet (FIG. 4B). This is an instruction packet (combined instruction packet) after being performed.

  The instruction code 701 of the combined instruction packet indicates a scalar store instruction and is the same as the instruction codes 501 and 601. The address 702 is the same as the addresses 502 and 602. Assume that the byte enable 703 of the combined instruction packet is obtained by performing an OR process on the byte enable 503 of the hold instruction packet and the byte enable 603 of the reception instruction packet. Assume that the combined instruction packet store data 704 is obtained by selecting the valid one indicated by the hold instruction packet store data 504 and the accept instruction packet store data 604 in units of 1 byte. However, when valid bytes exist in both packets, it is considered that the store instructions for the same address are consecutive, and the store data 604 of the reception instruction packet received late is given priority.

  On the other hand, if the received instruction packet is (A) a scalar store instruction packet, and (i) the held instruction packet is determined to be invalid, (ii) the held instruction packet is a valid instruction packet other than the scalar store instruction packet. Or (iii) if the hold instruction packet is a scalar store instruction packet and the addresses do not match, the address comparison / buffer control unit 11b1 causes the address conversion unit 13 to output the hold instruction packet and A scalar store instruction packet is held in the instruction packet buffer unit 11b2.

  Thereby, when executing a scalar store instruction to the same address, the number of instruction packets issued from the scalar processing unit 11 to the address conversion unit 13 can be reduced. As a result, the data transfer bandwidth can be made efficient and the data transfer load of the memory network 14 and the like can be reduced. On the other hand, even if the preceding instruction and the subsequent instruction are scalar store instructions, if the addresses targeted by both instructions do not match, the instruction packets are not overtaken and the instruction packets are issued in the order in which the instructions were generated. Can do.

  When the received instruction packet is (B) vector load / store instruction packet and the hold instruction packet is valid, the address comparison / buffer control unit 11b1 determines whether the hold instruction packet is a scalar store instruction packet or a scalar store instruction packet. If so, it is determined whether the addresses of the reception instruction packet and the holding instruction packet overlap. When the reception instruction packet is (B) vector load / store instruction packet and the holding instruction packet is a scalar store instruction packet and their addresses do not overlap, or the reception instruction packet is (B) vector load / store instruction When the hold instruction packet is not valid, the address comparison / buffer control unit 11b1 outputs the vector load / store instruction packet, which is the reception instruction packet, to the address conversion unit 13 by overtaking the hold instruction packet.

  On the other hand, if the reception instruction packet is (B) vector load / store instruction packet and the holding instruction packet is a scalar store instruction packet and their addresses overlap, or the reception instruction packet is (B) vector load / store If it is a store instruction packet and the hold instruction packet is valid but not a scalar store instruction packet, the address comparison / buffer control unit 11b1 outputs the hold instruction packet to the address conversion unit 13, and receives a reception instruction packet (vector load / Store the instruction packet) in the instruction packet buffer unit 11b2.

  Thus, if the addresses do not overlap, overtaking control can be performed in which the vector load / store instruction is executed with priority over the scalar store instruction.

  When the received instruction packet is (C) a scalar load instruction packet and the hold instruction packet is valid, the address comparison / buffer control unit 11b1 determines whether the hold instruction packet is a scalar store instruction packet or a scalar store instruction packet. For example, it is determined whether the addresses of the reception instruction packet and the holding instruction packet match. When the reception instruction packet is (C) a scalar load instruction packet and the holding instruction packet is a scalar store instruction packet and their addresses do not match, or the reception instruction packet is (C) a scalar load instruction packet When the hold instruction packet is not valid, the address comparison / buffer control unit 11b1 outputs the scalar load instruction packet, which is the reception instruction packet, to the address conversion unit 13 by overtaking the hold instruction packet.

  On the other hand, if the reception instruction packet is (C) a scalar load instruction packet and the holding instruction packet is a scalar store instruction packet and the addresses match, or the reception instruction packet is (C) a scalar load instruction packet, When the hold instruction packet is valid but not the scalar store instruction packet, the address comparison / buffer control unit 11b1 outputs the hold instruction packet to the address conversion unit 13, and receives the reception instruction packet (scalar load instruction packet). 11b2.

  Thereby, if the addresses do not match, overtaking control can be performed in which the scalar load instruction is executed with priority over the scalar store instruction.

  When the received command packet is (D) other command packet and the held command packet is valid, the address comparison / buffer control unit 11b1 outputs the held command packet to the address converting unit 13, and receives the received command packet (others). Instruction packet) is held in the instruction packet buffer unit 11b2.

  On the other hand, when the received command packet is (D) other command packet and the held command packet is not valid, the address comparison / buffer control unit 11b1 uses the received command packet as it is as the address conversion unit. 13 to output.

  As a result, other command packets that are valid packets can be output with priority over packets that are not valid.

  When the received instruction packet is (E) an invalid instruction packet and the retained instruction packet is valid, the address comparison / buffer control unit 11b1 determines whether or not the retained instruction packet is a scalar store instruction packet. When the received instruction packet is (E) an invalid instruction packet and the retained instruction packet is a scalar store instruction packet, the address comparison / buffer control unit 11b1 holds the retained instruction packet in the instruction packet buffer unit 11b2. The reception instruction packet is output to the address conversion unit 13 as it is.

  On the other hand, when the reception instruction packet is (E) an invalid instruction packet and the holding instruction packet is an invalid instruction packet other than a scalar store instruction packet, or the reception instruction packet is (E) an invalid instruction packet, If the retained instruction packet is also an invalid instruction packet, the address comparison / buffer control unit 11b1 outputs the retained instruction packet to the address conversion unit 13, and retains the received instruction packet (invalid instruction packet) in the instruction packet buffer unit 11b2. Let

  Thereby, it is possible to prevent the instruction packet from staying in the instruction packet buffer unit 11b2 when a valid packet does not follow.

(3. Operation of instruction buffer unit of embodiment 1)
The operation of the instruction buffer unit that executes the combination process and the overtaking control process will be described below. When the vector processor 1 is turned on, the instruction buffer unit 11b starts an instruction packet control process shown in the flowchart of FIG.

  The address comparison / buffer control unit 11b1 determines whether or not an instruction packet has been received (step S11). If it is determined that the instruction packet has been received (step S11; Yes), the address comparison / buffer control unit 11b1 determines the type of the received instruction packet (accepted instruction packet) (step S12). On the other hand, when it is determined that the instruction packet has not been received (step S11; No), the process waits as it is.

When the address comparison / buffer control unit 11b1 determines that the received instruction packet is a “scalar store instruction packet” (step S12; a scalar store instruction packet), it starts a scalar store instruction packet control process (FIG. 6) (step S12). S13).
When the address comparison / buffer control unit 11b1 determines that the received instruction packet is a “vector load / store instruction packet” (step S12; vector load / store instruction packet), vector load / store instruction packet control processing (FIG. 7). ) Is started (step S14).
When the address comparison / buffer control unit 11b1 determines that the received instruction packet is a “scalar load instruction packet” (step S12; a scalar load instruction packet), it starts a scalar load instruction packet control process (FIG. 8) (step 8). S15).
When the address comparison / buffer control unit 11b1 determines that the received instruction packet is “other instruction packet” (step S12; other instruction packet), the other instruction packet control process (FIG. 9) is started (step 9). S16).
If the address comparison / buffer control unit 11b1 determines that the received instruction packet is an “invalid instruction packet” (step S12; invalid instruction packet), it starts control processing (FIG. 10) of the invalid instruction packet (FIG. 10). Step S17).

(3.1 Scalar store instruction packet control processing)
The address comparison / buffer control unit 11b1 determines whether or not the retained instruction packet is valid (step S131). If it is determined that the hold instruction packet is valid (step S131; Yes), the address comparison / buffer control unit 11b1 determines whether the hold instruction packet is a scalar store instruction packet (step S132). On the other hand, when it is determined that the retained instruction packet is not valid (step S131; No), the address comparison / buffer control unit 11b1 outputs the currently retained invalid instruction packet to the address conversion unit 13, and receives the received instruction packet. (Scalar store instruction packet) is held in the instruction packet buffer unit 11b2 (step S135).

  If it is determined in step S132 that the holding instruction packet is a scalar store instruction packet (step S132; Yes), the address comparison / buffer control unit 11b1 accepts the address of the holding instruction packet (preceding scalar store instruction packet). The address of the instruction packet (subsequent scalar store instruction packet) is compared (step S133).

  On the other hand, when it is determined in step S132 that the held instruction packet is a valid instruction packet other than the scalar store instruction packet (step S132; No), the address comparison / buffer control unit 11b1 converts the held instruction packet into an address conversion unit. The received instruction packet (scalar store instruction packet) is held in the instruction packet buffer unit 11b2 (step S135). That is, when the received instruction packet is a scalar store instruction packet and the held instruction packet is a valid instruction packet other than the scalar store instruction packet, the address comparison / buffer control unit 11b1 generates an instruction packet without performing overtaking control. The instruction packets are output to the address conversion unit 13 in the order in which they are performed.

  If it is determined in step S133 that the address of the holding instruction packet matches the address of the reception instruction packet (step S133; Yes), the address comparison / buffer control unit 11b1 combines the holding instruction packet and the reception instruction packet. The combined instruction packet is held in the instruction packet buffer unit 11b2 (step S134). For example, when the holding instruction packet is the instruction packet shown in FIG. 4A and the reception instruction packet is the instruction packet shown in FIG. 4B, the address comparison / buffer control unit 11b1 combines them to The instruction packet shown in 4 (c) is generated. Then, the address comparison / buffer control unit 11b1 holds the generated instruction packet in the instruction packet buffer unit 11b2.

  On the other hand, if it is determined in step S133 that the addresses do not match (step S133; No), the address comparison / buffer control unit 11b1 outputs the retained instruction packet (the preceding scalar store instruction packet) to the address conversion unit 13. The reception instruction packet (subsequent scalar store instruction packet) is held in the instruction packet buffer unit 11b2 (step S135).

  After the process of step S134 or step S135, the address comparison buffer control unit 13 ends the scalar store instruction packet control process.

(3.2 Vector load / store instruction packet control processing)
The address comparison / buffer control unit 11b1 determines whether or not the hold instruction packet is valid (step S141). If it is determined that the hold instruction packet is valid (step S141; Yes), the address comparison / buffer control unit 11b1 determines whether the hold instruction packet is a scalar store instruction packet (step S142). On the other hand, when it is determined that the hold instruction packet is not valid (step S141; No), the address comparison / buffer control unit 11b1 outputs the reception instruction packet (vector load / store instruction packet) to the address conversion unit 13 as it is ( Step S145).

  If it is determined in step S142 that the holding instruction packet is a scalar store instruction packet (step S142; Yes), the address comparison / buffer control unit 11b1 determines the address of the holding instruction packet (scalar store instruction packet) and the received instruction packet. The address of (vector load / store instruction packet) is compared (step S143).

  On the other hand, when it is determined in step S142 that the held instruction packet is a valid instruction packet other than the scalar store instruction packet (step S142; No), the address comparison / buffer control unit 11b1 converts the held instruction packet into an address conversion unit. The received instruction packet (vector load / store instruction packet) is held in the instruction packet buffer unit 11b2 (step S144). That is, when the reception instruction packet is a vector load / store instruction packet and the holding instruction packet is a valid instruction packet other than the scalar store instruction packet, the address comparison / buffer control unit 11b1 does not perform overtaking control, The instruction packets are output to the address translation unit 13 in the order in which the packets are generated.

  In step S143, when the address of the holding instruction packet and the address of the reception instruction packet, that is, the number of elements based on the base address overlap (step S143; Yes), the address comparison / buffer control unit 11b1 The held instruction packet (scalar store instruction packet) is output to the address conversion unit 13, and the reception instruction packet (vector load / store instruction packet) is held in the instruction packet buffer unit 11b2 (step S144).

  On the other hand, if it is determined in step S143 that the addresses do not overlap (step S143; No), the address comparison / buffer control unit 11b1 holds the held instruction packet (scalar store instruction packet) as it is, and receives the received instruction packet (vector The load / store instruction packet) is prioritized and output to the address translation unit 13 (step S145).

  After the processes in steps S144 and S145, the address comparison buffer control unit 13 ends the vector load / store instruction packet control process.

(3.3 Scalar load instruction packet control processing)
The address comparison / buffer control unit 11b1 determines whether or not the retained instruction packet is valid (step S151). If it is determined that the hold instruction packet is valid (step S151; Yes), the address comparison / buffer control unit 11b1 determines whether the hold instruction packet is a scalar store instruction packet (step S152). On the other hand, when it is determined that the hold instruction packet is not valid (step S151; No), the address comparison / buffer control unit 11b1 outputs the reception instruction packet (scalar load instruction packet) as it is to the address conversion unit 13 (step S155). ).

  If it is determined in step S152 that the holding instruction packet is a scalar store instruction packet (step S152; Yes), the address comparison / buffer control unit 11b1 determines the address of the holding instruction packet (scalar store instruction packet) and the received instruction packet. The address of the (scalar load instruction packet) is compared (step S153).

  On the other hand, when it is determined in step S152 that the held instruction packet is a valid instruction packet other than the scalar store instruction packet (step S152; No), the address comparison / buffer control unit 11b1 converts the held instruction packet into an address conversion unit. 13, the reception instruction packet (scalar load instruction packet) is held in the instruction packet buffer unit 11b2 (step S154). That is, when the received instruction packet is a scalar load instruction packet and the held instruction packet is a valid instruction packet other than a scalar store instruction packet, the address comparison / buffer control unit 11b1 does not perform overtaking control and generates an instruction packet. The instruction packets are output to the address conversion unit 13 in the order in which they are performed.

  If it is determined in step S153 that the address of the holding instruction packet matches the address of the receiving instruction packet (step S153; Yes), the address comparison / buffer control unit 11b1 addresses the holding instruction packet (scalar store instruction packet). The received instruction packet (scalar load instruction packet) is output to the conversion unit 13 and held in the instruction packet buffer unit 11b2 (step S154).

  On the other hand, if it is determined in step S153 that the addresses do not match (step S153; No), the address comparison / buffer control unit 11b1 holds the held instruction packet (scalar store instruction packet) as it is, and receives the received instruction packet (scalar). The load command packet) is prioritized and output to the address translation unit 13 (step S155).

  After the processes of step S154 and step S155, the address comparison buffer control unit 13 ends the scalar load instruction packet control process.

(3.4 Other instruction packet control processing)
The address comparison / buffer control unit 11b1 determines whether or not the retained instruction packet is valid (step S161). When it is determined that the hold command packet is valid (step S161; Yes), the address comparison / buffer control unit 11b1 outputs the hold command packet to the address conversion unit 13, and receives the reception command packet (other command packets). The instruction packet buffer unit 11b2 holds the instruction packet (step S162). On the other hand, if it is determined that the retained instruction packet is not valid (step S161; No), the address comparison / buffer control unit 11b1 outputs the received instruction packet as it is to the address conversion unit 13 (step S163).

  After the processing of step S162 and step S163, the address comparison buffer control unit 13 ends the other instruction packet control processing.

(3.5 Control processing of invalid instruction packet)
The address comparison / buffer control unit 11b1 determines whether or not the retained instruction packet is valid (step S171). If it is determined that the hold instruction packet is valid (step S171; Yes), the address comparison / buffer control unit 11b1 determines whether the hold instruction packet is a scalar store instruction packet (step S172). On the other hand, when it is determined that the retained instruction packet is not valid (step S171; No), the address comparison / buffer control unit 11b1 outputs the currently retained invalid instruction packet to the address conversion unit 13, and receives the received instruction packet. (Invalid instruction packet) is held in the instruction packet buffer unit 11b2 (step S174).

  If it is determined in step S172 that the holding instruction packet is a scalar store instruction packet (step S172; Yes), the address comparison / buffer control unit 11b1 converts the holding instruction packet (scalar store instruction packet) into the instruction packet buffer unit 11b2. The received instruction packet (invalid instruction packet) is output to the address conversion unit 13 as it is (step S173).

  On the other hand, when it is determined in step S172 that the held instruction packet is a valid instruction packet other than the scalar store instruction packet (step S172; No), the address comparison / buffer control unit 11b1 converts the held instruction packet into an address conversion unit. The received instruction packet (invalid instruction packet) is held in the instruction packet buffer unit 11b2 (step S174).

  After the processes in steps S173 and S174, the address comparison buffer control unit 13 ends the control process for the invalid instruction packet.

  According to the present embodiment, the number of instruction packets issued to the address translation unit can be reduced, and the data transfer load can be reduced. If the address of the store instruction and the address of the load instruction do not overlap, the load instruction can be overtaken and executed preferentially, and the processing speed of the vector processing device can be increased.

(4. Outline Configuration of Vector Processing Device of Embodiment 2)
As shown in FIG. 1, the vector processing device 1 according to the second embodiment includes a scalar processing unit 11, a vector processing unit 12, an address conversion unit 13, a memory network 14, a memory 15, Consists of The vector processing unit 12, the address conversion unit 13, the memory network 14, and the memory 15 have the same functions as those in the first embodiment.

(5. Outline configuration of scalar processing unit of embodiment 2)
In addition to the functions of the first embodiment, the scalar processing unit of the second embodiment has a function of outputting a retained instruction packet even when there is no instruction packet to be compared when the instruction packet is retained for a certain period of time. .
The address comparison / buffer control unit 11b1 that implements functions different from those of the vector processing apparatus of the first embodiment will be described below.

  The address comparison / buffer control unit 11b1 includes a counter (not shown), and controls the instruction packet buffer unit 11b2 as follows during a period in which the instruction buffer unit 11b does not accept an instruction packet.

  The address comparison / buffer control unit 11b1 measures an elapsed time after the instruction packet is held in the instruction packet buffer unit 11b2 by a counter. Then, the address comparison / buffer control unit 11b1 outputs the retained instruction packet to the address conversion unit 13 when the predetermined time has elapsed. On the other hand, when the elapsed time does not exceed the predetermined threshold, the address comparison / buffer control unit 11b1 waits while holding the instruction packet in the instruction packet buffer unit 11b2.

  As a result, it is possible to prevent the instruction packet from staying in the instruction packet buffer unit 11b1 and delaying the processing of the entire vector processing apparatus 1. In addition, it is possible to ensure that the time required for processing the store instruction is below a certain value.

(6. Operation of instruction buffer unit of embodiment 2)
Hereinafter, operations performed by each unit of the instruction buffer unit of the present embodiment will be described. When the vector processing apparatus 1 is powered on, the instruction buffer unit 11b starts an instruction packet control process shown in the flowchart of FIG. In the flowchart of FIG. 11, steps having the same step numbers as those in the flowchart of FIG. 5 perform the same processes as those in the flowchart of FIG. Hereinafter, steps for performing different processes will be described.

  If it is determined in step S11 that the instruction packet has not been received (step S11; No), the address comparison / buffer control unit 11b1 has passed the predetermined time since the instruction packet buffer unit 11b2 held the instruction packet. Whether or not (step S27). If it is determined that the predetermined time has elapsed (step S27; Yes), the address comparison / buffer control unit 11b1 outputs the retained instruction packet to the address conversion unit 13 (step S28). Then, the process returns to step S11.

  On the other hand, if it is determined that the predetermined time has not elapsed (step S27; No), the address comparison / buffer control unit 11b1 returns to step S11 and subsequently determines whether or not an instruction packet has been received.

  According to this embodiment, it is possible to prevent the instruction packet from staying in the buffer for a long time.

  In the above embodiment, the vector processing apparatus is not limited to the above configuration. For example, a plurality of scalar processing units, vector processing units, memories, etc. may be provided. In this embodiment, the instruction packet is transmitted from the scalar processing unit to the vector processing unit via the address conversion unit. However, the present invention is not limited to this, and the instruction packet is transmitted directly from the scalar processing unit to the vector processing unit. You may do it. The format of each instruction packet is not limited to that shown in the embodiment. For example, when the vector processing apparatus has a plurality of scalar processing units, an identifier for identifying the scalar processing unit that issued the instruction packet may be included in the instruction packet.

  In the above-described embodiment, the address comparison / buffer control unit 11 b 1 may not output an invalid instruction packet to the address conversion unit 13. Alternatively, the address comparison / buffer control unit 11b1 can output invalid instruction packets in any order. For example, in steps S135 and S174, the address comparison / buffer control unit 11b1 does not output the retained invalid instruction packet to the address conversion unit 13, and overwrites the instruction packet buffer unit 11b2 with the received instruction packet. It is good. In step S173, the address comparison / buffer control unit 11b1 may not output an invalid instruction packet that is an accepted instruction packet to the address conversion unit 13.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1)
A vector processing apparatus comprising a scalar processing unit that performs a scalar operation, a vector processing unit that performs a vector operation, and a storage unit,
The scalar processing unit is
Issuing a first instruction packet or a second instruction packet indicating an instruction to load data from the storage unit or an instruction to store data in the storage unit,
An instruction packet buffer unit for storing a first instruction packet issued by the scalar processing unit;
A type of the first instruction packet and a second instruction packet issued after the first instruction packet is determined, and a first address designated by the first instruction packet and a second instruction packet are A buffer control unit that compares a second address to be designated and outputs an instruction to combine the first instruction packet and the second instruction packet;
A combining processor that combines the first instruction packet and the second instruction packet based on the output instruction;
With
The buffer control unit
The instruction indicated by the first instruction packet is a scalar store instruction, the instruction indicated by the second instruction packet is (a) a scalar store instruction, and the first address matches the second address. The combination processing unit outputs the instruction to combine, and stores the combined packet in the instruction packet buffer unit;
(B) a vector load instruction or a vector store instruction, and if the first address and the second address do not overlap, output the second instruction packet;
(C) A vector processing device that outputs a second instruction packet when the first address and the second address do not coincide with each other in a scalar load instruction.

(Appendix 2)
The buffer control unit
When the instruction indicated by the first instruction packet is a scalar store instruction, the instruction indicated by the second instruction packet is a scalar store instruction, and the first address and the second address do not match, The vector processing apparatus according to appendix 1, wherein a first instruction packet is output and the second instruction packet is stored in the instruction packet buffer unit.

(Appendix 3)
The buffer control unit
The instruction indicated by the first instruction packet is a scalar store instruction, the instruction indicated by the second instruction packet is a vector load instruction or a vector store instruction, and the first address and the second address are 3. The vector processing device according to appendix 1 or 2, wherein when there is an overlap, the first instruction packet is output and the second instruction packet is stored in the instruction packet buffer unit.

(Appendix 4)
The buffer control unit
When the instruction indicated by the first instruction packet is a scalar store instruction, the instruction indicated by the second instruction packet is a scalar load instruction, and the first address matches the second address, The vector processing device according to any one of appendices 1 to 3, wherein the first instruction packet is output and the second instruction packet is stored in the instruction packet buffer unit.

(Appendix 5)
The buffer control unit
If the instruction indicated by the first instruction packet is a vector load instruction, a vector store instruction, or a scalar load instruction, the first instruction packet is output. The vector processing device described in 1.

(Appendix 6)
The buffer control unit measures an elapsed time after the instruction packet buffer unit stores the first instruction packet, and outputs the first instruction packet when the elapsed time exceeds a predetermined value. The vector processing device according to any one of supplementary notes 1 to 5, wherein:

(Appendix 7)
A scalar processing unit that performs a scalar operation; a vector processing unit that performs a vector operation; and a storage unit, wherein the scalar processing unit loads data from the storage unit or stores data in the storage unit The first instruction packet or the second instruction packet indicating that the scalar processing unit includes an instruction packet buffer unit, a buffer control unit, and a combination processing unit. A vector processing method for
The vector processing method is
An instruction packet buffer step in which the instruction packet buffer unit stores a first instruction packet issued by the scalar processing unit;
The buffer control unit determines a type of the first instruction packet and a second instruction packet issued after the first instruction packet, and a first address designated by the first instruction packet; A buffer control step of comparing a second address specified by a second instruction packet and outputting an instruction to combine the first instruction packet and the second instruction packet;
A combining processing step in which the combining processing unit combines the first instruction packet and the second instruction packet based on the output instruction;
With
In the buffer control step, the buffer control unit includes:
The instruction indicated by the first instruction packet is a scalar store instruction, the instruction indicated by the second instruction packet is (a) a scalar store instruction, and the first address matches the second address. The combination processing unit outputs the instruction to combine, and stores the combined packet in the instruction packet buffer unit;
(B) a vector load instruction or a vector store instruction, and if the first address and the second address do not overlap, output the second instruction packet;
(C) A vector processing method characterized by outputting the second instruction packet when the first address and the second address do not coincide with each other in a scalar load instruction.

(Appendix 8)
Computer
A scalar processing unit that performs a scalar operation; a vector processing unit that performs a vector operation; and a storage unit, wherein the scalar processing unit loads data from the storage unit or stores data in the storage unit A program for functioning as a vector processing device that issues a first instruction packet or a second instruction packet indicating
The program causes the computer to
In the scalar processing unit,
An instruction packet buffer unit for storing a first instruction packet issued by the scalar processing unit;
A type of the first instruction packet and a second instruction packet issued after the first instruction packet is determined, and a first address designated by the first instruction packet and a second instruction packet are A buffer control unit that compares a second address to be designated and outputs an instruction to combine the first instruction packet and the second instruction packet;
A combining processor that combines the first instruction packet and the second instruction packet based on the output instruction;
Function as
The buffer control unit
The instruction indicated by the first instruction packet is a scalar store instruction, the instruction indicated by the second instruction packet is (a) a scalar store instruction, and the first address matches the second address. The combination processing unit outputs the instruction to combine, and stores the combined packet in the instruction packet buffer unit;
(B) a vector load instruction or a vector store instruction, and if the first address and the second address do not overlap, output the second instruction packet;
(C) A program that causes a scalar load instruction to output the second instruction packet when the first address and the second address do not match.

  According to the present invention, it is possible to provide a vector processing device, a vector processing method, and a program suitable for improving processing performance by controlling an instruction packet.

1, 9 Vector processing unit 11, 91 Scalar processing unit 11a, 91a L1 cache 11b Instruction buffer unit 11b1 Address comparison / buffer control unit 11b2 Instruction packet buffer unit 11b3 Join processing unit 12, 92 Vector processing unit 13, 93 Address conversion unit 14 94 Memory network 15, 95 Memory

Claims (5)

A vector processing apparatus comprising a scalar processing unit that performs a scalar operation, a vector processing unit that performs a vector operation, and a storage unit,
The scalar processing unit is
Issuing a first instruction packet and a second instruction packet indicating an instruction to load data from the storage unit or an instruction to store data in the storage unit;
An instruction packet buffer unit for storing a first instruction packet issued by the scalar processing unit;
It determines the type of the second command packet issued after said first command packet and the first instruction packet, the first address of the first instruction packet designated, the second instruction A buffer control unit that compares a second address specified by the packet and outputs an instruction to combine the first instruction packet and the second instruction packet;
A combining processor that combines the first instruction packet and the second instruction packet based on the output instruction;
With
The buffer control unit
The instruction indicated by the first instruction packet is a scalar store instruction, the instruction indicated by the second instruction packet is (a) a scalar store instruction, and the first address matches the second address. The combination processing unit outputs the combination instruction, the combined packet is stored in the instruction packet buffer unit as the first instruction packet , and the first address and the second address do not match , Outputting the first instruction packet, causing the second instruction packet to be stored in the instruction packet buffer unit as the first instruction packet,
(B) a vector load instruction, when said first address and said second address does not overlap, the second outputs an instruction packet, the second address and the first address duplicate If so, the first instruction packet is output, the second instruction packet is stored in the instruction packet buffer unit as the first instruction packet,
(C) In the case of a scalar load instruction, when the first address and the second address do not match, the second instruction packet is output , and the first address and the second address match Output the first instruction packet, store the second instruction packet as the first instruction packet in the instruction packet buffer unit,
(D) In the case of a vector store instruction, when the first address and the second address do not overlap, the second instruction packet is output, and the first address and the second address overlap. In this case, the vector processing apparatus outputs the first instruction packet, and stores the second instruction packet in the instruction packet buffer unit as the first instruction packet . The buffer control unit
The first command packet indicates instruction vector load instruction, vector store instruction, or, if a scalar load instruction, vector processing apparatus according to claim 1, wherein the outputting the first command packet . The buffer control unit measures an elapsed time after the instruction packet buffer unit stores the first instruction packet, and outputs the first instruction packet when the elapsed time exceeds a predetermined value. vector processing apparatus according to claim 1 or 2, characterized in that. A scalar processing unit that performs a scalar operation; a vector processing unit that performs a vector operation; and a storage unit, wherein the scalar processing unit loads data from the storage unit or stores data in the storage unit The first instruction packet and the second instruction packet are issued, and the scalar processing unit includes an instruction packet buffer unit, a buffer control unit, and a combination processing unit. A vector processing method for
The vector processing method is
An instruction packet buffer step in which the instruction packet buffer unit stores a first instruction packet issued by the scalar processing unit;
The buffer control unit determines the type of the second command packet issued after said first command packet and the first instruction packet, the first address of the first instruction packet designated compares the second address the second instruction packet is specified, the buffer control step of outputting an instruction to combine said first instruction packet and said second instruction packet,
A combining processing step in which the combining processing unit combines the first instruction packet and the second instruction packet based on the output instruction;
With
In the buffer control step, the buffer control unit includes:
The instruction indicated by the first instruction packet is a scalar store instruction, the instruction indicated by the second instruction packet is (a) a scalar store instruction, and the first address matches the second address. The combination processing unit outputs the combination instruction, the combined packet is stored in the instruction packet buffer unit as the first instruction packet , and the first address and the second address do not match , Outputting the first instruction packet, causing the second instruction packet to be stored in the instruction packet buffer unit as the first instruction packet,
(B) a vector load instruction, when said first address and said second address does not overlap, the second outputs an instruction packet, the second address and the first address duplicate If so, the first instruction packet is output, the second instruction packet is stored in the instruction packet buffer unit as the first instruction packet,
(C) In the case of a scalar load instruction, when the first address and the second address do not match, the second instruction packet is output , and the first address and the second address match Output the first instruction packet, store the second instruction packet as the first instruction packet in the instruction packet buffer unit,
(D) In the case of a vector store instruction, when the first address and the second address do not overlap, the second instruction packet is output, and the first address and the second address overlap. In this case, the vector instruction method outputs the first instruction packet and stores the second instruction packet in the instruction packet buffer unit as the first instruction packet . Computer
A scalar processing unit that performs a scalar operation; a vector processing unit that performs a vector operation; and a storage unit, wherein the scalar processing unit loads data from the storage unit or stores data in the storage unit A program for functioning as a vector processing device that issues a first instruction packet and a second instruction packet indicating
The program causes the computer to
In the scalar processing unit,
An instruction packet buffer unit for storing a first instruction packet issued by the scalar processing unit;
It determines the type of the second command packet issued after said first command packet and the first instruction packet, the first address of the first instruction packet designated, the second instruction A buffer control unit that compares a second address specified by the packet and outputs an instruction to combine the first instruction packet and the second instruction packet;
A combining processor that combines the first instruction packet and the second instruction packet based on the output instruction;
Function as
The buffer control unit
The instruction indicated by the first instruction packet is a scalar store instruction, the instruction indicated by the second instruction packet is (a) a scalar store instruction, and the first address matches the second address. The combination processing unit outputs the combination instruction, the combined packet is stored in the instruction packet buffer unit as the first instruction packet , and the first address and the second address do not match , Outputting the first instruction packet, causing the second instruction packet to be stored in the instruction packet buffer unit as the first instruction packet,
(B) a vector load instruction, when said first address and said second address does not overlap, the second outputs an instruction packet, the second address and the first address duplicate If so, the first instruction packet is output, the second instruction packet is stored in the instruction packet buffer unit as the first instruction packet,
(C) In the case of a scalar load instruction, when the first address and the second address do not match, the second instruction packet is output , and the first address and the second address match Output the first instruction packet, store the second instruction packet as the first instruction packet in the instruction packet buffer unit,
(D) In the case of a vector store instruction, when the first address and the second address do not overlap, the second instruction packet is output, and the first address and the second address overlap. The first instruction packet is output, and the second instruction packet is stored in the instruction packet buffer unit as the first instruction packet.
Program for causing to function as.

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