JP5567455B2 - Signal input circuit - Google Patents

Description

  The present invention relates to a signal input circuit capable of inputting a voltage exceeding the voltage of a high potential power supply terminal to a signal input terminal while having a function of pulling up the signal input terminal.

  As signal input circuits having a conventional pull-up function, there are circuits as shown in FIGS. The signal input circuit of FIG. 7 has a high potential power supply terminal 1 with a voltage VDD, a low potential power supply terminal 2 with a voltage VSS (= GND), and a signal input terminal 3, and an ESD protection circuit 5 is constituted by a diode D1 and a resistor R1. The signal input circuit is composed of an enhancement type PMOS transistor MP1 having a source / drain connected between the high potential power supply terminal 1 and the opposite side of the signal input terminal 3 of the resistor R1 and a gate connected to the ground GND. ing. INV1 is an inverter for shaping the waveform of the input signal voltage.

  The signal input circuit of FIG. 7 pulls up the input side of the inverter INV1 to the voltage VDD of the high potential power supply terminal 1 because the transistor MP1 is on when the signal input terminal 3 is open. When the “H” level voltage (voltage close to VDD) is input to the signal input terminal 3, the transistor MP1 is turned on, so that the “H” level voltage is increased. On the other hand, when an “L” level voltage (a voltage close to VSS) is input to the signal input terminal 3, the transistor MP1 becomes a load when viewed from the signal input terminal 3. Therefore, the transistor MP1 has a small output current or a high output resistance with respect to the pre-stage circuit so that the transistor MP1 can be sufficiently driven with the capability of the driver of the pre-stage circuit connected to the signal input terminal 3. The on-resistance value is set.

  In the signal input circuit of FIG. 8, another enhancement type PMOS transistor MP2 is additionally connected in parallel with the transistor MP1 of the signal input circuit of FIG. 7, and the input signal voltage is supplied to the gate of the three-stage inverters INV1, INV2, INV3. This is a circuit configured to input after waveform shaping processing.

  In the signal input circuit of FIG. 8, when the “H” level voltage is inputted to the signal input terminal 3, the added transistor MP2 is also turned on to enhance the function of pulling up the signal input terminal 3. Yes. When an “L” level voltage is input to the signal input terminal 3, the added transistor MP2 is turned off to reduce the pull-up function and to improve the capability of the driver of the previous circuit connected to the signal input terminal 3. Reduction is possible.

  The signal input circuit of FIG. 9 is obtained by replacing the inverter INV1 with a hysteresis inverter INV4 in the signal input circuit of FIG. In the signal input circuit of FIG. 9, when the signal voltage inputted to the signal input terminal 3 fluctuates near the threshold voltage of the hysteresis inverter INV4, it is possible to prevent the output of the inverter INV4 from becoming unstable.

  In any of the above signal input circuits, when the signal voltage input to the signal input terminal 3 is at “H” level, the input side of the inverter INV1 or INV4 is “H” level, and when it is “L” level, it is “L” level. When open, the “H” level is held by the pull-up function. The pull-up circuit is described in Patent Document 1.

JP-A-6-125261

  However, in the circuit configuration described with reference to FIGS. 7 to 9, when a voltage equal to or higher than VDD is input to the signal input terminal 3, the voltage is a parasitic diode Dp2 (typically shown in FIG. When the forward voltage (shown in FIG. 7) is exceeded, current flows from the drain of the transistor MP1 connected to the signal input terminal 3 to the high potential power supply terminal 1 via the parasitic diode Dp2. For this reason, a large load is connected to the driver of the previous circuit connected to the signal input terminal 3, and the driver may be destroyed. In addition, if a current forcibly flows into the high-potential power supply terminal 1, the voltage VDD of the high-potential power supply terminal 1 is not stabilized, and there is a risk that the circuit malfunctions or other circuits that receive the supply of the voltage VDD are destroyed. is there. Another problem is that when the signal input terminal 3 is open, the voltage VDD rises to the threshold voltage of the transistor MP1 (or MP2 in addition thereto) when the voltage VDD of the high potential power supply terminal 1 rises. Until that time, the transistor MP1 (or MP2 in addition to this) does not exhibit the pull-up function, so that the voltage of the signal input terminal 3 is not determined during that time, and the output voltage of the subsequent inverter INV1 becomes unstable. there were.

  In order to solve the above problem, as shown in FIG. 10, an input tolerant circuit 6 is connected to the signal input terminal 3 so that the signal voltage at the signal input terminal 3 exceeds the voltage VDD at the high potential power supply terminal 1. Or when the voltage VDD of the high potential power supply terminal 1 is not sufficiently raised, measures to prevent current from flowing from the signal input terminal 3 to the high potential power supply terminal 1 or a high potential power supply as shown in FIG. It has been necessary to take measures to divide the output voltage of the driver 8 of the previous circuit using the voltage VCC of the terminal 7 as a power source and input the divided voltage to the signal input terminal 3 by the resistors R2 and R3. D2 and D3 are ESD protection diodes. For this reason, the design effort and cost are increased, and the current consumption is increased due to an increase in circuit area and additional circuits.

  The object of the present invention is to prevent the above-described problem from occurring even when the signal voltage input to the signal input terminal exceeds the voltage of the high potential power supply terminal while having the pull-up function of the signal input terminal. The present invention provides a signal input circuit.

To achieve the above object, a signal input circuit according to a first aspect of the present invention is a signal input circuit comprising a high potential power supply terminal, a low potential power supply terminal, and a signal input terminal, wherein the drain and gate are the high potential power supply. A first depletion type NMOS transistor having a source connected to the signal input terminal, a back gate connected to the low potential power supply terminal, a drain connected to the high potential power supply terminal, and a source connected to the high potential power supply terminal. A second depletion type connected to the signal input terminal, connected to the output terminal of the even-numbered inverter for waveform shaping connected to the signal input terminal, and connected to the low-potential power supply terminal. And an NMOS transistor .
According to a second aspect of the present invention, in the signal input circuit according to the first aspect, the on-resistance of the first depletion type NMOS transistor is set to the “L” level voltage of the driver of the preceding circuit connected to the signal input terminal. It is characterized by being set to a value higher than the output impedance at the time of output.
The invention according to claim 3 is the signal input circuit according to claim 1 or 2, wherein an ESD protection circuit is connected between the signal input terminal and the low potential power supply terminal .

According to the present invention, since the pull-up transistor is a depletion type NMOS transistor, even if the input voltage input to the signal input terminal is equal to or higher than the voltage of the high-potential power supply terminal, Since no current flows toward the terminal, it is possible to eliminate a factor that causes an increase in current consumption of the driver of the preceding circuit connected to the signal input terminal. In addition, since the current does not forcibly flow from the signal input terminal to the high potential power supply terminal, the voltage of the high potential power supply terminal can be prevented from becoming unstable, and the abnormal operation of the circuit and the voltage are supplied. The risk of destruction of other circuits can also be avoided. Furthermore, since it is not necessary to take measures with external parts to avoid them, it is possible to avoid an increase in design effort and cost, an increase in circuit area, an increase in current consumption due to additional circuits, and the like. Furthermore , the pull-up function can be reliably maintained even when the voltage of the high potential power supply terminal is low. As a result, the pull-up operation is performed almost simultaneously with the rise of the voltage of the high-potential power supply terminal, so there is an effect of suppressing the instability of the signal input terminal when the power is turned on, and it also serves as a countermeasure for preventing malfunctions and popping noises. .

1 is a circuit diagram of a signal input circuit according to a first exemplary embodiment of the present invention. It is a circuit diagram of the signal input circuit of the 2nd Example of this invention. It is a circuit diagram of the signal input circuit of the 3rd Example of the present invention. It is a circuit diagram of the signal input circuit of the 4th example of the present invention. It is a circuit diagram of the signal input circuit of the 5th Example of this invention. It is a circuit diagram of the signal input circuit of the 6th example of the present invention. It is a circuit diagram of the conventional signal input circuit. It is a circuit diagram of another conventional signal input circuit. It is a circuit diagram of another conventional signal input circuit. FIG. 6 is a circuit diagram of a conventional signal input circuit in which measures are taken such as when the input signal voltage is higher than the voltage at the high potential power supply terminal. FIG. 10 is a circuit diagram of another conventional signal input circuit in which measures are taken such as when the input signal voltage is higher than the voltage of the high potential power supply terminal.

<First embodiment>
FIG. 1 shows a signal input circuit according to a first embodiment of the present invention. In this embodiment, the enhancement type NMOS transistor MN1 is used as a pull-up transistor. The transistor MN1 has a gate and a drain connected to the high potential power supply terminal 1, a source connected to the signal input terminal 3, and a back gate connected to the low potential power supply terminal 2. The signal voltage input to the signal input terminal 3 is waveform-shaped by the inverter INV1 and taken in.

  When an “H” level voltage (a voltage close to VDD) is input to the signal input terminal 3, the gate-source voltage Vgs of the transistor MN1 becomes smaller than the threshold voltage, so that the transistor MN1 is turned off. . Therefore, the “H” level voltage of the signal input terminal 3 is input to the inverter INV1 as it is. When an “L” level voltage (a voltage close to VSS) is input to the signal input terminal 3, the output impedance (ON resistance) of the transistor MN1 is set in advance to be larger than the output impedance of the driver of the previous circuit. Thus, the “L” level voltage input to the signal input terminal 3 is prioritized, and the “L” level voltage is input as it is to the inverter INV1. When the signal input terminal 3 is open or has a high impedance, the transistor MN1 is turned on, so that the input voltage of the inverter INV1 is pulled up to the “H” level. When a voltage exceeding the voltage VDD of the high potential power supply terminal 1 is input to the signal input terminal 3, almost no current flows through the transistor MN1 due to the parasitic diode Dp1 in the reverse direction that is parasitic between the source and the back gate. The voltage VDD of the high potential power supply terminal 1 is not greatly affected. At this time, the high voltage is input to the inverter INV1. As described above, the signal input circuit of FIG. 1 has a pull-up function and functions normally without an abnormal current flowing even if a voltage equal to or higher than the voltage VDD of the high potential power supply terminal 1 is input to the signal input terminal 3. it can.

<Second embodiment>
FIG. 2 shows a signal input circuit according to a second embodiment of the present invention. In this embodiment, the pull-up enhancement type NMOS transistor MN1 in the signal input circuit of FIG. 1 is replaced with a depletion type NMOS transistor MN2. The display of the parasitic diode of the transistor MN2 is omitted.

  When the enhancement type transistor MN1 is used as a pull-up transistor as in the signal input circuit of FIG. 1, when the signal input terminal 3 is open or high impedance, the input voltage of the inverter INV1 is a high potential power supply. Since the voltage VDD of the terminal 1 is reduced by the gate-source voltage Vgs of the transistor MN1, the input voltage of the inverter INV1 does not rise to the voltage VDD of the high potential power supply terminal 1. However, when the voltage VDD is relatively high, the input voltage of the inverter INV1 becomes “H” level so that the input voltage becomes higher than the threshold voltage of the inverter INV1, and the pull-up function can be performed. However, when the voltage VDD decreases, the input voltage of the inverter INV1 becomes close to the threshold voltage of the inverter INV1 due to the decrease of the voltage Vgs, and the operation of the inverter INV1 may not be stable.

  On the other hand, if the pull-up transistor is replaced with a depletion type NMOS transistor MN2 having a threshold voltage of 0 V or lower, even if the signal input terminal 3 is open or high impedance, the input voltage of the inverter INV1 Therefore, even when the voltage VDD is relatively low, the pull-up function can be realized with certainty. In other states of the signal input terminal 3, the operation is the same as that of the signal input circuit of FIG.

<Third embodiment>
FIG. 3 shows a signal input circuit according to a third embodiment of the present invention. This embodiment is an example in which an ESD protection circuit 4 including a GG (Gate Grounded) NMOS transistor MN3 using a drain-source parasitic bipolar polar NPN transistor and a resistor R1 is added to the signal input circuit of FIG. is there. Note that the display of the parasitic diode Dp1 of the transistor MN1 is omitted. The operation is the same as that of the signal input circuit of FIG.

<Fourth embodiment>
FIG. 4 shows a signal input circuit according to a fourth embodiment of the present invention. In this embodiment, an ESD protection circuit 5 including a diode D1 and a resistor R1 is added to the signal input circuit of FIG. Note that the display of the parasitic diode Dp1 of the transistor MN1 is omitted. The operation is the same as that of the signal input circuit of FIG.

<Fifth embodiment>
FIG. 5 shows a signal input circuit according to a fifth embodiment of the present invention. In this embodiment, in the signal input circuit of FIG. 2, another depletion type NMOS transistor MN4 having the source and drain connected in common is connected to the source and drain of the depletion type transistor MN2 functioning as a pull-up transistor. In this embodiment, the voltage input to the signal input terminal 3 is input to the gate of the transistor MN4 via the inverters INV1 and INV2. The display of parasitic diodes of the transistors MN2 and MN4 is omitted.

  When the voltage input to the signal input terminal 3 is higher than the “H” level or the voltage VDD, the gate voltage of the transistor MN4 becomes VDD and the pull-up function is enhanced, but the pull-up voltage is the input voltage. In addition, even when the input voltage is higher than the voltage VDD, the operation is the same as that of the signal input circuit of FIG. When the voltage input to the signal input terminal 3 is at “L” level, the transistor MN4 is turned off because the gate voltage is at “L” level (= VSS). In this embodiment, the capability of the driver of the previous circuit that outputs the signal is small, and the burden can be reduced.

<Sixth embodiment>
FIG. 6 shows a signal input circuit according to a sixth embodiment of the present invention. This embodiment is an example in which an ESD protection circuit 4 including a GGNMOS transistor MN3 and a resistor R1 is added to the signal input circuit of FIG. 2, and the inverter INV1 is replaced with a hysteresis inverter INV4. The display of the parasitic diode of the transistor MN2 is omitted.

  In the signal input circuit of FIG. 6, when the signal voltage input to the signal input terminal 3 fluctuates near the threshold voltage of the hysteresis inverter INV4, the output of the inverter INV4 can be prevented from becoming unstable. Other operations are the same as those of the signal input circuit of FIG.

1: High-potential power supply terminal, 2: Low-potential power supply terminal, 3: Signal input terminal, 4, 5: ESD protection circuit, 6: Input tolerant circuit, 7: High-potential power supply terminal, 8: Driver of previous circuit MN1: Enhancement Type NMOS transistors MN2, MN4: depletion type NMOS transistors MN3: GGNMOS transistors MP1, MP2: enhancement type PMOS transistors D1 to D3: diodes Dp1, Dp2: parasitic diodes INV1, INV2, INV3: inverters INV4: hysteresis inverters

Claims (3)

In a signal input circuit having a high potential power supply terminal, a low potential power supply terminal, and a signal input terminal,
A first depletion type NMOS transistor having a drain and a gate connected to the high potential power supply terminal, a source connected to the signal input terminal, and a back gate connected to the low potential power supply terminal;
The drain is connected to the high potential power supply terminal, the source is connected to the signal input terminal, the gate is connected to the output terminal of the even-numbered inverter for waveform shaping connected to the signal input terminal, and the back gate is A second depletion type NMOS transistor connected to the low potential power supply terminal;
Signal input circuit, characterized in that it comprises. The signal input circuit according to claim 1,
A signal input characterized in that an on-resistance of the first depletion type NMOS transistor is set to a value higher than an output impedance at the time of “L” level voltage output of a driver of a preceding circuit connected to the signal input terminal. circuit. The signal input circuit according to claim 1 or 2,
A signal input circuit, wherein an ESD protection circuit is connected between the signal input terminal and the low potential power supply terminal .

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