JP5516904B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a MEMS resonator and a method for manufacturing the MEMS resonator.

In recent years, MEMS has been steadily growing in acceleration sensors and video devices. ME
MS is an abbreviation for Micro Electro Mechanical System, and there are various interpretations in the concept range encompassed by the MS, and it is sometimes called a micromachine or MST (Micro System Technology). The term “fabricated micro functional element” is meant. They are manufactured on the basis of microfabrication technology cultivated with conventional semiconductors. However, it is currently manufactured by a single MEMS or manufactured by a process such as manufacturing an IC later after manufacturing. They are used in electrical appliances and automobiles to open up new markets. The MEMS manufacturing process is arranged based on conventional semiconductor microfabrication technology. For example, a capacitive pressure sensor using a diaphragm formed at the same time as forming a gate of an active element on the same semiconductor substrate is known (for example,
Patent Document 1). In addition, it is known that a pressure sensor mixed semiconductor device can be reduced in size, function, and reliability by forming a pressure detection unit of a pressure sensor using a conductive layer of an electronic circuit (for example, Patent Documents). 2).

JP-T-2004-526299 JP 2006-126182 A

However, Patent Document 1 discloses a capacitance type MEMS structure and a CMOS (Complement
ary Metal Oxide Semiconductor). Patent Document 2 describes MEM
S structure part, CMOS circuit part, and ONO (oxide film / nitride film / oxide film) capacitor part 1
Although formed on the chip at the same time, the MEMS structure is formed of a wiring layer. The ONO capacitor portion uses a diffusion layer of a silicon substrate as a lower electrode. In other words, until now CMO
The S circuit portion and the ONO capacitor portion, the MEMS structure portion, and the CMOS circuit portion could be formed simultaneously, but the three devices were not formed simultaneously. Therefore, there were the following problems. ON
When the O capacitor portion is not provided, the ONO capacitor portion cannot be used, so that the CMOS circuit portion configuration is limited (variation is narrow) (for example, AD conversion circuit, other circuits that require capacitance other than the substrate electrode, etc.) . In addition, SIP (System
in Package) configuration, which increases process, costs, and noise from wiring such as wire bonding. When there is no MEMS structure part, the above problems such as noise increase occur. Further, the MEMS is additionally processed by Pre- / Post-Process or the like. Since this cannot be used as a machining process, the problem of an increase in the number of processes and an increase in cost occurs.

The present invention has been made paying attention to such a conventional problem, and its purpose is to simplify the process and realize cost reduction, and further, a MEMS resonator that simplifies the system and enables noise countermeasures. And it is providing the manufacturing method of a MEMS resonator.

(1) A method for manufacturing a MEMS resonator according to the present invention is a method for manufacturing a MEMS resonator having a semiconductor device and a MEMS structure formed on a substrate, wherein the semiconductor device includes an upper electrode, a lower electrode, and a semiconductor device. An ONO capacitor unit having a CMOS circuit unit,
And forming the lower electrode of the ONO capacitor portion using a first silicon layer, the lower structure of the MEMS structure portion, and the upper electrode of the ONO capacitor portion as a second silicon layer. Forming the upper structure of the MEMS structure portion and the gate electrode of the CMOS circuit portion using a third silicon layer.

According to the present invention, the MEMS structure portion, the CMOS circuit portion, and the ONO capacitor portion can be made into one chip. As a result, the process is simplified and the cost is reduced.
Simplifies the system and enables noise countermeasures.

(2) A MEMS resonator according to the present invention includes a semiconductor device and an ME formed on a substrate.
A MEMS resonator having an MS structure portion, wherein the semiconductor device includes an ONO capacitor portion and a CMOS circuit portion.

According to the present invention, the MEMS structure portion, the CMOS circuit portion, and the ONO capacitor portion can be made into one chip. As a result, the process is simplified and the cost is reduced.
Simplifies the system and enables noise countermeasures.

(3) In this MEMS resonator, the MEMS structure part includes a lower structure and an upper structure, and the ONO capacitor part includes a lower electrode and an upper electrode, and the CMO
The S circuit unit includes a gate electrode, and the lower electrode of the ONO capacitor unit is formed using a first silicon layer, and the lower structure of the MEMS structure unit and the upper electrode of the ONO capacitor unit Is formed using a second silicon layer, and the upper structure of the MEMS structure portion and the gate electrode of the CMOS circuit portion are formed using a third silicon layer,
It may be formed.

It is a schematic plan view which shows the MEMS resonator which concerns on embodiment to which this invention is applied. It is sectional drawing of the MEMS resonator which concerns on embodiment to which this invention is applied. It is a figure for demonstrating the manufacturing method of the MEMS resonator which concerns on embodiment to which this invention is applied. It is a figure for demonstrating the manufacturing method of the MEMS resonator which concerns on embodiment to which this invention is applied. It is a figure for demonstrating the manufacturing method of the MEMS resonator which concerns on embodiment to which this invention is applied.

  Embodiments to which the present invention is applied will be described below with reference to the drawings.

FIG. 1 is a schematic plan view showing a MEMS resonator according to an embodiment to which the present invention is applied. FIG. 2 is a cross-sectional view of a MEMS resonator according to an embodiment to which the present invention is applied. As shown in FIG. 1, the MEMS resonator 2 according to the present embodiment includes a substrate 10, a MEMS structure portion 4 formed on the substrate 10, an ONO capacitor portion 6 as a semiconductor device, and a CMOS circuit portion 8. , Is composed of.

The substrate 10 is a single crystal semiconductor substrate such as silicon (Si) or gallium arsenide (GaAs).
) Or the like can be used. In particular, a single crystal silicon substrate is desirable.
The thickness of the substrate 10 is 100 to 1000 μm.

An element isolation oxide film 12 is formed on the surface of the substrate 10 as shown in FIG. The element isolation oxide film 12 is a thermal oxide film. The element isolation oxide film 12 is made of LOCOS (Local oxid
It is a field insulating film formed by the ation of silicon method. The film thickness of the element isolation oxide film 12 is 0.1 to 2 μm. On the element isolation oxide film 12, the MEMS structure portion 4 and the ONO
A capacitor unit 6 is disposed.

A base nitride film 14 is formed on the surface of the element isolation oxide film 12. The base nitride film 14 is a SiN film. The base nitride film 14 has a thickness of 0.1 to 2 μm. The base nitride film 14 is necessary under the MEMS structure portion 4. The base nitride film 14 may be under the ONO capacitor unit 6.

In the region of the MEMS structure portion 4 on the surface of the base nitride film 14, a lower structure 16 of the MEMS structure portion 4 and an upper structure 18 of the MEMS structure portion 4 are formed. The lower structure 16 of the MEMS structure portion 4 is formed using the second silicon layer 52 (see FIG. 4A). The lower structure 16 of the MEMS structure 4 and the upper electrode 30 of the ONO capacitor 6 are simultaneously formed using the second silicon layer 52. The upper structure 18 of the MEMS structure portion 4 is formed using the third silicon layer 54 (see FIG. 4C). MEM
The upper structure 18 of the S structure portion 4 and the gate electrode 34 of the CMOS circuit portion 8 are simultaneously formed using the third silicon layer 54. The material of the lower structure 16 of the MEMS structure part 4 is Poly-Si, amorphous Si, or the like. Lower structure 1 of MEMS structure part 4
The thickness of 6 is 0.05 to 100 μm. The material of the upper structure 18 of the MEMS structure part 4 is Poly-Si, amorphous Si, or the like. The thickness of the upper structure 18 of the MEMS structure portion 4 is 0.05 to 100 μm.

A second field interlayer film 22 is formed on the lower structure 16 of the MEMS structure portion 4. A contact hole 24 is formed in the upper portion of the lower structure 16 of the MEMS structure portion 4.

In the region of the ONO capacitor unit 6 on the surface of the base nitride film 14, the ONO capacitor unit 6
The lower electrode 26 is formed. The lower electrode 26 of the ONO capacitor unit 6 is formed using the first silicon layer 26 (see FIG. 3A). The material of the lower electrode 26 of the ONO capacitor unit 6 is Poly-Si, amorphous Si, or the like. The thickness of the lower electrode 26 of the ONO capacitor unit 6 is 0.05 to 100 μm.

An ONO capacitor interlayer insulating film 28 is formed on the lower electrode 26 of the ONO capacitor unit 6. The ONO capacitor interlayer insulating film 28 includes three layers of a lower interlayer insulating film 28A, an intermediate interlayer insulating film 28B, and an upper interlayer insulating film 28C (see FIG. 3D). O
The material of the NO capacitor interlayer insulating film 28 is SiO _{2 at} the position of the lower interlayer insulating film 28A / Si ₃ N _{4 at} the position of the intermediate interlayer insulating film 28B / SiO ₂ at the position of the upper interlayer insulating film 28C. O
The film thickness of the NO capacitor interlayer insulation film 28 is 1-50 nm / in at the location of the lower interlayer insulation film 28A.
The location of the intermediate interlayer insulating film 28B is 1 to 50 nm / the location of the upper interlayer insulating film 28C is 1 to 50n.
m.

An upper electrode 30 of the ONO capacitor unit 6 is formed on the ONO capacitor interlayer insulating film 28. The upper electrode 30 of the ONO capacitor unit 6 is formed of the second silicon layer 52 (FIG. 4 (
A)). Upper electrode 30 of ONO capacitor unit 6 and MEMS
The lower structure 16 of the structure body 4 is simultaneously formed using the second silicon layer 52. The material of the upper electrode 30 of the ONO capacitor unit 6 is Poly-Si and amorphous Si.
Etc. The thickness of the upper electrode 30 of the ONO capacitor unit 6 is 0.05 to 100 μm.

A second field interlayer 22 is formed on the upper electrode 30 of the ONO capacitor unit 6. A contact hole 24 is formed on the upper electrode 30 of the ONO capacitor unit 6.

In the region of the CMOS circuit portion 8 on the surface of the substrate 10, there are a gate oxide film 32 and a gate electrode 34.
Etc. are formed. The gate electrode 34 of the CMOS circuit portion 8 is the third
It is formed using the silicon layer 54 (see FIG. 4C). The gate electrode 34 of the CMOS circuit unit 8 and the upper structure 18 of the MEMS structure unit 4 are formed using the third silicon layer 54.
It is formed at the same time. The material of the gate electrode 34 of the CMOS circuit unit 8 is Poly-Si, amorphous Si, or the like. The thickness of the gate electrode 34 of the CMOS circuit portion 8 is 0.05.
˜100 μm.

A second field interlayer film 22 is formed on the CMOS circuit portion 8. A contact hole 24 is formed above the diffusion layer (source, drain) 36 of the CMOS circuit portion 8.

A plug 38 made of a titanium nitride film and a tungsten film is formed inside the contact hole 24 in each region 4, 6, 8.

On the surface of the second field interlayer film 22, a first metal wiring layer 40 connected to the plug 38.
Is formed. The material of the first metal wiring layer 40 is AL, Cu, Ti, TiN, W, or the like. The space between the first metal wiring layers 40 is 0.1 to 3 μm.

A second metal wiring layer 44 connected to the first metal wiring layer 40 via the via hole 42 is formed on the first metal wiring layer 40. The material of the second metal wiring layer 44 is AL, Cu
, Ti, TiN, and W. The interlayer of the second metal wiring layer 44 is 0.1 to 3 μm. The first metal wiring layer 40 and the second metal wiring layer 44 are composed of a silicon oxide-based wiring layer interlayer film 46.
Are insulated from each other. The wiring layer interlayer film 46 is a CVD oxide film or the like. The film thickness of the wiring layer interlayer film 46 is 0.2 to 1 μm. In manufacturing the semiconductor device according to the present embodiment, CMP (Chemical Mechanical Polishing) is used at key points. For this reason, the first
The metal wiring layer 40 and the second metal wiring layer 44 are formed substantially flat.

A passivation film 48 is formed on the surface of the second metal wiring layer 44. The passivation film 48 is a CVD oxide film, a CVD-SiN film, a polyimide film, or the like.
The thickness of the passivation film 48 is as follows: oxide film = 0.1 to 2 μm, nitride film = 0.1 to 5 μm,
And polyimide film = 0.5 to 20 μm.

The opening 20 of the MEMS structure portion 4 is a region substantially corresponding to a part of the lower structure 16 and the movable portion of the upper structure 18, and a predetermined gap is provided between the lower structure 16 and the upper structure 18. Opened to ensure.

According to the present embodiment, the MEMS structure portion, the CMOS circuit portion, and the ONO capacitor portion can be made into one chip. This simplifies the process and lowers costs, and further simplifies the system and enables noise countermeasures.

The MEMS structure unit 4 may be a switch, an acceleration sensor, an actuator, or the like. The CMOS circuit unit 8 may be an analog / digital mixed circuit such as a temperature sensor for temperature compensation, an analog / digital conversion circuit, a logic circuit, a clock, and a power supply control circuit.

Next, a method for manufacturing a MEMS resonator according to an embodiment to which the present invention is applied will be described with reference to the drawings.

3 to 5 are diagrams for explaining a method of manufacturing the MEMS resonator according to the embodiment to which the present invention is applied. In the manufacturing method of the MEMS resonator according to the present embodiment, first, as shown in FIG. 3A, the first silicon layer 26 is formed. Specifically, after forming an element isolation oxide film (Locos, trench, etc.) 12 on the substrate 10, a first silicon nitride film 14 serving as an anchor at the time of release is formed. The first silicon nitride film 14 includes a base nitride film 14 (
FIG. 2). Thereafter, a first silicon layer 26 is formed on the first silicon nitride film 14.
The material of the first silicon layer 26 is Poly-Si, amorphous Si, or the like. The interlayer of the first silicon layer 26 is 0.05 to 100 μm. The first silicon layer 26 is the lower electrode 26 of the ONO capacitor unit 6 (see FIG. 2). By using the first silicon layer 26, the lower electrode 26 of the ONO capacitor unit 6 is formed.

Next, as shown in FIG. 3B, a lower interlayer insulating film 28A is formed. Specifically, the first
By oxidizing the surface of the silicon layer 26, a lower interlayer insulating film 28A of the ONO capacitor interlayer insulating film 28 (see FIG. 2) of the ONO capacitor unit 6 is formed.

Next, as shown in FIG. 3C, a second silicon nitride film 28B is formed. In particular,
A second silicon nitride film 28B is formed on part of the lower interlayer insulating film 28A and the base nitride film 14. The second silicon nitride film 28B becomes the intermediate interlayer insulating film 28B. Intermediate interlayer insulating film 28B
Is a layer of the ONO capacitor interlayer insulating film 28.

Next, as shown in FIG. 3D, an upper interlayer insulating film 28C is formed. Specifically, the surface of the intermediate interlayer insulating film 28B is oxidized to form the upper interlayer insulating film 28C. Upper interlayer insulating film 2
8C is one layer of the ONO capacitor interlayer insulating film 28.

Next, as shown in FIG. 4A, a second silicon layer 52 is formed. Specifically, the second silicon layer 52 is formed on the base nitride film 14 and the upper interlayer insulating film 28C. The material of the second silicon layer 52 is Poly-Si, amorphous Si, or the like. The interlayer of the second silicon layer 52 is 0.05 to 100 μm. The second silicon layer 52 may be doped with impurities. For example, ion implantation and thermal diffusion. The second silicon layer 52 is formed of the MEMS structure part 4.
These are the lower structure 16 (see FIG. 2) and the upper electrode 30 of the ONO capacitor unit 6. By using the second silicon layer 52, the lower structure 16 of the MEMS structure portion 4 and the upper electrode 30 of the ONO capacitor portion 6 are formed simultaneously.

According to the present embodiment, as described above, the combined use prevents the increase in the number of processes and realizes simultaneous formation.

Next, as shown in FIG. 4B, a gate oxide film 32 is formed. Specifically, the oxide film that has been formed so far is peeled once and newly oxidized again. By forming the gate oxide film 32, the surface of the second silicon layer 52 is also oxidized simultaneously. Oxidizing the surface of the second silicon layer 52 oxidizes the surfaces of the lower structure 16 of the MEMS structure portion 4 and the upper electrode 30 of the ONO capacitor portion 6. The oxidation of the surface of the lower structure 16 of the MEMS structure part 4 becomes the gap thickness of the MEMS structure part 4. The oxidation process may be performed a plurality of times as necessary when forming a gate oxide film separately for Lv, Hv and the like. In that case, 2nd-gate oxidation of the CMOS circuit portion 8 and gap oxidation of the MEMS structure portion 4, and gate oxidation after 2nd of the CMOS circuit portion 8 and gap oxidation of the MEMS structure portion 4 are combined. . In addition, tunnel oxide film formation such as EEPROM can also be used. Of course, not only the deposition of the silicon film but also the lithography process is combined.

According to the present embodiment, as described above, the combined use prevents the increase in the number of processes and realizes simultaneous formation.

Next, as shown in FIG. 4C, a third silicon layer 54 is formed. Specifically, CMO
A third silicon layer 54 is formed on the gate oxide film 32 of the S circuit unit 8 (see FIG. 2), the upper electrode 30 of the ONO capacitor unit 6, and the lower structure 16 of the MEMS structure unit 4. The material of the third silicon layer 54 is Poly-Si, amorphous Si, or the like. Third silicon layer 54
The interlayer is 0.05 to 100 μm. The third silicon layer 54 is the upper structure 18 of the MEMS structure portion 4 and the gate electrode 34 of the CMOS circuit portion 8. By using the third silicon layer 54, the upper structure 18 of the MEMS structure portion 4 and the gate electrode 34 of the CMOS circuit portion 8 are formed simultaneously.

According to the present embodiment, as described above, the combined use prevents the increase in the number of processes and realizes simultaneous formation.

Next, as shown in FIG. 4D, a salicide region 56 is formed. Specifically, the salicide region (wiring location) is divided and the oxide film is removed. Thereafter, when Ti is deposited over the entire surface and heat treatment is performed, the portion from which the oxide film has been removed is salicided. In this process, in the case of silicide having a structure for release etching, the entire surface may be silicided after the third silicon layer 54 is deposited. The Ti region that is not salicided is removed by RCA cleaning or the like. The material of the salicide region 56 is Ti, W, Mo, Co, Ni, Ta, Pt, Pd, or the like. The salicide region 56 has a thickness of 0.01 to 1 μm.

In the manufacturing method of the MEMS resonator of the present embodiment, each silicon layer may be subjected to impurity implantation (or thermal diffusion) or silicidized to reduce the resistance. However,
The MEMS structure portion 4 can select silicide (select depending on the case of melting by release, etc.).

Next, as shown in FIG. 5A, a second field interlayer film 22 is formed. In particular,
A second field interlayer film 22 is formed on the upper structure 16 of the MEMS structure section 4, on the upper electrode 30 of the ONO capacitor section 6 and on the CMOS circuit section 8. As the thin film forming method, LTO, HTO, PSG, BPSG, SOG, or the like is used. Therefore, the second field interlayer film 22 is formed substantially flat.

Next, as shown in FIG. 5B, a first metal wiring layer 40, a wiring layer interlayer film 46, a second metal wiring layer 44, and a passivation film 48 are formed. Specifically, the upper part of the lower structure 16 of the MEMS structure part 4 of the second field interlayer film 22, the upper electrode 3 of the ONO capacitor part 6.
Contact holes 24 are formed in the upper portion of 0 and the upper portion of the diffusion layer (source, drain) 36 of the CMOS circuit portion 8. A plug 38 is formed inside the contact hole 24. A plug 38 is formed on the surface of the salicide region. A first metal wiring layer 40 connected to the plug 38 is formed on the surface of the second field interlayer film 22. A second metal wiring layer 44 connected to the first metal wiring layer 40 through the via hole 42 is formed on the first metal wiring layer 40.
The first metal wiring layer 40 and the second metal wiring layer 44 are formed so as to be insulated from each other by the wiring layer interlayer film 46. In manufacturing the semiconductor device of this embodiment, CMP (Ch
emical Mechanical Polishing). For this reason, the first metal wiring layer 40 and the second metal wiring layer 44 are formed substantially flat. A plurality of wiring layers may be formed. A passivation film 48 is formed on the surface of the second metal wiring layer 44.

Next, as shown in FIG. 2, release etching is performed. Specifically, the portions other than the MEMS structure portion are protected with a resistant organic film such as a resist or polyimide, and release etching is performed.

According to the present embodiment, the MEMS structure portion 4, the ONO capacitor portion 6, and the CMOS circuit portion 8 are formed simultaneously in the process of forming the MEMS structure on the silicon substrate surface simultaneously with a semiconductor device such as a transistor. can do. Further, the gate electrode 34 of the MEMS structure portion 4 and the CMOS circuit portion 8 and the electrodes 26 and 30 of the ONO capacitor portion 6 are all formed of a deposited layer of silicon. Furthermore, while forming the electrodes of the MEMS structure part 4, the ONO capacitor part 6 and the CMOS circuit part 8 and the formation of the interlayer insulating film in each process, it is efficiently created without greatly increasing the number of processes. A flow can be realized. This
Three devices can be created on one chip without any problems. M
Since the ONO capacitor unit 6 can be mounted on the chip of the EMS structure unit 4 -CMOS circuit unit 8, design variations of the CMOS circuit unit 8 are widened (detection, amplification, calculation, AD conversion, etc.), and the convenience of the product is improved. improves.

According to the present embodiment, the MEMS structure portion, the CMOS circuit portion, and the ONO capacitor portion can be made into one chip. This simplifies the process and lowers costs, and further simplifies the system and enables noise countermeasures.

The present embodiment can be used for a product in which a MEMS structure using a silicon material and a MEMS structure portion and a semiconductor device (CMOS, ONO capacitor) are to be integrated into one chip. MEMS
The application field of the structure part can be used for sensors, RF relations, switches, video relations, and the like.

2 ... MEMS resonator, 4 ... MEMS structure, 6 ... ONO capacitor, 8 ... CM
OS circuit unit, 10 ... substrate, 12 ... element isolation oxide film, 14 ... base nitride film (first silicon nitride film), 16 ... lower structure, 18 ... upper structure, 20 ... opening, 22 ... second field Interlayer film, 24 ... contact hole, 26 ... lower electrode (first silicon layer), 28 ... ONO capacitor interlayer insulation film, 28A ... lower interlayer insulation film, 28B ... second silicon nitride film (intermediate interlayer insulation film), 28C ... Upper interlayer insulating film, 30 ... upper electrode, 32 ... gate oxide film, 34 ... gate electrode, 36 ... diffusion layer (source, drain), 38 ... plug, 40 ... first metal wiring layer, 42
... via hole, 44 ... second metal wiring layer, 46 ... wiring layer interlayer film, 48 ... passivation film, 52 ... second silicon layer, 54 ... third silicon layer, 56 ... salicide region.

Claims (6)

A method for manufacturing a semiconductor device including a MEMS structure portion, a capacitor portion, and a CMOS circuit portion formed on a substrate,
The MEMS structure part includes a lower structure and an upper structure,
The CMOS circuit unit includes a gate electrode,
The capacitor unit includes an upper electrode and a lower electrode,
The upper structure and the gate electrode are formed in the same process,
A first salicide region is provided on the lower structure,
A second salicide region is provided on the upper electrode;
A third salicide region is provided on the gate electrode;
The method of manufacturing a semiconductor device , wherein the first salicide region, the second salicide region, and the third salicide region are formed in the same process.   The method of manufacturing a semiconductor device according to claim 1, wherein the upper structure and the gate electrode are made of Poly-Si.   The method of manufacturing a semiconductor device according to claim 1, wherein the upper structure and the gate electrode are amorphous Si.   4. The method of manufacturing a semiconductor device according to claim 1, wherein a gap is provided between the lower structure and the upper structure. 5.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the MEMS structure portion is a switch, an acceleration sensor, or an actuator. 6.   The method for manufacturing a semiconductor device according to claim 1, wherein the MEMS structure portion is a sensor.

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