JP5484694B2 - 半導体モジュールおよび半導体モジュールを備える携帯機器 - Google Patents
半導体モジュールおよび半導体モジュールを備える携帯機器 Download PDFInfo
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- JP5484694B2 JP5484694B2 JP2008199072A JP2008199072A JP5484694B2 JP 5484694 B2 JP5484694 B2 JP 5484694B2 JP 2008199072 A JP2008199072 A JP 2008199072A JP 2008199072 A JP2008199072 A JP 2008199072A JP 5484694 B2 JP5484694 B2 JP 5484694B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
図1は、実施の形態1に係る半導体モジュール10の構成を示す断面図である。図2は、図1のA−A線を切断面とする平面図である。
実施の形態1に係る半導体モジュール10の製造方法について図3乃至図5を参照して説明する。
上述した実施の形態1では、突起部80が半導体素子40の全体を取り囲んでいるが、突起部80は必ずしも半導体素子40の全体を取り囲んでいなくてもよい。
図7は、実施の形態2に係る半導体モジュール10の構成を示す概略断面図である。実施の形態2に係る半導体モジュール10は、封止樹脂50の側方において、突起部80が露出している点が実施の形態1と相違する。実施の形態2における、その他の構成は実施の形態1と同様であり、実施の形態1と同様な構成については適宜説明を省略する。
実施の形態2に係る半導体モジュール10の製造方法について、図8を参照し、実施の形態1の製造方法との相違点を中心に説明する。
図9は、実施の形態3に係る半導体モジュール10の構成を示す概略図である。実施の形態3に係る半導体モジュール10は、主に金属箔120で封止樹脂50が被覆されている点で実施の形態2と相違する。
実施の形態3に係る半導体モジュール10の製造方法について、図10および実施の形態2の製造方法を参照しつつ説明する。
Claims (7)
- 所定パターンの配線層と、
前記配線層と対向する素子電極を有し、前記配線層上に絶縁樹脂層を介して搭載された半導体素子と、
前記配線層から前記半導体素子の側に突出し、前記絶縁樹脂層を貫通して前記素子電極と接続された突起電極と、
前記半導体素子を封止する封止樹脂と、
前記半導体素子の少なくとも1辺に沿って前記配線層と一体的に形成され、前記配線層から前記半導体素子の側に突出し、前記封止樹脂に埋め込まれた突起部と、
を備えることを特徴とする半導体モジュール。 - 前記突起部の先端部が前記突起電極と前記素子電極との接合部分よりも上方に位置していることを特徴とする請求項1に記載の半導体モジュール。
- 前記突起部が前記半導体素子の各辺に沿って設けられていることを特徴とする請求項1または2に記載の半導体モジュール。
- 前記突起部と前記突起電極とが同じ材料で形成されていることを特徴とする請求項1乃至3のいずれか1項に記載の半導体モジュール。
- 前記突起電極と前記配線層とが一体的に形成されていることを特徴とする請求項1乃至4のいずれか1項に記載の半導体モジュール。
- 前記封止樹脂を被覆する金属箔をさらに備え、
前記金属箔が前記突起部のうち、接地電位に固定された突起部と電気的に接続されていることを特徴とする請求項1乃至5のいずれか1項に記載の半導体モジュール。 - 請求項1乃至6のいずれか1項に記載の半導体モジュールを備えた携帯機器。
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JP2008199072A JP5484694B2 (ja) | 2008-07-31 | 2008-07-31 | 半導体モジュールおよび半導体モジュールを備える携帯機器 |
PCT/JP2009/003598 WO2010013470A1 (ja) | 2008-07-31 | 2009-07-29 | 半導体モジュールおよび半導体モジュールを備える携帯機器 |
US13/056,851 US8373281B2 (en) | 2008-07-31 | 2009-07-29 | Semiconductor module and portable apparatus provided with semiconductor module |
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JP2008199072A JP5484694B2 (ja) | 2008-07-31 | 2008-07-31 | 半導体モジュールおよび半導体モジュールを備える携帯機器 |
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JP2010040610A JP2010040610A (ja) | 2010-02-18 |
JP5484694B2 true JP5484694B2 (ja) | 2014-05-07 |
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JP4930567B2 (ja) * | 2009-10-02 | 2012-05-16 | 富士通株式会社 | 中継基板、プリント基板ユニットおよび中継基板の製造方法 |
JP4930566B2 (ja) * | 2009-10-02 | 2012-05-16 | 富士通株式会社 | 中継基板、プリント基板ユニット、および、中継基板の製造方法 |
JP5431232B2 (ja) * | 2010-03-31 | 2014-03-05 | 三洋電機株式会社 | 半導体装置 |
JP5776968B2 (ja) * | 2011-03-29 | 2015-09-09 | 大日本印刷株式会社 | 半導体装置および半導体装置の製造方法 |
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