JP5313651B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor element in which a substrate for growth can be easily peeled by wet etching processing and further improvement in light extraction efficiency and securing of mechanical strength are made compatible. <P>SOLUTION: The method of manufacturing the semiconductor element includes: a process of forming a first cavity-containing layer containing a plurality of first cavities on a substrate for growth; a process of forming a second cavity-containing layer containing a plurality of second cavities on the first cavity-containing layer, respective partition wall portions between the second adjacent cavities being provided above the first cavities; a process of epitaxially growing a semiconductor layer on the second cavity-containing layer; a process of bonding a support substrate onto the semiconductor layer; and a process of making an etchant flow in into each of the first and second cavities to connect the first cavities and second cavities, and removing the substrate for growth from the semiconductor layer. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor light emitting device formed using metal organic vapor phase epitaxy.

  A semiconductor light emitting device such as a light emitting diode is manufactured by forming a semiconductor film composed of an n layer, an active layer, a p layer, etc. on a growth substrate such as a sapphire substrate, and forming electrodes on the growth substrate and the semiconductor surface. Is done. When the growth substrate is an insulator, a part of the semiconductor layer is etched using a technique such as reactive ion etching to expose the n layer, and an electrode is formed on each of the n layer and the p layer. To do.

  Semiconductor light emitting devices have been improved in efficiency and output due to recent technological advances. However, as the output increases, the amount of heat generated from the semiconductor light emitting element also increases, and this causes problems such as a decrease in reliability such as a decrease in efficiency of the semiconductor light emitting element and a deterioration of the semiconductor film. In order to solve this problem, the growth substrate having a relatively low thermal conductivity is removed, and instead, the semiconductor film is supported by a metal having a relatively high thermal conductivity. By adopting such a structure, the heat dissipation of the semiconductor light emitting device can be improved, and the light emission efficiency, particularly the light extraction efficiency can be improved by removing the growth substrate. That is, it is possible to reduce the light component that is totally reflected at the interface due to light absorption that occurs when light passes through the growth substrate and the difference in refractive index between the semiconductor film and the growth substrate. Generally, the growth substrate is peeled off by using a laser lift-off (LLO) method. On the other hand, in Patent Document 1, a separation layer having a flow hole for allowing an etchant to enter between a growth substrate and a semiconductor film is formed, and the etchant is passed through the flow hole to etch the separation layer. A technique for separating the substrate for use and the semiconductor layer is described.

In addition, a technique is known in which a light emitting surface of a semiconductor light emitting element is processed to have an unevenness in order to improve the light extraction efficiency of the semiconductor light emitting element. By performing uneven processing on the light emitting surface, light that is incident at a critical angle or more and totally reflected at the interface between the semiconductor light emitting element and the sealing resin can be reduced, so that light extraction efficiency is improved. This uneven shape can be formed by performing an appropriate treatment on the light emitting surface of the semiconductor light emitting element. Patent Document 2 describes a semiconductor light emitting device in which light extraction efficiency is improved by forming a hemispherical concavo-convex pattern on the surface of an n-type gallium nitride layer and further forming a plurality of protrusions on the surface of the concavo-convex pattern. Has been.
JP 2001-36139 A JP 2007-36240 A

  As described above, the unevenness for improving the light extraction efficiency formed on the surface of the semiconductor light emitting device can be easily formed by wet etching the surface of the GaN film. By subjecting the surface of the GaN film to wet etching, a large number of hexagonal pyramidal projections called so-called micro cones derived from the crystal structure of GaN are formed on the surface. In order to further improve the light extraction efficiency, it is necessary to increase the size of the hexagonal pyramidal projections to some extent.

  Here, FIGS. 1A and 1B show that the collet of the chip mounter is in contact with the surface of the semiconductor film on which the relatively large protrusions are formed and the surface of the semiconductor film on which the relatively small protrusions are formed. It shows the force applied to the protruding valley when it is done. As shown in FIG. 1A, when a relatively large protrusion of about 1 to 4 μm is formed on the surface of the semiconductor film, the force applied to the valley of the protrusion when the semiconductor element is mounted on the mounting substrate or the stem. Becomes larger. That is, in this case, cracks are likely to occur due to external pressure. On the other hand, when the projection size is reduced, as shown in FIG. 1B, the pressure is dispersed and the force applied to the valley portion of the projection is reduced, so that the occurrence of cracks can be suppressed. However, if the projection size is reduced, the effect of improving the light extraction efficiency is reduced. That is, in the case where the light extraction efficiency is to be improved by forming a plurality of protrusions on the surface of the semiconductor film, the light extraction efficiency and the mechanical strength of the semiconductor film are in a trade-off relationship. It was difficult to secure at a high level.

On the other hand, when the growth substrate is peeled off using the LLO method, the nitride semiconductor that has absorbed the laser light may be decomposed to generate N ₂ gas, which may cause cracks in the semiconductor film. In addition, in order to carry out the LLO method, it is necessary to introduce an expensive dedicated device, resulting in an increase in cost. Further, in the LLO method, it is difficult to process a large number of wafers at once, and a process in which laser light is scanned over the entire surface of the wafer requires a relatively long processing time. As the wafer diameter increases, the processing time becomes longer. Therefore, if the growth substrate can be easily removed using wet etching, it is often advantageous from the viewpoint of quality, cost, processing time, and the like.

  The present invention has been made in view of such points, and the growth substrate can be easily peeled off by a wet etching process. Further, the improvement of the light extraction efficiency and the securing of the mechanical strength of the semiconductor film are achieved at the same time. Another object of the present invention is to provide a method for manufacturing a semiconductor device.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming a first cavity-containing layer including a plurality of first cavities on a growth substrate, and the second second including a plurality of second cavities and adjacent to each other. Forming a second cavity-containing layer on the first cavity-containing layer, each of the partition walls between the cavities being provided above each of the first cavities; and a semiconductor layer on the second cavity-containing layer Epitaxially growing, bonding a support substrate on the semiconductor layer, flowing an etchant into each of the first and second cavities, and each of the first cavities and each of the second cavities And bonding to remove the growth substrate from the semiconductor layer.

  The step of forming the first cavity-containing layer includes a step of forming a first mask for selective growth on the growth substrate, and a group III nitride is selected on the growth substrate via the first mask. And a first selective growth step of forming a layer having a cavity provided on the first mask along the first mask, and the step of forming the second cavity-containing layer includes the first selective growth step. Forming a second mask for selective growth on the first cavity-containing layer, and selectively growing group III nitride on the first cavity-containing layer through the second mask along the second mask. And a second selective growth step of forming a layer having a cavity provided on the second mask.

  The first selective growth step includes a process of alternately performing a first step and a second step of growing the group III nitride at a different growth rate a plurality of times.

  The first mask has a stripe pattern in which mask portions and non-mask portions are alternately arranged. The second mask has a stripe pattern in which mask portions and non-mask portions are alternately arranged, and the non-mask portion of the second mask is provided on the mask portion of the first mask.

  Further, the method for manufacturing a laminated structure of the present invention includes a step of forming a first cavity-containing layer including a plurality of cavities on a growth substrate, and a partition wall portion between the cavities adjacent to each other including the plurality of cavities. Forming a second cavity-containing layer on each first cavity-containing layer, each of which is provided on top of each cavity inside the first cavity-containing layer.

  The semiconductor wafer of the present invention includes a growth substrate, a first cavity-containing layer made of a group III nitride semiconductor including a plurality of first cavities formed on the growth substrate, and the first cavity. A group III nitride semiconductor formed on the containing layer, including a plurality of second cavities, and each of the partition portions between the second cavities adjacent to each other is provided on top of each of the first cavities And a group III nitride semiconductor layer epitaxially grown on the second cavity-containing layer.

  The stacked structure of the present invention includes a growth substrate, a first cavity-containing layer made of a group III nitride semiconductor including a plurality of first cavities formed on the growth substrate, and the first cavity-containing layer. A group III nitride formed on the cavity-containing layer, including a plurality of second cavities, and each of the partition walls between the second cavities adjacent to each other is provided on top of each of the first cavities And a second cavity-containing layer made of a semiconductor.

BEST MODE FOR CARRYING OUT THE INVENTION

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a manufacturing process flow diagram of a semiconductor light emitting device according to an embodiment of the present invention. 3-5 is sectional drawing for every manufacturing process of the semiconductor light-emitting device which is an Example of this invention.

(First Mask Layer Forming Step Step S1)
First, a growth substrate is prepared. In this example, a C-plane sapphire substrate 10 capable of forming a GaN-based semiconductor epitaxial layer by MOCVD (metal organic vapor phase epitaxy) was used as a growth substrate.

Next, a first mask layer for selectively growing a GaN film is formed on the sapphire substrate 10. The first mask layer is composed of SiO ₂ masks 20 arranged in a stripe pattern on the sapphire substrate 10. The procedure for forming the first mask layer is as follows. First, a SiO ₂ film having a thickness of about 150 nm is deposited on the sapphire substrate 10 by an EB (electron beam) method or the like. Then, this was formed a resist mask SiO ₂ film is subjected to striped patterning by selectively removing the SiO ₂ film by dry etching using, for example, CHF _3. In this embodiment, the SiO ₂ film is removed by 1μm wide, to form a stripe pattern in which the mask portion and the non-masked portions are continuous by leaving the SiO ₂ of 4μm wide. That is, SiO ₂ masks 20 having a width of 4 μm are formed on the sapphire substrate 10 at a pitch of 5 μm. Each of the SiO ₂ masks 20 arranged in a stripe shape is formed so as to extend from one end on the sapphire substrate 10 to the other end facing the sapphire substrate 10 (FIG. 3A).

In this embodiment, the first mask layer is formed of SiO _2. However, for example, TiO ₂ , SiN, or TiN can be used. Although the film thickness of the SiO ₂ film can be formed, for example, in the range of 100 to 500 nm, it is preferably 100~200nm considering the growing ease of film formation time and subsequent GaN film.

Further, the SiO ₂ film forming method is not limited to the EB method, and for example, a sputtering method, a plasma CVD method, or a thermal CVD method may be used. Etching of the SiO ₂ film is not limited to dry etching using CHF _{3 but} may be dry etching using CF ₄ and C ₂ F ₈ or the like, and HF, BHF, NH ₄ F + HF, KOH, NaOH (oxidation) Material), hot phosphoric acid, and wet etching using phosphoric acid + sulfuric acid (nitride).

Also, the width of each of the SiO ₂ mask 20, machining accuracy and, after it is preferable that the 1~4μm in consideration of forming a cavity 41 on the SiO ₂ mask 20 in step. The non-mask portion of the SiO ₂ mask 20 is desirably 1 to 3 μm.

The SiO ₂ mask 20 is only required to be discretely formed on the sapphire substrate 10 with an appropriate interval, and is not limited to a stripe shape, and an axis parallel to the crystal orientation <10-10> of the GaN crystal and the same. It may be a polygon having sides parallel to the equivalent axis, or a pattern in which such polygons are arranged in a grid. As will be described later, a cavity into which an etchant for wet etching flows is formed above the mask. For this reason, the mask pattern is a continuous pattern extending from one end of the sapphire substrate 10 to the other end facing the sapphire substrate 10 and preferably has no isolated region on the wafer. As a result, the etchant introduced from the wafer end surface can penetrate to the center of the wafer, and the growth substrate can be quickly removed.

The first mask layer may be formed by first forming a pattern with a photoresist on the sapphire substrate 10, then depositing a SiO ₂ film, and lifting off unnecessary portions deposited on the resist mask. .

  Further, the growth substrate is not limited to the sapphire substrate, and may be any substrate suitable for the growth of a semiconductor layer such as a Si or SiC substrate.

(Thermal cleaning process step S2)
Next, thermal cleaning of the sapphire substrate 10 on which the SiO ₂ mask 20 is formed is performed. Specifically, the sapphire substrate 10 was set in an MOCVD apparatus and treated for 7 minutes in a reducing atmosphere (hydrogen flow rate 10LM, nitrogen flow rate 7LM) controlled at 1000 ° C. The atmospheric temperature may be 1000 ° C. or higher, and the treatment time may be 3 to 20 minutes.

(Low-temperature buffer layer forming step Step S3)
Next, a low-temperature buffer layer 30 made of GaN is formed on the sapphire substrate 10 on which the SiO ₂ mask 20 is formed. The sapphire substrate 10 is set in an MOCVD apparatus controlled to an atmospheric temperature of 525 ° C., and trimethylgallium (TMG) (flow rate 10 μmol / min) and ammonia (flow rate 10 μmol / min) in a mixed atmosphere of nitrogen (flow rate 13.5 LM) and hydrogen (flow rate 6 LM). NH ₃ ) (flow rate: 3.3 LM) was supplied (in this case, the V / III ratio was about 14000) to form the low-temperature buffer layer 30 with a thickness of about 150 nm. Thereafter, the temperature inside the MOCVD apparatus was raised to 800 ° C. and kept for 30 seconds for annealing.

When a GaN film is grown on the sapphire substrate 10 on which the SiO ₂ mask 20 is formed under such conditions, a GaN single crystal does not grow on the SiO ₂ mask 20 but a polycrystal grows. GaN nucleus growth occurs in the exposed portion of the substrate 10 (FIG. 3B).

In addition, in this process, atmospheric temperature can be set to the range of 425-625 degreeC. The TMG flow rate can be set in the range of 9 to 45 μmol / min, but is set in the range of 10 to 23 μmol in order to improve the film formation uniformity of the buffer layer 30 and the crystallinity of the upper semiconductor epitaxial layer 70. Is preferred. The V / III ratio can be set in the range of 3000 to 25000, but is preferably set in the range of 6000 to 14000 in order to increase the crystallinity of the semiconductor epitaxial layer 30. In the range of the V / III ratio, the NH ₃ flow rate can be set in the range of 3.3 to 5.5 LM. The thickness of the buffer layer 30 can be set in the range of 30 to 1000 nm, but is preferably 30 to 400 nm in order to fuse nuclei with a thin film while forming a cavity.

(First cavity-containing layer forming step Step S4)
A process for growing GaN on the buffer layer 30 formed in the previous step under conditions that promote vertical growth (referred to as a first step) and a process for growing a GaN film under conditions that promote lateral growth (see FIG. The first cavity-containing layer 40 having the cavities 41 on the SiO ₂ mask 20 is formed on the sapphire substrate 10 by alternately repeating a second step).

Specifically, the temperature inside the MOCVD apparatus is controlled to 800 ° C., and TMG is supplied at a flow rate of 23 μmol / min in an atmosphere of a nitrogen flow rate of 6 LM and a hydrogen flow rate of 7.5 LM. ₃ is supplied at a flow rate of 2.2 LM, and a GaN film having a thickness of about 20 nm is formed on the low-temperature buffer layer 30. In this first step, vertical growth of the GaN film mainly occurs in the portion where the low temperature buffer layer 30 is grown.

On the other hand, in the second step, TMG is supplied at a flow rate of 45 μmol / min and NH ₃ is supplied at a flow rate of 4.4 LM to form a GaN film 20 having a thickness of about 80 nm. In this second step, lateral growth of the GaN film occurs mainly starting from the top of the GaN film grown in the vertical direction through the first step.

Since the flow rates of TMG and NH ₃ are different between the first step and the second step, the growth rate of the GaN film is different, and the balance between adsorption and decomposition / desorption of Ga atoms and N atoms constituting the GaN film is different from each other. Therefore, it is thought that a difference occurs in the growth direction. The growth rate of the GaN film in the first step is 23 nm / min, and the growth rate of the GaN film in the second step is 45 nm / min.

By repeating four sets alternately the first step and second step, GaN films adjoining each other sandwiching the SiO ₂ mask 20 is fused, a cavity 41 is formed in the upper portion of each of the SiO ₂ mask 20.

Each of the cavities 41 is formed along the SiO ₂ mask 20 arranged in a stripe shape. That is, each of the cavities 41 has an opening provided along the outer edge of the sapphire substrate 10 and is formed so as to communicate from one end of the wafer side surface to the other opposite end. Each of the cavities 41 functions as an etchant introduction hole for introducing an etchant into the first cavity-containing layer 20 when the sapphire substrate 10 is peeled off by wet etching in the subsequent growth substrate peeling step (step S9). Further, in this step, the lateral growth is performed a plurality of times, so that crystal defects generated at the interface between the sapphire substrate 10 and the GaN film are bent and do not propagate to the upper layer portion. Defect density is reduced.

In this step, the ambient temperature can be set in the range of 700 to 900 ° C. In the first step, the TMG flow rate can be set to a range of 10 to ₃₀ μmol / min, and the NH ₃ flow rate can be set to a range of 1 to ₃ LM. In the second step, the TMG flow rate can be set to a range of ₃₀ to 70 μmol / min, and the NH ₃ flow rate can be set to a range of ₃ to 7 LM. Further, the film thickness of the GaN film formed in the first step can be changed in the range of 10 to 60 nm and the film thickness of the GaN film formed in the second step can be changed in the range of 30 to 140 nm according to the size and shape of the cavity 41. It is.

Next, a GaN film is further epitaxially grown on the GaN film in which the cavity 41 is formed, and the surface is planarized to complete the first cavity-containing layer 40. Specifically, the temperature inside the MOCVD apparatus is controlled to 1000 ° C., and TMG (flow rate 45 μmol / min) and NH ₃ (flow rate 4.4 LM) are mixed in a mixed atmosphere of nitrogen (flow rate 6 LM) and hydrogen (flow rate 7.5 LM). (In this case, the V / III ratio is about 5000) to form a planarization layer having a film thickness of about 1.5 μm, thereby completing the first cavity-containing layer (FIG. 3C).

In this step, the TMG flow rate can be set in the range of 10 to 70 μmol / min. The V / III ratio can be set in the range of 2000 to 22500, but is preferably set in the range of 3000 to 8000 from the viewpoint of flatness and crystallinity. In the range of the V / III ratio, the NH ₃ flow rate can be set in the range of 3.3 to 5.5 LM. The film thickness of the planarizing layer can be set in the range of 1 to 10 μm. However, when the film thickness is increased, the processing time in the subsequent growth substrate removing step (step S9) is increased.

(Second Mask Layer Forming Step Step S5)
Next, a _second mask layer in which SiO ₂ masks 50 are arranged in stripes is formed on the first cavity-containing layer 40. Each of the SiO ₂ masks 50 constituting the second mask layer is formed so as to extend in the same width, the same pitch, and the same direction as, for example, each of the SiO ₂ masks 20 in the first mask layer. Further, each of the non-mask portions 51 positioned between the SiO ₂ masks 50 completely overlaps each of the SiO ₂ masks 20 in the lower first mask layer, and between each of the SiO ₂ masks 20. The SiO ₂ mask 50 is arranged so that each of the positioned non-mask portions 21 completely overlaps with each of the SiO ₂ masks 50 in the upper second mask layer (FIG. 3D).

The method for forming the second mask layer is the same as that for the first mask layer. That is, after the formation of the first cavity-containing layer 40, the wafer is taken out from the MOCVD apparatus, and an SiO ₂ film having a thickness of about 150 nm is deposited on the first cavity-containing layer 40 by an EB (electron beam) method or the like. Subsequently, after forming a resist mask on the SiO ₂ film, for example, by selectively removing the SiO ₂ film by dry etching using CHF _3, striped to the mask portion and the non-masked portion is continuous Patterning is performed. In this embodiment, the SiO ₂ film having a width of 1 μm is removed as in the SiO ₂ mask 20 in the first mask layer, leaving 4 μm width of SiO ₂ so as to have a relative positional relationship with the first mask layer as described above. A stripe pattern of the second mask layer was formed. Each of the SiO ₂ masks 50 is provided so as to extend from one end of the wafer to the other end facing the wafer.

In this embodiment, the second mask layer is formed of SiO _2. However, for example, Si, Ti oxide, SiN, or TiN can be used. Although the film thickness of the SiO ₂ film can be formed, for example, in the range of 100 to 500 nm, it is preferably 100~200nm considering the growing ease of film formation time and subsequent GaN film.

Further, the SiO ₂ film forming method is not limited to the EB method, and for example, a sputtering method, a plasma CVD method, or a thermal CVD method may be used. Etching of the SiO ₂ film is not limited to dry etching using CHF _{3 but} may be dry etching using CF ₄ and C ₂ F ₈ or the like, and HF, BHF, NH ₄ F + HF, KOH, NaOH (oxidation) Material), hot phosphoric acid, and wet etching using phosphoric acid + sulfuric acid (nitride).

Also, the width of each of the SiO ₂ mask 50, machining accuracy and, after it is preferable that the 1~4μm in consideration of forming a cavity 61 on the SiO ₂ mask 50 in step. The non-mask portion of the SiO ₂ mask 20 (that is, the formation pitch of the SiO ₂ mask 50) is preferably 1 to 3 μm.

Further, the SiO ₂ mask 50 is not limited to a stripe shape as long as the relative positional relationship with the first mask layer as described above is ensured, and an axis parallel to the crystal orientation <10-10> of the GaN crystal and the same as this. It may be a polygon having sides parallel to a simple axis, or a pattern in which such polygons are arranged in a grid. As will be described later, a cavity into which an etchant for wet etching flows is formed above the mask. For this reason, the mask pattern is a continuous pattern extending from one end of the sapphire substrate 10 to the other end facing the sapphire substrate 10 and preferably has no isolated region on the wafer. As a result, the etchant introduced from the wafer end surface can penetrate to the center of the wafer, and the growth substrate can be quickly removed. The second mask layer is formed by first forming a pattern with a photoresist on the first cavity-containing layer 40, then depositing a SiO ₂ film, and lifting off unnecessary portions deposited on the resist mask. May be.

(Second cavity-containing layer forming step Step S6)
Next, a GaN film is epitaxially grown on the first cavity-containing layer 40 on which the second mask layer is formed, thereby forming the second cavity-containing layer 60 having the cavity 61 on the SiO ₂ mask 50. Specifically, the wafer subjected to each of the above steps is set in an MOCVD apparatus controlled to an atmospheric temperature of 700 ° C., and TMG is flowed at 45 μmol / min and NH ₃ is flowed at 5.5 LM in an atmosphere with nitrogen flow of 13.5 LM. Then, SiH ₄ is supplied as a dopant gas, and a GaN film having a thickness of about 500 nm doped with Si of 5 × 10 ¹⁸ atoms / cm ³ is grown on the first cavity-containing layer 40.

Doing growth of GaN film on the first void-containing layer 40 SiO ₂ mask 50 is formed in such a condition, on the SiO ₂ mask 50 is GaN film does not grow, the SiO ₂ mask 50 is not formed The GaN film grows only in the portion. Then, by continuing growth in this condition, and fusion GaN film between the adjacent sides of the SiO ₂ mask 50, a cavity 61 is formed in the upper portion of each of the SiO ₂ mask 50. Thereafter, the ambient temperature is raised to 1000 ° C. while supplying TMG and NH ₃ , and a GaN film having a thickness of about 1 μm is epitaxially grown to complete the second cavity-containing layer 60 (FIG. 3E).

Each of the cavities 61 is formed along the SiO ₂ mask 50 arranged in a stripe shape. That is, each of the cavities 41 has an opening provided along the outer edge of the sapphire substrate 10 and communicates from one end of the wafer side surface to the other opposite end. Each of the cavities 50 functions as an etchant introduction hole for introducing an etchant into the second cavity-containing layer 20 when the sapphire substrate 10 is peeled off by wet etching in the subsequent growth substrate removing step (step S9). In addition, since each of the SiO ₂ masks 50 has the above-described relative positional relationship with the SiO ₂ mask 20 in the first mask layer, the cavities 61 and the first cavities in the second cavity-containing layer 60 are provided. The relative positional relationship with the cavity 41 inside the containing layer 40 also conforms to this. That is, each of the partition portions between the cavities 61 adjacent to each other is located at the upper part of each of the cavities 40.

In this step, the TMG flow rate can be set in the range of 10 to 70 μmol / min. The V / III ratio can be set in the range of 2000 to 22500, but is preferably set in the range of 3000 to 8000 from the viewpoint of flatness and crystallinity. In the above V / III ratio range, the NH ₃ flow rate can be set in the range of 3.3 to 5.5 LM. The total film thickness of the second cavity-containing layer 60 can be set in the range of 0.5 to 3 μm. Further, the same steps as those for the first cavity-containing layer 40 may be repeated.

(Semiconductor Epitaxial Layer Formation Step Step S7)
Next, a semiconductor epitaxial layer 70 including an n layer 71 made of a GaN-based semiconductor, a light emitting layer 72, and a p layer 73 is formed on the second cavity-containing layer 60 by MOCVD (FIG. 4F).

Specifically, the ambient temperature is set to 1000 ° C., TMG (flow rate 45 μmol / min), NH ₃ (flow rate 4.4 LM), and SiH ₄ as a dopant gas are supplied, and Si is doped at 5 × 10 ¹⁸ atoms / cm ^3. An n layer 71 having a thickness of about 1 to 10 μm is formed. The flow rate of TMG can be changed in the range of 10 to 70 μmol / min. NH ₃ can be changed within a range of 3.3 to 5.5LM. The V / III ratio can be set in the range of 2000 to 22500, more preferably 3000 to 8000.

Next, the ambient temperature is set to 760 ° C., TMG (flow rate 3.6 μmol / min), trimethylindium (TMI) (flow rate 3.6 μmol / min) and NH ₃ (flow rate 4.4 LM) are supplied, and GaN / In _y A strain relaxation layer (not shown) is formed by forming 30 pairs of Ga _1-y N (2 nm each). The flow rates of TMG and TMI can be changed in the range of 1 to 10 μmol / min. In this case, it is necessary to simultaneously change the TMI and the TMG flow rate so that the In composition is about y = 0.2. The flow rate of NH ₃ can be changed in the range of 3.3 to 5.5LM. In _x Ga _1-x N may be formed instead of GaN. In this case, it is necessary to adjust the flow rate so as to satisfy x <y. Moreover, the film thickness of the strain relaxation layer can be changed in the range of 50 to 300 nm by changing the film thickness and the number of pairs of each layer of GaN / In _y Ga _1-y N. Further, the strain relaxation layer may be doped with Si at a maximum of 5 × 10 ¹⁷ atoms / cm ³ .

Next, the ambient temperature is set to 730 ° C., TMG (flow rate 3.6 μmol / min), TMI (flow rate 10 μmol / min) and NH ₃ (flow rate 4.4 LM) are supplied, and a GaN barrier layer / In _y GaN well layer ( By forming five pairs each of 14 nm / 2 nm), the light emitting layer 72 having a multiple quantum well structure is formed. The flow rates of TMG and TMI can be changed in the range of 1 to 10 μmol / min. In this case, it is necessary to simultaneously change the TMI and TMG flow rates so that the y value indicating the In composition ratio is about 0.35. The flow rate of NH ₃ can be changed in the range of 3.3 to 5.5LM. The light emitting layer 72 may be doped with Si at a maximum of 5 × 10 ¹⁷ atoms / cm ³ .

Next, the ambient temperature was set to 870 ° C., TMG (flow rate 8.1 μmol / min), trimethylaluminum (TMA) (flow rate 7.6 μmol / min), NH ₃ (flow rate 4.4 LM), and CP2Mg (bis- By supplying cyclopentadienyl Mg), a p-Al _z Ga _1-z N layer (not shown) having a thickness of about 40 nm doped with 1 × 10 ²⁰ atoms / cm ³ of Mg is formed. The TMG flow rate can be changed in the range of 4 to 20 μmol / min. In this case, it is necessary to simultaneously change the flow rates of TMG and TMA so that the composition of Al is about Z = 0.2. The flow rate of NH ₃ can be changed in the range of 3.3 to 5.5LM. Moreover, the film thickness of the p-AlzGa _1-z N layer can be changed in the range of 20 to 60 nm.

Next, the ambient temperature is set to 870 ° C., and TMG (flow rate: 18 μmol / min), NH ₃ (flow rate: 4.4 LM), and CP2Mg (bis-cyclopentadienyl Mg) as a dopant gas are supplied, whereby Mg becomes 1 × 10 ²⁰ atoms / A p 3 layer 73 having a thickness of about 200 nm doped with cm ³ is formed. The TMG flow rate can be changed in the range of 8 to 36 μmol / min. The flow rate of NH ₃ can be changed in the range of 3.3 to 5.5LM. Further, the thickness of the p layer 33 can be changed within a range of 100 to 300 nm. Subsequently, the p layer 73 is activated by performing heat treatment for about 1 minute in a nitrogen atmosphere at about 900 ° C.

(Support Substrate Bonding Step Step S8)
Next, Pt (10 Å) and Ag (3000 Å) are deposited in this order on the p layer 73 by the EB method or the like to form the electrode layer 81. The Pt layer ensures ohmic contact with the p layer 73, and the Ag layer ensures high reflectivity. Subsequently, Ti (1000 Å), Pt (2000 Å) and Au (2000 Å) are deposited in this order to form the adhesive layer 82. The adhesive layer 82 constitutes an adhesive portion with the support substrate 90 described later (FIG. 4G).

Next, a support substrate 90 for supporting the semiconductor epitaxial layer 70 is prepared instead of the sapphire substrate 10. For example, a Si single crystal substrate can be used as the support substrate 90. On the support substrate 90, an adhesive layer 91 in which Pt, Ti, Ni, Au, and AuSn are laminated in this order is formed by the EB method or the like. Subsequently, the adhesive layer 91 and the adhesive layer 82 formed on the semiconductor epitaxial layer 70 are brought into close contact with each other and thermocompression-bonded in a vacuum or an N ₂ atmosphere, so that the support substrate 90 is provided on the p layer 73 side of the semiconductor epitaxial layer 70. Is pasted (FIG. 4H). The support substrate 90 may be formed by growing a metal film such as Cu on the semiconductor epitaxial layer 70.

(Growth substrate removal and concavo-convex forming step Step S9)
Next, the sapphire substrate 10 is peeled off by immersing the wafer that has undergone the above steps in 5M-KOH at a liquid temperature of 50 ° C. and etching the first and second cavity-containing layers 40 and 60. In this wet etching process, the etchant flows into the cavities 41 and 61 formed in the first and second cavity-containing layers 40 and 60. In wet etching using KOH, the etching rate in the direction perpendicular to the C-plane of GaN is higher than the etching rate in the lateral direction. For this reason, the inside of the cavities 41 and 61 is anisotropic etching in which etching proceeds upward in the stacking direction of the GaN film. That is, by this wet etching process, the cavities 41 and 61 are respectively expanded upward (FIG. 5 (i)). The sapphire substrate 10 is peeled from the semiconductor light emitting device including the semiconductor epitaxial layer 70 and the support substrate 90 when the etching progresses and the lower layer cavity 41 is combined with the upper layer cavity 61. Since the etching of the GaN film proceeds in the cavity 61 forming portion, the n layer 71 will be exposed after the sapphire substrate 10 is peeled off, but the part corresponding to the region between the adjacent cavities 61 is Since the sapphire substrate 10 is peeled before the etching reaches the n layer 71, this portion remains as the convex portion 100. That is, by this wet etching treatment, a rectangular uneven pattern having a relatively long period corresponding to the SiO ₂ mask pattern is formed on the peeling surface on the semiconductor light emitting element side after peeling the sapphire substrate 10 (in this embodiment, The convex portions 100 having a width of 1 μm are formed with a period of 4 μm so as to coincide with the SiO ₂ mask pattern). In this wet etching process, a large number of hexagonal pyramidal projections (microcones) having a width of about 0.2 μm derived from the crystal structure of GaN are formed on the etched surface along the long-period uneven surface. That is, in this step, the sapphire substrate 10 is peeled from the semiconductor light emitting element by performing an etching process by flowing an etchant into the cavities 41 and 61 formed in the first and second cavity-containing layers 40 and 60, Irregularities having a relatively long period and irregularities having a relatively short period are simultaneously formed on the surface of the semiconductor light emitting element (FIG. 5 (j)).

The etchant is not limited to KOH as long as it can etch a group III nitride semiconductor. For example, hot phosphoric acid, a mixed solution of hot phosphoric acid and sulfuric acid, or the like may be used. Alternatively, the GaN film may be etched after removing the SiO ₂ mask using HF or the like. In this case, etching becomes easy because the etchant easily enters the cavities 41 and 61.

(Electrode formation step Step S10)
Next, Ti and Al are sequentially deposited on the surface of the n layer 71 having the unevenness as described above by an EB method or the like, and further Ti / Au is deposited on the outermost surface to improve the bondability. It forms (FIG.5 (k)). In addition to Ti / Al, Al / Rh, Al / Ir, Al / Pt, Al / Pd, or the like may be used as the electrode material.

(Chip Separation Process Step S11)
Next, the semiconductor epitaxial layer 70 with the support substrate on which the n-electrode 110 is formed is separated into individual chips. In this step, first, a pattern in which grooves are provided between the chips on the surface of the semiconductor epitaxial layer 50 is patterned with a resist. Next, a trench is formed from the surface of the semiconductor epitaxial layer 70 to a depth reaching the electrode layer 81 by using reactive ion etching (Reactive Ion Etching). Thereafter, the support substrate 90 and the like are diced and separated into chips. A technique such as laser scribing may be used. The semiconductor light emitting device is completed through the above steps.

  As described above, according to the method for manufacturing a semiconductor light emitting device of the present invention, it is possible to peel off the sapphire substrate only by wet etching without using the LLO method. Problems such as cracks in the semiconductor film caused by peeling of the growth substrate used can be avoided. Furthermore, according to the method for manufacturing a semiconductor light emitting device of the present invention, batch processing of a plurality of wafers can be facilitated in the growth substrate peeling step, and productivity can be improved. Further, as described above, since the surface of the n layer 71 serving as the light extraction surface has irregularities with a relatively long period and irregularities with a relatively short period, the light extraction efficiency and the mechanical strength of the GaN film are high. It becomes possible to secure by level. That is, the mechanical strength is ensured by reducing the size of the microcone formed on the surface of the n layer, and the light extraction efficiency lowered thereby is complemented by the long-period unevenness. Even when the size of the microcone is small, Fresnel reflection resulting from the difference in refractive index of the interface is suppressed, and has a certain effect on improving the light extraction efficiency. According to the method for manufacturing a semiconductor light emitting device of the present invention, it is possible to simultaneously perform the formation of the concave / convex pattern on the light extraction surface and the separation of the growth substrate.

FIGS. 1A and 1B show protrusion valleys when a collet contacts the surface of a semiconductor film on which a relatively large protrusion is formed and the surface of a semiconductor film on which a relatively small protrusion is formed. It is the figure which showed the force added to a part. It is a manufacturing process flowchart of the semiconductor light-emitting device which is an Example of this invention. FIGS. 3A to 3E are cross-sectional views for each manufacturing process of the semiconductor light emitting device according to the embodiment of the present invention. 4F to 4H are cross-sectional views for each manufacturing process of the semiconductor light emitting device according to the embodiment of the present invention. 5 (i) to 5 (k) are cross-sectional views for each manufacturing process of the semiconductor light emitting device according to the embodiment of the present invention.

Explanation of symbols

10 sapphire substrate 20 SiO ₂ mask 21 mask portion 22 unmasked portion 40 first cavity-containing layer 41 cavity 50 SiO ₂ mask 51 unmasked portion 60 second void-containing layer 70 semiconductor epitaxial layer 90 the support substrate

Claims (11)

Forming a first cavity-containing layer including a plurality of first cavities on a growth substrate;
Each of the partition portions between the second cavities adjacent to each other including a plurality of second cavities is provided on top of each of the first cavities, and the partition portions between the first cavities adjacent to each other Forming on the first cavity-containing layer a second cavity-containing layer in which each of the second cavities is provided on each of the first cavity, and
Epitaxially growing a semiconductor layer on the second cavity-containing layer;
Bonding a support substrate on the semiconductor layer;
Introducing an etchant into each of the first and second cavities to couple each of the first cavities and each of the second cavities to remove the growth substrate from the semiconductor layer; The manufacturing method of the semiconductor element characterized by the above-mentioned. The step of forming the first cavity-containing layer includes
Forming a first mask for selective growth on the growth substrate;
A first selective growth step of selectively growing group III nitride on the growth substrate through the first mask to form a layer having a cavity provided on the first mask along the first mask. And including
The step of forming the second cavity-containing layer includes
Forming a second mask for selective growth on the first cavity-containing layer;
A second selection is performed in which a group III nitride is selectively grown on the first cavity-containing layer through the second mask to form a layer having a cavity provided on the second mask along the second mask. The method for manufacturing a semiconductor device according to claim 1, further comprising a growth step. The first selective growth step includes a first step of growing the group III nitride under conditions that promote vertical growth, and a second step of growing the group III nitride under conditions that promote lateral growth . The method for manufacturing a semiconductor device according to claim 2, further comprising a process of alternately performing the steps a plurality of times.   The first mask has an axis parallel to <10-10> of the crystal orientation of the group III nitride and a side parallel to an axis equivalent to this axis, and the other side from one end of the growth substrate. 4. The method of manufacturing a semiconductor element according to claim 2, wherein the semiconductor element has a pattern continuous to an end.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the first mask has a stripe pattern in which mask portions and non-mask portions are alternately arranged.   The second mask has a stripe pattern in which a mask portion and a non-mask portion are alternately arranged, and the non-mask portion of the second mask is positioned on the mask portion of the first mask. A method for manufacturing a semiconductor device according to claim 4 or 5.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the first mask has a mask portion having a width of 1 μm to 4 μm and a non-mask portion having a width of 1 μm to 3 μm.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the second mask has a width of the mask portion of 1 μm to 4 μm and a width of the non-mask portion of 1 μm to 3 μm.   9. The method of manufacturing a semiconductor device according to claim 1, wherein the etching of the first and second cavity-containing layers is anisotropic etching that proceeds in the stacking direction.   In the first selective growth step, a group III nitride is selectively grown on the growth substrate through the first mask at a temperature lower than the growth temperature of the semiconductor layer before the first and second steps are performed. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of:   The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer includes a light emitting layer.

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