JP5169152B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a TaC film as a mask.

  In recent years, in response to the demand for higher performance of semiconductor devices such as transistors and diodes, proposals have been made to employ SiC (silicon carbide), which is a wide bandgap semiconductor, as a material constituting the semiconductor device. On the other hand, the manufacturing process of a semiconductor device includes a step of forming a region where the type and concentration of impurities are different from the surrounding region inside the semiconductor device. In such a process, in a semiconductor device (SiC semiconductor device) employing SiC as a material constituting the semiconductor device, an SiC layer containing a desired impurity is selectively formed at a desired position in addition to being formed by ion implantation. , By a method of forming by epitaxial growth or the like (selective growth).

  In order to perform the selective growth in the manufacturing process of the SiC semiconductor device, a mask that covers a region other than the desired region in which the selective growth is performed is necessary. In the SiC semiconductor device, since the SiC growth performed by epitaxial growth or the like is performed at a high temperature, the mask is preferably made of a material having a high melting point and hardly causing SiC nucleation.

On the other hand, a proposal has been made to employ TaC (tantalum carbide), which has a high melting point and is unlikely to cause SiC nucleation, as a material constituting the SiC selective growth mask (see, for example, Non-Patent Document 1). ).
C. Li et. al, “Selective Growth of 4H-SiC on 4H-SiC Substrates Using a High Temperature Mask”, Materials Science Forum, Vol. 457-460, p. 185-188, 2004

In the manufacturing process of the SiC semiconductor device, a part of the SiC layer may be removed by etching and the SiC may be selectively grown in the region. In such a case, if selective growth can be performed using a mask for performing etching, the manufacturing process can be simplified. However, in etching using a gas containing F (fluorine) such as CF ₄ (carbon tetrafluoride), CHF ₃ (methane trifluoride), and SF ₆ (sulfur hexafluoride) as a SiC etching gas. The difference between the etching rate of SiC and the etching rate of TaC is small. Therefore, the etching ratio of SiC to TaC in etching using a gas containing F is small, and it is not easy to etch SiC using a mask composed of TaC. As a result, as described above, TaC has a high melting point and has an excellent characteristic that SiC nucleation hardly occurs. Therefore, despite being promising as a material constituting a mask for selective growth of SiC, There is a problem that a process of performing selective growth using a mask for performing etching cannot be employed.

On the other hand, first, a TaC film and a SiO ₂ (silicon dioxide) film are sequentially formed on SiC, and SiC is etched using the SiO ₂ film on the TaC film as a mask, and then SiC is selected using the TaC film as a mask. A step of performing growth may be employed. However, when such a process is adopted, there is a problem that the manufacturing process of the SiC semiconductor device becomes complicated.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can simplify the manufacturing process by allowing TaC to be used as a mask material for etching SiC.

  A method of manufacturing a semiconductor device according to the present invention includes a step of preparing an SiC member, a step of forming a TaC film on the SiC member, a step of forming the TaC film into a mask shape, and TaC formed into a mask shape. And a step of etching the SiC member using the film as a mask. In the step of etching the SiC member, the SiC member is etched by dry etching using a mixed gas containing a gas containing F and a gas containing O.

  The present inventor has studied in detail the etching rate of SiC and TaC in etching using an etching gas containing a gas containing F. As a result, by adding a gas containing O (oxygen) to an etching gas containing a gas containing F, it is possible to greatly suppress the etching rate of TaC while suppressing a change in the etching rate of SiC. I found it. That is, when etching SiC using an etching gas containing a gas containing F, by adding a gas containing O, the selectivity ratio of SiC to TaC is improved, and the mask for etching TaC into SiC It can be adopted as a material of

In the method for manufacturing a semiconductor device of the present invention, in the step of etching the SiC member, the SiC member is etched by dry etching using a mixed gas containing a gas containing F and a gas containing O. Therefore, etching of SiC members, such as a SiC substrate produced in a manufacturing process of a SiC semiconductor device and a SiC layer formed on the substrate, can be performed using a mask made of TaC. As a result, according to the method for manufacturing a semiconductor device of the present invention, TaC can be employed as a mask material for performing SiC etching, whereby the manufacturing process can be simplified. Can be provided. Further, in the method for manufacturing a semiconductor device of the present invention, the step of forming the TaC film into a mask shape includes the step of etching the TaC film at a first etching rate using an etching gas containing a gas containing F. By using an etching gas having a higher volume ratio of O-containing gas than the etching gas used in the step of etching at the first etching rate, the TaC film has a second etching rate lower than the first etching rate. Etching.

Here, the etching rate is a reduction amount per unit time of the thickness of a member to be etched in etching. Examples of the gas containing F include CF ₄ , CHF ₃ , SF ₆ , C _x F _y gas such as C ₄ F ₈ , C ₅ F ₈ , C ₄ F ₆ , NF _{3, and the} like. It is done. Further, examples of the gas containing O include O ₂ (oxygen), CO _x , NO _{x, and the} like.

  Preferably, in the method for manufacturing a semiconductor device, the mixed gas used for the dry etching contains a gas containing O in a volume ratio of 30% to 80%.

  By setting the volume ratio of the gas containing O contained in the mixed gas used for dry etching to 30% or more, it becomes possible to make the selection ratio of SiC to TaC be 2 or more, and etch TaC with SiC. It becomes easier to adopt as a mask material. On the other hand, the fall of the etching rate of SiC can be suppressed by making the volume ratio of the gas containing O contained in the mixed gas used for dry etching 80% or less.

  As described above, when TaC is etched using an etching gas containing a gas containing F, the etching rate of TaC can be suppressed by adding a gas containing O. According to the configuration of the step of forming the TaC film into a mask shape, first, the TaC film is efficiently etched at a high etching rate by using an etching gas having a low volume ratio of a gas containing O. Thereafter, the TaC film is etched so as to ensure high shape accuracy at a low etching rate by using an etching gas in which the volume ratio of the gas containing O is increased. Then, when the TaC film is formed into a desired shape, the etching is finished. Thereby, the TaC film can be formed into a mask shape with high shape accuracy and efficiently.

  Preferably, in the method for manufacturing the semiconductor device, the thickness of the TaC film in the step of forming the TaC film into a mask shape is 30 nm or more.

  As a result, the TaC film is formed into a mask having a sufficient thickness, and an etching gas having a relatively low selectivity can be employed in the process of etching the SiC member using the mask, and is used for etching SiC. The range of selection of the etching gas is widened.

  Preferably, in the manufacturing method of the semiconductor device, after the step of etching the SiC member, SiC is used on the SiC member exposed from the TaC film by using the TaC film used as a mask in the etching of the SiC member as a mask. The method further includes a step of epitaxial growth.

  A TaC film that has high heat resistance and is unlikely to generate SiC nuclei is suitable as a mask for selective growth of SiC. As described above, by performing selective growth using the TaC film used as a mask for SiC etching, the manufacturing process of the SiC semiconductor can be simplified.

  As is apparent from the above description, according to the method for manufacturing a semiconductor device of the present invention, TaC can be employed as a mask material for etching SiC, thereby simplifying the manufacturing process of the semiconductor device. It becomes possible.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view showing a configuration of a MOSFET (Metal Oxide Field Effect Transistor) as a semiconductor device according to the first embodiment which is an embodiment of the present invention. With reference to FIG. 1, the structure of MOSFET which is a semiconductor device in Embodiment 1 of this invention is demonstrated.

  Referring to FIG. 1, MOSFET 1 in the present embodiment includes an SiC substrate 11, an n-type SiC layer 12, a pair of p bodies 13, an n source region 14, and an n drain region 15. The SiC substrate 11 is made of 4H—SiC whose conductivity type is n-type (first conductivity type). N-type SiC layer 12 is formed on SiC substrate 11 and is an epitaxial layer made of SiC of n-type conductivity. The pair of p bodies 13 is an epitaxial layer made of SiC having a p-type conductivity (second conductivity type), and the first main surface 12A that is the main surface on the SiC substrate 11 side in the n-type SiC layer 12 They are formed so as to face each other across a region including the second main surface 12B, which is the opposite main surface. The n source region 14 and the n drain region 15 are formed in a region including a second surface 13B that is a surface opposite to the first surface 13A that is the surface on the SiC substrate 11 side in the pair of p bodies 13, Is made of n-type SiC.

  Further, referring to FIG. 1, MOSFET 1 includes a gate oxide film 16, a source electrode 17A, a gate electrode 17B, a drain electrode 17C, a source wiring 18A, a gate wiring 18B, a drain wiring 18C, and a passivation film. 19. Gate oxide film 16 is in contact with second main surface 12B of n-type SiC layer 12 and second surface 13B of the pair of p bodies 13 and from the upper surface of n source region 14 to the upper surface of n drain region 15. It is formed to extend up to. The source electrode 17A made of a conductor has n sources out of the second surface 131B which is the surface opposite to the first surface 131A which is the surface on the SiC substrate 11 side in one p body 131 of the pair of p bodies 13. It arrange | positions so that the area | region 14 may contact the area | region in which it was formed.

  The gate electrode 17B made of a conductor is disposed on the second main surface 12B of the n-type SiC layer 12 with the gate oxide film 16 interposed therebetween, and the n source region 14 is formed on the second surface 131B of one p body 131. This region extends from the formed region to the region where the n drain region 15 is formed on the second surface 132B of the other p body 132. The drain electrode 17C made of a conductor has n drains in the second surface 132B which is the surface opposite to the first surface 132A which is the surface on the SiC substrate 11 side in the other p body 132 of the pair of p bodies 13. It arrange | positions so that the area | region 15 may be contacted.

  Furthermore, the source wiring 18A, the gate wiring 18B, and the drain wiring 18C made of a conductor are disposed on the source electrode 17A, the gate electrode 17B, and the drain electrode 17C so as to be in contact with the source electrode 17A, the gate electrode 17B, and the drain electrode 17C, respectively. Has been. The passivation film 19 made of an insulator is formed so as to surround the source wiring 18A, the gate wiring 18B, the drain wiring 18C, and the gate electrode 17B.

  Next, the operation of MOSFET 1 will be described. Referring to FIG. 1, when the voltage of gate electrode 17B is 0 V, that is, in the off state, a pn junction that is reversely biased between n source region 14 and n drain region 15 located immediately below gate oxide film 16 is formed. Formed and non-conducting. On the other hand, when a positive voltage is applied to the gate electrode 17B, an inversion layer is formed in the channel region 13C, which is a region in contact with the gate oxide film 16 of the p body 13. As a result, the n source region 14 and the n drain region 15 are electrically connected, and a current flows between the n source region 14 and the n drain region 15.

  Next, a method for manufacturing a MOSFET according to the first embodiment, which is an embodiment of a method for manufacturing a semiconductor device according to the present invention, will be described. FIG. 2 is a flowchart showing an outline of the method of manufacturing the MOSFET in the first embodiment. 3 to 8 are schematic cross-sectional views for explaining the MOSFET manufacturing method in the first embodiment.

Referring to FIG. 2, in the MOSFET manufacturing method in the first embodiment, first, a substrate preparation step is performed in step (S10). Specifically, referring to FIG. 3, it is made of 4H—SiC, and includes n-type impurities (impurities whose conductivity type is n-type), so that the conductivity type is n-type (first conductivity type). A SiC substrate 11 is prepared. This SiC substrate 11 contains, for example, N, which is an n-type impurity, at a concentration of about 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²⁰ / cm ³ and has a thickness of about 300 to 500 μm.

Next, with reference to FIG. 2, an n-type SiC layer forming step is performed as a step (S20). Specifically, referring to FIG. 3, one main surface of SiC substrate 11 prepared in step (S10) is made of SiC and contains n-type impurities, so that the conductivity type becomes n-type. The n-type SiC layer 12 is formed by epitaxial growth. The n-type SiC layer 12 contains n as an n-type impurity at a concentration of about 1 × 10 ¹⁴ to 1 × 10 ¹⁸ / cm ³ , for example, 1 × 10 ¹⁶ / cm ³ , and has a thickness of about 1 to 200 μm, for example, It has a thickness of 10 μm. The n-type SiC layer 12 formed on the SiC substrate 11 constitutes an SiC member, and the steps (S10) and (S20) constitute an SiC member preparation step for preparing the SiC member.

  Next, referring to FIG. 2, as a step (S30), a TaC film forming step of forming a TaC film on n-type SiC layer 12 is performed. Specifically, referring to FIG. 4, TaC film 81 made of TaC is formed on n-type SiC layer 12 by PVD (Physical Vapor Deposition), for example, sputtering. The thickness of the TaC film 81 is 30 nm or more and 1000 nm or less, for example, about 250 nm.

Next, referring to FIG. 2, as a step (S40), a TaC mask forming step of forming TaC film 81 into a mask shape is performed. Specifically, referring to FIGS. 4 and 5, first, resist 91 is applied on TaC film 81 formed in step (S30). Thereafter, exposure and development are performed to form a mask pattern having an opening corresponding to the desired shape of the p body 13. Then, the TaC film 81 is etched using the resist 91 on which the mask pattern is formed as a mask. Etching of the TaC film 81 can be performed, for example, by ICP-RIE (Inductive Coupled Plasma-Reactive Ion Etching). ICP-RIE can be performed, for example, under conditions where the antenna power is 400 W, the bias is 20 W, the pressure is 0.6 Pa, and the SF ₆ gas, which is an etching gas, flows into the etching apparatus at a flow rate of 50 sccm. Thereby, the TaC film 81 is formed into a mask pattern having an opening corresponding to a desired shape of the p body 13.

In this step (S40), SF ₆ containing no oxygen (O ₂ ) except for impurities may be supplied into the etching apparatus, or SF containing 90% or less of O ₂ in volume fraction. A mixed gas of ₆ and O ₂ may be supplied. Further, the step (S40) is high when SF ₆ containing no O ₂ except for impurities is supplied into the etching apparatus after the step of forming a mask pattern on the resist 91 is performed, as shown in FIG. After the high rate etching step in which the TaC film 81 is etched at the etching rate, and after the high rate etching step, a mixed gas of SF ₆ and O ₂ is supplied into the etching apparatus so that the etching rate is lower than that in the high rate etching step. A low-rate etching step in which the TaC film 81 is etched.

When TaC is etched using a gas such as SF ₆ , CF ₄ , or CHF ₃ , the etching rate of TaC can be suppressed by adding O ₂ gas. As described above, first, the TaC film is efficiently etched at a high etching rate by using SF ₆ that does not contain O ₂ gas except impurities, and then a mixed gas of SF ₆ and O ₂ is used. By using the TaC film so as to ensure high shape accuracy at a low etching rate, the TaC film 81 can be efficiently formed into a mask shape with high shape accuracy.

  Next, referring to FIG. 2, as a step (S50), n-type SiC layer (SiC member) 12 formed on SiC substrate 11 is etched using TaC film 81 formed in a mask shape as a mask. An n-type SiC layer etching step is performed. Specifically, referring to FIGS. 5 and 6, after resist 91 is removed, TaC film 81 formed in a mask shape in step (S40) is used as a mask to form desired p body 13. The region of the n-type SiC layer 12 to be formed is removed by etching. The thickness of the n-type SiC layer 12 removed in the step (S50) is, for example, not less than 0.3 μm and not more than 2 μm, more specifically about 0.8 μm.

Etching of n-type SiC layer 12 can be performed, for example, by ICP-RIE. ICP-RIE is performed, for example, under conditions where the antenna power is 400 W, the bias is 20 W, the pressure is 0.6 Pa, and the etching gas SF ₆ gas and O ₂ gas are each flowed into the etching apparatus at a flow rate of 50 sccm. can do. That is, in the step (S50), the n-type SiC layer 12 is etched by dry etching using a mixed gas containing SF ₆ gas and O ₂ gas.

Here, the mixed gas containing SF ₆ gas and O ₂ gas in the etching apparatus contains O ₂ gas in a volume ratio of 30% to 80%, specifically about 50%. As a result, the selection ratio of SiC to TaC in the etching in the step (S50) is about 5. Therefore, as described above, when the thickness of the TaC film 81 is 0.25 μm, and the n-type SiC layer 12 is etched by 0.8 μm in the step (S50), the TaC film 81 used as the mask has the step ( S50) Even after completion, it remains with a thickness of about 0.1 μm.

Next, referring to FIG. 2, as a step (S60), the TaC film 81 used as a mask for etching the n-type SiC layer 12 in the step (S50) is used as a mask to be exposed from the TaC film 81. A selective growth step of epitaxially growing SiC on the n-type SiC layer 12 is performed. Specifically, referring to FIGS. 6 and 7, the conductivity type becomes p-type (second conductivity type) by containing p-type impurities on n-type SiC layer 12 exposed from TaC film 81. A pair of p bodies 13 made of SiC (one p body 131 and the other p body 132) are formed by epitaxial growth. As a result, the region of n-type SiC layer 12 removed in step (S50) is filled with a pair of p bodies 13. The pair of p bodies 13 contains Al, B, etc. as p-type impurities at a concentration of 1 × 10 ¹⁵ / cm ^{3 to} 1 × 10 ¹⁹ / cm ³ , for example, 1 × 10 ¹⁸ / cm ³ .

  Next, referring to FIG. 2, as step (S70), an n-type impurity is introduced into each of the pair of p bodies 13 formed in step (S60), so that n source region 14 and n drain region are formed. An n-type impurity introduction step for forming 15 is performed. Specifically, referring to FIGS. 7, 8 and 1, first, TaC film 81 of FIG. 7 is removed as shown in FIG. 8 using, for example, hydrofluoric acid, and then the n source shown in FIG. Region 14 and n drain region 15 are formed in a region including second surface 131B of one p body 131 and second surface 132B of the other p body 132, for example, by ion implantation.

  Next, referring to FIG. 2, as a step (S80), activation is performed in which a member made of SiC formed by completing the steps up to step (S70) is heated to a temperature of 1400 ° C. or higher and 1900 ° C. or lower. An annealing step is performed. Thereby, the n-type impurity and the p-type impurity contained in the member are activated. Further, as a step (S90), a gate oxide film forming step for forming a gate oxide film is performed. Specifically, referring to FIG. 1, first, second main surface 12B of n-type SiC layer 12 exposing the upper surfaces of p body 13, n source region 14 and n drain region 15 is thermally oxidized. As a result, a thermal oxide film is formed in the region including the second main surface 12B. Thereafter, a part of the thermal oxide film is formed by, for example, photolithography and etching so that a region extending from the upper surface of the n source region 14 to the upper surface of the n drain region 15 remains in the formed thermal oxide film. Removed. Thereby, the gate oxide film 16 is formed.

  Next, referring to FIG. 2, as step (S100), n source region 14 and n drain region 15 are brought into contact with n source region 14 and n drain region 15, and n source region 14 and n drain region 15 are brought into contact with each other. An ohmic electrode forming step is performed in which the source electrode 17A and the drain electrode 17C are formed as ohmic electrodes made of a conductor capable of ohmic contact. Specifically, referring to FIG. 1, a source electrode 17A made of a conductive material such as Ni (nickel) that can be in ohmic contact with n source region 14 is formed on n source region 14 by vapor deposition or the like. On the n drain region 15, a drain electrode 17C made of a conductor capable of making ohmic contact with the n drain region 15, such as Ni, is formed by vapor deposition or the like.

  Next, referring to FIG. 2, in step (S110), a gate electrode forming step is performed in which a gate electrode is formed on gate oxide film 16 so as to be in contact with gate oxide film 16. Specifically, referring to FIG. 1, gate electrode 17B made of a conductor and extending from the upper surface of n source region 14 to the upper surface of n drain region 15 with gate oxide film 16 interposed therebetween It is formed by vapor deposition or the like.

  Next, referring to FIG. 2 and FIG. 1, in step (S120), a source wiring as an easily bonding wiring made of a metal such as Al (aluminum) on source electrode 17A, gate electrode 17B and drain electrode 17C. A wiring formation process is performed in which 18A, gate wiring 18B and drain wiring 18C are formed. Referring to FIGS. 2 and 1, in step (S130), a passivation film 19 made of an insulator is formed so as to surround source wiring 18A, gate wiring 18B, drain wiring 18C and gate electrode 17B. A process is performed. Through the above process, MOSFET 1 in the present embodiment is completed.

In the method for manufacturing MOSFET 1 in the present embodiment, in the step (S50), the n-type SiC layer is etched by dry etching using a mixed gas containing SF ₆ gas and O ₂ gas. Therefore, etching of the n-type SiC layer 12 produced in the manufacturing process of the MOSFET 1 can be performed using a mask made of the TaC film 81. As a result, according to the method for manufacturing MOSFET 1 in the present embodiment, it is possible to simplify the manufacturing process of MOSFET 1 by adopting TaC as a mask material for etching SiC.

(Embodiment 2)
Next, a semiconductor device according to the second embodiment which is an embodiment of the present invention will be described. FIG. 9 is a schematic cross-sectional view showing the configuration of a JFET (Junction Field Effect Transistor) according to the second embodiment.

  Referring to FIG. 9, JFET 3 as the semiconductor device in the second embodiment is formed on SiC substrate 31, first p-type SiC layer 32 formed on SiC substrate 31, and first p-type SiC layer 32. The n-type SiC layer 33 and the second p-type SiC layer 34 formed on the n-type SiC layer 33 are provided. The SiC substrate 31 is made of 4H—SiC whose conductivity type is n-type (first conductivity type). The first p-type SiC layer 32 and the second p-type SiC layer 34 are epitaxial layers made of SiC whose conductivity type is p-type (second conductivity type). N-type SiC layer 33 is an epitaxial layer made of SiC of n-type conductivity.

  Further, JFET 3 includes an n source region 35, a p gate region 36, and an n drain region 37 formed so as to penetrate the second p type SiC layer 34 in the thickness direction and extend into the n type SiC layer 33. ing. That is, the bottoms of the n source region 35, the p gate region 36, and the n drain region 37 are spaced from the upper surface of the first p-type SiC layer 32 (the boundary between the first p-type SiC layer 32 and the n-type SiC layer 33). They are spaced apart. N source region 35 and n drain region 37 are epitaxial layers made of SiC containing n type impurities at a higher concentration than n type SiC layer 33 and having n type conductivity. The p gate region 36 is an epitaxial layer containing p-type impurities at a higher concentration than the second p-type SiC layer 34 and made of SiC having a conductivity type of p-type.

  Furthermore, on the n source region 35, the p gate region 36, and the n drain region 37, the source electrode 41A and the gate electrode 41B are in contact with the upper surfaces of the n source region 35, the p gate region 36, and the n drain region 37. And the drain electrode 41C is formed. The source electrode 41A, the gate electrode 41B, and the drain electrode 41C are made of a conductor such as metal. An oxide film 38 is formed between the electrodes 41A, 41B, and 41C. Thereby, between each adjacent electrode 41A, 41B, 41C is insulated.

  On the source electrode 41A, the gate electrode 41B, and the drain electrode 41C, the source wiring 42A, the gate wiring 42B, and the drain wiring 42C are formed so as to be in contact with the upper surfaces of the source electrode 41A, the gate electrode 41B, and the drain electrode 41C. Yes. The source wiring 42A, the gate wiring 42B, and the drain wiring 42C are made of a conductor such as metal. Then, a passivation film 43 made of an insulator is formed so as to surround the source wiring 42A, the gate wiring 42B, and the drain wiring 42C.

  Next, the operation of JFET 3 will be described. Referring to FIG. 9, when the voltage of gate electrode 41B is 0 V, the region (channel region) sandwiched between p gate region 36 and first p type SiC layer 32 in n type SiC layer 33 is completely It is not depleted, and the n source region 35 and the n drain region 37 are electrically connected via the channel region. Therefore, current flows as electrons move from the n source region 35 toward the n drain region 37.

  On the other hand, when a negative voltage is applied to the gate electrode 41B, the above-described depletion of the channel region proceeds, and the n source region 35 and the n drain region 37 are electrically cut off. Therefore, electrons cannot move from the n source region 35 toward the n drain region 37, and no current flows.

  Next, a method for manufacturing a JFET according to the second embodiment, which is an embodiment of a method for manufacturing a semiconductor device according to the present invention, will be described. FIG. 10 is a flowchart showing an outline of a method of manufacturing a JFET in the second embodiment. FIGS. 11 to 21 are schematic cross-sectional views for explaining the method of manufacturing the JFET in the second embodiment.

  Referring to FIG. 10, in the method for manufacturing a JFET in the second embodiment, first, a substrate preparation step is performed in step (S210). Specifically, referring to FIG. 11, similarly to the step (S10) of the first embodiment, SiC substrate 31 made of 4H—SiC and having an n-type conductivity by including an n-type impurity. Is prepared.

Next, with reference to FIG. 10, a 1st p-type SiC layer formation process is implemented as process (S220). Specifically, referring to FIG. 11, one main surface of SiC substrate 31 prepared in step (S <b> 210) is made of SiC, and includes p-type impurities, whereby the conductivity type becomes p-type. The first p-type SiC layer 32 is formed by epitaxial growth. This first p-type SiC layer 32 contains p-type impurities such as Al and B at a concentration of about 1 × 10 ¹⁵ to 1 × 10 ¹⁸ / cm ³ , for example, 1 × 10 ¹⁶ / cm ³ , and about 2 to 50 μm. It has a thickness, for example, 10 μm.

Next, with reference to FIG. 10, an n-type SiC layer formation process is implemented as process (S230). Specifically, referring to FIG. 11, n is formed of SiC on the first p-type SiC layer 32 formed in the step (S220), and the conductivity type is n-type by including n-type impurities. A type SiC layer 33 is formed by epitaxial growth. The n-type SiC layer 33 contains N as an n-type impurity at a concentration of about 1 × 10 ¹⁶ to 2 × 10 ¹⁸ / cm ³ , for example, 2 × 10 ¹⁷ / cm ³ , and about 0.1 to 1.5 μm. For example, 0.4 μm.

Next, referring to FIG. 10, a second p-type SiC layer forming step is performed as a step (S240). Specifically, referring to FIG. 11, the second p, which is made of SiC on the n-type SiC layer 33 formed in the step (S230) and has a p-type conductivity by containing p-type impurities. A type SiC layer 34 is formed by epitaxial growth. The second p-type SiC layer 34 includes p-type impurities such as Al and B at a concentration of about 1 × 10 ¹⁶ to 2 × 10 ¹⁸ / cm ³ , for example, 2 × 10 ¹⁷ / cm ^3, and has a thickness of 0.1 to 1 μm. It has a thickness of about, for example, 0.2 μm. The n-type SiC layer 33 and the second p-type SiC layer 34 formed on the SiC substrate 31 constitute an SiC member, and the steps (S210) to (S240) constitute an SiC member preparation step for preparing the SiC member. .

  Next, referring to FIG. 10, as a step (S250), a TaC film forming step of forming a TaC film on second p-type SiC layer 34 is performed. Specifically, referring to FIG. 12, TaC film 81 made of TaC is formed on second p-type SiC layer 34 by PVD, for example, sputtering. The thickness of the TaC film 81 is 30 nm or more and 1000 nm or less, for example, about 200 nm.

  Next, referring to FIG. 2, as a step (S260), a TaC mask forming step of forming TaC film 81 into a mask shape is performed. Specifically, referring to FIGS. 12 and 13, first, resist 91 is applied onto TaC film 81 formed in step (S250). Thereafter, exposure and development are performed, so that a mask pattern having openings corresponding to the desired shapes of the n source region 35 and the n drain region 37 is formed. Then, the TaC film 81 is etched using the resist 91 on which the mask pattern is formed as a mask. Etching of the TaC film 81 can be performed in the same manner as in the step (S40) of the first embodiment. As a result, the TaC film 81 is formed into a mask pattern having openings corresponding to the desired shapes of the n source region 35 and the n drain region 37.

  Next, referring to FIG. 10, as a step (S270), n-type SiC layer 33 and second p-type SiC layer formed on SiC substrate 31 using TaC film 81 formed in a mask shape as a mask. A SiC layer etching step for etching 34 (SiC member) is performed. Specifically, referring to FIGS. 13 and 14, in step (S270), after resist 91 is removed, TaC film 81 formed in the mask shape in step (S260) is used as a mask. The regions of the n-type SiC layer 33 and the second p-type SiC layer 34 where the desired n source region 35 and n drain region 37 are to be formed are removed by etching. The thicknesses of the n-type SiC layer 33 and the second p-type SiC layer 34 removed in the step (S270) are the thickness of the p-type SiC layer 34 + 0.05 μm or more, the thickness of the p-type SiC layer 34 + the thickness of the n-type SiC layer 33. -0.05 μm or so. As a result, the region to be removed penetrates the second p-type SiC layer 34 in the thickness direction and extends to the inside of the n-type SiC layer 33. Etching of n-type SiC layer 33 and second p-type SiC layer 34 can be performed under the same conditions as in step (S50) of the first embodiment.

Next, referring to FIG. 10, as step (S280), TaC film 81 used as a mask for etching n-type SiC layer 33 and second p-type SiC layer 34 in step (S270) is used as a mask. Then, an n ⁺ region selective growth step is performed in which SiC containing high-concentration n-type impurities is epitaxially grown on the n-type SiC layer 33 exposed from the TaC film 81. Specifically, referring to FIG. 14 and FIG. 15, SiC whose conductivity type is n-type by containing high-concentration n-type impurities on n-type SiC layer 33 exposed from TaC film 81. An n source region 35 and an n drain region 37 made of are formed by epitaxial growth. As a result, one of the regions of the pair of n-type SiC layer 33 and second p-type SiC layer 34 removed in the step (S270) is filled with the n source region 35, and the other region is filled with the n drain region 37. The In the n source region 35 and the n drain region 37, N, P, As, etc. as n-type impurities have a concentration of 1 × 10 ¹⁸ / cm ³ or more and 1 × 10 ²¹ / cm ³ or less, for example, 1 × 10 ¹⁹ / cm ^3. Contains.

  Next, referring to FIG. 10, as a step (S290), a TaC film re-forming step of forming a TaC film again on second p-type SiC layer 34 is performed. Specifically, referring to FIGS. 115 to 17, after TaC film 81 shown in FIG. 15 used as a mask in step (S280) is removed as shown in FIG. As shown in FIG. 17, the TaC film 81 is formed again by the same procedure as in the step (S250).

  Next, referring to FIG. 10, as a step (S300), a TaC mask re-forming step for forming the re-formed TaC film 81 into a mask shape is performed. Specifically, referring to FIGS. 17 and 18, first, a resist is applied on TaC film 81 formed in step (S290). Thereafter, exposure and development are performed to form a mask pattern having an opening corresponding to the desired shape of the p gate region 36. Then, the resist on which the mask pattern is formed is used as a mask, and the TaC film 81 is etched. Etching of the TaC film 81 can be performed in the same manner as in the step (S40) of the first embodiment. Thereby, the TaC film 81 is formed into a mask pattern having an opening corresponding to the desired shape of the p gate region 36.

  Next, referring to FIG. 10, as a step (S310), n-type SiC layer 33 in which n source region 35 and n drain region 37 are formed using TaC film 81 formed in a mask shape as a mask, and A second SiC layer etching step for etching the second p-type SiC layer 34 (SiC member) is performed. Specifically, referring to FIG. 18 and FIG. 19, n-type SiC layer in which a desired p gate region 36 is to be formed using TaC film 81 formed in a mask shape in step (S <b> 300) as a mask. The regions of 33 and the second p-type SiC layer 34 are removed by etching. The thicknesses of the n-type SiC layer 33 and the second p-type SiC layer 34 removed in the step (S310) are the thickness of the p-type SiC layer 34 + 0.05 μm or more, the thickness of the p-type SiC layer 34 + the thickness of the n-type SiC layer 33. -0.05 μm or so. As a result, the region to be removed penetrates the second p-type SiC layer 34 in the thickness direction and extends to the inside of the n-type SiC layer 33. Etching of n-type SiC layer 33 and second p-type SiC layer 34 can be performed under the same conditions as in step (S50) of the first embodiment.

Next, referring to FIG. 10, as step (S320), TaC film 81 used as a mask for etching n-type SiC layer 33 and second p-type SiC layer 34 in step (S310) is used as a mask. Then, a p ⁺ region selective growth step is performed in which SiC containing high-concentration p-type impurities is epitaxially grown on the n-type SiC layer 33 exposed from the TaC film 81. Specifically, referring to FIG. 19 and FIG. 20, SiC whose conductivity type is p-type by containing high-concentration p-type impurities on n-type SiC layer 33 exposed from TaC film 81. A p-gate region 36 made of is formed by epitaxial growth. As a result, the regions of n-type SiC layer 33 and second p-type SiC layer 34 removed in step (S310) are filled with p-gate region 36. The p gate region 36 contains Al, B, etc. as p-type impurities at a concentration of 1 × 10 ¹⁷ / cm ³ or more and 2 × 10 ²⁰ / cm ³ or less, for example, 1 × 10 ¹⁸ / cm ³ .

  Next, referring to FIG. 10, FIG. 20, and FIG. 21, as a step (S330), a member made of SiC shown in FIG. 20 formed by completing the steps up to step (S320) is shown in FIG. Thus, after the TaC film 81 is removed, an activation annealing step is performed in which the member is heated to a temperature of 1400 ° C. or higher and 1900 ° C. or lower. Thereby, the n-type impurity and the p-type impurity contained in the member are activated. Further, as a step (S340), an oxide film forming step for forming an oxide film is performed. Specifically, referring to FIG. 9, oxide film 38 is formed on the upper surface of second p-type SiC layer 34 where the upper surfaces of n source region 35, p gate region 36 and n drain region 37 are exposed. . The oxide film 38 can be formed by, for example, thermal oxidation, CVD (Chemical Vapor Deposition), or the like.

  Next, referring to FIG. 10, as a step (S350), the n source region 35, the p gate region 36 and the n drain region 37 are contacted on the n source region 35, the p gate region 36 and the n drain region 37. Then, an electrode forming step is performed in which a source electrode 41A, a gate electrode 41B, and a drain electrode 41C made of a conductor that can make ohmic contact with at least the n source region 35 and the n drain region 37, such as Ni, are formed.

  This electrode formation process can be implemented as follows, for example. First, a resist film having openings corresponding to the shapes of the desired source electrode 41A, gate electrode 41B, and drain electrode 41C is formed on the oxide film 38 by photolithography. Then, using this as a mask, a part of oxide film 38 is removed by RIE, for example. Thereafter, a metal such as Ni constituting the source electrode 41A, the gate electrode 41B, and the drain electrode 41C is evaporated from the resist film to the inside of the opening formed in the oxide film 38 to form a metal film. Thereafter, by removing the resist film, the metal film on the oxide film 38 is removed (lifted off), and the source electrode 41A, the gate electrode 41B, and the drain electrode 41C are formed by the metal film remaining in the opening. .

  Next, referring to FIGS. 10 and 9, in step (S360), source wiring 42A as a wiring made of metal such as Al that can be easily bonded on gate electrode 41A, gate electrode 41B, and drain electrode 41C, gate A wiring formation process for forming the wiring 42B and the drain wiring 42C is performed. 10 and 9, in the step (S370), a passivation process is performed in which a passivation film 43 made of an insulator is formed so as to surround the source wiring 42A, the gate wiring 42B, and the drain wiring 42C. . The JFET 3 in the present embodiment is completed through the above steps.

In the method for manufacturing JFET 3 in the present embodiment, the SiC layer is etched by dry etching using a mixed gas containing SF ₆ gas and O ₂ gas in steps (S270) and (S310). Therefore, the n-type SiC layer 33 and the second p-type SiC layer 34 produced in the manufacturing process of the JFET 3 can be etched using the mask made of the TaC film 81. As a result, according to the manufacturing method of JFET 3 in the present embodiment, it is possible to simplify the manufacturing process of JFET 3 by using TaC as a mask material for etching SiC.

  In the embodiment described above, the epitaxial layer formed on the SiC substrate has been described as the SiC member prepared in the method for manufacturing a semiconductor device of the present invention. However, the SiC member of the present invention is not limited to this, For example, a SiC substrate may be used.

  Further, as described above, the method of manufacturing a semiconductor device of the present invention is characterized in that a mask made of TaC can be used particularly in etching of a SiC member. Therefore, although the case where the semiconductor device to be manufactured is a MOSFET and the case of a JFET has been described in the above embodiment, the semiconductor device that can be manufactured by the method for manufacturing a semiconductor device of the present invention is not limited thereto. The manufacturing method of the semiconductor device of the present invention includes a body portion such as a pn diode, a bipolar transistor, and an IGBT (Insulated Gate Bipolar Transistor), and a guard ring such as a Schottky diode, a pn diode, a bipolar transistor, and an IGBT. The present invention can be applied to various semiconductor device manufacturing methods including a withstand voltage holding structure.

  Embodiment 1 of the present invention will be described below. In the case where SiC is dry-etched with an etching gas containing a gas containing F using a TaC film as a mask, the volume ratio of the gas containing O in the etching gas, the etching rate of SiC, and the SiC relative to TaC A test was conducted to investigate the relationship with the selectivity. The test procedure is as follows.

First, a SiC substrate was prepared, and a TaC film was formed on the SiC substrate. The thickness of the TaC film was 0.3 μm. Next, after applying a resist on the TaC film, patterning was performed by photolithography, and the TaC film was etched using the resist as a mask. For etching the TaC film, SF ₆ was used as an etching gas. Further, the SiC substrate was etched using a mixed gas of SF ₆ which is a gas containing F and O ₂ which is a gas containing O as an etching gas. The etching of the SiC substrate uses ICP-RIE, and the conditions of a power of 400 W, a bias of 20 W, a flow rate of 50 sccm into the etching device of SF ₆ and a pressure of 0.6 Pa are fixed, and then the flow rate of O _{2 into} the etching device. This was performed under the condition of changing.

Then, the etching rate of SiC and the selection ratio of SiC to TaC in each volume ratio of O ₂ in the mixed gas changed by changing the flow rate of O _{2 into} the etching apparatus were investigated.

Next, the test results of this example will be described. FIG. 22 is a diagram showing test results of Example 1. In FIG. 22, circles indicate the selection ratio of SiC to TaC, and triangles indicate the etching rate of SiC. In FIG. 22, the horizontal axis represents the volume ratio of O _{2 in} the mixed gas, the left vertical axis represents the etching rate of SiC, and the right vertical axis represents the selection ratio of SiC to TaC. Here, the etching rate of SiC represents the amount of decrease in the thickness of the SiC substrate per minute. Further, the selection ratio of SiC to TaC represents the ratio of the decrease amount of the thickness of the SiC substrate to the decrease amount of the thickness of the TaC film per unit time.

Referring to FIG. 22, it is confirmed that the selection ratio of SiC to TaC increases as the volume ratio of O _{2 in} the mixed gas increases. On the other hand, even if the volume ratio of O _{2 in} the mixed gas increases, the change in the etching rate of SiC is relatively small. From this, by mixing O ₂ which is a gas containing O with SF ₆ which is a gas containing F, the selectivity ratio of SiC to TaC is increased without substantially affecting the etching rate of SiC. It was confirmed that it was possible.

  Furthermore, referring to FIG. 22, when the volume ratio of oxygen exceeds 80%, the increase in the selection ratio of SiC to TaC is saturated and the etching rate of SiC starts to decrease. From this, it can be said that the volume ratio of oxygen is preferably 80% or less. Further, in order to use TaC as an etching mask for SiC, the selection ratio is preferably 2 or more. From this, it can be said that the volume ratio of oxygen is preferably 30% or more with reference to FIG. Furthermore, it can be seen from FIG. 22 that when the volume ratio of oxygen is 50% or more, the selection ratio is significantly increased, and it becomes easier to use TaC as an SiC etching mask. Therefore, the volume ratio of oxygen in the mixed gas is preferably 50% or more.

  The embodiments and examples disclosed herein are illustrative in all respects and should not be construed as being restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The method for manufacturing a semiconductor device of the present invention can be applied particularly advantageously to a method for manufacturing a semiconductor device using a TaC film as a mask.

1 is a schematic cross-sectional view showing a configuration of a MOSFET according to a first embodiment. 3 is a flowchart showing an outline of a method of manufacturing a MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 5 is a schematic cross-sectional view showing a configuration of a JFET in a second embodiment. 5 is a flowchart showing an outline of a method for manufacturing a JFET in a second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the second embodiment. It is a figure which shows the test result of Example 1.

Explanation of symbols

  1 MOSFET, 3 JFET, 11, 31 SiC substrate, 12 n-type SiC layer, 12A 1st main surface, 12B 2nd main surface, 13p body, 13A 1st surface, 13B 2nd surface, 13C channel region, 131 p body, 131A, 132A first surface, 131B, 132B second surface, 132 p body, 14, 35 n source region, 15, 37 n drain region, 16 gate oxide film, 17A, 41A source electrode 17B, 41B gate electrode, 17C, 41C drain electrode, 18A, 42A source wiring, 18B, 42B gate wiring, 18C, 42C drain wiring, 19, 43 passivation film, 32 1st p-type SiC layer, 33 n-type SiC layer, 34 second p-type SiC layer, 36 p gate region, 38 oxide film, 81 TaC film, 9 Resist.

Claims (4)

Preparing a SiC member;
Forming a TaC film on the SiC member;
Forming the TaC film into a mask shape;
Using the TaC film formed in a mask shape as a mask, and etching the SiC member,
In the step of etching the SiC member, said SiC member by dry etching using a mixed gas containing a gas containing gas and O containing F is etched,
The step of forming the TaC film into a mask shape includes:
Etching the TaC film at a first etching rate using an etching gas containing a gas containing F;
By using an etching gas having a higher volume ratio of O-containing gas than the etching gas used in the step of etching at the first etching rate, the second etching rate is lower than the first etching rate. And a step of etching the TaC film .   The method of manufacturing a semiconductor device according to claim 1, wherein the mixed gas contains a gas containing O in a volume ratio of 30% to 80%. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a film thickness of the TaC film in the step of forming the TaC film into a mask shape is 30 nm or more. After the step of etching the SiC member, using the TaC film as a mask, the SiC onto the SiC member exposed from the TaC film further comprising a step of epitaxially growing, either of claims 1-3 1 A method for manufacturing a semiconductor device according to item.

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