JP5109684B2 - Detection device and electronic device - Google Patents

Description

  The present invention relates to a detection device and an electronic apparatus equipped with the detection device.

  The following is known as one of detection devices used for a two-dimensional sensor, an image sensor, an optical touch sensor, and the like. That is, a photoelectric conversion element as a detection element, a capacitive element whose stored charge amount changes according to the amount of light received by the photoelectric conversion element, and a transistor, and charge storage in the capacitive element by on / off operation of the transistor This is a detection device configured to read the amount (see, for example, Patent Document 1).

  In addition, when the photoelectric conversion element is replaced with a storage capacitor in the above, the amount of charge stored in the capacitor changes according to an increase or decrease caused by an external factor of the storage capacitor. The detection device can also be configured to use a storage capacitor as the detection element.

JP-A-4-212458

  In the detection apparatus as described above, the detection resolution is improved as the detection elements are arranged at higher density. However, when various components such as transistors and wirings connected to the terminals of the transistors are arranged at a high density, there are problems that the characteristics of the transistors are deteriorated and the characteristics are increased. Alternatively, there is a problem that signal delay occurs due to the complicated wiring structure, and the yield decreases.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 Substrate, a plurality of scanning lines, a plurality of detection lines, a plurality of first power supply lines, a plurality of second power supply lines, the scanning lines, and the detection arranged on the substrate A plurality of unit circuits provided corresponding to the intersection with the line, the unit circuit having a first terminal connected to the detection line and a second terminal connected to the first power supply line, A first transistor that supplies a detection signal corresponding to the potential of the gate electrode to the detection line, and a detection element that is connected to the gate electrode of the first transistor and changes the gate potential of the first transistor according to an external factor A second transistor having a first terminal connected to the gate electrode of the first transistor, a second terminal connected to the second power supply line, and a gate electrode connected to the scan line; Maintain the gate potential of the transistor A first capacitive element that has a first transistor, the direction of the channel length, and are detection device along the direction of the channel length of the second transistor.

  According to such a configuration, since the first transistor outputs a current having a magnitude corresponding to an external factor to the detection line, the current for the unit circuit selected by the scanning line is sequentially detected, so that Can be detected. Here, since the channel length direction of the first transistor is along the channel length direction of the second transistor, the channel region of the first transistor and the channel region of the second transistor are arranged together in the smallest region. can do. Here, the channel length refers to the length of the channel region along the direction from the first terminal to the second terminal of the transistor. As a result, the first transistor and the second transistor can be arranged with high density. In the above configuration, the first power supply line and the second power supply line may be electrically connected. That is, the first power supply line and the second power supply line may be shared. In this way, the circuit configuration of the detection device can be simplified. In addition, it is possible to simplify the layer structure of the unit circuit and increase the density of the unit circuit.

  Application Example 2 In the detection device, the first transistor and the second transistor have a channel length direction that intersects the extending direction of the scanning line and the extending direction of the detection line in plan view. The detection device is arranged as follows.

  According to such a configuration, since the arrangement pitch of the channel regions of the first transistor and the second transistor can be reduced, the arrangement pitch of the unit circuits can be reduced. Thereby, the resolution of a detection apparatus can be improved. In the above description, “in plan view” means “as viewed from the normal direction of the substrate”.

  Application Example 3 In the detection device, the first transistor and the second transistor have a channel length direction with respect to an extension direction of the scanning line and an extension direction of the detection line in plan view. A detection device arranged to form an angle of 45 degrees.

  According to such a configuration, the arrangement pitch of the channel regions of the first transistor and the second transistor can be reduced in both the scanning line extending direction and the detecting line extending direction. It is possible to reduce the arrangement pitch of the unit circuits. Thereby, the resolution of a detection apparatus can be improved.

  Application Example 4 In the detection device, the first terminal and the second terminal of the first transistor along a direction intersecting the extending direction of the scanning line and the extending direction of the detection line in a plan view. And a first terminal and a second terminal of the second transistor are arranged along a direction intersecting the extending direction of the scanning line and the extending direction of the detection line in plan view.

  According to such a configuration, the first terminal and the second terminal of each transistor can be arranged in a state of being separated from each other. Further, when the wiring is arranged along the extending direction of the scanning line or the detection line, the wiring can be arranged in a straight line while minimizing a region overlapping with the first transistor and the second transistor. For this reason, signal delay due to complicated wiring can be prevented.

  Application Example 5 In the detection device, the first transistor of the first transistor extends in a direction that forms an angle of 45 degrees with respect to the extending direction of the scanning line and the extending direction of the detection line in plan view. 1 terminal and 2nd terminal are arrange | positioned, and the 1st terminal of the said 2nd transistor is along the direction which makes an angle of 45 degree | times with respect to the extending direction of the said scanning line and the extending direction of the said detection line in planar view And a detection device in which the second terminal is arranged.

  According to such a configuration, the first terminal and the second terminal of each transistor can be arranged in a state of being separated from each other. Further, when the wiring is arranged along the extending direction of the scanning line or the detection line, the wiring can be arranged in a straight line while minimizing a region overlapping with the first transistor and the second transistor. For this reason, signal delay due to complicated wiring can be prevented.

  Application Example 6 In the detection device described above, in the unit circuit, the first transistor and the second transistor are arranged between the detection line and the second power supply line in a plan view. .

  According to such a configuration, the second power supply line and the detection line can be arranged linearly. For this reason, signal delay due to complicated wiring can be prevented.

  Application Example 7 In the detection device, the first terminal of the first transistor and the first terminal of the second transistor are arranged along the extending direction of the scanning line in plan view, and in plan view. A detection device in which a second terminal of the first transistor and a second terminal of the second transistor are arranged along an extending direction of the scanning line.

  According to such a configuration, the wiring extending in the direction along the scanning line can be arranged linearly. For this reason, signal delay due to complicated wiring can be prevented.

  Application Example 8 In the detection device, the first transistor and the second transistor have a channel length direction perpendicular to the scanning line extending direction in a plan view.

  According to such a configuration, the wiring extending in the direction perpendicular to the scanning line can be overlapped with the first transistor and the second transistor, and these components can be arranged at high density.

  Application Example 9 In the detection device, the first terminal and the second terminal of the first transistor are arranged along a direction perpendicular to the extending direction of the scanning line in plan view, and the plan view A detection device in which a first terminal and a second terminal of the second transistor are arranged along a direction perpendicular to an extending direction of a scanning line.

  According to such a configuration, when the wiring extending in the direction along the scanning line is arranged, the wiring can be arranged linearly while minimizing a region overlapping the first transistor and the second transistor. For this reason, signal delay due to complicated wiring can be prevented.

  Application Example 10 In the detection device, the channel region of the first transistor and the channel region of the second transistor are arranged along a direction forming a certain angle with respect to the extending direction of the scanning line in plan view. Is a detection device.

  According to such a configuration, when the wiring extending in the direction parallel to the scanning line is connected to the channel region of the first transistor or the second transistor, it is not necessary to bend the wiring in a complicated manner, and the wiring is linear. Can be arranged. Thereby, signal delay due to complicated wiring can be prevented.

  Application Example 11 In the detection device, the gate electrode of the first transistor is arranged along the extending direction of the scanning line in plan view.

  According to such a configuration, the gate electrode of the first transistor can be arranged linearly. In addition, wiring other than the gate electrode can be easily arranged in a straight line in the direction along the scanning line. Thereby, signal delay due to complicated wiring can be prevented.

  Application Example 12 In the detection apparatus, the detection element is a photoelectric conversion element that converts light energy into electric energy.

  According to such a configuration, it is possible to detect external light as an external factor.

  Application Example 13 In the detection device, the detection element is a second capacitance element whose capacitance changes due to deformation.

  According to such a configuration, an external force applied to the detection element as an external factor can be detected.

  Application Example 14 Provided corresponding to the intersection of a substrate, a plurality of scanning lines, a plurality of detection lines, a plurality of power supply lines, and the scanning lines and the detection lines disposed on the substrate. A plurality of unit circuits, wherein the unit circuit has a first terminal connected to the detection line and a second terminal connected to the power supply line, and detects the detection signal corresponding to the potential of the gate electrode. A first transistor supplied to the line; a detection element connected to the gate electrode of the first transistor and changing the gate potential of the first transistor according to an external factor; and a first terminal serving as the gate of the first transistor. A second transistor having a second terminal connected to the power source line and a gate electrode connected to the scanning line; and a first capacitor element that holds a gate potential of the first transistor. Have Ri, the first transistor, the direction of the channel length, and are detection device along the direction of the channel length of the second transistor.

  According to such a configuration, since the first transistor outputs a current having a magnitude corresponding to an external factor to the detection line, the current for the unit circuit selected by the scanning line is sequentially detected, so that Can be detected. Here, since the channel length direction of the first transistor is along the channel length direction of the second transistor, the channel region of the first transistor and the channel region of the second transistor are arranged together in the smallest region. can do. As a result, the first transistor and the second transistor can be arranged with high density. In addition, since each unit circuit can have a configuration having a single power supply line, the circuit configuration of the detection device can be simplified as compared with a configuration having a plurality of power supply lines. In addition, since it is not necessary to form a plurality of power supply lines in different layers, the layer structure of the unit circuit can be simplified. Furthermore, the arrangement area of the power supply lines can be reduced, and the unit circuits can be configured with higher density.

  Application Example 15 Electronic equipment including the detection device.

  According to such a configuration, it is possible to realize an electronic device including an input interface with high detection sensitivity.

  Hereinafter, embodiments of a detection device and an electronic device will be described with reference to the drawings. In the drawings shown below, the dimensions and ratios of the components are appropriately different from the actual ones in order to make the components large enough to be recognized on the drawings.

<First Embodiment>
(A. Circuit configuration and operation)
FIG. 1 shows the configuration of the detection apparatus according to the first embodiment. As shown in the figure, the detection apparatus 1 includes a pixel region A, a Y driver 100, a first X driver 200A, a second X driver 200B, and a control circuit 300. Among these, in the pixel region A, m scanning lines 10 extending in the X direction, m first power supply lines 11 extending in the X direction in pairs with each scanning line 10, and in the X direction N second power supply lines 12 extending in the orthogonal Y direction and n detection lines 14 extending in the Y direction in pairs with each second power supply line 12 are formed. A pixel circuit 40 (unit circuit) is disposed at a position corresponding to each intersection of the scanning line 10 and the second power supply line 12. Therefore, these pixel circuits 40 are arranged in a matrix of m rows × n columns.

  The Y driver 100 selects the pixel circuits 40 arranged in the pixel region A in units of rows for each horizontal scanning period, and outputs the scanning signals Y1 to Ym to each scanning line 10. The first X driver 200A samples and holds the detection signals X1 to Xn supplied from the n detection lines 14, and generates an integrated detection signal VID based on the result of the sample and hold. The second X driver 200 </ b> B supplies the power supply voltage RSL to the second power supply line 12. The power supply voltage RSL is one of the first power supply potential VDD and the second power supply potential VSS. Further, the first X driver 200A precharges each detection line 14 to the second power supply potential VSS at a predetermined timing. As will be described later, when the potential of the first power supply line 11 is the first power supply potential VDD, detection signals X1 to Xn having a magnitude corresponding to the amount of incident light are output from each pixel circuit 40. Note that signals output from the m pixel circuits 40 arranged in the column direction are time-division multiplexed on each of the detection signals X1 to Xn. The control circuit 300 supplies various control signals such as a clock signal to the Y driver 100, the first X driver 200A, and the second X driver 200B.

  FIG. 2 shows the configuration of the pixel circuit 40. This pixel circuit 40 is arranged in the i (i is an integer of 1 ≦ i ≦ m) row j (j is an integer of 1 ≦ j ≦ n) column, but the other pixel circuits 40 are similarly configured. . The pixel circuit 40 includes a photodiode 47 as a detection element. The photodiode 47 outputs a current having a magnitude corresponding to the amount of incident light, and is a photoelectric conversion element that converts light energy into electrical energy. The anode of the photodiode 47 is connected to a fixed potential, and the cathode thereof is connected to the gate of the amplification transistor 45 as the first transistor. A first capacitive element 43 that holds the gate potential of the amplification transistor 45 is provided between the gate of the amplification transistor 45 and the first power supply line 11. The charge output from the photodiode 47 is accumulated in the first capacitor element 43. A reset transistor 41 as a second transistor is provided between the gate of the amplification transistor 45 and the second power supply line 12. The reset transistor 41 functions as a switching element, and is turned on when the scanning signal Yi becomes a selection potential and turned off when the scanning signal Yi becomes a non-selection potential. When the reset transistor 41 is on, the potential of the second power supply line 12 is supplied to the gate of the amplification transistor 45. Further, the drain of the amplification transistor 45 is electrically connected to the first power supply line 11, while its source is electrically connected to the detection line 14. Note that the relationship between the drain and the source in the amplification transistor 45 is defined as the drain having the higher potential and the source having the lower potential, so the drain and the source may be reversed depending on the bias.

  FIG. 3 shows a block diagram of the first X driver 200A. The first X driver 200A includes processing units Ua1 to Uan respectively corresponding to the n detection lines 14. Here, the processing unit Ua1 will be described, but the other processing units are configured similarly. The transfer gate 20, the capacitive element 21, and the capacitive element 22 function as a sample and hold circuit. The transfer gate 20 is turned on when the sampling signal SHG is at a high level, and is turned off when the sampling signal SHG is at a low level. As a result, the detection signal X1 is captured and held. The inverter 23 functions as an amplifier circuit. The transfer gate 24 is used to bias the input of the inverter 23 to an intermediate potential. That is, when the control signal AMG goes high, the input and output of the inverter 23 are short-circuited, and the input potential is biased to an intermediate potential. The output terminal of the inverter 23 is connected to the wiring L through the switching transistor 25. The output signal of the shift register 26 is supplied to the gate of the switching transistor 25. The shift register 26 sequentially transfers the transfer start pulse DX according to the X clock signal XCK to generate an output signal. With this output signal, each of the processing units Ua1 to Uan exclusively supplies a detection signal to the wiring L, and the detection signal is synthesized by the wiring L and output as an integrated detection signal VID via the buffer B. The sampling signal SHG, the control signal AMG, the transfer start pulse DX, and the X clock signal XCK are supplied from the control circuit 300.

  FIG. 4 is a block diagram showing a configuration of the second X driver 200B. The second X driver 200B includes processing units Ub1 to Ubn corresponding to n columns. Here, the processing unit Ub1 will be described, but the other processing units are similarly configured. The transistors 27 and 28 are turned on / off by a control signal SG1 and a control signal SG2. Here, the control signal SG2 is obtained by inverting the control signal SG1. Accordingly, the transistor 27 and the transistor 28 are exclusively turned on to supply the first power supply potential VDD or the second power supply potential VSS to the second power supply line 12. Further, the transistor 29 is turned on when the control signal RG becomes high level, and supplies the second power supply potential VSS to the detection line 14. Thereby, the detection line 14 can be precharged.

  Next, the operation of the detection device 1 will be described. FIG. 5 is a timing chart showing signal waveforms of each part of the detection apparatus 1. The scanning signals Y1 to Ym sequentially become high level during a part of each horizontal scanning period. As shown in this figure, the i-th horizontal scanning period includes a reset period Trest, an initialization period Tini, a detection period Tdet, and a readout period Tread.

  First, in the reset period Trest, the gate potential of the amplification transistor 45 is set to the second power supply potential VSS. As shown in FIG. 5, during this period, the scanning signal Yi is at a high level, so that the reset transistor 41 is turned on. At this time, the control signal SG1 becomes low level, while the control signal SG2 becomes high level, so that the transistor 28 is turned on, and the second power supply potential VSS is supplied to the amplification transistor 45 via the second power supply line 12. Supplied to the gate. Further, since the control signal RG becomes high level, the transistor 29 is turned on, and the second power supply potential VSS is precharged to the detection line 14. When m = n = 3, the gate potential of the amplification transistor 45 is set to the second power supply potential VSS in all the pixel circuits 40 as shown in FIG.

  Next, in the initialization period Tini, the control signal SG1 becomes high level, the transistor 27 is turned on, and the first power supply potential VDD is supplied to the gate of the amplification transistor 45 through the second power supply line 12 and the reset transistor 41. . As shown in FIG. 7, in the initialization period Tini, the first power supply potential VDD is supplied only to the rows where the scanning signals Y1 to Ym are at a high level. In the example shown in FIG. In the pixel circuits 40 in other rows, the second power supply potential VSS written in the reset period Trest is held by the first capacitor element 43. In the initialization period Tini, since the sampling signal SHG and the control signal AMG are at a high level, the transfer gates 20 and 24 are turned on. At this time, since the second power supply potential VSS is supplied to the detection line 14, the potential of one terminal of the capacitor 21 becomes the second power supply potential VSS, and the potential of the other terminal is set to an intermediate potential. Thereby, the potential of the capacitive element 21 is initialized.

  Next, in the detection period Tdet, as shown in FIG. 5, the potential of the power supply signal GPi becomes the first power supply potential VDD. Further, since the control signal RG is at a low level, the transistor 29 is turned off, and the second power supply potential VSS is not supplied to the detection line 14. As shown in FIG. 8, in the detection period Tdet, detection signals X1 to X3 are output from the pixel circuits 40 in the selected row (in this example, the second row).

  FIG. 9 shows the bias of the selected pixel circuit 40 in the second row and second column. As shown in this figure, the gate potential Vg of the amplification transistor 45 becomes Vg = VDD−Vpd when the voltage of the photodiode 47 is Vpd. The voltage Vpd changes according to the amount of light incident on the photodiode 47. That is, the photodiode 47 changes the gate potential of the amplification transistor 45 according to the amount of incident light as an external factor. Then, a current determined according to the gate potential is output to the detection line 14 as the detection signal X2. In other words, the amplification transistor 45 supplies the detection signal X <b> 2 corresponding to the potential of the gate electrode to the detection line 14.

  When the potential of the detection line 14 is Vsense, the potential Vsense changes as shown in FIG. Here, the characteristic Q1 indicates a case where the amount of incident light is small and dark, and the characteristic Q2 indicates a case where the amount of incident light is large and bright. That is, in the dark, since the voltage Vpd of the photodiode 47 is small, the gate potential Vg is high. For this reason, a large current flows out from the source of the amplification transistor 45, and the potential Vsense of the detection line 14 rises rapidly. On the other hand, when it is bright, the voltage Vpd of the photodiode 47 is large, so the gate potential Vg is low. For this reason, since the current flowing out from the source of the amplification transistor 45 is small, the potential Vsense of the detection line 14 rises gently. When Vsense = Vg−Vth, the amplification transistor 45 is turned off. As described above, since the amount of electric charge flowing out to the detection line 14 differs according to the amount of incident light, this is detected as a voltage in the processing unit Ua2.

(B. Detailed configuration of pixel circuit)
Next, a detailed configuration of the pixel circuit 40 will be described. FIG. 11 is a plan view of a region including a plurality of pixel circuits 40 in the detection apparatus 1, and FIG. 12 is an enlarged plan view of the pixel circuits 40. The pixel circuits 40 are arranged in a matrix along a plurality of rows and columns. Hereinafter, the row or column of the pixel circuit 40 is also simply referred to as “row” or “column”. 19 and 20 are cross-sectional views of the detection apparatus 1 taken along lines BB and CC in FIG. 11, respectively. As shown in FIGS. 19 and 20, the pixel circuit 40 includes a first layer including semiconductor layers 41a and 45a, a second layer including gate electrodes 41g and 45g, a second power supply line 12, a detection line 14, and the like. A third layer including the scan line 10 and a first power supply line 11b, and a fifth layer including the first power supply line 11a and the like. FIG. 13 is a plan view showing the components of the first layer and the third layer extracted from the components shown in FIG. FIG. 14 is a plan view showing the components of the first layer, the second layer, and the fourth layer extracted from the components shown in FIG. FIG. 15 is a plan view showing the components of the first layer and the fifth layer extracted from the components shown in FIG.

  First, the configuration of the pixel circuit 40 will be described with reference to the cross-sectional view of FIG. A base insulating film 51 made of silicon oxide or the like is formed on the substrate 5. As the substrate 5, a quartz substrate, a glass substrate, or the like can be used. A first layer including semiconductor layers 41 a and 45 a is formed on the base insulating film 51. A gate insulating film 52 made of silicon oxide or the like is formed on the first layer, and a second layer including gate electrodes 41g and 45g is formed thereon.

  The semiconductor layer 41a is made of, for example, a polysilicon film as a silicon film, and includes a channel region 41c in which a channel is formed by an electric field from the gate electrode 41g, a drain region 41d as a first terminal, and a source region 41s as a second terminal. I have. Similarly, the semiconductor layer 45a is made of a polysilicon film, and includes a channel region 45c in which a channel is formed by an electric field from the gate electrode 45g, a drain region 45d as a first terminal, and a source region 45s as a second terminal. The semiconductor layers 41a and 45a may have an LDD (Lightly Doped Drain) structure. For example, a low concentration drain region is provided between the channel region 41c (45c) and the drain region 41d (45d), and a low concentration source region is provided between the channel region 41c (45c) and the source region 41s (45s). It is good also as a structure.

  The gate electrodes 41g and 45g are, for example, a simple metal or alloy containing at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). , Metal silicide, polysilicide, a laminate of these, or conductive polysilicon. The gate electrodes 41g and 45g are formed at least in regions overlapping the channel regions 41c and 45c, respectively, in plan view. Here, “in plan view” means “seen from the normal direction of the substrate 5” (the same applies hereinafter).

  As shown in FIG. 14, the semiconductor layer 41a and the semiconductor layer 45a are arranged so as to be parallel to each other. That is, the semiconductor layer 41a is provided along the extending direction of the semiconductor layer 45a. For this reason, the channel length direction of the channel region 41c is a direction along the channel length direction of the channel region 45c. Alternatively, the channel length direction of the channel region 41c may be parallel to the channel length direction of the channel region 45c. Here, the channel region 41c (45c) is a region overlapping the gate electrode 41g (45g) in the semiconductor layer 41a (45a), and the channel length is the drain region 41d (45d) in the channel region 41c (45c). ) To the source region 41s (45s). According to such a configuration, since the channel region 41c and the channel region 45c can be arranged together in the smallest region, the amplification transistors 45 and the reset transistors 41 can be arranged at high density. Further, when the semiconductor layers 41a and 45a are low-temperature polysilicon formed through laser annealing, the transistor characteristics can be controlled by the size of the channel regions 41c and 45c. Further, particularly when the semiconductor layers 41a and 45a are low-temperature polysilicon, the current characteristics of the amplification transistor 45 and the reset transistor 41 can be made uniform, for example, the on-current and the off-current can be made the same. In the detection apparatus 1, when a certain pixel circuit 40 is not operated, both the amplification transistor 45 and the reset transistor 41 must be surely turned off, but this operation is easy to perform according to the above configuration.

  More specifically, the amplification transistor 45 needs to make the sensitivity of the output current sensitive to the gate potential in the vicinity of the threshold region when the pixel circuit 40 is operated. Further, when not operating, the S / N ratio of the detection signal Xn for the pixel circuit 40 to be operated is taken, and therefore it is necessary to be surely turned off. In addition, the reset transistor 41 can reliably hold the gate potential of the amplification transistor 45 at the time of light detection by reliably turning off in response to the potential of the scanning line 10 becoming low level. The S / N ratio of the detection signal Xn can be improved. As described above, the channel length of the channel region 41c is arranged so as to be along the channel length of the channel region 45c, so that these operations are facilitated.

  As shown in FIG. 11, the channel lengths of the channel regions 41c and 45c are arranged such that the extending direction in plan view intersects the extending direction of the scanning line 10 and the extending direction of the detection line 14. ing. Alternatively, the channel length extending direction may be arranged along the diagonal direction of the pixel circuit 40. Alternatively, the extending direction of the channel length may be arranged to form an angle of 45 degrees with respect to the extending direction of the scanning line 10 and the extending direction of the detection line 14. Similarly, the first power supply lines 11a and 11b and the second power supply line 12 may be crossed or may have an angle of 45 degrees. In the present embodiment, the scanning lines 10 and the first power supply lines 11a and 11b are arranged along the horizontal direction (row direction) in the drawing, and the second power supply lines 12 and the detection lines 14 are arranged in the vertical direction (see FIG. (Column direction). According to such a configuration, the arrangement pitch of the channel regions 41c and 45c and the arrangement pitch of the semiconductor layers 41a and 45a can be reduced in the vertical direction and the horizontal direction in FIG. Can be reduced. Thereby, the resolution of the detection apparatus 1 can be improved.

  Here, when the semiconductor layers 41a and 45a are low-temperature polysilicon formed through laser annealing, the channel regions 41c and 45c make an angle of 45 degrees with respect to the longitudinal direction of the light flux of the annealing laser. It is desirable to be arranged in. In this way, annealing can be completed with a small number of laser irradiations on the semiconductor layers 41a and 45a. For this reason, the characteristic dispersion | variation by laser annealing can be reduced.

  Further, as shown in FIG. 11, the amplification transistor 45 includes a drain region 45d (first terminal) and a source region 45s (second terminal), the scanning line 10, the first power supply lines 11a and 11b, The two power supply lines 12 and the detection lines 14 are arranged along the direction intersecting the extending direction. Alternatively, the drain region 45d and the source region 45s may be disposed along the diagonal direction of the pixel circuit 40. Alternatively, the drain region 45d and the source region 45s may be arranged along a direction that forms an angle of 45 degrees with respect to the scanning line 10. Similarly, in the reset transistor 41, the drain region 41d (first terminal) and the source region 41s (second terminal) have the scanning line 10, the first power supply lines 11a and 11b, the second power supply line 12, and the detection in plan view. It arrange | positions along the direction which cross | intersects with respect to the extending direction of the line 14. FIG. Alternatively, the drain region 41 d and the source region 41 s may be arranged along the diagonal direction of the pixel circuit 40. Alternatively, the drain region 41 d and the source region 41 s may be arranged along a direction that forms an angle of 45 degrees with respect to the scanning line 10. According to such a configuration, the first terminal and the second terminal of each transistor can be arranged in a state of being separated from each other. In addition, when the wirings extending in the vertical direction and the horizontal direction in FIG. 11 are arranged, they can be arranged in a straight line while minimizing a region overlapping the amplification transistor 45 and the reset transistor 41. For this reason, signal delay due to complicated wiring can be prevented.

  Further, as shown in FIG. 11, the drain region 45d of the amplification transistor 45 and the drain region 41d of the reset transistor 41 are arranged along the extending direction of the scanning line 10 and the first power supply lines 11a and 11b in plan view. ing. The source region 45s of the amplification transistor 45 and the source region 41s of the reset transistor 41 are arranged along the extending direction of the scanning line 10 and the first power supply lines 11a and 11b in plan view. According to such a configuration, the wiring extending in the horizontal direction (row direction) in FIG. 11, that is, the scanning line 10 and the first power supply lines 11a and 11b can be arranged linearly. For this reason, signal delay due to complicated wiring can be prevented.

  The gate electrode 45g extends to a position overlapping the drain region 41d of the reset transistor 41 in plan view, and is electrically connected to the drain region 41d through a contact hole 72 (FIG. 19). As a result, the amplification transistor 45 can be controlled by the output of the reset transistor 41. Since the semiconductor layers 41a and 45a are arranged as described above, the drain region 41d is located on a line segment extending from the channel region 45c in the minor axis direction of the semiconductor layer 45a, that is, a vertical bisector of the semiconductor layer 45a. It exists on the line. Therefore, the gate electrode 45g can be easily formed up to the drain region 41d by simply extending in the minor axis direction of the semiconductor layer 45a starting from the channel region 45c. Further, a wide contact portion in the drain region 41d can be secured.

  Referring back to FIG. 19, a third layer including the second power supply line 12, the detection line 14, and the like is formed on the second layer with an interlayer insulating film 53 made of silicon oxide or the like interposed therebetween. In addition, relay electrodes 61, 62 and 65 (FIGS. 13 and 20) are also formed on the third layer. The second power supply line 12 is electrically connected to the source region 41 s of the reset transistor 41 through a contact hole 71 provided through the interlayer insulating film 53 and the gate insulating film 52. The detection line 14 is electrically connected to the drain region 45 d of the amplification transistor 45 through a contact hole 73 provided through the interlayer insulating film 53 and the gate insulating film 52. The relay electrode 61 is electrically connected to the drain region 41 d of the reset transistor 41 through a contact hole 72 provided through the interlayer insulating film 53 and the gate insulating film 52. The relay electrodes 62 and 65 are electrically connected to the source region 45 s of the amplification transistor 45 through a contact hole 74 provided through the interlayer insulating film 53 and the gate insulating film 52.

  The planar arrangement of the third layer components is shown in FIG. The second power supply line 12 and the detection line 14 extend along the column direction of the pixel circuit 40 (FIG. 11), and the second power supply line 12 is arranged on the left end side of the pixel circuit 40 in FIG. 14 is arranged on the right end side of the pixel circuit 40 in FIG. Therefore, in the pixel circuit 40, the amplification transistor 45 and the reset transistor 41 are disposed between the second power supply line 12 and the detection line 14 in plan view. In other words, the connection between the second power supply line 12 and the reset transistor 41 and the connection between the detection line 14 and the amplification transistor 45 are closer to the outer edge of the pixel circuit 40 than the channel regions 41c and 45c (FIG. 11). Located in the area. According to such a configuration, wiring extending in the vertical direction (column direction) in FIG. 11, that is, the second power supply line 12 and the detection line 14 can be arranged linearly. For this reason, signal delay due to complicated wiring can be prevented.

  The relay electrode 61 is disposed at least in a region overlapping the contact hole 72 in the drain region 41 d (FIG. 11) of the reset transistor 41. The relay electrodes 62 and 65 are arranged at least in a region overlapping the contact hole 74 in the source region 45 s of the amplification transistor 45. Here, the relay electrode 62 is disposed in the pixel circuit 40 in a certain row, and the relay electrode 65 is disposed in the pixel circuit 40 in the row adjacent to the pixel circuit 40. That is, the relay electrodes 62 and 65 are arranged every other row. More specifically, the relay electrode 62 is formed in the pixel circuit 40 having the first power supply line 11a (FIG. 11), and the relay electrode 65 is formed in the pixel circuit 40 having the first power supply line 11b (FIG. 11). . The relay electrode 65 extends to the arrangement area of the contact hole 78 (FIG. 14) in the arrangement area of the first power supply line 11b.

  Referring back to FIG. 19, a fourth layer including the scanning lines 10 and the like is formed on the third layer with an interlayer insulating film 54 made of silicon oxide or the like interposed therebetween. In the fourth layer, the first power supply line 11b is formed in addition to the scanning line 10 (FIGS. 14 and 20). The scanning line 10 is electrically connected to the gate electrode 41 g of the reset transistor 41 through a contact hole 75 provided through the interlayer insulating films 54 and 53. The first power supply line 11b is electrically connected to the relay electrode 65 (FIG. 20) through a contact hole 78 provided through the interlayer insulating films 54 and 53. Here, since the relay electrode 65 is connected to the source region 45s of the amplification transistor 45, the first power supply line 11b is electrically connected to the source region 45s. As will be described later, in this embodiment, two types of first power supply lines 11a and 11b are formed in different layers as the first power supply line. The first power line 11b in the third layer is one of them.

  The planar arrangement of the components of the fourth layer is shown in FIG. The scanning line 10 is disposed so as to overlap at least a part of the gate electrode 41g of the reset transistor 41 in plan view. In this embodiment, it is further arranged in a straight line so as to cross the channel region 45c of the amplification transistor 45 and the channel region 41c of the reset transistor 41. Further, the scanning line 10 is arranged with a certain angle with respect to the channel length direction of the channel regions 41c and 45c. In the present embodiment, the certain angle is 45 degrees. As described above, the scanning line 10 and the gate electrode 41g of the reset transistor 41 are electrically connected via the contact hole 75 formed in the normal direction of the substrate 5 on the gate electrode 41g. As described above, the scanning line 10 is disposed so as to pass above the two transistors in a layer different from the second layer and the third layer, and is connected to the gate electrode 41 g in the normal direction of the substrate 5. Therefore, it is not necessary to separately provide a region for wiring of the scanning line 10, and a region for connecting wiring between the scanning line 10 and the reset transistor 41 becomes unnecessary. For this reason, the amplification transistors 45 and the reset transistors 41 can be arranged with high density. In this specification, the connection in the normal direction of the substrate 5 means that, for example, in the case of connection by a contact hole, the contact hole formation direction has a component in the normal direction of the substrate 5. It is not limited to the case where the holes are formed strictly along the normal direction of the substrate 5.

  The first power supply line 11b is arranged in parallel with the scanning line 10, that is, linearly along the row direction. The first power supply line 11b is arranged every other row.

  Referring back to FIG. 19, a fifth layer including the first power supply line 11a and the relay electrodes 63 and 64 (FIG. 20) is formed on the fourth layer with an interlayer insulating film 55 made of silicon oxide or the like interposed therebetween. . The first power supply line 11 a is the other of the two types of first power supply lines 11. The first power supply line 11 a is electrically connected to the relay electrode 62 through a contact hole 77 provided through the interlayer insulating films 55 and 54. Here, since the relay electrode 62 is connected to the source region 45s of the amplification transistor 45, the first power supply line 11a is electrically connected to the source region 45s. The relay electrode 63 is electrically connected to the relay electrode 61 through a contact hole 76 provided through the interlayer insulating films 55 and 54. The relay electrode 64 is electrically connected to the relay electrode 65 through a contact hole 77 provided through the interlayer insulating films 55 and 54.

  The planar arrangement of the components of the fifth layer is shown in FIG. The first power supply line 11 a is arranged along the row direction of the pixel circuit 40, and a part of the first power supply line 11 a is arranged to protrude to the arrangement region of the contact holes 74 and 77. The relay electrode 63 is disposed at least in a region overlapping the contact holes 72 and 76 in the drain region 41 d of the reset transistor 41. The relay electrode 64 is disposed at least in a region overlapping the contact holes 74 and 77 in the source region 45 s of the amplification transistor 45. The relay electrode 64 is disposed only in the pixel circuit 40 having the first power supply line 11b.

  Here, the arrangement of the first power supply lines 11a and 11b will be described with reference to FIG. FIG. 17 is a plan view showing the first power supply lines 11a and 11b, the semiconductor layers 41a and 45a, etc. extracted from FIG. The first power supply lines 11 a and 11 b are both linearly extended in a direction parallel to the scanning line 10. More specifically, the first power supply line 11 a is formed on the upper end side of the pixel circuit 40 in FIG. 17, and the first power supply line 11 b is formed on the lower end side of the pixel circuit 40. The rows of the pixel circuits 40 where the first power supply lines 11a are formed and the rows of the pixel circuits 40 where the first power supply lines 11b are formed are alternately arranged. Therefore, the first power supply line 11a and the first power supply line 11b are arranged at positions close to each other in plan view.

  As described above, the first power supply line 11a is formed in the fifth layer (FIG. 19), and the first power supply line 11b is formed in a fourth layer different from this (FIG. 20). For this reason, compared with the case where the first power supply lines 11a and 11b are formed in the same layer, the first power supply lines 11a and 11b can be arranged at positions closer to each other in plan view. For this reason, the arrangement pitch of the pixel circuits 40 in the vertical direction (column direction) in FIG. 17 can be reduced.

  Further, as shown in FIG. 18, the first power supply lines 11a and 11b may be arranged so as to partially overlap in a plan view. In this way, the arrangement pitch of the pixel circuits 40 in the column direction can be further reduced.

  Returning to FIG. 19, a planarizing film 56 made of acrylic resin or the like is formed on the fifth layer. On the planarizing film 56, the first capacitor element 43 and the photodiode 47 as the detection element are arranged in this order. Are stacked. The first capacitor element 43 and the photodiode 47 are formed for each pixel circuit 40.

  The first capacitive element 43 has a configuration in which a second electrode 43b made of Al—Nd, an insulating film 43d made of silicon nitride, etc., and a first electrode 43a made of Al—Nd, etc. are sequentially stacked from the lower layer side. ing. The second electrode 43b is electrically connected to the first power supply line 11a or the relay electrode 64 (FIG. 20) via a contact hole 79b formed in the planarizing film 56. Therefore, the second electrode 43 b is electrically connected to the source region 45 s of the amplification transistor 45 via the relay electrode 62 or the relay electrode 65. The contact hole 79b is formed in a region overlapping the second electrode 43b in plan view. The first electrode 43 a is electrically connected to the relay electrode 63 through a contact hole 79 a formed in the planarizing film 56. Therefore, the first electrode 43 a is electrically connected to the drain region 41 d of the reset transistor 41 and the gate electrode 45 g of the amplification transistor 45 through the relay electrode 61. The contact hole 79a is formed in a region overlapping the first electrode 43a in plan view. As described above, according to the configuration in which the electrical connection is performed by the contact holes 79a and 79b provided in the normal direction of the substrate 5, the connection can be reliably performed, and the line / space of the wiring provided in the same layer can be achieved. Can be widened. The first electrode 43a partially overlaps the semiconductor layer 41a in plan view, and the second electrode 43b partially overlaps the semiconductor layer 45a in plan view. Such a feature also provides an effect that the line / space of the wiring provided in the same layer can be widened.

  Further, the connection between the first electrode 43 a and the drain region 41 d of the reset transistor 41 and the connection between the gate electrode 45 g of the amplification transistor 45 and the drain region 41 d of the reset transistor 41 are made through the same contact hole 72. (Common contact structure). According to such a configuration, it is possible to reduce the area used for the contact in plan view, and it is possible to arrange the pixel circuits 40 with high density.

  The planar arrangement of the first electrode 43a and the second electrode 43b is shown in FIG. The second electrode 43b is formed in a region of the pixel circuit 40 excluding the drain region 41d of the reset transistor 41, and the first electrode 43a is formed over substantially the entire surface of the pixel circuit 40. Therefore, the channel region 45c of the amplification transistor 45 and the channel region 41c of the reset transistor 41 are covered with at least one of the first electrode 43a and the second electrode 43b in plan view. According to such a configuration, the channel regions 45c and 41c (FIG. 11) can be shielded by one or two shielding layers (first electrode 43a and second electrode 43b), so that the amplification transistor 45 and the reset transistor 41 off-current can be reduced. Thereby, the S / N ratio of the detection signal Xn can be improved.

  Returning to FIG. 19, the first electrode 43 a of the first capacitor 43 also serves as the cathode of the photodiode 47. In the photodiode 47, a first electrode 43a as a cathode, an n layer 47n made of amorphous silicon, an i layer 47i, a p layer 47p, and a transparent anode 48 made of ITO (Indium Tin Oxide) are laminated in this order from the lower layer side. It has a configuration. As shown in FIG. 16, the photodiode 47 is formed in a rectangular area near the center of the pixel circuit 40 in plan view. An insulating layer 57 made of silicon nitride or the like is formed around the rectangular region of the photodiode 47. As described above, according to the configuration in which the first electrode 43 a of the first capacitor 43 is also used as the cathode of the photodiode 47 and the photodiode 47 is formed so as to overlap the first capacitor 43, the first capacitor 43, the photo The area occupied by the diodes 47 can be increased.

(Modification 1-1)
Although the detection apparatus 1 of the present embodiment uses the photodiode 47 as the detection element, various other detection elements can be used. FIG. 21 is a cross-sectional view of the detection apparatus 1 using the second capacitive element 44 as a detection element, and the position of the cross section corresponds to the position of the line BB in FIG. The second capacitive element 44 is formed so as to overlap the first capacitive element 43, and has a configuration in which a first electrode 43a, an insulating layer 44d, and a second electrode 44b are stacked from the lower layer. Here, the first electrode 43 a is a common electrode with the first capacitive element 43. A substrate 6 made of glass or transparent resin is disposed on the second capacitor element 44. When the substrate 6 is deformed due to an external factor, the thickness of the insulating layer 44d changes, and the capacitance of the second capacitor element 44 changes accordingly. As a result, the amount of charge accumulated in the second capacitor element 44 varies, and the gate potential of the amplification transistor 45 changes. As described above, the second capacitive element 44 changes the gate potential of the amplification transistor 45 due to an external factor. Therefore, the external factor can also be detected by the detection device 1 using the second capacitive element 44 as the detection element.

(Modification 1-2)
In the detection device 1 of the present embodiment, each pixel circuit 40 has two power supply lines (first power supply line 11 and second power supply line 12). These power supply lines are electrically connected to be shared. In other words, each pixel circuit 40 may have a single power supply line. FIG. 22 is a circuit diagram of the detection apparatus 1 having the pixel circuit 40 having such a configuration. In each pixel circuit 40, one terminal of the first capacitive element 43 is electrically connected to the second power supply line 12 (also simply referred to as the power supply line 12 in this modification). Further, one ends (source or drain) of the reset transistor 41 and the amplification transistor 45 are both electrically connected to the power supply line 12. In this way, the power supply voltage RSL can be supplied via the power supply line 12 to the terminal of the first capacitor element 43 and one end of the reset transistor 41 and the amplification transistor 45. Here, the power supply voltage RSL is one of the first power supply potential VDD and the second power supply potential VSS.

  Even with such a configuration, a detection operation similar to that in the above-described embodiment can be performed. That is, first, in the reset period Trest, the reset transistor 41 is turned on, and the second power supply potential VSS is supplied to the gate of the amplification transistor 45 through the power supply line 12. Further, the second power supply potential VSS is precharged to the detection line 14. Next, in the initialization period Tini, the first power supply potential VDD is supplied to the gate of the amplification transistor 45 via the power supply line 12 and the reset transistor 41 in the row where the scanning signals Y1 to Ym are at a high level. At this time, the first power supply potential VDD is also supplied to the other end of the first capacitive element 43 via the power supply line 12. Next, in the detection period Tdet, detection signals X1 to X3 are output from the pixel circuits 40 in the selected row. At this time, the amplification transistor 45 outputs detection signals X1 to X3 having a magnitude corresponding to the gate potential. Here, since the gate potential of the amplification transistor 45 changes according to the amount of light incident on the photodiode 47, the detection signals X1 to X3 have a magnitude corresponding to the amount of incident light.

  FIG. 23 is a plan view of a region including a plurality of pixel circuits 40 of the detection apparatus 1 according to this modification. FIG. 24 is a plan view showing the arrangement of the first layer (the layer where the semiconductor layers 41a and 45a are formed) and the third layer (the layer where the power supply line 12 is formed) among the components shown in FIG. . As shown in these drawings, the power supply line 12 is arranged along the vertical direction (column direction) in the drawing, and a branch portion for connecting the source region 41 s and the source region 45 s in each pixel circuit 40. 12a. The branch portion 12 a electrically connects the source region 41 s and the source region 45 s through the contact holes 71 and 74. The source regions 41 s and 45 s are electrically connected to the second electrode 43 b of the first capacitor element 43 through the contact hole 77.

  The detection device 1 of this modification does not have the first power supply lines 11a and 11b. Therefore, the fifth layer (FIG. 15) including the first power supply line 11a and the relay electrodes 63 and 64 included in the first embodiment can be omitted. In this case, a relay electrode is newly provided on the fourth layer including the scanning line 10 at a position corresponding to the relay electrodes 63 and 64, and the first electrode 43a and the second electrode 43b of the first capacitor 43 are provided on the relay electrode. May be electrically connected to each other.

  According to the configuration of this modification, each pixel circuit (unit circuit) 40 has a single power supply line 12, and therefore the circuit configuration of the detection apparatus 1 is simplified compared to a configuration having a plurality of power supply lines. Can be In addition, since it is not necessary to form a plurality of power supply lines 12 in different layers, the layer structure of the pixel circuit 40 can be simplified. Furthermore, the arrangement area of the power supply lines 12 can be reduced, and the pixel circuits 40 can be configured with higher density.

(Modification 1-3)
The detection device 1 according to the present embodiment or the modification includes the features listed below, but does not have to include all of these features, and includes a detection device including only some of these features. It may be. According to the detection device having any one or more of the following features, an effect corresponding to the feature can be obtained.

  A configuration in which the channel length direction of the reset transistor 41 is along the channel length direction of the amplification transistor 45. According to such a configuration, the amplification transistors 45 and the reset transistors 41 can be arranged with high density. Further, the current characteristics of the amplification transistor 45 and the reset transistor 41 can be made uniform, and for example, the on current and the off current can be made the same.

  A configuration in which the channel length direction of the reset transistor 41 and the channel length direction of the amplification transistor 45 intersect with the extending direction of the scanning line 10 and the extending direction of the detection line 14 in plan view. Alternatively, the channel length direction of the reset transistor 41 and the channel length direction of the amplification transistor 45 form an angle of 45 degrees with respect to the extending direction of the scanning line 10 and the extending direction of the detection line 14 in plan view. Constitution. According to such a configuration, the arrangement pitch in the column direction and the row direction of the semiconductor layers 41a and 45a can be reduced, so that the size of the pixel circuit 40 in the vertical direction can be reduced. Thereby, the resolution of the detection apparatus 1 can be improved.

  A drain region 45d (first terminal) and a source region 45s (second terminal) of the amplification transistor 45 are arranged along a direction intersecting the extending direction of the scanning line 10 and the extending direction of the detection line 14 in plan view. And a drain region 41d (first terminal) and a source region 41s (second terminal) of the reset transistor 41 along a direction intersecting the extending direction of the scanning line 10 and the extending direction of the detection line 14 in plan view. The configuration where is placed. Alternatively, the drain region 45d and the source region 45s of the amplifying transistor 45 are arranged along a direction that forms an angle of 45 degrees with the extending direction of the scanning line 10 and the extending direction of the detection line 14 in plan view. Thus, the drain region 41d and the source region 41s of the reset transistor 41 are arranged along a direction that forms an angle of 45 degrees with the extending direction of the scanning line 10 and the extending direction of the detection line 14. According to such a configuration, when wirings extending in the column direction and the row direction are arranged, they can be arranged linearly while minimizing a region overlapping the amplification transistor 45 and the reset transistor 41. For this reason, signal delay due to complicated wiring can be prevented.

  A drain region 45d of the amplifying transistor 45 and a drain region 41d of the reset transistor 41 are arranged along the extending direction of the scanning line 10 in plan view, and the amplifying transistor 45 is extended along the extending direction of the scanning line 10 in plan view. A configuration in which the source region 45s and the source region 41s of the reset transistor 41 are arranged. According to such a configuration, the wiring extending in the row direction can be arranged linearly. For this reason, signal delay due to complicated wiring can be prevented.

  A configuration in which the connection between the first electrode 43a and the drain region 41d of the reset transistor 41 and the connection between the gate electrode 45g of the amplification transistor 45 and the drain region 41d of the reset transistor 41 are made through the same contact hole 72 (common contact). Construction). According to such a configuration, it is possible to reduce the area used for the contact in plan view, and it is possible to arrange the pixel circuits 40 with high density.

  In each pixel circuit 40, the amplification transistor 45 and the reset transistor 41 are arranged between the second power supply line 12 and the detection line 14 in plan view. Alternatively, the connection portion between the second power supply line 12 and the reset transistor 41 and the connection portion between the detection line 14 and the amplification transistor 45 are located in a region closer to the outer edge portion of the pixel circuit 40 than the channel regions 41c and 45c. Constitution. According to such a configuration, the wiring extending in the column direction, that is, the second power supply line 12 and the detection line 14 can be arranged linearly. For this reason, signal delay due to complicated wiring can be prevented.

  A configuration in which the scanning line 10 overlaps at least part of the gate electrode 41g of the reset transistor 41 in plan view. Alternatively, the scanning line 10 is arranged linearly so as to cross the channel region 45 c of the amplification transistor 45 and the channel region 41 c of the reset transistor 41. Alternatively, the scanning line 10 and the gate electrode 41g of the reset transistor 41 are electrically connected via a contact hole 75 formed in the normal direction of the substrate 5 on the gate electrode 41g. According to such a configuration, the scanning line 10 is disposed so as to pass over the two transistors in a layer different from the second layer and the third layer, and is connected to the gate electrode 41 g in the normal direction of the substrate 5. Therefore, it is not necessary to separately provide a region for wiring of the scanning line 10, and a region for connecting wiring between the scanning line 10 and the reset transistor 41 becomes unnecessary. For this reason, the amplification transistors 45 and the reset transistors 41 can be arranged with high density.

  The first power supply line 11a is formed on the upper end side of the pixel circuit 40, the first power supply line 11b is formed on the lower end side of the pixel circuit 40, and the row of the pixel circuit 40 in which the first power supply line 11a is formed; A configuration in which rows of pixel circuits 40 in which one power supply line 11b is formed are alternately arranged. Alternatively, the first power supply line 11a and the first power supply line 11b are formed in different layers. According to such a configuration, the first power supply lines 11a and 11b can be arranged at positions closer to each other in plan view. For this reason, the arrangement pitch of the pixel circuits 40 in the column direction can be reduced.

  A configuration in which the first power supply lines 11a and 11b are arranged so as to partially overlap in a plan view. According to such a configuration, the arrangement pitch of the pixel circuits 40 in the column direction can be reduced.

  A configuration in which the first electrode 43 a and the second electrode 43 b of the first capacitive element 43 are electrically connected to a relay electrode or the like through contact holes 79 a and 79 b provided in the normal direction of the substrate 5. Alternatively, the first electrode 43a and the semiconductor layer 41a are partially overlapped in plan view, or the second electrode 43b and the semiconductor layer 45a are partially overlapped in plan view. According to such a configuration, the connection can be reliably performed, and the line / space of the wiring provided in the same layer can be widened.

  A configuration in which the channel region 45c of the amplification transistor 45 and the channel region 41c of the reset transistor 41 are covered with at least one of the first electrode 43a and the second electrode 43b of the first capacitor 43 in plan view. According to such a configuration, the channel regions 45c and 41c can be shielded by one or two shielding layers (the first electrode 43a and the second electrode 43b). Can be reduced. Thereby, the S / N ratio of the detection signal Xn can be improved.

  A configuration in which the first electrode 43 a of the first capacitor 43 also serves as the cathode of the photodiode 47. According to such a configuration, the occupied areas of the first capacitor element 43 and the photodiode can be increased.

  A configuration in which the second capacitive element 44 is used in place of the photodiode 47 as the detection element. Even with such a configuration, an external factor can be detected.

  A configuration in which each pixel circuit 40 has a single power supply line 12. According to such a configuration, the circuit configuration of the detection device can be simplified. In addition, it is possible to simplify the layer structure of the unit circuit and increase the density of the unit circuit.

<Second Embodiment>
Next, a second embodiment of the detection device will be described. The detection device of this embodiment is different from the first embodiment in the arrangement of components of the pixel circuit 40, and the other points are the same as those of the first embodiment.

  FIG. 25 is a plan view of a region including a plurality of pixel circuits 40 in the detection apparatus 2 according to the present embodiment, and FIG. 26 is an enlarged plan view of the pixel circuits 40. FIG. 30 is a cross-sectional view of the detection device 2 taken along the line DD in FIG. As shown in FIG. 30, the pixel circuit 40 includes a first layer including semiconductor layers 41a and 45a, a second layer including gate electrodes 41g and 45g, a third layer including detection lines 14, and the like. , A fourth layer including the first power supply line 11 and the like, and a fifth layer including the second power supply line 12 and the like. FIG. 27 is a plan view showing the components of the first layer and the fifth layer extracted from the components shown in FIG. FIG. 28 is a plan view showing the components of the first layer and the second layer extracted from the components shown in FIG. FIG. 29 is a plan view showing the components of the first layer, the third layer, and the fourth layer extracted from the components shown in FIG.

  First, the configuration of the pixel circuit 40 will be described with reference to the cross-sectional view of FIG. A base insulating film 51 made of silicon oxide or the like is formed on the substrate 5. A first layer including semiconductor layers 41 a and 45 a is formed on the base insulating film 51. A gate insulating film 52 made of silicon oxide or the like is formed on the first layer, and a second layer including gate electrodes 41g and 45g is formed thereon.

  The semiconductor layer 41a is made of, for example, a polysilicon film, and includes a channel region 41c in which a channel is formed by an electric field from the gate electrode 41g, a drain region 41d as a first terminal, and a source region 41s as a second terminal. Similarly, the semiconductor layer 45a includes a channel region 45c in which a channel is formed by an electric field from the gate electrode 45g, a drain region 45d as a first terminal, and a source region 45s as a second terminal. The semiconductor layers 41a and 45a may have an LDD structure. The gate electrodes 41g and 45g are formed at least in regions overlapping the channel regions 41c and 45c, respectively, in plan view.

  As shown in FIG. 28, the semiconductor layers 41a and 45a are arranged in a staggered pattern so as to be staggered in the column direction. Each of the semiconductor layers 41a and 45a is composed of a silicon film formed in a line across the boundary line between two adjacent pixel circuits 40, and has a symmetrical shape in the longitudinal direction. That is, one semiconductor layer 41a has a configuration in which a drain region 41d, a channel region 41c, a source region 41s, a channel region 41c, and a drain region 41d are arranged in a line. Among these, the source region 41 s is shared by the two adjacent pixel circuits 40 and is electrically connected to the second power supply line 12. Similarly, one semiconductor layer 45a has a configuration in which a drain region 45d, a channel region 45c, a source region 45s, a channel region 45c, and a drain region 45d are arranged in a line. Among these, the source region 45 s is shared by the two adjacent pixel circuits 40 and is electrically connected to the first power supply line 11. In the above, the channel regions 41c and 45c are regions overlapping the gate electrodes 41g and 45g in the semiconductor layers 41a and 45a. According to such a configuration, since the number of contacts between the semiconductor layers 41a and 45a and the wiring can be reduced, the yield in the manufacturing process can be improved.

  Further, the semiconductor layer 41a and the semiconductor layer 45a are arranged so as to be parallel to each other. That is, the semiconductor layer 41a is provided along the extending direction of the semiconductor layer 45a. For this reason, the channel length direction of the channel region 41c is a direction along the channel length direction of the channel region 45c. Alternatively, the channel length direction of the channel region 41c may be parallel to the channel length direction of the channel region 45c. According to such a configuration, since the channel region 41c and the channel region 45c can be arranged together in the smallest region, the amplification transistors 45 and the reset transistors 41 can be arranged at high density. Further, when the semiconductor layers 41a and 45a are low-temperature polysilicon formed through laser annealing, the transistor characteristics can be controlled by the size of the channel regions 41c and 45c. In particular, when the semiconductor layers 41a and 45a are low-temperature polysilicon, the current characteristics of the amplifying transistor 45 and the reset transistor 41 can be made uniform, for example, the on current and the off current can be made the same. In the detection device 2, when a certain pixel circuit 40 is not operated, both the amplification transistor 45 and the reset transistor 41 must be surely turned off, but this operation is easy to perform according to the above configuration.

  As shown in FIG. 28, the channel length of the channel regions 41c and 45c is such that the extending direction in plan view is perpendicular to the extending direction (row direction) of the scanning line 10 (FIG. 29). According to such a configuration, the wiring in the column direction such as the second power supply line 12 and the detection line 14 can be overlapped with the amplification transistor 45 and the reset transistor 41, and these components can be arranged at high density. it can.

  In the amplification transistor 45, the drain region 45d (first terminal) and the source region 45s (second terminal) are perpendicular to the extending direction (row direction) of the scanning line 10 and the first power supply line 11 in plan view. Arranged along the direction. Similarly, in the reset transistor 41, the drain region 41d (first terminal) and the source region 41s (second terminal) are perpendicular to the extending direction (row direction) of the scanning line 10 and the first power supply line 11 in plan view. It is arranged along various directions. According to such a configuration, when wirings extending in the row direction, that is, the scanning lines 10 and the first power supply lines 11 are arranged, they are arranged linearly while minimizing a region overlapping the amplification transistor 45 and the reset transistor 41. can do. For this reason, signal delay due to complicated wiring can be prevented. In the case of low-temperature polysilicon formed through laser annealing, the semiconductor layers 41a and 45a can be easily annealed with linear laser light parallel to the column direction of the pixel circuit 40. The electrical characteristics of the semiconductor layers 41a and 45a are strongly dependent on the crystal direction. In particular, in the case of laser annealing, this dependency is significant depending on the direction of laser irradiation. For this reason, according to the configuration of the present embodiment, the semiconductor layers 41a and 45a with high uniformity of electrical characteristics can be obtained.

  As shown in FIG. 28, in each pixel circuit 40, the channel region 45c of the amplification transistor 45 and the channel region 41c of the reset transistor 41 are arranged so as to be staggered in the column direction. Similarly, the contacts between the amplification transistor 45 and the reset transistor 41 and various wirings are also arranged to be staggered in the column direction. In other words, the channel region 45c of the amplification transistor 45 and the channel region 41c of the reset transistor 41 are arranged along a direction that forms a certain angle with respect to the extending direction of the scanning line 10 in plan view. According to such a configuration, when the wiring in the row direction, that is, the scanning line 10 and the first power supply line 11 are connected to the channel regions 41c and 45c, the drain regions 41d and 45d, and the source regions 41s and 45s, these row directions It is not necessary to bend the wiring in a complicated manner, and the wiring can be arranged in a straight line. Thereby, signal delay due to complicated wiring can be prevented.

  The gate electrode 45g extends to a position overlapping the drain region 41d of the reset transistor 41 in plan view, and is electrically connected to the drain region 41d through the contact hole 82. As a result, the amplification transistor 45 can be controlled by the output of the reset transistor 41. Since the semiconductor layers 41a and 45a are arranged as described above, the drain region 41d exists on a line segment extending from the channel region 45c in the minor axis direction of the semiconductor layer 45a. Therefore, the gate electrode 45g can be easily formed up to the drain region 41d by simply extending in the minor axis direction of the semiconductor layer 45a starting from the channel region 45c. Further, a wide contact portion in the drain region 41d can be secured. The gate electrode 45g is arranged linearly along the extending direction of the scanning line 10. As a result, wirings other than the gate electrode 45g are also easily arranged in a straight line in the direction along the scanning line 10. Thereby, signal delay due to complicated wiring can be prevented.

  Returning to FIG. 30, a third layer including the detection line 14 and the like is formed on the second layer with an interlayer insulating film 53 made of silicon oxide or the like interposed therebetween. In addition, relay electrodes 66 and 67 are also formed on the third layer. The detection line 14 is electrically connected to the drain region 45 d of the amplification transistor 45 through a contact hole 83 provided through the interlayer insulating film 53 and the gate insulating film 52. The relay electrodes 66 and 67 are electrically connected to the drain region 41d and the source region 41s of the reset transistor 41 through contact holes 82 and 81 provided through the interlayer insulating film 53 and the gate insulating film 52, respectively. Yes.

  The planar arrangement of the third layer components is shown in FIG. The detection lines 14 are arranged in parallel in the vertical direction (column direction) in the figure, and are partially bent in a dogleg shape so as to avoid the contact holes 84 of the first power supply line 11. The relay electrode 66 is disposed at least in a region overlapping the contact hole 82 in the drain region 41 d of the reset transistor 41. The relay electrode 67 is disposed at least in a region overlapping the contact hole 81 in the source region 41 s of the reset transistor 41.

  Referring back to FIG. 30, a fourth layer including the scanning line 10, the first power supply line 11, and the like is formed on the third layer with an interlayer insulating film 54 made of silicon oxide or the like interposed therebetween. The scanning line 10 is electrically connected to the gate electrode 41 g of the reset transistor 41 through a contact hole 85 provided through the interlayer insulating films 54 and 53. The first power supply line 11 is electrically connected to the source region 45 s of the amplification transistor 45 through a contact hole 84 provided through the interlayer insulating films 54 and 53 and the gate insulating film 52.

  The planar arrangement of the components of the fourth layer is shown in FIG. The scanning line 10 extends along the horizontal direction (row direction) in the figure, and is disposed so as to overlap at least a part of the gate electrode 41g of the reset transistor 41 in plan view. As described above, the scanning line 10 and the gate electrode 41g of the reset transistor 41 are electrically connected via the contact hole 85 formed in the normal direction of the substrate 5 on the gate electrode 41g. As described above, the scanning line 10 is disposed so as to pass above the two transistors in a layer different from the second layer and the third layer, and is connected to the gate electrode 41 g in the normal direction of the substrate 5. Therefore, it is not necessary to separately provide a region for wiring of the scanning line 10, and a region for connecting wiring between the scanning line 10 and the reset transistor 41 becomes unnecessary. For this reason, the amplification transistors 45 and the reset transistors 41 can be arranged with high density.

  The first power supply line 11 extends along the horizontal direction (row direction) in the figure, and is disposed so as to overlap at least a part of the source region 45s of the amplification transistor 45 in plan view. Here, the first power supply line 11 is formed at a position sandwiched between two adjacent rows among the rows of the pixel circuit 40, and one first power supply line 11 is formed for the two adjacent rows. Each first power supply line supplies power to the row of two adjacent pixel circuits 40. That is, the first power supply line 11 is shared by adjacent row of pixel circuits 40. Further, the constituent elements of the two pixel circuits 40 adjacent to each other with the first power supply line 11 interposed therebetween are configured symmetrically with respect to the extending direction of the first power supply line 11. According to such a configuration, the arrangement density of the pixel circuits 40 can be improved by minimizing the number of first power supply lines 11. That is, as compared with the configuration in which two first power supply lines 11 are formed between adjacent rows of the pixel circuits 40, it is necessary to provide an arrangement region of the first power supply lines 11 and a space between the two first power supply lines. Therefore, the arrangement pitch of the pixel circuits 40 can be reduced. In addition, since the components of the pixel circuit 40 are arranged symmetrically with respect to a line, variation in characteristics of the pixel circuit 40 can be reduced.

  Referring back to FIG. 30, a fifth layer including the second power supply line 12 and the relay electrodes 63 and 64 is formed on the fourth layer with an interlayer insulating film 55 made of silicon oxide or the like interposed therebetween. The second power supply line 12 is electrically connected to the relay electrode 67 through a contact hole 86 provided through the interlayer insulating films 55 and 54. Here, since the relay electrode 67 is connected to the source region 41s of the reset transistor 41, the second power supply line 12 is electrically connected to the source region 41s. The relay electrode 63 is electrically connected to the relay electrode 66 through a contact hole 87 provided through the interlayer insulating films 55 and 54. The relay electrode 64 is electrically connected to the first power supply line 11 and thus to the source region 45 s of the amplification transistor 45 through a contact hole 88 provided through the interlayer insulating film 55.

  A connection portion between the relay electrode 64 and the first power supply line 11, that is, a formation position of the contact hole 88 partially overlaps the detection line 14 in plan view. Thus, according to the configuration of the present embodiment, the upper layer region of the detection line 14 can be used effectively. Thereby, the pixel circuits 40 can be formed with high density.

  The planar arrangement of the components of the fifth layer is shown in FIG. The second power supply line 12 extends along the vertical direction (column direction) in the figure, and has a branch portion for connection to the source region 41 s of the reset transistor 41. As described above, since the source region 41s of the reset transistor 41 is shared by the two adjacent pixel circuits 40, power is supplied to the two reset transistors 41 through one contact to the source region 41s. Can do.

  Here, as shown in FIG. 25, both the second power supply line 12 and the detection line 14 are wirings extending along the column direction, the second power supply line 12 is the fifth layer, and the detection line 14 is The third layer is formed in a layer different from the third layer. For this reason, the 2nd power supply line 12 and the detection line 14 can be arrange | positioned so that at least one part may overlap by planar view. In the present embodiment, the second power supply line 12 and the detection line 14 partially overlap. According to such a configuration, since two wirings can be overlapped, the arrangement pitch of the pixel circuits 40 in the row direction can be reduced, and the pixel circuits 40 can be formed with high density.

  Referring back to FIG. 30, a planarizing film 56 made of acrylic resin or the like is formed on the fifth layer. On the planarizing film 56, a first capacitor element 43 and a photodiode 47 as a detection element are arranged in this order. Are stacked. The first capacitor element 43 and the photodiode 47 are formed for each pixel circuit 40.

  The first capacitive element 43 has a configuration in which a second electrode 43b made of Al—Nd, an insulating film 43d made of silicon nitride, etc., and a first electrode 43a made of Al—Nd, etc. are sequentially stacked from the lower layer side. ing. The second electrode 43 b is electrically connected to the relay electrode 64 through a contact hole 79 b formed in the planarizing film 56. Therefore, the second electrode 43 b is electrically connected to the source region 45 s of the amplification transistor 45 via the relay electrode 64 and the first power supply line 11. The contact hole 79b is formed in a region overlapping the second electrode 43b in plan view. The first electrode 43 a is electrically connected to the relay electrode 63 through a contact hole 79 a formed in the planarizing film 56. Therefore, the first electrode 43 a is electrically connected to the drain region 41 d of the reset transistor 41 and the gate electrode 45 g of the amplification transistor 45 through the relay electrodes 63 and 66. The contact hole 79a is formed in a region overlapping the first electrode 43a in plan view. As described above, according to the configuration in which the electrical connection is performed by the contact holes 79a and 79b provided in the normal direction of the substrate 5, the connection can be reliably performed, and the line / space of the wiring provided in the same layer can be achieved. Can be widened. The first electrode 43a partially overlaps the semiconductor layer 41a in plan view, and the second electrode 43b partially overlaps the semiconductor layer 45a in plan view. Such a feature also provides an effect that the line / space of the wiring provided in the same layer can be widened.

  Further, the connection between the first electrode 43 a and the drain region 41 d of the reset transistor 41 and the connection between the gate electrode 45 g of the amplification transistor 45 and the drain region 41 d of the reset transistor 41 are made through the same contact hole 82. (Common contact structure). According to such a configuration, it is possible to reduce the area used for the contact in plan view, and it is possible to arrange the pixel circuits 40 with high density.

  The second electrode 43 b is formed in the pixel circuit 40 except for the drain region 41 d of the reset transistor 41 and the vicinity thereof, and the first electrode 43 a is formed over substantially the entire surface of the pixel circuit 40. Therefore, the channel region 45c of the amplification transistor 45 and the channel region 41c of the reset transistor 41 are covered with at least one of the first electrode 43a and the second electrode 43b in plan view. According to such a configuration, the channel regions 45c and 41c can be shielded by one or two shielding layers (the first electrode 43a and the second electrode 43b). Can be reduced. Thereby, the S / N ratio of the detection signal Xn can be improved.

  The first electrode 43 a of the first capacitive element 43 also serves as the cathode of the photodiode 47. The photodiode 47 has a configuration in which a first electrode 43a as a cathode, an n layer 47n made of amorphous silicon, an i layer 47i, a p layer 47p, and a transparent anode 48 made of ITO are laminated in this order from the lower layer side. ing. An insulating layer 57 made of silicon nitride or the like is formed around the photodiode 47. As described above, according to the configuration in which the first electrode 43 a of the first capacitor 43 is also used as the cathode of the photodiode 47 and the photodiode 47 is formed so as to overlap the first capacitor 43, the first capacitor 43, the photo The area occupied by the diodes 47 can be increased.

(Modification 2-1)
Although the detection apparatus 2 of the present embodiment uses the photodiode 47 as the detection element, various other detection elements can be used. FIG. 31 is a cross-sectional view of the detection apparatus 2 using the second capacitive element 44 as the detection element, and the position of the cross section corresponds to the position of the line DD in FIG. The second capacitive element 44 is formed so as to overlap the first capacitive element 43, and has a configuration in which a first electrode 43a, an insulating layer 44d, and a second electrode 44b are stacked from the lower layer. Here, the first electrode 43 a is a common electrode with the first capacitive element 43. A substrate 6 made of glass or transparent resin is disposed on the second capacitor element 44. When the substrate 6 is deformed due to an external factor, the thickness of the insulating layer 44d changes, and the capacitance of the second capacitor element 44 changes accordingly. As a result, the amount of charge accumulated in the second capacitor element 44 varies, and the gate potential of the amplification transistor 45 changes. As described above, the second capacitive element 44 changes the gate potential of the amplification transistor 45 due to an external factor. Therefore, the external factor can also be detected by the detection device 2 using the second capacitive element 44 as the detection element.

(Modification 2-2)
In the detection device 2 of the present embodiment, each pixel circuit 40 has two power supply lines (first power supply line 11 and second power supply line 12). These power supply lines are electrically connected to be shared. In other words, each pixel circuit 40 may have a single power supply line 12. A circuit diagram of the detection apparatus 2 including the pixel circuit 40 having such a configuration is the same as that of the above-described modification 1-2, and is illustrated in FIG. Even with such a configuration, a detection operation similar to that in the above-described embodiment can be performed.

  FIG. 32 is a plan view of a region including a plurality of pixel circuits 40 of the detection device 2 according to this modification. FIG. 33 is a plan view showing the arrangement of the first layer (layer in which the semiconductor layers 41a and 45a are formed) and the fifth layer (layer in which the power supply line 12 is formed) among the components shown in FIG. . As shown in these figures, the power supply line 12 is arranged along the vertical direction (column direction) in the figure, and contact holes 81, 84, 86 are provided at branch portions extending in the direction intersecting the column direction. , 88 are electrically connected. More specifically, the power supply line 12 is electrically connected to the source region 41 s via the contact holes 81 and 86, and is electrically connected to the source region 45 s via the contact hole 89. Further, the power supply line 12 is electrically connected to the second electrode 43b of the first capacitive element 43 at the position of the contact hole 79b.

  The detection device 2 of this modification does not have the first power supply line 11. Therefore, the first power supply line 11 can be omitted in the fourth layer (FIG. 29) including the first power supply line 11 and the scanning line 10 included in the second embodiment.

  According to the configuration of this modification, each pixel circuit (unit circuit) 40 has a single power supply line 12, and therefore the circuit configuration of the detection device 2 is simplified compared to a configuration having a plurality of power supply lines. Can be In addition, since it is not necessary to form a plurality of power supply lines 12 in different layers, the layer structure of the pixel circuit 40 can be simplified. Furthermore, the arrangement area of the power supply lines 12 can be reduced, and the pixel circuits 40 can be configured with higher density.

(Modification 2-3)
The detection device 2 according to the present embodiment or the above modification includes the features listed below, but does not need to include all of these features, and includes only some of these features. It may be. According to the detection device having any one or more of the following features, an effect corresponding to the feature can be obtained.

  Each of the semiconductor layers 41a and 45a is constituted by a silicon film formed in a continuous manner over two adjacent pixel circuits 40. Among these, the source region 41 s of the semiconductor layer 41 a is shared by the two adjacent pixel circuits 40 and is electrically connected to the second power supply line 12. In addition, the source region 45 s of the semiconductor layer 45 a is shared by two adjacent pixel circuits 40 and is electrically connected to the first power supply line 11. According to such a configuration, since the number of contacts between the semiconductor layers 41a and 45a and the wiring can be reduced, the yield in the manufacturing process can be improved.

  A configuration in which the channel length direction of the reset transistor 41 is along the channel length direction of the amplification transistor 45. According to such a configuration, the amplification transistors 45 and the reset transistors 41 can be arranged with high density. Further, the current characteristics of the amplification transistor 45 and the reset transistor 41 can be made uniform, and for example, the on current and the off current can be made the same.

  A configuration in which the extending direction of the channel lengths of the channel regions 41 c and 45 c in a plan view is perpendicular to the extending direction of the scanning line 10. According to such a configuration, the wiring in the column direction such as the second power supply line 12 and the detection line 14 can be overlapped with the amplification transistor 45 and the reset transistor 41, and these components can be arranged at high density. it can.

  A drain region 45d (first terminal) and a source region 45s (second terminal) of the amplification transistor 45 are disposed along a direction perpendicular to the extending direction of the scanning line 10 and the first power supply line 11 in plan view, In addition, the drain region 41d (first terminal) and the source region 41s (second terminal) of the reset transistor 41 are arranged. According to such a configuration, the semiconductor layers 41 a and 45 a can be easily annealed by linear laser light parallel to the column direction of the pixel circuit 40. Further, when the wirings extending in the row direction are arranged, they can be arranged in a straight line while minimizing a region overlapping with the amplification transistor 45 and the reset transistor 41. For this reason, signal delay due to complicated wiring can be prevented.

  In each pixel circuit 40, the channel region 45c of the amplification transistor 45 and the channel region 41c of the reset transistor 41 are arranged so as to be staggered in the column direction. Or the structure arrange | positioned so that the contact of the amplification transistor 45 and the reset transistor 41, and various wiring may become alternate about a column direction. Alternatively, the channel region 45 c of the amplification transistor 45 and the channel region 41 c of the reset transistor 41 are arranged along a direction that forms a certain angle with respect to the extending direction of the scanning line 10 in plan view. According to such a configuration, when the wiring in the row direction, that is, the scanning line 10 and the first power supply line 11 are connected to the channel regions 41c and 45c, the drain regions 41d and 45d, and the source regions 41s and 45s, these row directions It is not necessary to bend the wiring in a complicated manner, and it can be arranged in a straight line. Thereby, signal delay due to complicated wiring can be prevented.

  A configuration in which the connection between the first electrode 43a and the drain region 41d of the reset transistor 41 and the connection between the gate electrode 45g of the amplification transistor 45 and the drain region 41d of the reset transistor 41 are made through the same contact hole 82 (common contact) Construction). According to such a configuration, it is possible to reduce the area used for the contact in plan view, and it is possible to arrange the pixel circuits 40 with high density.

  A configuration in which the scanning line 10 overlaps at least part of the gate electrode 41g of the reset transistor 41 in plan view. The scanning line 10 and the gate electrode 41g of the reset transistor 41 are electrically connected via a contact hole 85 formed in the normal direction of the substrate 5 on the gate electrode 41g. According to such a configuration, the scanning line 10 is disposed so as to pass over the two transistors in a layer different from the second layer and the third layer, and is connected to the gate electrode 41 g in the normal direction of the substrate 5. Therefore, it is not necessary to separately provide a region for wiring of the scanning line 10, and a region for connecting wiring between the scanning line 10 and the reset transistor 41 becomes unnecessary. For this reason, the amplification transistors 45 and the reset transistors 41 can be arranged with high density.

  The first power supply line 11 is formed at a position sandwiched between two adjacent rows among the rows of the pixel circuits 40, and one first power supply line 11 is formed for the two adjacent rows. Configuration to supply power to the row. According to such a configuration, the arrangement density of the pixel circuits 40 can be improved by minimizing the number of first power supply lines 11. That is, as compared with the configuration in which two first power supply lines 11 are formed between adjacent rows of the pixel circuit 40, it is necessary to provide a space between the arrangement region of the first power supply lines 11 and the two first power supply lines. Therefore, the arrangement pitch of the pixel circuits 40 can be reduced.

  Alternatively, the components of the two pixel circuits 40 that are adjacent to each other with the first power supply line 11 interposed therebetween are configured to be line-symmetric with respect to the extending direction of the first power supply line 11. According to such a configuration, variation in characteristics of the pixel circuit 40 can be reduced.

  A configuration in which the second power supply line 12 and the detection line 14 both extend along the column direction and are formed in different layers. Or the structure by which the 2nd power supply line 12 and the detection line 14 are arrange | positioned so that at least one part may overlap by planar view. According to such a configuration, since two wirings can be overlapped, the arrangement pitch of the pixel circuits 40 in the row direction can be reduced, and the pixel circuits 40 can be formed with high density.

  A configuration in which the first electrode 43 a and the second electrode 43 b of the first capacitive element 43 are electrically connected to a relay electrode or the like through contact holes 79 a and 79 b provided in the normal direction of the substrate 5. According to such a configuration, the connection can be reliably performed, and the line / space of the wiring provided in the same layer can be widened.

  A configuration in which the channel region 45c of the amplification transistor 45 and the channel region 41c of the reset transistor 41 are covered with at least one of the first electrode 43a and the second electrode 43b of the first capacitor 43 in plan view. According to such a configuration, the channel regions 45c and 41c can be shielded by one or two shielding layers (the first electrode 43a and the second electrode 43b). Can be reduced. Thereby, the S / N ratio of the detection signal Xn can be improved.

  A configuration in which the first electrode 43 a of the first capacitor 43 also serves as the cathode of the photodiode 47. According to such a configuration, the occupied areas of the first capacitor element 43 and the photodiode 47 can be increased.

  A configuration in which the second capacitive element 44 is used in place of the photodiode 47 as the detection element. Even with such a configuration, an external factor can be detected.

  A configuration in which each pixel circuit 40 has a single power supply line 12. According to such a configuration, the circuit configuration of the detection device can be simplified. In addition, it is possible to simplify the layer structure of the unit circuit and increase the density of the unit circuit.

<Electronic equipment>
The above-described detection device 1 (including the detection device 2; the same applies hereinafter) can be mounted and used in a mobile phone 500 as an electronic device as shown in FIG. 34, for example. The mobile phone 500 includes a display unit 510 and operation buttons 520. The display unit 510 can display various information including information input by the operation buttons 520 and incoming call information. The display unit 510 incorporates the detection device 1 therein. When a touch pen, a finger, or the like is brought close to the detection device 1, a change in the amount of incident light is detected by the detection device 1, and the position information is input to the electronic device. Thus, the mobile phone 500 has a user interface using the detection device 1.

  The detection device 1 can be used for various electronic devices such as a mobile computer, a digital camera, a digital video camera, an in-vehicle device, and an audio device, in addition to the mobile phone 500. The detection device 1 can be applied to an image reading device such as a scanner or an imaging device.

The block diagram which shows the structure of a detection apparatus. FIG. 3 is a circuit diagram illustrating a configuration of a pixel circuit. The block diagram which shows the structure of a 1st X driver. The block diagram which shows the structure of a 2nd X driver. The timing chart which shows the signal waveform of each part of a detection apparatus. Explanatory drawing which shows the signal flow in a reset period. Explanatory drawing which shows the flow of the signal in an initialization period. Explanatory drawing which shows the flow of the signal in a detection period. Explanatory drawing which shows the bias of a pixel circuit. The graph which shows the time change of the electric potential of a detection line. The top view in the area | region containing a some pixel circuit of a detection apparatus. The enlarged plan view of a pixel circuit. The top view which shows arrangement | positioning of the 1st layer and 3rd layer among the components of FIG. The top view which shows arrangement | positioning of a 1st layer, a 2nd layer, and a 4th layer among the components of FIG. The top view which shows arrangement | positioning of the 1st layer and 5th layer among the components of FIG. The top view which shows arrangement | positioning of a 1st capacitive element and a photodiode. The top view which extracts and shows a 1st power supply line, a semiconductor layer, etc. from FIG. The top view which shows the modification of arrangement | positioning of a 1st power supply line. Sectional drawing of the detection apparatus along the BB line in FIG. Sectional drawing of the detection apparatus along CC line in FIG. Sectional drawing of the detection apparatus using the 2nd capacitive element as a detection element. The circuit diagram of the detecting device concerning modification 1-2. The top view in the area | region containing a several pixel circuit of the detection apparatus which concerns on the modification 1-2. The top view which shows arrangement | positioning of the 1st layer and 3rd layer among the components of FIG. The top view in the area | region containing several pixel circuits of a detection apparatus. The enlarged plan view of a pixel circuit. The top view which shows arrangement | positioning of the 1st layer and 5th layer among the components of FIG. The top view which shows arrangement | positioning of the 1st layer and 2nd layer among the components of FIG. The top view which shows arrangement | positioning of a 1st layer, a 3rd layer, and a 4th layer among the components of FIG. FIG. 26 is a cross-sectional view of the detection device along line DD in FIG. 25. Sectional drawing of the detection apparatus using the 2nd capacitive element as a detection element. The top view in the area | region containing a some pixel circuit of the detection apparatus which concerns on modification 2-2. The top view which shows arrangement | positioning of the 1st layer and 5th layer among the components of FIG. The perspective view of the mobile telephone as an electronic device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,2 ... Detection apparatus 5,6 ... Substrate, 10 ... Scanning line 11, 11, 11a, 11b ... First power supply line, 12 ... Second power supply line, 14 ... Detection line, 40 ... Pixel circuit as unit circuit, 41 ... Reset transistor as second transistor, 41a, 45a ... Semiconductor layer, 41c, 45c ... Channel region, 41d, 45d ... Drain region, 41g, 45g ... Gate electrode, 41s, 45s ... Source region, 43 ... First capacitance Element 43a ... first electrode 43b ... second electrode 43d ... insulating film 44 ... second capacitor element 44b ... second electrode 44d ... insulating layer 45 ... amplifying transistor as first transistor 47 ... detection Photodiode as element 48... Anode 51. Base insulating film 52. Gate insulating film 53 54 54 Interlayer insulating film 56 Planarizing film 57 Insulating layer 61 67 ... relay electrode, 71~78,79a, 79b, 81~89 ... contact hole, 500 ... mobile phone as an electronic apparatus.

Claims (15)

A substrate,
Corresponding to the intersection of a plurality of scanning lines, a plurality of detection lines, a plurality of first power supply lines, a plurality of second power supply lines, and the scanning lines and the detection lines disposed on the substrate. A plurality of unit circuits provided,
The unit circuit is
A first transistor having a first terminal connected to the detection line and a second terminal connected to the first power line, and supplying a detection signal corresponding to a potential of a gate electrode to the detection line;
A detection element connected to the gate electrode of the first transistor and changing a gate potential of the first transistor according to an external factor;
A second transistor having a first terminal connected to the gate electrode of the first transistor, a second terminal connected to the second power supply line, and a gate electrode connected to the scan line;
A first capacitive element provided between the gate electrode of the first transistor and the first power supply line and holding the gate potential of the first transistor;
The detection device according to claim 1, wherein a channel length direction of the first transistor is along a channel length direction of the second transistor. The detection device according to claim 1,
The detection is characterized in that the first transistor and the second transistor are arranged so that a channel length direction intersects the extending direction of the scanning line and the extending direction of the detection line in a plan view. apparatus. The detection device according to claim 1 or 2,
The first transistor and the second transistor are arranged such that the channel length direction forms an angle of 45 degrees with respect to the extending direction of the scanning line and the extending direction of the detection line in plan view. A detection device characterized by that. The detection device according to any one of claims 1 to 3,
A first terminal and a second terminal of the first transistor are arranged along a direction intersecting the extending direction of the scanning line and the extending direction of the detection line in plan view, and the scanning line extends in plan view. A detection apparatus, wherein a first terminal and a second terminal of the second transistor are arranged along a direction intersecting a current direction and an extending direction of the detection line. The detection device according to any one of claims 1 to 4,
The first terminal and the second terminal of the first transistor are arranged along a direction that forms an angle of 45 degrees with respect to the extending direction of the scanning line and the extending direction of the detection line in plan view. The first terminal and the second terminal of the second transistor are arranged along a direction that forms an angle of 45 degrees with respect to the extending direction of the scanning line and the extending direction of the detection line. Detection device. The detection device according to any one of claims 1 to 5,
In the unit circuit, the first transistor and the second transistor are arranged between the detection line and the second power supply line in a plan view. The detection device according to any one of claims 1 to 6,
A first terminal of the first transistor and a first terminal of the second transistor are disposed along the extending direction of the scanning line in plan view, and the first terminal of the first transistor is disposed along the extending direction of the scanning line in plan view. 2. A detection apparatus comprising a second terminal of one transistor and a second terminal of the second transistor. The detection device according to claim 1,
The detection device, wherein the first transistor and the second transistor have a channel length direction perpendicular to an extending direction of the scanning line in a plan view. The detection device according to claim 8,
A first terminal and a second terminal of the first transistor are arranged along a direction perpendicular to the extending direction of the scanning line in plan view, and along a direction perpendicular to the extending direction of the scanning line in plan view. And a first terminal and a second terminal of the second transistor are arranged. The detection device according to claim 8 or 9, wherein
A detection device, wherein the channel region of the first transistor and the channel region of the second transistor are arranged along a direction forming a certain angle with respect to the extending direction of the scanning line in plan view. . The detection device according to any one of claims 8 to 10,
The detection device, wherein the gate electrode of the first transistor is arranged along the extending direction of the scanning line in a plan view. The detection device according to any one of claims 1 to 11,
The detection device is a photoelectric conversion device that converts light energy into electrical energy. The detection device according to any one of claims 1 to 11,
The detection device according to claim 1, wherein the detection element is a second capacitance element whose capacitance is changed by deformation. A substrate,
A plurality of scanning lines, a plurality of detection lines, a plurality of power supply lines, and a plurality of unit circuits provided corresponding to the intersections of the scanning lines and the detection lines, disposed on the substrate; Prepared,
The unit circuit is
A first transistor having a first terminal connected to the detection line and a second terminal connected to the power line, and supplying a detection signal corresponding to the potential of the gate electrode to the detection line;
A detection element connected to the gate electrode of the first transistor and changing a gate potential of the first transistor according to an external factor;
A second transistor having a first terminal connected to the gate electrode of the first transistor, a second terminal connected to the power supply line, and a gate electrode connected to the scan line;
A first capacitive element provided between the gate electrode of the first transistor and the first power supply line and holding the gate potential of the first transistor;
The detection device according to claim 1, wherein a channel length direction of the first transistor is along a channel length direction of the second transistor.   An electronic apparatus comprising the detection device according to claim 1.

Images