JP5065707B2 - 電子部品の実装構造 - Google Patents
電子部品の実装構造 Download PDFInfo
- Publication number
- JP5065707B2 JP5065707B2 JP2007045596A JP2007045596A JP5065707B2 JP 5065707 B2 JP5065707 B2 JP 5065707B2 JP 2007045596 A JP2007045596 A JP 2007045596A JP 2007045596 A JP2007045596 A JP 2007045596A JP 5065707 B2 JP5065707 B2 JP 5065707B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- substrate portion
- resin material
- mounting structure
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Coils Or Transformers For Communication (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
1a・・・コア
1b・・・保持部
2・・・リード端子
3・・・基板
3a・・・実装基板部
3b・・・放熱基板部
4・・・電極パッド
5・・・凹部
6・・・接着材
7・・・樹脂材
Claims (3)
- 上側の実装基板部および下側の放熱基板部からなり、前記実装基板部の上面から前記放熱基板部にかけて凹部が形成されているとともに該凹部の周囲に複数の電極パッドが形成された基板と、
複数の前記電極パッドに接続された複数のリード端子が接続されて前記凹部内に底面および側面から離れた位置に配置された、銅線が巻き付けられたボビンにフェライトから成るコアが取り付けられたトランスである電子部品と、
前記凹部内の前記電子部品の周囲に充填された、ゴム硬さが70以下である樹脂材とを具備することを特徴とする電子部品の実装構造。 - 前記凹部は、前記実装基板部に形成された貫通孔と、前記放熱基板部に形成された穴とから成り、
前記電子部品の一部は、前記穴に入り込んでいることを特徴とする請求項1に記載の電子部品の実装構造。 - 前記樹脂材の上面がゴム硬さが80以上の樹脂材で覆われていることを特徴とする請求項1または請求項2に記載の電子部品の実装構造。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007045596A JP5065707B2 (ja) | 2007-02-26 | 2007-02-26 | 電子部品の実装構造 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007045596A JP5065707B2 (ja) | 2007-02-26 | 2007-02-26 | 電子部品の実装構造 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008210959A JP2008210959A (ja) | 2008-09-11 |
JP5065707B2 true JP5065707B2 (ja) | 2012-11-07 |
Family
ID=39787019
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007045596A Expired - Fee Related JP5065707B2 (ja) | 2007-02-26 | 2007-02-26 | 電子部品の実装構造 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5065707B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5471716B2 (ja) * | 2010-03-30 | 2014-04-16 | トヨタ自動車株式会社 | リアクトルの製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0730055A (ja) * | 1993-06-24 | 1995-01-31 | Toppan Printing Co Ltd | マルチチップモジュール実装型プリント配線板 |
JPH07335451A (ja) * | 1994-06-03 | 1995-12-22 | Murata Mfg Co Ltd | コイル部品 |
JPH09321182A (ja) * | 1996-05-29 | 1997-12-12 | Shiaru:Kk | 樹脂封止型半導体装置 |
JP2000232115A (ja) * | 1999-02-10 | 2000-08-22 | Sony Corp | 半導体装置の製造方法 |
JP2003318042A (ja) * | 2002-04-22 | 2003-11-07 | Tokyo Coil Engineering Kk | 小型トランス |
-
2007
- 2007-02-26 JP JP2007045596A patent/JP5065707B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2008210959A (ja) | 2008-09-11 |
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