JP5063640B2 - Semiconductor device - Google Patents

Description

  The invention disclosed in this specification relates to a semiconductor device using a crystalline semiconductor, particularly to a structure of an insulated gate transistor. In addition, the present invention relates to the configuration of a semiconductor circuit, an electro-optical device, and an electronic device that is a combination of such a semiconductor circuit including such transistors.

  Note that in this specification, the above transistors, semiconductor circuits, electro-optical devices, and electronic devices are all included in the category of “semiconductor devices”. That is, all devices that can function using semiconductor characteristics are called semiconductor devices. Accordingly, the semiconductor device described in the claims includes not only a single element such as a transistor but also a semiconductor circuit, an electro-optical device, and an electronic apparatus in which the semiconductor device is integrated.

  In the current VLSI and ULSI, the element size tends to be miniaturized in order to further improve the degree of integration. This flow can be seen in both MOSFETs using bulk single crystals and TFTs using thin films. At present, devices having a channel length of 1 μm or less and further 0.2 μm or less are required.

  However, a phenomenon called the short channel effect is known as a factor that prevents miniaturization. The short channel effect is various problems such as lowering of the source-drain breakdown voltage and lowering of the threshold voltage which are caused as the channel length is shortened (submicron device I; Mitsumasa Koyanagi et al., Pp88-138, Maruzen) Company, 1987).

  According to the reference book, the punch-through phenomenon is best known as one of the causes of the pressure drop. This phenomenon is due to the fact that the drain side depletion layer has a potential effect on the source side due to the shortening of the channel length, and the diffusion potential on the source side is lowered (drain induced barrier lowering phenomenon), so that majority carriers are controlled by the gate voltage. Is a difficult situation.

  Such a short channel effect is a problem that must be overcome when miniaturization is performed. A typical example of the short channel effect is a decrease in threshold voltage. This is also thought to be caused by the spread of the depletion layer.

  Various measures have been taken against the short channel effect as described above, but the most commonly taken measure is channel doping. Channel doping is a technique for suppressing a short channel effect by adding a small amount of an impurity element such as P (phosphorus) or B (boron) to the entire channel formation region (Japanese Patent Laid-Open Nos. 4-206971 and 4). -286339).

  Channel doping is performed for the purpose of controlling the threshold voltage and suppressing punch-through. However, the channel doping technique has a drawback in that it seriously restricts the field effect mobility (hereinafter referred to as mobility) of the TFT. That is, the intentionally added impurity element inhibits the movement of carriers, and the carrier mobility is greatly reduced.

  The present invention has been made in view of the above problems, and provides a semiconductor device having a completely new structure capable of simultaneously realizing high operating performance (high mobility) and high reliability (high withstand voltage characteristics), and a method for manufacturing the same. The task is to do.

The configuration of the invention disclosed in this specification is as follows.
A semiconductor device having a circuit formed of a transistor including a source region, a drain region, and an active region formed using a crystalline semiconductor.
The active region is composed of a Si _x Ge _1-x (0 <X <1) region formed by locally adding germanium and a Si region to which germanium is not added,
A depletion layer extending from the drain region toward the source region is suppressed by the Si region.

Further, the configuration of the other invention is as follows:
A semiconductor device having a circuit formed of a transistor including a source region, a drain region, and an active region formed using a crystalline semiconductor.
The active region is composed of a Si _x Ge _1-x (0 <X <1) region formed by locally adding germanium and a Si region to which an element selected from group 13 or group 15 is added. The depletion layer extending from the drain region toward the source region is suppressed by the Si region, and the threshold voltage is controlled.

In the above configuration, the active region is configured such that the Si _x Ge _1-x (0 <X <1) region and the Si region are substantially parallel to each other and alternately arranged.
The Si _x Ge _1-x (0 <X <1) region is preferably formed from the source region to the drain region.

Further, the configuration of the other invention is as follows:
A semiconductor device having a circuit formed of a transistor including a source region, a drain region, and an active region formed using a crystalline semiconductor.
In the active region, Si _x Ge _1-x (0 <X <1) regions formed by adding germanium and Si regions not added by germanium are arranged substantially parallel to each other and alternately arranged. The Si _x Ge _1-x (0 <X <1) region is formed from the source region to the drain region.

Further, the configuration of the other invention is as follows:
A semiconductor device having a circuit formed of a transistor including a source region, a drain region, and an active region formed using a crystalline semiconductor.
A Si _x Ge _1-x (0 <X <1) region formed by adding germanium is locally provided at an interval in a junction between the active region and the source region. And

Further, the configuration of the other invention is as follows:
A semiconductor device having a circuit formed of a transistor including a source region, a drain region, and an active region formed using a crystalline semiconductor.
A Si _x Ge _1-x (0 <X <1) region formed by adding germanium is locally formed at an interval in a junction between the active region and the drain region. And

  The gist of the present invention is that two regions having different band structures are intentionally formed by locally adding germanium to the active region, and the difference between the band structures is used to change from the drain side to the source side. The purpose is to suppress the depletion layer that spreads toward you. Note that the active region refers to a region sandwiched between source / drain regions (or between LDD regions).

  In addition, the present inventors define the term “pinning” in the sense of “suppression” because the effect of suppressing the depletion layer can be understood as if the depletion layer is pinned. A semiconductor device using the present invention is called a pinning FET (or pinning TFT) and is clearly distinguished from a conventional semiconductor device.

  The semiconductor device of the present invention having the above-described configuration simultaneously achieves high operating performance and high reliability. Details regarding the semiconductor device of the present invention will be described with reference to the following embodiments.

  According to the present invention, adverse effects due to the short channel effect can be suppressed or prevented even in a fine semiconductor device having a very small channel length and channel width. That is, it is possible to solve the decrease in the breakdown voltage between the source and the drain and the decrease in the threshold voltage due to punch-through.

  Furthermore, since the above effect can be obtained without adding extra impurities to the channel formation region (region where carriers move), carrier mobility is not impaired. As a result, extremely high mobility is realized, and there is an advantage that high speed operation characteristics (high frequency characteristics) are excellent.

In addition, by utilizing the Si _x Ge _1-x region as a minority carrier lead-out wiring, it is possible to prevent a decrease in source-drain breakdown voltage due to impact ionization.

  With the above synergistic effect, it is possible to realize a semiconductor device that simultaneously achieves high operating performance and high reliability. In addition, an electro-optical device and a semiconductor circuit that employ the semiconductor device of the present invention, and an electronic apparatus equipped with them can obtain very high performance and high reliability.

The figure which shows the structure of the semiconductor device (FET) of this invention. The figure which shows the band structure of an active region. The figure which shows the definition of channel length and channel width. The figure which shows the energy state of an active region. The figure which shows the energy state of an active region typically. The figure which shows the structure of the semiconductor device (TFT) of this invention. The figure which shows the structure of an active region. The figure which shows the structure of an active region. The figure which shows the structure of an active region. The figure which shows the structure of an active region. FIG. 5 is a diagram for explaining a configuration of a CMOS circuit. 1 is a diagram illustrating a schematic configuration of an electro-optical device. FIG. 9 illustrates a structure of a semiconductor circuit. FIG. 10 illustrates an example of an electronic device.

  The structure of the pinning FET of the present invention will be described with reference to FIG. 1A is a top view, FIG. 1B is a cross-sectional view of the top view cut along A-A ′, and FIG. 1C is a cross-sectional view of the top view cut along B-B ′.

In FIG. 1A, 101 is a source region, 102 is an active region, 103 is a drain region, and 104 is a field oxide film. A plurality of regions 105 provided so as to cross the active region 102 are regions where germanium (Ge) is locally added (hereinafter abbreviated as Si _x Ge _1-x (0 <X <1) region). It is.

In the composition represented by Si _x Ge _1-x , a relationship of 0 <X <1 is established. That is, the Si _x Ge _1-x region is not composed of only Si or Ge. Specifically, germanium is added at a concentration such that x falls within the range of 0.05 to 0.95.

  In the active region 102, the region 106 to which germanium is not added is a region made of intrinsic or substantially intrinsic silicon (hereinafter abbreviated as Si region).

  In addition, LDD regions 107 are provided at both ends of the active region 102, and a gate electrode 108 is provided on the active region 102 through a gate insulating film. The gate electrode 108 is made of silicon having conductivity. In addition, a material containing aluminum as a main component, tantalum, tungsten, molybdenum, or the like can be used. Further, a source electrode 109 and a drain electrode 110 are provided through an interlayer insulating film, and are in contact with the source region 101 and the drain region 103, respectively.

Here, the Si _x Ge _1-x region and the Si region, which are features of the present invention, will be described. As described above, in the present invention, the active region 102 is composed of the Si _x Ge _1-x region 105 and the Si region 106. As shown in FIG. 1A, the most typical configuration is a configuration in which Si _x Ge _1-x regions 105 and Si regions 106 are arranged substantially parallel to each other and alternately. In such a configuration, it can be considered that the active region 102 is divided into a plurality of Si regions 106 by the Si _x Ge _1-x regions 105.

The Si _x Ge _1-x region 105 can be formed by adding germanium using a mass-separated ion implantation method. Here, changes in the band gap when germanium is added will be described with reference to FIG.

The energy band diagram shown in FIG. 2 schematically shows changes in the band structure between adjacent Si _x Ge _1-x regions and Si regions. Although the band structure at the Si / Si _x Ge _1-x interface is still under study, it is reported that the band structure shown in Fig. 2 is formed near the interface between the Si _x Ge _1-x layer and the Si layer. Has been.

That is, in the Si _x Ge _1-x region, the valence band (Ev) rises significantly compared to the conduction band (Ec), and this portion becomes an extremely narrow gap. Therefore, the band gap (Eg ₂ ) of the Si _x Ge _1-x region is smaller than the band gap (Eg ₁ ) of the Si region as shown in the schematic diagram shown in FIG.

At this time, the band gap of the Si _x Ge _1-x region varies depending on the amount of germanium contained in the composition. In the present invention, _x is changed so that 0 <X <1, preferably 0.05 <x <0.95 (typically 0.5 <x <0.95) in the composition represented by Si _x Ge _1-x . Further, by this control, the band gap (Eg ₂ ) of the Si _x Ge _1-x region changes between 0.66 <Eg ₂ <1.6 (typically 0.66 <Eg ₂ <1.1).

In the case of such a band structure, carriers (electrons or holes) during FET operation tend to move preferentially in the Si _x Ge _1-x region with a narrow energy gap. Accordingly, the Si _x Ge _1-x region functions as a carrier movement path. Such a tendency is the same in both the N channel type and the P channel type.

  Here, the channel length and the channel width are defined with reference to FIG. In FIG. 3, a distance between the source region 301 and the drain region 302 (corresponding to the length of the active region 303) is defined as a channel length (L). The present invention is particularly effective when the length is 2 μm or less, typically 30 to 500 nm (more preferably 50 to 200 nm). A direction along the channel length is referred to as a channel length direction.

  The length of the active region 303 in the direction orthogonal to the channel length direction is referred to as the total channel width (W). A direction along the total channel width is referred to as a channel width direction.

Next, the width of an arbitrary Si _x Ge _1-x region 304 (referred to as channel width) is denoted by w _i . Desirably, the minimum width of the width v _{i is set to such} an extent that the quantum effect does not occur (about 3 nm), and the maximum width is set to be about the same as the maximum depletion layer width of the drain side depletion layer.

The maximum depletion layer width is inevitably determined if the substrate concentration (or well concentration) and the impurity concentration of the drain region are determined. For example, if the substrate or well concentration is about 1 × 10 ¹⁶ atoms / cm ^3, it is about 300 nm.

For the above reasons, the width (w _i ) of the Si _x Ge _1-x region 304 is less than 2 μm, preferably 50 to 300 nm (more preferably 1 to 50 nm). When the total width of all Si _x Ge _1-x regions existing in the active region 303 is W, the following equation is defined.

Note that the Si _x Ge _1-x region 304 functions as a region where carriers move (hereinafter referred to as a channel formation region). Therefore, it is necessary to provide at least one Si _x Ge _1-x region for the active region 303. That is, i = 1 to m, and 1 to m Si _x Ge _1-x regions are formed. The total sum (W) of the channel widths v _i described above is referred to as an effective channel width.

The Si _x Ge _1-x region 304 is doped with germanium in the range of 1 × 10 ¹⁷ to 5 × 10 ¹⁹ atoms / cm ³ (preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ³ ). Can be formed. The band gap of the Si _x Ge _1-x region 304 changes depending on the addition concentration. However, since excessive addition of germanium may hinder the movement of carriers, the upper limit is preferably about 1 × 10 ¹⁹ atoms / cm ³ .

Next, the width of the Si region 305 (referred to as pinning width) is set to v _j . As with the Si _x Ge _1-x region 304, the pinning width v _j is 1 μm or less, preferably 50 to 300 nm (more preferably 1 to 50 nm), so that a pinning effect can be obtained. Further, when the total sum of the widths v _j of the Si region 305 is V, the following equation is defined.

Note that since the Si region 305 functions as a region for suppressing the spread of the depletion layer, it is necessary to provide at least one Si region with respect to the active region 303. That is, j = 1 to n, and 1 to n Si regions are formed. The total sum (V) of the above-described pinning widths v _i is referred to as an effective pinning width.

The total sum of the effective channel width (W) and the effective pinning width (V) is defined as the _total channel width (W _total ), which is defined by the following equation.

Since the semiconductor device of the present invention defined as described above is applied in particular to a semiconductor device having an extremely small channel length, the formation of the Si _x Ge _1-x region is performed with extremely fine dimensions. Must-have.

Therefore, the formation of the Si _x Ge _1-x region 105 in FIG. 1A requires extremely fine exposure technology and ion implantation technology. That is, it is preferable to combine an exposure technique using excimer laser, electron beam, X-ray or the like and an ion implantation technique using ion implantation, plasma doping, laser doping or the like. It is also possible to add impurities without using a focused ion beam (FIB) or the like.

  In particular, in order to precisely control the amount of germanium introduced, it is preferable to use a technique capable of precise concentration control as the ion implantation technique.

  Next, FIG. 1B will be described. Note that in FIG. 1B, portions described in FIG. 1A are described using the same reference numerals.

  In FIG. 1B, reference numeral 111 denotes a single crystal silicon substrate, which uses an N-type or P-type silicon substrate. As the silicon substrate 111, any silicon substrate formed by a normal CZ method, FZ method, or other methods can be used. However, in order to increase carrier mobility, it is preferable to use a high-resistance silicon substrate with a small amount of dopant (impurity element addition concentration).

  In this embodiment, an example in which the pinning FET is formed using the silicon substrate as it is is shown, but an N-type or P-type impurity well may be formed and the pinning FET may be formed therein. .

112 is a channel stopper formed under the field oxide film 104, 113 is a gate insulating film, and 114 is an interlayer insulating film. Further, a region other than the Si _x Ge _1-x region 105 in the active region 102 becomes the Si region 106.

Then, by forming the Si _x Ge _1-x region 105 in a stripe shape with respect to the active region 102, the Si region 106 is also formed in a stripe shape. The Si region 106 is preferably formed deep so that a depletion layer extending from the drain side to the source side is effectively pinned. Basically, it should be deeper than the junction depth of the source / drain regions.

  Next, FIG. 1C will be described. In FIG. 1C, a region 107 provided inside the source region 101 and the drain region 103 is an LDD region. The LDD region 107 is formed using the sidewall 115.

As shown in FIG. 1C, forming the Si _x Ge _1-x region 105 so as to penetrate into the LDD region 107 is effective because carriers move smoothly until reaching the LDD region. is there. Of course, it can be formed so as to penetrate into the drain region 103, or can be formed so as not to penetrate into the LDD region.

  The pinning FET of the present invention is based on the configuration as described above. However, the most important is the configuration of the active region, and the element structure not directly related to the active region is not limited to the structure of FIG.

Next, the role played by the Si _x Ge _1-x region 105 and the Si region 106 and the effects obtained thereby will be described by taking an N-channel FET as an example.

  First, the first effect will be described. The most important object of the present invention is to suppress (pinning) a depletion layer spreading from the drain side to the source side, and to prevent a potential barrier on the source side from being lowered due to the drain voltage. In addition, by suppressing the spread of the depletion layer, it is possible to sufficiently prevent a decrease in threshold voltage and a breakdown voltage due to punch-through.

  In FIG. 1, the Si region 106 remaining locally in the active region 102 acts as a potential stopper (barrier) against the depletion layer spreading from the drain side, and effectively suppresses the spread of the depletion layer. Therefore, the diffusion potential on the source side is not lowered due to the spread of the depletion layer, and the punch-through phenomenon is prevented. In addition, since the increase in depletion layer charge due to the spread of the depletion layer is suppressed, a decrease in threshold voltage can be avoided.

As described above, the formation of the Si _x Ge _1-x region 105 in the active region distinguishes between the striped channel formation region and the pinning region, which is a very serious problem in miniaturization. It is possible to suppress or prevent the short channel effect. This effect is the most important effect of the semiconductor device of the present invention.

Next, the second effect will be described. In the N-channel FET of the present invention, the Si _x Ge _1-x region provided in a stripe shape functions as a channel formation region, so that a carrier movement path is defined and unnecessary carrier scattering can be prevented.

FIG. 4 shows the energy state (potential state) of the active region 102 when the pinning TFT of this embodiment operates. In FIG. 4, regions indicated by 401 and 402 correspond to the energy state of the Si region 106, and a region indicated by 403 corresponds to the energy state of the Si _x Ge _1-x region 105.

As apparent from FIG. 4, the Si _x Ge _1-x region 105 is sandwiched between Si regions 106 having a larger band gap than the Si _x Ge _1-x region. _{The x} Ge _1-x region 105 is moved preferentially.

Both the Si _x Ge _1-x region and the Si region are intrinsic or substantially intrinsic regions. That is, in the N-channel pinning FET, the Si _x Ge _1-x region 105 serving as a channel formation region is configured as an intrinsic or substantially intrinsic region, and electrons move through the region.

  Here, the intrinsic region refers to a region to which an impurity element imparting N-type or P-type and an impurity element such as carbon, nitrogen, or oxygen is not intentionally added. The substantially intrinsic region refers to a region in which the conductivity type is intentionally offset by the addition of a reverse conductivity type impurity or a region having one conductivity type in a range in which the threshold voltage can be controlled.

For example, the dopant concentration (concentration of phosphorus, arsenic, boron, indium, antimony, etc.) is 1 × 10 ¹⁸ atoms / cm ³ or less (preferably 1 × 10 ¹⁷ atoms / cm ³ or less), and carbon, nitrogen, A silicon substrate having an oxygen concentration of 2 × 10 ¹⁸ atoms / cm ³ or less can be said to be substantially intrinsic.

  In that sense, it can be said that all single crystal silicon substrates generally used for semiconductors are substantially intrinsic unless an impurity element imparting one conductivity type is intentionally added in the process.

In addition, the threshold voltage of an N-type or P-type well formed at a concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ atoms / cm ³ as used in a general VLSI process can be controlled. It can be regarded as intrinsic.

  When the region where carriers move is intrinsic or substantially intrinsic, the decrease in mobility due to impurity scattering is extremely small, and high mobility can be obtained. This is a major difference between the present invention and the channel doping method.

In addition, as shown in FIG. 1A, when a linear Si _x Ge _1-x region is provided from the source region to the drain region, an effect that an electron movement path is defined by the Si region can be obtained.

As described above, the energy state of the Si _x Ge _1-x region sandwiched between the Si regions is as shown in FIG. In the configuration shown in FIG. 1A, it is considered that a plurality of slits in an energy state as shown in FIG. 4 are arranged.

FIG. 5 schematically shows this state. In FIG. 5, reference numeral 501 denotes a Si region (pinning region), and 502 _{denotes a} Si _x Ge _1-x region (channel formation region). Reference numeral 503 denotes majority carriers (electrons here). As shown in FIG. 5, the electrons 503 move preferentially in the Si _x Ge _1-x region 502 that is low in energy.

  By defining the movement path of majority carriers in this way, scattering due to self collision between carriers (carrier scattering) is reduced. This greatly contributes to improving the mobility of the FET.

Furthermore, it is known that the carrier mobility is higher when the Si _x Ge _1-x layer is used as a channel formation region than when the Si layer is used as a channel formation region. That is, the present invention uses the Si _x Ge _1-x region as a carrier movement path, and thus has an advantage that higher mobility can be realized than the conventional MOSFET.

  Next, the third effect will be described. The pinning region of the present invention plays a very important role in preventing a decrease in source / drain breakdown voltage due to impact ionization.

  Minority carriers (holes in this case) generated by impact ionization (impact ionization phenomenon) cause conduction of parasitic bipolar transistors, or accumulation near the source to lower the diffusion potential on the source side, etc. Causes the phenomenon.

However, in the case of an N-channel pinning FET having a structure as shown in FIG. 1, the Si _x Ge _1-x region 105 becomes a potential groove for holes (see FIG. 2). The hole moves to the Si _x Ge _1-x region 105.

However, in the upper part of the Si _x Ge _1-x region (particularly near the interface with the gate insulating film), electrons are induced by the gate voltage to form a channel. Holes generated by impact ionization are swept below the channel by the gate voltage, and therefore gather at the bottom of the Si _x Ge _1-x region.

Then, the holes are drawn to the source region side by the potential difference between the source and the drain, flow under the Si _x Ge _1-x region, and reach the source region 101. In this way, the holes drawn to the source region are drawn through the external terminal, so that the outflow or accumulation of holes to the substrate terminal can be prevented.

  In this way, the pinning region of the present invention functions as a path for allowing minority carriers (here, holes) generated by impact ionization to flow in the opposite direction to the majority carriers (here, electrons) and pulling them out as they are. .

  This third effect can prevent a carrier injection-induced breakdown phenomenon due to impact ionization, and thus has a very high breakdown voltage due to a synergistic effect with the first effect (preventing a decrease in breakdown voltage due to punch-through). A highly reliable semiconductor device can be realized.

  Due to the above effects, the pinning TFT of the present invention can simultaneously realize high reliability and high mobility. Although the above description is based on an N-channel FET as an example, a P-channel FET can basically obtain the same effect only by different handling of holes and electrons.

  In the first embodiment, an example in which the present invention is applied to a MOSFET using a bulk single crystal has been described. In addition to this, the present invention can be applied to a thin film transistor (TFT) using a crystalline semiconductor thin film.

  As the crystalline semiconductor thin film, a single crystal semiconductor thin film, a polycrystalline semiconductor thin film, or the like can be used. The single crystal semiconductor thin film can be obtained by using a known technique such as a method using oxygen ion implantation (SIMOX), a method using bonding, an ELTRAN method, or a smart cut method.

  In addition, the polycrystalline semiconductor thin film is a method for crystallizing an amorphous semiconductor thin film using a technique described in JP-A-7-30652, JP-A-9-312260, a technique using laser annealing, etc. It can be obtained using a method of directly forming a film by a CVD method.

  In particular, by utilizing the technique described in Japanese Patent Application Laid-Open No. 9-312260, a silicon thin film called a continuous grain boundary crystalline silicon film (Continuous Grain Silicon: CGS) having excellent crystallinity can be obtained. Since the TFT using this silicon film has electrical characteristics that surpass those of the conventional MOSFET, it can be used as an alternative element of the MOSFET in the LSI technology ahead. Therefore, it can be said that it is very effective to apply the present invention to a TFT using such a silicon film.

  In addition, a crystalline semiconductor thin film formed by any means can be used. Here, a configuration when the present invention is applied to a TFT will be described with reference to FIG.

In FIG. 6, 601 is a source region, 602 is a drain region, 603 is an active region, 604 is a Si _x Ge _1-x region, 605 is a Si region, and 606 is an LDD region. These are formed using a crystalline semiconductor thin film.

  Reference numeral 607 denotes a gate electrode mainly composed of aluminum, 608 denotes an anodic oxide film obtained by anodizing the gate electrode, 609 denotes a source electrode, and 610 denotes a drain electrode. Note that the gate electrode 607 can be formed using tantalum, tungsten, molybdenum, or silicon with conductivity.

  Next, FIG. 6B is a cross-sectional view taken along A-A ′ of FIG. In FIG. 6B, 611 is a substrate having an insulating surface, 612 is a base film, and a crystalline semiconductor thin film is formed thereon. As the substrate 611, a substrate having heat resistance that can withstand the maximum temperature of the process is used. Reference numeral 613 denotes a gate insulating film, and an interlayer insulating film 614 is provided on the gate electrode 607 and the anodic oxide film 608 thereon.

Next, FIG. 6C shows a cross-sectional view of FIG. 6A cut along BB ′. As shown in FIG. 6C, the basic structure of the TFT of the present invention is similar to that of the TFT using the technique described in Japanese Patent Laid-Open No. 7-13518, but Si _x Ge _1-x is formed in the active region 603. The difference is that a region 604 is provided.

  As described above, the present invention is engineering for the active region (directly under the gate electrode) and is not a technology influenced by other TFT structures. That is, the present invention is not limited to the TFT structure shown in FIG. 6, and can be applied to TFTs having any structure.

  The pinning FET shown in the first embodiment or the pinning TFT shown in the second embodiment can easily constitute a CMOS circuit (inverter circuit) by complementary combination of an N-channel type and a P-channel type.

  In that case, pinning FETs having exactly the same structure can be combined in the N-channel type and the P-channel type, but the configuration of the pinning region can be different between the two as shown in this embodiment.

  Here, FIG. 7 is a top view showing only an active region and a source / drain region of a CMOS circuit in which an N-channel pinning FET and a P-channel pinning FET are complementarily combined. Reference numeral 701 denotes a source region of the N-channel pinning FET, 702 denotes the drain region, 704 denotes a source region of the P-channel pinning FET, and 705 denotes the drain region.

FIG. 7 is characterized in that the width of the Si _x Ge _1-x region 705 formed in the P-channel pinning FET is thicker than the width of the Si _x Ge _1-x region 706 formed in the N-channel pinning FET. is there. In other words, the Si region 707 of the P-channel pinning FET is thinner than the Si region 708 formed in the N-channel pinning FET.

  With such a configuration, the N-channel pinning FET has a larger area occupied by the pinning region (Si region) 708, so that the structure is more suitable for suppressing the spread of the depletion layer from the drain side. In other words, the structure emphasizes reliability.

On the other hand, since the area occupied by the channel formation region (Si _x Ge _1-x region) 705 is larger in the P-channel FET, the structure is suitable for increasing the amount of carrier movement or increasing the mobility. . That is, the structure emphasizes the flow of a large current and the high-speed operation.

  Conventionally, in the CMOS circuit, the N-channel type has high mobility but poor reliability in many cases, and conversely the P-channel type has high reliability but often low mobility.

  However, when the structure of the present embodiment is employed, a combination that compensates for the disadvantages of both the N-channel type and the P-channel type is possible by configuring a CMOS circuit with pinning FETs. As a result, it is possible to correct the characteristic difference between the two, and to realize a CMOS circuit with a high characteristic balance and high reliability.

  In this embodiment, an example in which an impurity element for increasing an energy barrier is added to a region functioning as a pinning region in the semiconductor devices described in Embodiments 1 to 3 will be described.

  Specifically, in the case of an N-channel pinning FET, an element selected from group 13 (typically boron, gallium, or indium) is added to a Si region that behaves as a pinning region. In the case of a P-channel pinning FET, an element selected from group 15 (typically phosphorus, arsenic or antimony) is added to the Si region.

  In an N-channel semiconductor device, since majority carriers are electrons, a group 13 element that shifts the band structure in a direction that hinders the movement of electrons is used. In this case, since the group 13 element shifts the threshold voltage in the positive direction, the threshold voltage can be controlled using this.

  On the contrary, in the P-channel type semiconductor device, since the majority carriers are holes, a group 15 element that shifts the band structure in a direction that prevents the movement of holes is used. At this time, since the group 15 element shifts the threshold voltage in the negative direction, the threshold voltage may be controlled using this.

  With such a structure, a region in which carriers move (channel formation region) and a region in which the depletion layer is prevented from spreading (pinning region) are more clearly distinguished. Such addition of impurities may be performed by any one of ion plantation, plasma doping, and laser doping.

  At this time, it is more effective to simultaneously add oxygen to the region to which the group 13 or group 15 element is added. The addition of oxygen increases the breakdown voltage at the junction with the drain region. Further, the addition of oxygen may be performed using any of the above-described addition means by directly using the mask used for adding the group 13 or group 15 element.

  In the present embodiment, a configuration for effectively utilizing the fourth effect described in the first embodiment will be described. The description will be made with reference to FIG. 8 using an N-channel semiconductor device as an example.

In FIG. 8, reference numeral 801 denotes a source region, 802 denotes a drain region, and 803 denotes a Si _x Ge _1-x region (channel formation region). Reference numeral 804 denotes a connection portion (contact hole position) between a source electrode (not shown) and the source region 801.

The fourth effect, that is, the effect of preventing the accumulation of minority carriers (holes) generated by impact ionization is achieved by the generated holes escaping under the Si _x Ge _1-x region 803 to the source region. The

Therefore, direct source electrode (figure Si _x Ge if the _1-x region 803 Oke long formed enough to reach the inside of the connection portion 804, Si _x Ge _1-x region 803 as shown in FIG. 8 (Not shown) is in contact. By doing so, holes that have moved to the source region 801 through the Si _x Ge _1-x region 803 are extracted to the outside by the source electrode.

  The effect of the present embodiment can be obtained in the same manner even in a P-channel type semiconductor device. It is also effective to apply not only to single elements such as FETs and TFTs but also to CMOS circuits.

  However, since the deterioration phenomenon due to impact ionization is unlikely to be a problem in the P-channel type semiconductor device, the configuration of this embodiment may be applied only to the N-channel type semiconductor device.

  In the present embodiment, an example of an active region having a configuration different from that of the first embodiment will be described. The description will be made by taking the N channel type as an example.

  The most important effect of the present invention is to suppress a depletion layer spreading from the drain side toward the source side. In order to obtain the effect, a pinning region for suppressing the depletion layer may be provided somewhere in the active region.

  As such an example, a configuration as shown in FIG. 9 can be considered. In the configuration of FIG. 9, germanium is added to almost the entire surface of the active region, and the Si region 901 is not in contact with the source region 902 and the drain region 903.

  In this case, the depletion layer spreading from the drain side is cut at the Si region 901. Further, since the Si region 901 is not in contact with the junction 904 between the active region and the drain region, electric field concentration does not occur at the junction between the Si region and the drain region, which is effective in improving the breakdown voltage.

In this embodiment, an example in which the structure of the Si _x Ge _1-x region is different from those in the first to sixth embodiments will be described with reference to FIG.

In FIG. 10, 11 is a source region, 12 is a drain region, and 13 is a Si _x Ge _1-x region. In the configuration of FIG. 10, the Si _x Ge _1-x region 13 enters the source region 11 and does not contact the drain region 12.

In such a configuration, electrons drawn from the source region go to the drain region 12 through the Si _x Ge _{1 -x} region 11, but the Si _x Ge _{1 -x} region 13 is interrupted in the middle. From there, the structure reaches the drain region 12 through the Si region 14.

In this case, minority carriers (here, holes) generated by impact ionization fall into the valence band of the Si _x Ge _1-x region 13 and are extracted as they are to the source region 11. When combined with the configuration of the sixth embodiment, a more remarkable effect can be obtained.

  The configuration of this embodiment can achieve the same effect even in a P-channel type semiconductor device. Moreover, the effect of another Example can be added by using in combination with the structure of another Example, and the effect of a present Example can be utilized still more effectively.

  When the CMOS circuit shown in Embodiment 3 is configured, the present invention can be applied to only one of them. For example, in the configuration of FIG. 11A, an N-channel FET uses a conventional FET using channel doping (channel-doped FET), and a P-channel FET uses the pinning FET of the present invention.

  In the configuration shown in FIG. 11A, since a conventional channel dope is used for the N-channel FET, a certain degree of restriction is imposed on mobility. Conversely, P-channel FETs achieve high mobility by pinning. Therefore, the output difference between the characteristics of the N channel type and the P channel type is alleviated, and it becomes easy to construct a CMOS circuit with stable operation.

  Of course, it is possible to adopt a configuration as shown in FIG. In the configuration of FIG. 11B, a pinning FET is used as the N-channel FET, and a conventional FET using channel doping is used as the P-channel FET.

  In this embodiment, the FET is described as an example, but it goes without saying that the same applies to the case where the present invention is applied to a TFT.

  In order to form a more suitable circuit as in the present embodiment, it is necessary to devise a method for mixing the pinning semiconductor device of the present invention and a conventional semiconductor device using channel dope in place.

  The present invention can be applied not only to a top gate type semiconductor device (typically a planar type semiconductor device) but also to a bottom gate type semiconductor device (typically an inverted stagger type semiconductor device).

  Even when the present invention is applied to a bottom gate type semiconductor device, it can be combined with the structure of another embodiment.

  In this example, an example in which an electro-optical device is configured using the pinning TFT of the present invention will be described. An electro-optical device is defined as a device that converts an electrical signal into an optical signal and vice versa.

  Examples of the electro-optical device include an active matrix type liquid crystal display device, an EL (electroluminescence) display device, and an EC (electrochromics) display device. It is also possible to produce an image sensor or CCD.

  FIG. 12 shows an arrangement example of a part of the liquid crystal module (element formation side substrate). 21 is a substrate having an insulating surface, 22 is a pixel matrix circuit, 23 is a source side driving circuit, 24 is a gate side driving circuit, and 25 is a logic circuit.

  The source side drive circuit 23 is mainly composed of a shift register circuit, a sampling circuit, a buffer circuit, and the like. The gate side drive circuit 24 is mainly composed of a shift register circuit, a buffer circuit, and the like. The logic circuit 25 includes various signal processing circuits such as a clock generation circuit, a memory circuit, an arithmetic circuit, and a signal conversion circuit.

  The pinning TFT of the present invention can be applied to all the above circuits. Further, it may be partially adopted depending on the required performance. For example, it is effective to apply a pinning TFT to a circuit (such as a logic circuit or a shift register circuit) that requires high-speed operation characteristics. It is also effective to apply a pinning TFT to a pixel matrix circuit that requires high breakdown voltage characteristics.

  On the other hand, the advantage of using a pinning TFT is not utilized for a circuit that requires a large current, such as a buffer circuit or a sampling circuit. Since the effective channel width of the pinning TFT of the present invention is narrowed by the amount of forming the pinning region, it is difficult to increase the on-current compared to the conventional TFT of the same size.

  Therefore, a conventional TFT using channel dope is used for a circuit that requires a large current, and the pinning TFT of the present invention is used for a circuit that emphasizes high speed operation and high voltage resistance without handling a large current. A system is preferred.

  In this embodiment, an example in which the electro-optical device is configured using the pinning TFT shown in the second embodiment is shown. However, the driving circuit and the logic circuit are assembled using the CMOS circuit shown in the third embodiment as a basic circuit. In addition, the liquid crystal module of this embodiment can be configured by using the pinning FET shown in Embodiment 1.

  The pinning FET or the pinning TFT according to the present invention can construct not only an electro-optical device as shown in the tenth embodiment but also a semiconductor circuit such as VLSI and ULSI. Note that a semiconductor circuit is defined as an electric circuit that controls and converts an electric signal using semiconductor characteristics.

  For example, the present invention can be applied to a microprocessor such as a RISC processor or an ASIC processor integrated on one chip. Further, the present invention can be applied to all integrated circuits using semiconductors from signal processing circuits such as D / A converters to high-frequency circuits for portable devices (mobile phones, PHS, mobile computers).

  FIG. 13 shows an example of a microprocessor. The microprocessor typically includes a CPU core 31, a RAM 32, a clock controller 33, a cache memory 34, a cache controller 35, a serial interface 36, an I / O port 37, and the like.

  Needless to say, the microprocessor illustrated in FIG. 13 is a simplified example, and various circuit designs are performed on an actual microprocessor depending on the application.

  However, it is an IC (Integrated Circuit) 38 that functions as the center of a microprocessor having any function. The IC 38 is a functional circuit in which an integrated circuit formed on the semiconductor chip 39 is protected with ceramic or the like.

  The MOSFETs 40 (N channel type) and 41 (P channel type) having the structure of the present invention constitute the integrated circuit formed on the semiconductor chip 39. Note that power consumption can be suppressed by configuring a basic circuit with a CMOS circuit as a minimum unit.

  The microprocessor shown in this embodiment is mounted on various electronic devices and functions as a central circuit. Typical electronic devices include personal computers, portable information terminal devices, and all other home appliances. Further, a computer for controlling a vehicle (such as an automobile or a train) may be used.

  In addition to this, it is also effective to apply the pinning FET to a circuit using a high frequency, such as an input / output signal control circuit of a cellular phone, specifically an MMIC (microwave module IC).

  Of course, a semiconductor device using a conventional channel dope is used for a portion that needs to handle a large current as in the tenth embodiment, and a pinning semiconductor of the present invention is used for a portion that requires high speed operation performance and high breakdown voltage performance. A configuration using an apparatus is desirable.

  The pinning semiconductor device of the present invention is also effective when a circuit for countermeasures against static electricity is configured by taking advantage of the feature of simultaneously realizing high breakdown voltage and high speed operation.

  As described above, the pinning semiconductor device of the present invention is a semiconductor device that simultaneously satisfies high operating performance and high withstand voltage characteristics (high reliability), and therefore can be applied to any semiconductor circuit.

  Electro-optical devices and semiconductor circuits configured using the pinning semiconductor device of the present invention are used as components of various electronic devices. Note that the electronic device described in this embodiment is defined as a product on which a semiconductor circuit or an electro-optical device is mounted.

  Examples of such electronic devices include a video camera, a still camera, a projector, a head mounted display, a car navigation system, a personal computer, a portable information terminal (mobile computer, mobile phone, etc.), and the like. An example of them is shown in FIG.

  FIG. 14A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, an audio input unit 2003, a display device 2004, operation switches 2005, and an antenna 2006. The present invention can be applied to the audio output unit 2002, the audio output unit 2003, the display device 2004, and the like.

  FIG. 14B illustrates a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102, the audio input unit 2103, the image receiving unit 2106, and the like.

  FIG. 14C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the camera unit 2202, the image receiving unit 2203, the display device 2205, and the like.

  FIG. 14D illustrates a head mounted display which includes a main body 2301, a display device 2302, and a band portion 2303. The present invention can be applied to the display device 2302.

  FIG. 14E illustrates a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be applied to the display device 2403.

  FIG. 14F illustrates a front projector, which includes a main body 2501, a light source 2502, a display device 2503, an optical system 2504, and a screen 2505. The present invention can be applied to the display device 2503.

  As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Further, the present invention can be applied to all products that require the electro-optical device according to the tenth embodiment and the semiconductor circuit according to the eleventh embodiment.

101 source region 102 active region 103 drain region 104 field oxide film 105 Si _x Ge _1-x region 106 Si region 107 LDD region 108 gate electrode 109 source electrode 110 drain electrode 111 single crystal silicon substrate 112 channel stopper 113 gate insulating film 114 interlayer Insulating film 115 sidewall

Claims (12)

A single crystal silicon substrate provided with a source region, a drain region, and an active region;
The active region includes a plurality of Si _x Ge _1-x (0 <X <1) regions and a plurality of Si regions,
The plurality of Si _x Ge _1-x (0 <X <1) regions function as channel forming regions,
The plurality of Si _x Ge _1-x (0 <X <1) regions and the plurality of Si regions are provided approximately parallel to each other and alternately arranged in the channel width direction,
The plurality of Si _x Ge _1-x (0 <X <1) regions are not in contact with the drain region, respectively. Oite to claim 1,
The semiconductor device, wherein the single crystal silicon substrate is an N-type silicon substrate or a P-type silicon substrate. A transistor having a crystalline semiconductor film provided with a source region, a drain region, and an active region over an insulating surface;
The active region includes a plurality of Si _x Ge _1-x (0 <X <1) regions and a plurality of Si regions,
The plurality of Si _x Ge _1-x (0 <X <1) regions function as channel forming regions,
The plurality of Si _x Ge _1-x (0 <X <1) regions and the plurality of Si regions are provided approximately parallel to each other and alternately arranged in the channel width direction,
The plurality of Si _x Ge _1-x (0 <X <1) regions are not in contact with the drain region, respectively. In claim 3 ,
The transistor includes a gate electrode, and a gate insulating film provided between the crystalline semiconductor film and the gate electrode. In claim 3 or claim 4 ,
The semiconductor device, wherein the crystalline semiconductor film is a single crystal semiconductor film. In any one of Claim 3 thru | or 5 ,
The semiconductor device, wherein the crystalline semiconductor film is a polycrystalline semiconductor film. In any one of Claims 3 thru | or 6 ,
The semiconductor device is an N-channel transistor or a P-channel transistor. In any one of Claims 1 thru | or 7 ,
The semiconductor device, wherein the Si region is provided so as to be deeper than a junction depth of the source region and the drain region. In any one of Claims 1 thru | or 8 ,
The Si _x Ge _1-x (0 <X <1) region has a smaller band gap than the Si region. In any one of Claims 1 thru | or 9 ,
Germanium is added to the Si _x Ge _1-x (0 <X <1) region at a concentration of X in a range of 0.05 <X <0.95. An electronic device characterized by using the semiconductor device according to any one of claims 1 to 10. The electronic device according to claim 11 is a mobile phone, a camera, a computer, a display, or a projector.

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