JP5036854B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a random access memory including a memory cell having a magnetic tunnel junction (MTJ).

  An MRAM (Magnetic Random Access Memory) device has attracted attention as a storage device that can store nonvolatile data with low power consumption. An MRAM device is a storage device that performs non-volatile data storage using a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit and allows random access to each of the thin film magnetic bodies.

  In particular, in recent years, it has been announced that the performance of an MRAM device is dramatically improved by using a thin film magnetic material using a magnetic tunnel junction (MTJ) as a memory cell. For MRAM devices with memory cells with magnetic tunnel junctions, see “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, Feb 2000. (hereinafter Non-Patent Document 1) and “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, Feb. 2000. It is disclosed.

  FIG. 23 is a schematic diagram showing a configuration of a memory cell having a magnetic tunnel junction (hereinafter also simply referred to as an MTJ memory cell).

  Referring to FIG. 23, the MTJ memory cell includes a magnetic tunnel junction MTJ whose resistance value changes according to the data level of stored data, and an access transistor ATR. Access transistor ATR is formed of a field effect transistor, and is coupled between magnetic tunnel junction MTJ and ground voltage Vss.

  For MTJ memory cells, write word line WWL for instructing data writing, read word line RWL for instructing data reading, and the level of stored data at the time of data reading and data writing A bit line BL which is a data line for transmitting the electrical signal is disposed.

FIG. 24 is a conceptual diagram illustrating a data read operation from the MTJ memory cell.
Referring to FIG. 24, the magnetic tunnel junction MTJ includes a magnetic layer (hereinafter also simply referred to as a fixed magnetic layer) FL having a fixed magnetic field in a certain direction and a magnetic layer (hereinafter simply referred to as free magnetic layer) having a free magnetic field. VL). A tunnel barrier TB formed of an insulator film is disposed between the fixed magnetic layer FL and the free magnetic layer VL. In the free magnetic layer VL, either one of the magnetic field in the same direction as that of the fixed magnetic layer FL and the magnetic field in a direction different from that of the fixed magnetic layer FL is nonvolatilely written in accordance with the level of stored data.

  At the time of data reading, access transistor ATR is turned on in response to activation of read word line RWL. As a result, a sense current Is supplied as a constant current from a control circuit (not shown) flows through a current path from the bit line BL to the magnetic tunnel junction MTJ to the access transistor ATR to the ground voltage Vss.

  The resistance value of the magnetic tunnel junction MTJ changes according to the relative relationship in the magnetic field direction between the fixed magnetic layer FL and the free magnetic layer VL. Specifically, when the magnetic field direction of the pinned magnetic layer FL and the magnetic field direction written in the free magnetic layer VL are the same, the resistance of the magnetic tunnel junction MTJ is greater than when both magnetic field directions are different. The value becomes smaller.

  Therefore, at the time of data reading, the voltage drop generated at the magnetic tunnel junction MTJ by the sense current Is differs depending on the magnetic field direction stored in the free magnetic layer VL. Thus, if the supply of the sense current Is is started after the bit line BL is once precharged to a high voltage, the level of the data stored in the MTJ memory cell is read by monitoring the voltage level change of the bit line BL. Can do.

FIG. 25 is a conceptual diagram illustrating a data write operation for the MTJ memory cell.
Referring to FIG. 25, at the time of data writing, read word line RWL is inactivated and access transistor ATR is turned off. In this state, a data write current for writing a magnetic field in free magnetic layer VL is supplied to write word line WWL and bit line BL. The magnetic field direction of free magnetic layer VL is determined by a combination of directions of data write currents flowing through write word line WWL and bit line BL, respectively.

  FIG. 26 is a conceptual diagram illustrating the relationship between the direction of the data write current and the magnetic field direction during data writing.

  Referring to FIG. 26, magnetic field Hx indicated by the horizontal axis indicates the direction of magnetic field H (WWL) generated by the data write current flowing through write word line WWL. On the other hand, the magnetic field Hy indicated on the vertical axis indicates the direction of the magnetic field H (BL) generated by the data write current flowing through the bit line BL.

  The magnetic field direction stored in the free magnetic layer VL is newly written only when the sum of the magnetic fields H (WWL) and H (BL) reaches the region outside the asteroid characteristic line shown in the figure. . That is, when a magnetic field corresponding to the region inside the asteroid characteristic line is applied, the magnetic field direction stored in the free magnetic layer VL is not updated.

  Therefore, in order to update the data stored in the magnetic tunnel junction MTJ by the write operation, it is necessary to pass a current through both the write word line WWL and the bit line BL. The magnetic field direction once stored in the magnetic tunnel junction MTJ, that is, the stored data is held in a nonvolatile manner until new data writing is executed.

  Even during the data read operation, sense current Is flows through bit line BL. However, since the sense current Is is generally set to be about 1 to 2 digits smaller than the data write current described above, the stored data in the MTJ memory cell is erroneously read at the time of data reading due to the influence of the sense current Is. The possibility of rewriting is small.

  Non-Patent Documents 1 and 2 described above disclose techniques for constructing an MRAM device which is a random access memory by integrating such MTJ memory cells on a semiconductor substrate.

Roy Scheuerlein and 6 others, “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Using FET Switches and Magnetic Tunnel Junctions in Each Cell Junction and FET Switch in each Cell), (USA), 2000 IEICE International Solid Circuit Conference and Technical Papers TA7.2 (2000 IEEE ISSCC Digest of Technical Papers, TA7.2), p. 128-129 D. Durlam and five others, “Nonvolatile RAM based on Magnetic Tunnel Junction Elements” (USA), 2000 International Solid State Circuit Conference / Technology of the Institute of Electrical and Electronics Engineers, 2000 Proceedings TA7.3 (2000 IEEE ISSCC Digest of Technical Papers, TA7.3), p. 130-131

FIG. 27 is a conceptual diagram showing MTJ memory cells integrated and arranged in a matrix.
Referring to FIG. 27, a highly integrated MRAM device can be realized by arranging MTJ memory cells in a matrix on a semiconductor substrate. FIG. 27 shows a case where MTJ memory cells are arranged in n rows × m columns (n, m: natural numbers).

  As already described, it is necessary to arrange the bit line BL, the write word line WWL, and the read word line RWL for each MTJ memory cell. Therefore, n write word lines WWL1 to WWLn and read word lines RWL1 to RWLn and m bit lines BL1 to BLm are arranged for n × m MTJ memory cells arranged in a matrix. There is a need. As described above, an MTJ memory cell is generally provided with an independent word line corresponding to each of the read operation and the write operation.

FIG. 28 is a structural diagram of an MTJ memory cell arranged on a semiconductor substrate.
Referring to FIG. 28, access transistor ATR is formed in p type region PAR on semiconductor main substrate SUB. Access transistor ATR has source / drain regions 110 and 120 which are n-type regions, and a gate 130. Source / drain region 110 is coupled to ground voltage Vss through a metal wiring formed in first metal wiring layer M1. For the write word line WWL, a metal wiring formed in the second metal wiring layer M2 is used. The bit line BL is provided in the third metal wiring layer M3.

  The magnetic tunnel junction MTJ is disposed between the second metal wiring layer M2 provided with the write word line WWL and the third metal wiring layer M3 provided with the bit line BL. Source / drain region 120 of access transistor ATR is connected to magnetic tunnel junction MTJ through metal film 150 formed in the contact hole, first and second metal wiring layers M1 and M2, and barrier metal 140. Electrically coupled. The barrier metal 140 is a cushioning material provided to electrically couple the magnetic tunnel junction MTJ and the metal wiring.

  As already described, in the MTJ memory cell, the read word line RWL and the write word line WWL are provided as independent wirings. The write word line WWL and the bit line BL need to pass a data write current for generating a magnetic field having a magnitude greater than a predetermined value at the time of data writing. Therefore, the bit line BL and the write word line WWL are formed using metal wiring.

  On the other hand, the read word line RWL is provided to control the gate voltage of the access transistor ATR, and it is not necessary to actively flow a current. Therefore, from the viewpoint of increasing the degree of integration, the read word line RWL is formed using a polysilicon layer or a polycide structure in the same wiring layer as the gate 130 without newly providing an independent metal wiring layer. .

  Thus, when MTJ memory cells are integrated and arranged on a semiconductor substrate, it is necessary to provide one extra wiring layer for the write word line for data writing, which increases the number of metal wiring layers. This has led to an increase in manufacturing cost due to the complicated process steps.

  In addition, since a large number of MTJ memory cells belonging to the same memory cell column are always connected to each of the bit lines BL1 to BLm, the bit line capacity increases. As a result, it is particularly difficult to increase the speed of the data read operation.

  The present invention has been made to solve such problems, and an object of the present invention is to increase the speed of data read operation and reduce the number of wiring layers in an MRAM device having MTJ memory cells. This is to reduce the manufacturing cost.

  One aspect of the present invention is a semiconductor device including a memory array having a plurality of magnetic memory cells arranged in a matrix. Each of the plurality of magnetic memory cells has a resistance value that changes in accordance with the level of stored data to be written when the data write magnetic field applied by the first and second data write currents is larger than a predetermined magnetic field. A memory portion and a memory cell selection gate for allowing a data read current to pass through the memory portion during data reading are included. The semiconductor device is provided corresponding to each row of the magnetic memory cells, and a plurality of selectively activated according to the row selection result in order to flow the first data write current during data writing. Write word lines, a plurality of read word lines provided corresponding to the rows and operating corresponding memory cell selection gates according to the row selection result in data reading, and columns of magnetic memory cells And a plurality of data lines through which the second data write current and the data read current flow respectively at the time of data writing and at the time of data reading. Each of the plurality of data lines is electrically coupled to the storage unit via the memory cell selection gate in the plurality of magnetic memory cells belonging to the corresponding column. 1 voltage is set. The semiconductor device further includes a plurality of first wirings provided corresponding to the rows or columns of the magnetic memory cells for coupling each storage unit with a second voltage lower than the first voltage. In the region where the memory array is formed, the first wiring layer in which the plurality of first wirings are formed is an upper layer than the second wiring layer in which the plurality of data lines are formed.

  Preferably, each of the plurality of first wirings is a reference wiring fixed at the second voltage. Alternatively, preferably, the plurality of first wirings are wirings common to the plurality of write word lines, and each of the plurality of first wirings is fixed to the second voltage during data reading, while the data It functions as each write word line at the time of writing.

  In another aspect of the present invention, the semiconductor device includes a memory array having a plurality of magnetic memory cells arranged in a matrix. Each of the plurality of magnetic memory cells has a resistance value that changes in accordance with the level of stored data to be written when the data write magnetic field applied by the first and second data write currents is larger than a predetermined magnetic field. A memory portion and a memory cell selection gate for allowing a data read current to pass through the memory portion during data reading are included. The semiconductor device is provided corresponding to each row of the magnetic memory cells, and a plurality of selectively activated according to the row selection result in order to flow the first data write current during data writing. Write word lines and a plurality of read word lines provided corresponding to the rows and operating corresponding memory cell selection gates according to the row selection result in data reading, and rows of magnetic memory cells And a plurality of write data lines for flowing a second data write current at the time of data writing, and a plurality of write data lines corresponding to the columns, respectively, for flowing a data read current at the time of data reading And a plurality of read data lines. Each of the plurality of read data lines is electrically coupled to each of the plurality of storage units belonging to the corresponding column via each memory cell selection gate. In the region where the memory array is formed, the plurality of read data lines are formed in a lower wiring layer than the plurality of write data lines.

  According to the present invention, in an MRAM device (semiconductor device) having MTJ memory cells, it is possible to increase the data read operation speed and reduce the manufacturing cost by reducing the number of wiring layers.

It is a schematic block diagram which shows the whole structure of the MRAM device 1 according to Embodiment 1 of this invention. 1 is a block diagram showing a configuration of a memory array 10 according to a first embodiment. 3 is a circuit diagram showing a connection mode of MTJ memory cells according to the first embodiment. FIG. 6 is a timing chart illustrating data writing and data reading with respect to an MTJ memory cell according to the first embodiment. FIG. 4 is a structural diagram illustrating the arrangement of MTJ memory cells according to the first embodiment. FIG. 7 is a block diagram showing a configuration of a memory array 10 according to a modification of the first embodiment. FIG. 11 is a circuit diagram showing a connection mode of MTJ memory cells according to a modification of the first embodiment. FIG. 10 is a structural diagram illustrating an arrangement of MTJ memory cells according to a modification of the first embodiment. FIG. 6 is a block diagram showing a configuration of a memory array 10 according to a second embodiment. FIG. 11 is a circuit diagram showing a connection mode of MTJ memory cells according to the second embodiment. FIG. 11 is a structural diagram illustrating an arrangement of MTJ memory cells according to a second embodiment. FIG. 10 is a block diagram showing a configuration of a memory array 10 according to a modification of the second embodiment. FIG. 11 is a circuit diagram showing a connection mode of MTJ memory cells according to a modification of the second embodiment. FIG. 11 is a structural diagram showing an arrangement of MTJ memory cells according to a modification of the second embodiment. FIG. 7 is a block diagram showing a configuration of a memory array 10 according to a third embodiment. FIG. 11 is a circuit diagram showing a connection mode of MTJ memory cells according to a third embodiment. 12 is a timing chart illustrating a first operation example of data writing and data reading with respect to an MTJ memory cell according to the third embodiment. 11 is a timing chart illustrating a second operation example of data writing and data reading with respect to the MTJ memory cell according to the third embodiment. FIG. 11 is a structural diagram showing an arrangement of MTJ memory cells according to a third embodiment. FIG. 10 is a block diagram showing a configuration of a memory array 10 according to a modification of the third embodiment. FIG. 16 is a circuit diagram showing a connection mode of MTJ memory cells according to a modification of the third embodiment. FIG. 16 is a structural diagram illustrating an arrangement of MTJ memory cells according to a modification of the third embodiment. It is the schematic which shows the structure of the memory cell which has a magnetic tunnel junction part. It is a conceptual diagram explaining the data read-out operation | movement from an MTJ memory cell. It is a conceptual diagram explaining the data write-in operation | movement with respect to an MTJ memory cell. It is a conceptual diagram explaining the relationship between the direction of a data write current at the time of data writing, and a magnetic field direction. It is a conceptual diagram which shows the MTJ memory cell integratedly arranged by the matrix form. 2 is a structural diagram of an MTJ memory cell disposed on a semiconductor substrate. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Embodiment 1]
FIG. 1 is a schematic block diagram showing an overall configuration of an MRAM device 1 according to the first embodiment of the present invention.

  Referring to FIG. 1, MRAM device 1 performs random access in response to external control signal CMD and address signal ADD, and executes input of write data DIN and output of read data DOUT.

  The MRAM device 1 includes a control circuit 5 that controls the overall operation of the MRAM device 1 in response to a control signal CMD, and a memory array 10 having a plurality of MTJ memory cells arranged in a matrix of n rows × m columns. Prepare. Although the configuration of the memory array 10 will be described in detail later, a plurality of write word lines WWL and read word lines RWL are arranged corresponding to the respective MTJ memory cell rows, and a plurality of write word lines WWL are arranged corresponding to the respective MTJ memory cell columns. Bit line BL and reference line SL are arranged.

  The MRAM device 1 further includes a row decoder 20 that performs row selection in the memory array 10 in accordance with the row address RA indicated by the address signal ADD, and a memory in the memory array 10 in accordance with the column address CA indicated by the address signal ADD. A column decoder 25 for performing column selection, a word line driver 30 for selectively activating the read word line RWL and the write word line WWL based on the row selection result of the row decoder 20, and writing at the time of data writing Word line current control circuit 40 for flowing data write current to word line WWL, and read / write control circuits 50 and 60 for flowing data write current and sense current during data reading and data writing With.

  Read / write control circuits 50 and 60 control the voltage level of bit line BL at both ends of memory array 10, and bit data write current and sense current for executing data write and data read, respectively. Flow on line BL.

FIG. 2 is a block diagram showing a configuration of memory array 10 according to the first embodiment.
Referring to FIG. 2, memory array 10 has a plurality of MTJ memory cells MC arranged in n rows × m columns (n, m: natural numbers). In the configuration according to the first embodiment, read word line RWL, write word line WWL, bit line BL, and reference line SL are arranged for each MTJ memory cell MC. Read word line RWL and write word line WWL are arranged along the row direction corresponding to the rows of memory cells, respectively. On the other hand, the bit lines BL and the reference lines SL are arranged along the column direction corresponding to the columns of the memory cells.

  As a result, in the entire memory array 10, read word lines RWL1 to RWLn, write word lines WWL1 to WWLn, bit lines BL1 to BLm, and reference lines SL1 to SLm are provided. In the following, when the write word line, the read word line, the bit line, and the reference wiring are collectively expressed, they are represented using symbols WWL, RWL, BL, and SL, respectively, and a specific write word When a line, a read word line, and a bit line are shown, subscripts are added to these symbols and expressed as RWL1, WWL1.

  Word line current control circuit 40 couples write word lines WWL1 to WWLn to ground voltage Vss. Thereby, when write word line WWL is activated to a selected state (H level, power supply voltage Vcc), data write current Ip can be supplied to each write word line.

FIG. 3 is a circuit diagram showing a connection mode of MTJ memory cells according to the first embodiment.
Referring to FIG. 3, a read word line RWL, a write word line WWL, a bit line BL, and a reference line SL are provided for an MTJ memory cell including a magnetic tunnel junction MTJ and an access transistor ATR.

  The MTJ memory cell includes a magnetic tunnel junction MTJ and an access transistor ATR coupled in series. As already described, a MOS transistor that is a field effect transistor formed on a semiconductor substrate is typically applied to the access transistor ATR.

  Access transistor ATR has its gate coupled to read word line RWL. Access transistor ATR is turned on when read word line RWL is activated to a selected state (H level, power supply voltage Vcc), and electrically couples bit line BL and magnetic tunnel junction MTJ. On the other hand, when read word line RWL is deactivated to a non-selected state (L level, ground voltage Vss), access transistor ATR is turned off to electrically connect bit line BL and magnetic tunnel junction MTJ. Cut off.

  Magnetic tunnel junction MTJ is electrically coupled between reference line SL and access transistor ATR. Reference line SL is coupled to ground voltage Vss. Therefore, in response to turn-on of access transistor ATR, a current path from bit line BL to access transistor ATR to magnetic tunnel junction MTJ to reference line SL is formed. By causing the sense current Is to flow through this current path, a voltage drop corresponding to the stored data level of the magnetic tunnel junction MTJ is generated in the bit line BL.

  The write word line WWL is provided in parallel with the read word line RWL and in proximity to the magnetic tunnel junction MTJ. At the time of data writing, a data write current is supplied to write word line WWL and bit line BL, and the level of data stored in the MTJ memory cell is rewritten by the sum of magnetic fields generated by these data write currents.

  Thus, the read word line RWL and the write word line WWL are arranged in parallel. The bit line BL is arranged in a direction crossing the read word line RWL and the write word line WWL, and the reference line SL is arranged in parallel with the bit line BL.

  FIG. 4 is a timing chart illustrating data writing and data reading with respect to the MTJ memory cell according to the first embodiment.

First, the operation at the time of data writing will be described.
The word line driver 30 drives the voltage of the write word line WWL corresponding to the selected row to the selected state (H level) according to the row selection result of the row decoder 20. In the non-selected row, the voltage level of the write word line WWL remains in the non-selected state (L level).

  Read word line RWL is not activated and maintained in a non-selected state (L level) during data writing. Since each write word line WWL is coupled to the ground voltage Vss by the word line current control circuit 40, the data write current Ip flows through the write word line WWL of the selected row. On the other hand, no current flows through the write word line WWL in the non-selected row.

  Read / write control circuits 50 and 60 generate a data write current in a direction corresponding to the data level of the write data by controlling the voltage of bit line BL at both ends of memory array 10. For example, when the stored data of “1” is written, the bit line voltage on the read / write control circuit 60 side is set to a high voltage state (power supply voltage Vcc) and the read / write control circuit 50 side on the opposite side is set. Is set to a low voltage state (ground voltage Vss). Thereby, data write current + Iw flows through bit line BL in the direction from read / write control circuit 60 toward 50. On the other hand, when the stored data of “0” is written, the bit line voltages on the read / write control circuit 50 side and 60 side are set to the high voltage state (power supply voltage Vcc) and the low voltage state (ground voltage Vss), respectively. Data write current -Iw flows through bit line BL in the direction from read / write control circuit 50 to 60.

  At this time, it is not necessary to pass the data write current ± Iw to each bit line, and the read / write control circuits 50 and 60 can select a part corresponding to the selected column according to the column selection result of the column decoder 25. The voltage of the bit line BL described above may be controlled so that the data write current ± Iw is selectively supplied to the bit line.

  By setting the direction of the data write currents Ip and ± Iw in this way, the data write current in the reverse direction according to the level “1”, “0” of the stored data to be written at the time of data writing By selecting either + Iw or -Iw and fixing the data write current Ip of the write word line WWL in a fixed direction regardless of the data level, the direction of the data write current Ip flowing through the write word line WWL is changed. Since it can always be constant, the configuration of the word line current control circuit 40 can be simplified as described above.

Next, the operation at the time of data reading will be described.
At the time of data reading, word line driver 30 drives read word line RWL corresponding to the selected row to a selected state (H level) according to the row selection result of row decoder 20. In a non-selected row, the voltage level of read word line RWL is maintained in a non-selected state (L level). At the time of data reading, write word line WWL is not activated and is maintained in a non-selected state (L level).

  Before the data read operation, bit line BL is precharged to a high voltage state (power supply voltage Vcc), for example. When data reading is started from this state and read word line RWL is activated to H level in the selected row, corresponding access transistor ATR is turned on.

  Accordingly, in the MTJ memory cell, a current path of the sense current Is is formed between the reference line SL coupled to the ground voltage Vss and the bit line BL via the access transistor ATR. Due to the sense current Is, a different voltage drop occurs in the bit line BL depending on the data level of the storage data of the MTJ memory cell. In FIG. 4, when the data level stored as an example is “1” and the magnetic field directions in the fixed magnetic layer FL and the free magnetic layer VL are the same, the stored data is “1”. The voltage drop ΔV1 of the bit line BL is small, and the voltage drop ΔV2 of the bit line BL when the stored data is “0” is larger than ΔV1. By detecting the difference between these voltage drops ΔV1 and ΔV2, the level of data stored in the MTJ memory cell can be read.

  The voltage level of reference line SL is set to ground voltage Vss at the time of data reading. At the time of data writing, since access transistor ATR is turned off, reference line SL does not particularly affect magnetic tunnel junction MTJ. Therefore, the voltage level of the reference wiring SL may be set to the ground voltage Vss as in the data reading. As a result, reference wiring SL may be coupled to a node supplying ground voltage Vss, for example, in a region in read / write control circuit 50 or 60.

FIG. 5 is a structural diagram illustrating the arrangement of MTJ memory cells according to the first embodiment.
Referring to FIG. 5, access transistor ATR is formed in p type region PAR on semiconductor main substrate SUB. Bit line BL is formed in first metal interconnection layer M1, and is electrically coupled to one source / drain region 110 of access transistor ATR.

  The other source / drain region 120 is magnetically connected via the metal wiring provided in the first metal wiring layer M1 and the second metal wiring layer M2, the metal film 150 formed in the contact hole, and the barrier metal 140. Coupled with the tunnel junction MTJ. The write word line WWL is provided in the second metal wiring layer M2 in the vicinity of the magnetic tunnel junction. Read word line RWL is arranged in the same layer as gate 130 of access transistor ATR.

  The reference wiring SL is arranged in the third metal wiring layer M3 that is an independent metal wiring layer. Reference wiring SL is coupled to a node supplying ground voltage Vss at any node on the semiconductor substrate.

  As a result, in the MTJ memory cell, the magnetic tunnel junction MTJ and the bit line BL are not directly coupled but coupled via the access transistor ATR. As a result, each bit line BL is not directly coupled to a large number of magnetic tunnel junctions MTJ belonging to the corresponding memory cell column, and the corresponding read word line RWL is selected (H level). Only the MTJ memory cells belonging to the activated memory cell row are electrically coupled. In this way, the capacity of the bit line BL can be suppressed, and in particular, the operation at the time of data reading can be speeded up.

[Modification of Embodiment 1]
FIG. 6 is a block diagram showing a configuration of memory array 10 according to the modification of the first embodiment.

  Referring to FIG. 6, in memory array 10 according to the modification of the first embodiment, reference line SL has n reference lines SL1 to SLn corresponding to the memory cell rows as compared with the configuration shown in FIG. Different points are provided. Since other configurations are the same as those described in FIG. 2, detailed description thereof will not be repeated.

  FIG. 7 is a circuit diagram showing a connection mode of MTJ memory cells according to the modification of the first embodiment.

  Referring to FIG. 7, as in the first embodiment, read word line RWL, write word line WWL, bit line BL and reference line SL are arranged corresponding to the MTJ memory cell. Compared to the configuration of the MTJ memory cell described with reference to FIG. 3, in the MTJ memory cell according to the modification of the first embodiment, the reference wiring SL coupled to the magnetic tunnel junction MTJ is connected to the read word line RWL and the write word line. The difference is that it is arranged in parallel with WWL.

  FIG. 8 is a structural diagram illustrating the arrangement of MTJ memory cells according to the modification of the first embodiment.

  Referring to FIG. 8, similarly to the structure according to the first embodiment described in FIG. 5, bit line BL and write word line WWL are provided in first and second metal wiring layers M1 and M2, respectively. In the modification of the first embodiment, the reference wiring SL coupled to the magnetic tunnel junction MTJ is provided in parallel with the read word line RWL and the write word line WWL, so that the same wiring as one of these word lines is provided. It becomes possible to arrange in a layer. FIG. 8 shows an example in which the reference wiring SL is arranged in the second metal wiring layer M2 together with the write word line WWL.

  Thereby, in the MTJ memory cell according to the modification of the first embodiment, the reference wiring SL is not provided without providing a new metal wiring layer (third metal wiring layer M3 in FIG. 5) for arranging the reference wiring SL. Can be placed. As a result, in addition to the high-speed data reading described in the first embodiment, the manufacturing cost can be further reduced by reducing the number of metal wiring layers.

  Note that the MTJ memory cell according to the modification of the first embodiment differs from the MTJ memory cell according to the first embodiment only in the arrangement direction of the reference wiring SL. This can be executed by controlling the voltage and current of the line RWL, the write word line WWL, the read bit line RBL, and the write bit line WBL in the same manner as in FIG.

[Embodiment 2]
FIG. 9 is a block diagram showing a configuration of memory array 10 according to the second embodiment.

  Referring to FIG. 9, memory array 10 has MTJ memory cells arranged in n rows × m columns. A read word line RWL and a write word line WWL are arranged corresponding to each memory cell row, and a bit line BL is arranged corresponding to each memory cell column. Therefore, in the entire memory array 10, read word lines RWL1 to RWLn, write word lines WWL1 to WWLn, and bit lines BL1 to BLm are arranged. Word line current control circuit 40 couples each write word line WWL to ground voltage Vss.

  In the second embodiment, the function of the reference wiring SL that secures the path of the sense current Is by combining the magnetic tunnel junction MTJ with the ground voltage Vss at the time of data reading is shared by the write word line WWL. To reduce

FIG. 10 is a circuit diagram showing a connection mode of MTJ memory cells according to the second embodiment.
Referring to FIG. 10, access transistor ATR is electrically coupled between magnetic tunnel junction MTJ and write word line WWL. Magnetic tunnel junction MTJ is coupled between access transistor ATR and bit line BL. Access transistor ATR has its gate coupled to read word line RWL.

  Write word line WWL is set to ground voltage Vss at the time of data reading. As a result, when read word line RWL is activated to a selected state (H level) during data reading, access transistor ATR is turned on, and bit line BL to magnetic tunnel junction MTJ to access transistor ATR to write word line. A sense current Is can flow through the path of WWL.

  On the other hand, at the time of data writing, the access transistor ATR is turned off and the data write current is supplied to the bit line BL and the write word line WWL to correspond to the level of the stored data written to the magnetic tunnel junction MTJ. A magnetic field can be generated.

FIG. 11 is a structural diagram illustrating the arrangement of MTJ memory cells according to the second embodiment.
Referring to FIG. 11, write word line WWL and bit line BL are arranged in first metal wiring layer M1 and second metal wiring layer M2, respectively. Read word line RWL is arranged in the same layer as gate 130 of access transistor ATR.

  By setting the write word line WWL to the ground voltage Vss at the time of data reading, MTJ memory cells can be arranged by the two metal wiring layers M1 and M2 without providing the reference wiring SL. As a result, the number of metal wiring layers can be reduced and the manufacturing cost can be reduced.

  Next, data reading and data writing operations for the MTJ memory cell according to the second embodiment will be described.

  Referring to FIG. 4 again, at the time of data reading, write word line WWL is maintained in a non-selected state (L level). Since each write word line WWL is coupled to the ground voltage Vss by the word line current control circuit 40, the voltage level of the write word line WWL is the ground voltage Vss in the same manner as the voltage level of the reference wiring SL at the time of data reading. On the other hand, during data writing, no current flows through the reference line SL, and no magnetic field is generated for the MTJ memory cell.

  Therefore, even if reference wiring SL is omitted, the voltage and current of write word line WWL, read word line RWL and bit line BL are set in the same manner as in FIG. Thus, data reading and data writing operations can be executed.

[Modification of Embodiment 2]
FIG. 12 is a block diagram showing a configuration of memory array 10 according to the modification of the second embodiment.

  Referring to FIG. 12, also in the modification of the second embodiment, read word line RWL and write word line WWL are provided corresponding to each row of MTJ memory cells arranged in n rows × m columns. In contrast, bit line BL is arranged. Therefore, read word lines RWL1 to RWLn, write word lines WWL1 to WWLn, and bit lines BL1 to BLm are provided for the entire memory array 10. Word line current control circuit 40 couples each write word line WWL to ground voltage Vss.

  FIG. 13 is a circuit diagram showing a connection mode of MTJ memory cells according to the modification of the second embodiment.

  Referring to FIG. 13, bit line BL is electrically coupled to magnetic tunnel junction MTJ through access transistor ATR. Magnetic tunnel junction MTJ is coupled between write word line WWL and access transistor ATR. Read word line RWL is coupled to the gate of access transistor ATR. The read word line RWL and the write word line WWL are arranged in parallel, and the bit line BL is arranged in a direction intersecting with these word lines.

FIG. 14 is a structural diagram showing an arrangement of MTJ memory cells according to the modification of the second embodiment.
Referring to FIG. 14, bit line BL and write word line WWL are arranged in first metal wiring layer M1 and second metal wiring layer M2, respectively. Read word line RWL is arranged in the same layer as gate 130 of access transistor ATR. Magnetic tunnel junction MTJ is directly coupled to write word line WWL2. As a result, the interval between the write word line WWL and the magnetic tunnel junction MTJ can be narrowed, so that the magnetic coupling between the two can be set large during data writing. As a result, the data write current Ip flowing through the write word line can be reduced, and the generation of magnetic noise can be suppressed.

  Since the voltage and current settings of write word line WWL, read word line RWL, and bit line BL at the time of data writing and data reading are the same as in the second embodiment, detailed description will not be repeated. . Thus, also in the configuration according to the modification of the second embodiment, the MTJ memory cell can be arranged using the two metal wiring layers M1 and M2 without the reference wiring SL.

  Further, since the bit line BL is coupled to the magnetic tunnel junction MTJ via the access transistor ATR, each bit line BL is a target of data reading, that is, the corresponding read word line RWL is Only the MTJ memory cells belonging to the memory cell row activated in the selected state (H level) are electrically coupled. As a result, similar to the first embodiment, the capacity of the bit line BL can be suppressed, and the operation at the time of data reading can be speeded up.

[Embodiment 3]
FIG. 15 is a block diagram showing a configuration of memory array 10 according to the third embodiment.

  Referring to FIG. 15, in the third embodiment, read word line RWL and write word line WWL are provided corresponding to each row of MTJ memory cells arranged in n rows × m columns. On the other hand, the bit line is divided into a read bit line RBL used for data reading and a write bit line WBL used for data writing, and is arranged corresponding to each memory cell column. Therefore, read word lines RWL1 to RWLn, write word lines WWL1 to WWLn, read bit lines RBL1 to RBLm, and write bit lines WBL1 to WBLm are provided for the entire memory array 10.

  Note that the write bit line and the read bit line are also expressed using the symbols WBL and RBL, respectively, when collectively expressed, and when a specific write bit line and a read bit line are indicated, A suffix is added to the reference numeral, and it is expressed as WBL1, RBL1.

  Word line current control circuit 40 couples each write word line WWL to ground voltage Vss. Read / write control circuits 50 and 60 control the voltages across read bit line RBL and write bit line WBL.

FIG. 16 is a circuit diagram showing a connection mode of MTJ memory cells according to the third embodiment.
Referring to FIG. 16, access transistor ATR is electrically coupled between magnetic tunnel junction MTJ and read bit line RBL. That is, read bit line RBL is electrically coupled to magnetic tunnel junction MTJ through access transistor ATR.

  Magnetic tunnel junction MTJ is coupled to access transistor ATR and write bit line WBL. The read word line RWL and the write word line WWL are provided in directions intersecting with the read bit line RBL and the write bit line WBL, respectively. Read word line RWL is coupled to the gate of access transistor ATR.

  FIG. 17 is a timing chart illustrating a first operation example of data writing and data reading with respect to the MTJ memory cell according to the third embodiment.

First, the operation at the time of data writing will be described.
The word line driver 30 drives the voltage of the write word line WWL corresponding to the selected row to the selected state (H level) according to the row selection result of the row decoder 20. In the non-selected row, the voltage level of the write word line WWL remains in the non-selected state (L level). Since each write word line WWL is coupled to the ground voltage Vss by the word line current control circuit 40, the data write current Ip flows through the write word line WWL in the selected row.

  Write bit line WBL is controlled in the same manner as the voltage of bit line BL at the time of data writing described with reference to FIG. 4 from a state precharged to L level (ground voltage) before data writing. Thereby, data write current ± Iw corresponding to the data level of the stored data to be written can be supplied to write bit line WBL. As a result, data writing can be performed on the MTJ memory cell as in the case of FIG.

  On the other hand, read word line RWL is maintained in a non-selected state (L level) during data writing. Read bit line RBL is precharged to a high voltage state (Vcc). Since access transistor ATR maintains a turn-off state, no current flows through read bit line RBL during data writing.

Next, the operation at the time of data reading will be described.
At the time of data reading, write word line WWL is maintained in a non-selected state (L level), and its voltage level is fixed to ground voltage Vss by word line current control circuit 40.

  The word line driver 30 drives the read word line RWL corresponding to the selected row to the selected state (H level) according to the row selection result of the row decoder 20. In the non-selected row, the voltage level of the read word line RWL remains in the non-selected state (L level). Read bit line RBL is precharged to a high voltage state (Vcc) before data reading.

  Read / write control circuits 50 and 60 set write bit line WBL to ground voltage Vss and supply a certain amount of sense current Is for reading data to read bit line RBL during data reading. .

  In this state, by turning on the access transistor ATR in response to the activation of the read word line RWL, a current path of the sense current Is is formed in the MTJ memory cell. As a result, a voltage drop corresponding to the stored data appears on the read bit line RBL. As a result, a data read operation similar to that shown in FIG. 4 can be executed.

  As described above, since the voltage of read bit line RBL other than at the time of data reading including the time of data writing matches the precharge voltage at the time of data reading (power supply voltage Vcc in the example of FIG. 17), data There is no need to start a new precharge operation before reading. Therefore, the precharge operation can be made efficient, and the data reading can be speeded up.

  Similarly, by making the voltage of the write bit line WBL other than at the time of data writing coincide with the voltage (ground voltage Vss in the example of FIG. 17) set to form the sense current path at the time of data reading, Since it is not necessary to change the voltage of write bit line WBL at the time of data reading, data reading can be speeded up.

  FIG. 18 is a timing chart illustrating a second operation example of data writing and data reading with respect to the MTJ memory cell according to the third embodiment.

  In FIG. 18, the precharge voltage of read bit line RBL and the voltage of write bit line WBL other than during data writing are set to ground voltage Vss and power supply voltage Vcc, respectively. That is, the precharge voltage of the read bit line RBL and the voltage of the write bit line WBL other than at the time of data writing are set interchangeably with the case of FIG.

  The voltage and current waveforms in other parts in FIG. 18 are the same as those in FIG. 17, and therefore detailed description will not be repeated. Even with such voltage setting, the current path of the sense current Is can be formed in the MTJ memory cell in response to the turn-on of the access transistor ATR during data reading.

  Therefore, the polarity of the voltage change that occurs in read bit line RBL at the time of data reading is opposite to that in FIG. 17, but it is possible to execute the data reading operation and data writing operation.

  Similarly to the case of FIG. 17, since it is not necessary to perform the precharge operation of read bit line RBL and the voltage change of write bit line WBL before data reading, the data reading speed can be increased.

FIG. 19 is a structural diagram showing an arrangement of MTJ memory cells according to the third embodiment.
Referring to FIG. 19, read bit line RBL is formed in first metal interconnection layer M1 and coupled to source / drain region 110 of access transistor ATR. The write word line WWL is arranged in the second metal wiring layer M2. The write bit line WBL is coupled to the magnetic tunnel junction MTJ and formed in the third metal wiring layer M3. The MTJ memory cell is coupled to the source / drain region 120 of the access transistor ATR via the first and second metal wiring layers M1, M2, the metal film 150, and the barrier metal 140.

  Thus, the read bit line RBL is not directly coupled to the magnetic tunnel junction MTJ, but can be connected only to the magnetic tunnel junction MTJ of the MTJ memory cell that is the target of data reading via the access transistor ATR. . As a result, the capacity of the read bit line RBL can be suppressed, and the operation at the time of data reading can be speeded up.

  Further, since the interval between the write bit line WBL and the magnetic tunnel junction MTJ can be narrowed, the data that flows through the write bit line WBL at the time of data writing by setting a large magnetic coupling at the time of data writing. The current value of the write current ± Iw can be reduced. As a result, the magnetic noise can be further suppressed.

[Modification of Embodiment 3]
FIG. 20 is a block diagram showing a configuration of memory array 10 according to the modification of the third embodiment.

  Referring to FIG. 20, also in the modification of the third embodiment, the bit line is divided into write bit line WBL and read bit line RBL, and read bit lines RBL1 to RBL1 corresponding to the respective columns of MTJ memory cells. RBLm and write bit lines WBL1 to WBLm are arranged. Read word lines RWL1 to RWLn and write word lines WWL1 to WWLn are arranged corresponding to the respective rows of MTJ memory cells. In the modification of the third embodiment, the connection mode in each MTJ memory cell is different from that in the third embodiment.

  FIG. 21 is a circuit diagram showing a connection mode of MTJ memory cells according to the modification of the third embodiment.

  Referring to FIG. 21, in the MTJ memory cell according to the modification of the third embodiment, access transistor ATR is electrically coupled between read bit line RBL and magnetic tunnel junction MTJ. Magnetic tunnel junction MTJ is coupled between access transistor ATR and write word line WWL. Access transistor ATR has its gate coupled to read word line RWL.

  As described with reference to FIG. 17, since the voltage level of write word line WWL at the time of data reading is set to ground voltage Vss, write word line WWL is coupled to magnetic tunnel junction MTJ instead of write bit line WBL. Can do. Thus, at the time of data reading, in response to activation of read word line RWL, access transistor ATR is turned on, and between read bit line RBL-access transistor ATR-magnetic tunnel junction MTJ-write word line WWL. A current path for the sense current Is can be formed. Thereby, a voltage drop corresponding to the data stored in the magnetic tunnel junction MTJ can be generated in the read bit line RBL.

  On the other hand, at the time of data writing, magnetic field perpendicular to each other can be generated at magnetic tunnel junction MTJ by the data write currents flowing through write word line WWL and write bit line WBL.

  Therefore, in the data write and data read operations for the MTJ memory cell according to the modification of the third embodiment, the voltages and currents of read word line RWL, write word line WWL, read bit line RBL and write bit line WBL are set as shown in FIG. It can be executed by setting the same as in FIG.

  FIG. 22 is a structural diagram illustrating the arrangement of MTJ memory cells according to a modification of the third embodiment.

  Referring to FIG. 22, in the modification of the third embodiment, since write bit line WBL does not need to be coupled to other wiring or MTJ memory cells, the magnetic coupling with magnetic tunnel junction MTJ is improved. Can be arranged freely with priority. Write bit line WBL is arranged directly below magnetic tunnel junction MTJ using second metal interconnection layer M2, for example, as shown in FIG.

  The write word line WWL is electrically coupled to the magnetic tunnel junction MTJ and disposed in the third metal wiring layer M3. Arrangement of read word line RWL, access transistor ATR and read bit line RBL is the same as in FIG. 19, and therefore description thereof will not be repeated.

  With such a configuration, the read bit line RBL is coupled to the magnetic tunnel junction MTJ via the access transistor ATR. Therefore, the read bit line RBL is directly connected to a number of magnetic tunnel junctions MTJ belonging to the same memory cell column. The capacity of the read bit line RBL can be suppressed without connection. As a result, the data reading operation can be speeded up.

  Further, since the interval between the magnetic tunnel junction MTJ and the write word line WWL can be narrowed, the magnetic coupling at the time of data writing can be increased, and the amount of data write current Ip of the write word line WWL can be reduced. Can be set. By suppressing the amount of data write current flowing through the write word line WWL and the write bit line WBL, magnetic noise can be further suppressed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  10 memory array, 20 row decoder, 25 column decoder, 30 word line driver, 40 word line current control circuit, 50, 60 read / write control circuit, ATR access transistor, BL bit line, FL free magnetic layer, MTJ magnetic tunnel Junction, RBL read bit line, RWL read word line, TB tunnel barrier, VL pinned magnetic layer, WBL write bit line, WWL write word line.

Claims (4)

A semiconductor device,
A memory array having a plurality of magnetic memory cells arranged in a matrix;
Each of the plurality of magnetic memory cells includes:
A storage unit whose resistance value changes according to the level of stored data to be written when the data write magnetic field applied by the first and second data write currents is larger than a predetermined magnetic field;
A memory cell selection gate for allowing a data read current to pass through the storage unit during data read,
A plurality of writes provided corresponding to the rows of the magnetic memory cells and selectively activated in accordance with a row selection result in order to flow the first data write current during data writing A word line,
A plurality of read word lines, each provided corresponding to the row, for operating the memory cell selection gate corresponding to a row selection result in data reading;
A plurality of data lines provided corresponding to the columns of the magnetic memory cells, respectively, for flowing the second data write current and the data read current at the time of data writing and at the time of data reading, respectively. And further comprising
Each of the plurality of data lines is electrically coupled to the storage unit via the memory cell selection gate in the plurality of magnetic memory cells belonging to the corresponding column,
The plurality of data lines are set to a first voltage before execution of the data reading,
The semiconductor device includes:
A plurality of first wirings respectively provided corresponding to the rows or the columns of the magnetic memory cells for coupling each storage unit with a second voltage lower than the first voltage. ,
In the region where the memory array is formed, the first wiring layer in which the plurality of first wirings are formed is an upper layer than the second wiring layer in which the plurality of data lines are formed. apparatus.   2. The semiconductor device according to claim 1, wherein each of the plurality of first wirings is a reference wiring fixed to the second voltage. The plurality of first wirings are wirings common to the plurality of write word lines,
2. The semiconductor device according to claim 1, wherein each of the plurality of first wirings is fixed to the second voltage at the time of data reading, and functions as the write word line at the time of data writing. A semiconductor device,
A memory array having a plurality of magnetic memory cells arranged in a matrix;
Each of the plurality of magnetic memory cells includes:
A storage unit whose resistance value changes according to the level of stored data to be written when the data write magnetic field applied by the first and second data write currents is larger than a predetermined magnetic field;
A memory cell selection gate for allowing a data read current to pass through the storage unit during data read,
The semiconductor device includes:
A plurality of writes provided corresponding to the rows of the magnetic memory cells and selectively activated in accordance with a row selection result in order to flow the first data write current during data writing A word line,
A plurality of read word lines, each provided corresponding to the row, for operating the memory cell selection gate corresponding to a row selection result in the data read;
A plurality of write data lines provided corresponding to the columns of the magnetic memory cells, respectively, for flowing the second data write current during the data write;
A plurality of read data lines provided corresponding to the columns, respectively, for flowing the data read current during the data read;
Each of the plurality of read data lines is electrically coupled to each of the plurality of storage units belonging to the corresponding column via each memory cell selection gate,
The semiconductor device, wherein in the region where the memory array is formed, the plurality of read data lines are formed in a lower wiring layer than the plurality of write data lines.

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