JP5029564B2 - Multilayer capacitor - Google Patents

Description

  The present invention relates to a multilayer capacitor, and more particularly to an improvement for facilitating control of an equivalent series resistance (ESR) of the multilayer capacitor.

  In a power supply circuit, if the voltage fluctuation in the power supply line increases due to the impedance existing in the power supply line or ground, the operation of the driving circuit becomes unstable or interference between the circuits occurs via the power supply circuit. Cause oscillation. Therefore, normally, a decoupling capacitor is connected between the power supply line and the ground. The decoupling capacitor reduces the impedance between the power supply line and the ground, and plays the role of suppressing fluctuations in the power supply voltage and interference between circuits.

  In recent years, in communication devices such as mobile phones and information processing devices such as personal computers, the speed of signals has been increased in order to process a large amount of information, and the clock frequency of ICs used has been increased. Yes. For this reason, noise containing a large amount of harmonic components is likely to occur, and it is necessary to perform stronger decoupling in the IC power supply circuit.

  In order to enhance the decoupling effect, it is effective to use a decoupling capacitor having excellent impedance frequency characteristics, and examples of such a decoupling capacitor include a multilayer ceramic capacitor. Since the multilayer ceramic capacitor has a small ESL (equivalent series inductance), it has an excellent noise absorption effect over a wide frequency band as compared with an electrolytic capacitor.

  Another role of the decoupling capacitor is to supply charges to the IC. Usually, the decoupling capacitor is disposed in the vicinity of the IC, and when voltage fluctuation occurs in the power supply line, electric charges are rapidly supplied from the decoupling capacitor to the IC, thereby preventing the rise of the IC from being delayed.

  When the capacitor is charged / discharged, a back electromotive force dV represented by the equation: dV = L · di / dt is generated in the capacitor. If dV is large, the supply of charge to the IC is delayed. As the clock frequency of the IC increases, the current fluctuation amount di / dt per unit time tends to increase. That is, in order to reduce dV, it is necessary to reduce inductance L. For this reason, it is desired to further reduce the ESL of the capacitor.

  As a low ESL type multilayer ceramic capacitor with further reduced ESL, for example, an LW reverse type multilayer ceramic capacitor is known. In a typical multilayer ceramic capacitor, the length dimension (W dimension) of the end face of the capacitor body on which the external terminal electrodes are formed is the dimension in the length direction (L dimension) of the side surface adjacent to the end face of the capacitor body. Although smaller, in the LW reverse type multilayer ceramic capacitor, the dimension in the length direction (W dimension) of the end surface on which the external terminal electrode is formed is larger than the dimension in the length direction of the side surface (L dimension). . In such an LW reverse type multilayer ceramic capacitor, the ESL is reduced by widening and shortening the current path inside the capacitor body.

  However, in the low ESL type multilayer ceramic capacitor, since the current path is wide and short as described above, the ESR is reduced accordingly.

  In addition, the multilayer ceramic capacitor is required to have a large capacity. In order to increase the capacity of the multilayer ceramic capacitor, it is conceivable to increase the number of laminated ceramic layers and internal electrodes. In this case as well, the ESR is reduced by increasing the number of current paths. That is, in response to the demand for lower ESL and larger capacity, the ESR of multilayer ceramic capacitors tends to further decrease.

  However, it is known that when the ESR of the capacitor becomes too low, impedance mismatch occurs in the circuit, and a damped oscillation called “ringing” that distorts the rising of the signal waveform is likely to occur. When ringing occurs, the IC may malfunction due to a disturbed signal.

  Further, if the ESR of the capacitor becomes too low, the impedance frequency characteristic of the capacitor becomes too steep near the resonance frequency. As a result, the antiresonance point generated between the resonance frequency of another capacitor mounted in the vicinity becomes large, and the noise absorption effect in the frequency band near the antiresonance point may be reduced.

  In order to prevent a phenomenon which is not preferable in the circuit design as described above, it is effective to connect a resistance element in series with the line and dare to dull the waveform of the impedance frequency characteristic. In recent years, it has been proposed that the capacitor itself has a resistance component, and means for controlling the ESR of the capacitor has attracted attention.

  For example, Patent Documents 1 and 2 propose controlling ESR by including a resistance component in an external terminal electrode that is electrically connected to an internal electrode. In particular, in Patent Document 2, an external terminal electrode containing a resistance component is formed by baking the resistor paste applied on the capacitor body by immersing the capacitor body in a resistor paste containing a resistance material such as ITO. Multilayer ceramic capacitors are described.

  As described in Patent Documents 1 and 2, when the resistance component is included in the external terminal electrode, in order to control the ESR of the capacitor, the specific resistance of the resistance material is adjusted, or the coating thickness of the resistance paste is adjusted. A means such as can be considered.

  However, it is troublesome to prepare several types of resistance paste in order to adjust the specific resistance of the resistance material. Further, if the composition of the resistance paste is changed in order to adjust the specific resistance, other factors such as reactivity with the internal electrode and adhesion to the capacitor body may be affected.

Moreover, in order to adjust the application thickness of the resistance paste, it is necessary to adjust the viscosity of the resistance paste. In this case, as a result of changing the composition of the resistance paste, other factors may be affected. Furthermore, since there is a technical limit in thickening the resistance paste, there is a problem that control is particularly restricted in the direction of increasing ESR.
JP 2004-47983 A International Publication No. 2006/022258 Pamphlet

  Accordingly, an object of the present invention is to provide a multilayer capacitor that has low ESL and can easily perform ESR control at low cost and in a simple manner.

The multilayer capacitor in accordance with the inventions have made multilayer structure with a plurality of dielectric layers stacked, and opposite to each other extend in a plane direction of the first and second main surfaces and the dielectric layer facing each other And a capacitor body having a rectangular parallelepiped shape having first and second side surfaces and first and second end surfaces facing each other. A first external terminal electrode is formed on at least the second main surface and the first end surface of the capacitor body, and a first external terminal is formed on at least the second main surface and the second end surface of the capacitor body. in the terminal electrodes and the electrically insulated state, the second external terminal electrodes are formed.

  The capacitor body includes a first capacitor portion and a second capacitor portion that are arranged along the stacking direction of the dielectric layers. The first capacitor portion is provided with first and second internal electrodes facing each other with a predetermined dielectric layer so as to form a capacitance. The second capacitor portion has a capacitance. Third and fourth internal electrodes are provided opposite to each other with a predetermined dielectric layer formed therebetween.

The first internal electrode has a first capacitor portion and a first lead portion that is drawn from the first capacitor portion to at least the first end face and is electrically connected to the first external terminal electrode. The second internal electrode is drawn to at least the second end face from the second capacitor portion and the second capacitor portion facing the first capacitor portion via a predetermined dielectric layer, and is connected to the second external terminal. And a second lead portion electrically connected to the electrode.

The third internal electrode has a third capacitor portion and a third lead portion that is drawn from the third capacitor portion to the second main surface and is electrically connected to the first external terminal electrode. The fourth internal electrode is led to the second main surface from the fourth capacitor portion and the fourth capacitor portion facing the third capacitor portion via a predetermined dielectric layer, and is connected to the second external terminal. And a fourth lead portion electrically connected to the electrode.

In the product layer capacitors that have a such a configuration, in the present invention, to solve the technical problems described above, when compared with the same direction, the third lead portion, compared to the first lead-out portion It has a narrow part, and the 4th drawer part is characterized by having a narrow part compared with the 2nd drawer part .

The multilayer capacitor according to the present invention is preferably mounted with the second main surface facing the mounting surface.

In the multilayer capacitor in accordance with the present invention, the first external terminal electrode further has a portion formed on the first main surface, and faces the third lead portion on the same surface as the third internal electrode. A dummy electrode is further formed at a position where the dummy electrode is exposed to the first main surface and joined to the first external terminal electrode, while the second external terminal electrode is formed on the first main surface. And is exposed to the first main surface and joined to the second external terminal electrode at a position facing the fourth lead portion on the same plane as the fourth internal electrode. It is preferable that a dummy electrode is further formed.

  In the second capacitor unit, a plurality of third internal electrodes may be continuously arranged in the stacking direction.

  In the capacitor body, it is preferable that the second capacitor portion is sandwiched between the two first capacitor portions.

  According to the present invention, the third lead portion of the third internal electrode has a narrower portion than the first lead portion of the first internal electrode. The ESR per layer is higher than the ESR per layer in the first capacitor unit. Further, in the first capacitor unit, since the current path from the internal electrode to the external terminal electrode is more dispersed than in the second capacitor unit, the ESL of the first capacitor unit is relatively low. Thus, the resonance frequency becomes relatively high.

  From these facts, the characteristics of the multilayer capacitor according to the present invention are a combination of the low ESL characteristic of the first capacitor part and the high ESR characteristic of the second capacitor part. In addition, a multilayer capacitor having a high ESR can be obtained. Further, by changing the ratio of the width of the lead portion between the first capacitor portion and the second capacitor portion or the ratio of the number of stacked internal electrodes, the resonance point position and ESR can be easily controlled. it can.

According to the invention, also the second lead portion and a fourth lead portion, the lead portion of the fourth is, since it is to have a narrow portion as compared to the second lead portion, the capacitor body Since the balance of the arrangement of the lead portions inside can be made favorable, the laminated state of the capacitor body can be made stable.

  As a result of having a narrow portion in the second capacitor portion, when the width direction dimension of the exposed third lead portion becomes relatively short, the third internal electrode is connected to the first external terminal electrode. Since the contact area is relatively small, a good contact state cannot be obtained with the first external terminal electrode, and the capacity of the entire multilayer capacitor may be reduced. In such a case, when a plurality of third internal electrodes are continuously arranged in the stacking direction in the second capacitor unit, the third internal electrode is connected to the first external terminal electrode. Even when contact failure occurs between them, the remaining third internal electrode backs up to form a capacitance, so that a capacitance that does not deviate much from the design capacitance can be obtained.

Oite this inventions, the lead portion of the third lead portion and a fourth is under drawn to the second main surface, is mounted with its second major surface to the mounting surface side, a second capacitor It is possible to make the configuration effective when it is desired to lower the ESL of the multilayer capacitor as a whole while the portion functions as a high ESR portion.

A first reference example of interest to the present invention will be described with reference to FIGS. Tenth reference example to second without this first reference example as well as later, although outside the scope of the invention, and serves as a reference for understanding the present invention.

First, FIG. 1 is a perspective view showing an appearance of a multilayer capacitor 1 as a first reference example . The multilayer capacitor 1 has first and second main surfaces 2 and 3 facing each other, first and second side surfaces 4 and 5 facing each other, and first and second end surfaces 6 and 7 facing each other. A capacitor main body 8 having a rectangular parallelepiped shape is provided. The multilayer capacitor 1 is a so-called LW reverse type, and the longitudinal dimension Le of each of the first and second end faces 6 and 7 is the longitudinal dimension of each of the first and second side faces 6 and 7. Longer than Ls.

First and second external terminal electrodes 9 and 10 are formed on the first and second end faces 6 and 7 of the capacitor body 8, respectively. In this reference example , the first and second external terminal electrodes 9 and 10 extend to part of the first and second main surfaces 2 and 3 and the first and second side surfaces 4 and 5. Is formed.

  The capacitor body 8 has a laminated structure constituted by a plurality of laminated dielectric layers 11 (see FIGS. 3 and 4). The main surfaces 2 and 3 described above extend in the surface direction of the dielectric layer 11.

  FIG. 2 is a block diagram showing the arrangement state of the first and second capacitor portions 12 and 13 configured in the capacitor body 8 together with the mounting substrate 14 with a cross section taken along line AA in FIG. As shown in FIG. 2, the capacitor body 8 includes two first capacitors 12 and one second capacitor 13, and two second capacitors 13 are arranged along the stacking direction of the dielectric layers 11. The first capacitor portion 12 is arranged so that the second capacitor portion 13 is sandwiched between them. Further, at both ends in the stacking direction of the capacitor main body 8, the outer layer portion 15 that does not contribute to the capacitance formation is provided with no internal electrode.

  As shown in FIG. 2, the multilayer capacitor 1 is mounted with the second main surface 3 of the capacitor body 8 facing the mounting surface 16 provided by the surface of the mounting substrate 14. The first capacitor unit 12 is disposed closer to the mounting surface 16 than the second capacitor unit 13. Although not shown, the same applies when the multilayer capacitor 1 is mounted with the first main surface 2 of the capacitor body 8 facing the mounting surface 16 side.

  In order to realize a preferable configuration in which the second capacitor unit 13 is sandwiched between the two first capacitor units 12, in FIG. 2, one second capacitor unit is formed by the two first capacitors 12. 13 is arranged so that the first capacitor portion 12 is disposed at both ends in the stacking direction, but the first capacitor portion 12 is added to the first capacitor portion 13 in the intermediate portion in the stacking direction in addition to the second capacitor portion 13. Even if the capacitor unit 12 is disposed, two or more second capacitor units 13 may be disposed.

  As shown in FIG. 3, the first capacitor unit 12 is provided with first and second internal electrodes 17 and 18. The first and second internal electrodes 17 and 18 are opposed to each other through a predetermined dielectric layer 11 so as to form a capacitance. As shown in FIG. 4, the second capacitor unit 13 is provided with third and fourth internal electrodes 19 and 20. The third and fourth internal electrodes 19 and 20 are alternately arranged one by one in the stacking direction, and face each other with a predetermined dielectric layer 11 so as to form a capacitance.

  As shown in FIG. 3 (1), the first internal electrode 17 is drawn out from the first capacitor portion 21 and the first capacitor portion 21 to the first end face 6 and is electrically connected to the first external terminal electrode 9. And a first drawer portion 22 connected to each other. As shown in FIG. 3B, the second internal electrode 18 includes a second capacitor 23 and a second capacitor 23 that face the first capacitor 21 with a predetermined dielectric layer 11 interposed therebetween. The second lead portion 24 is drawn to the second end face 7 and electrically connected to the second external terminal electrode 10.

  As shown in FIG. 4 (1), the third internal electrode 19 is drawn from the third capacitor 25 and the third capacitor 25 to the first end face 6 and is electrically connected to the first external terminal electrode 9. And a third drawer portion 26 connected to each other. As shown in FIG. 4B, the fourth internal electrode 20 includes a fourth capacitor portion 27 and a fourth capacitor portion 27 that face the third capacitor portion 25 with a predetermined dielectric layer 11 interposed therebetween. A fourth lead portion 28 is provided on the second end face 7 and is electrically connected to the second external terminal electrode 10.

  The third and fourth lead portions 26 and 28 have narrower portions than the first and second lead portions 22 and 24, respectively. More specifically, the third and fourth lead portions 26 and 28 are generally shorter in the width direction than the third and fourth capacity portions 25 and 27 and have a constant width direction size, respectively. Thus, the third and fourth capacitor portions 25 and 27 are drawn out from the central portion in the width direction.

  As can be seen by referring to both FIG. 3 (1) and FIG. 4 (1), the first lead portion 22 and the third lead portion 26 are partly when projected in the stacking direction of the capacitor body 8. It arrange | positions so that it may mutually overlap. And the width direction dimension L1 of the 1st drawer | drawing-out part 22 exposed to the 1st end surface 6 is longer than the width direction dimension L2 of the 3rd drawer | drawing-out part 26 exposed to the 1st end surface 6 similarly.

As described above, in the multilayer capacitor 1 according to the first reference example , the third and fourth lead portions 26 and 28 have overall dimensions in the width direction as compared with the first and second lead portions 22 and 24, respectively. As a result, the contact area between the first internal electrode 17 and the first external terminal electrode 9 is larger than the contact area between the third internal electrode 19 and the second external terminal electrode 10. The ESR per layer in the second capacitor unit 13 is higher than the ESR per layer in the first capacitor unit 12. Further, the current path from the first internal electrode 17 to the first external terminal electrode 9 in the first capacitor unit 12 is such that the third internal electrode 19 to the first external terminal electrode 9 in the second capacitor unit 13. Compared with the current path up to, the ESL of the first capacitor unit 12 is relatively low and the resonance frequency is relatively high.

  As a result, the characteristics of the multilayer capacitor 1 are a combination of the low ESL characteristic of the first capacitor unit 12 and the high ESR characteristic of the second capacitor unit 13, and the multilayer capacitor 1 has a low ESL and a high ESR. It can be.

  From the viewpoint of increasing ESR, it is preferable that the capacity of the second capacitor unit 13 is larger than that of the first capacitor unit 12. Therefore, for example, the number of sets of the third and fourth internal electrodes 19 and 20 in the second capacitor unit 13 is made larger than the number of sets of the first and second internal electrodes 17 and 18 in the first capacitor unit 12. Many things are done.

  In addition, as described above, the first capacitor 12 in which the current path from the first internal electrode 17 to the first external terminal electrode 9 is further dispersed becomes the second capacitor unit 13 as shown in FIG. Therefore, the current loop between the mounting surface 16 and the multilayer capacitor 1 is dispersed, and the loop inductance is reduced. In particular, in the high frequency band, because the skin effect causes the current flowing in the first and second internal electrodes 17 and 18 of the lowermost layer of the multilayer capacitor 1 to greatly affect the ESL, the above-described effects become more prominent. .

When a preferred configuration is adopted in which the second capacitor portion 13 is sandwiched between the two first capacitor portions 12 as in this reference example , the first main surface 2 of the capacitor body 8 is mounted on the mounting surface, although not shown. Even when the multilayer capacitor 1 is mounted toward the side 16, the first capacitor portion 12 can be disposed closer to the mounting surface 16 than the second capacitor portion 13. Therefore, since there is no need to distinguish between the first main surface 2 and the second main surface 3 in mounting, the mounting process can be efficiently performed.

  If the above-described advantages are not particularly desired, for example, the capacitor body 8 may be composed of one first capacitor portion 12 and one second capacitor portion 13. In this case, it is preferable that the first capacitor unit 12 is mounted so as to be closer to the mounting surface 16 than the second capacitor unit 13.

  The aforementioned “ESR per layer” can be obtained, for example, as follows.

  First, the ESR of a capacitor is expressed by the following equation, where R is the resistance per electrode layer and N is the number of stacked layers.

ESR of capacitor = R (4N−2) / N ²
Next, in the first capacitor unit 12, the ESR of the entire first capacitor unit 12 is calculated as the ESR of the capacitor to calculate the resistance R per electrode layer, and the value of R is substituted into the above equation. Further, by substituting N = 2 (one capacitor layer is formed with two internal electrodes facing each other) into the above equation, “ESR per layer” can be calculated.

  The ESR per layer can be finely adjusted by adjusting the specific resistance of the material of the internal electrode or adjusting the thickness of the internal electrode.

In this reference example , the second and fourth lead portions 24 and 28 have the same relationship as that of the first and third lead portions 22 and 26 described above. If comprised in this way, since the balance of arrangement | positioning of the drawer | drawing-out part 22, 24, 26, and 28 in the inside of the capacitor | condenser main body 8 will become favorable, the effect that the lamination | stacking state of the capacitor | condenser main body 8 will be stabilized is acquired, for example. However, as in the illustrated reference example , the second and fourth drawer portions 24 and 28 do not necessarily have the same relationship as that of the first and third drawer portions 22 and 26. This is also true for other reference examples and embodiments described later.

  Next, details of each element provided in the multilayer capacitor 1 will be described.

The dielectric layer 11 is made of, for example, a dielectric ceramic mainly composed of BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , CaZrO _{3 and the} like. Note that subcomponents such as a Mn compound, an Fe compound, a Cr compound, a Co compound, and a Ni compound may be added to these main components. Moreover, it is preferable that the thickness of the dielectric material layer 11 shall be 1-10 micrometers, for example.

  For example, Ni, Cu, Ag, Pd, an Ag—Pd alloy, Au, or the like can be used as the conductive component contained in the internal electrodes 17 to 20. The metal serving as the conductive component is preferably the same for each of the internal electrodes 17 to 20. Moreover, it is preferable that the thickness after each baking of the internal electrodes 17-20 is 0.5-2.0 micrometers.

  As the conductive component contained in the external terminal electrodes 9 and 10, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, or the like can be used. External terminal electrodes 9 and 10 may have a structure composed of a plurality of layers. When Ni is used as the conductive component of the internal electrodes 17 to 20, the conductive component contained in the first layer of the external terminal electrodes 9 and 10 is used in order to improve the bondability between the internal electrodes 17 to 20 and the external terminal electrodes 9 and 10. It is preferable to use a base metal such as Cu, Ni or the like.

  The external terminal electrodes 9 and 10 may be a cofire that is fired at the same time as the internal electrodes 17 to 20, a postfire that is baked by applying a conductive paste, or may be formed by direct plating. Good. The final thickness of the external terminal electrodes 9 and 10 is preferably 20 to 100 μm at the thickest portion.

  A plating film may be formed on the external terminal electrodes 9 and 10. As the metal constituting the plating film, for example, Cu, Ni, Ag, Pd, Ag—Pd alloy, Au, or the like can be used. The plating film may have a structure composed of a plurality of layers, and the thickness of the plating film is preferably 1 to 10 μm per layer. Further, a stress relaxation resin layer may be formed between the external terminal electrodes 9 and 10 and the plating film.

  Next, an example of a method for manufacturing the multilayer capacitor 1 described above will be described.

  First, a ceramic green sheet to be the dielectric layer 11, a conductive paste for the internal electrodes 17 to 20, and a conductive paste for the external terminal electrodes 9 and 10 are prepared. These ceramic green sheets and various conductive pastes contain a binder and a solvent. As the binder and the solvent, known organic binders and organic solvents can be used, respectively. Further, the conductive paste for the external terminal electrodes 9 and 10 often contains a glass component.

  Next, a conductive paste is printed on the ceramic green sheet with a predetermined pattern by, for example, a screen printing method. Thereby, a ceramic green sheet on which a conductive paste film to be each of the internal electrodes 17 to 20 is formed is obtained.

  Next, a predetermined number of ceramic green sheets on which conductive paste films are formed as described above are stacked in a predetermined order, and a predetermined number of outer layer ceramic green sheets on which conductive paste films are not formed are stacked. By doing so, a mother laminate in a raw state can be obtained. The raw mother laminate is pressure-bonded in the laminating direction by means such as an isostatic press as required.

  Next, the raw mother laminate is cut into a predetermined size, whereby the raw capacitor body 8 is cut out.

  Next, the raw capacitor body 8 is fired. The firing temperature depends on the ceramic material contained in the ceramic green sheet and the metal material contained in the conductive paste film, but is preferably selected in the range of 900 to 1300 ° C., for example.

Next, a conductive paste is applied on the first and second end faces 6 and 7 of the sintered capacitor body 8 and baked, whereby external terminal electrodes 9 and 10 are formed. This baking temperature is preferably in the range of 700 to 900 ° C., and is preferably lower than the baking temperature for forming the first layer 19. As atmosphere at the time of baking, according to the kind of metal contained in the conductive paste, atmosphere such as air, N ₂ or water vapor + N ₂ is properly used.

  Next, if necessary, the surfaces of the external terminal electrodes 9 and 10 are plated to complete the multilayer capacitor 1.

Hereinafter, second to ninth reference examples of interest to the present invention will be described with reference to FIGS. 5 to 12, respectively. The multilayer capacitors according to the second to ninth reference examples have the appearance, The arrangement state of the first and second capacitor portions 12 and 13 is the same as that of the multilayer capacitor 1 according to the first reference example shown in FIG.

  5 to 7, 9, 11, and 12 correspond to FIG. 4. In each of FIGS. 5 to 7, 9, 11, and 12, the elements shown in FIG. The elements corresponding to are denoted by the same reference numerals, and redundant description is omitted. 8 and FIG. 10 correspond to FIG. 3, but in each of FIG. 8 and FIG. 10, elements corresponding to those shown in FIG. Description is omitted.

In the second reference example , as shown sequentially in FIGS. 5 (1) to (4), two third internal electrodes 19 and two fourth internal electrodes 20 are alternately arranged. Since the third and fourth internal electrodes 19 and 20 have relatively small contact areas with the first and second external terminal electrodes 9 and 10, respectively, the contact with the external terminal electrodes 9 and 10 is good. Otherwise, the capacity of the entire multilayer capacitor may be reduced. According to the second reference example , by continuously laminating the third and fourth internal electrodes 19 and 20 respectively, even when one of the two has contact breakage, Since the other one backs up to form a capacity, a capacity that does not deviate much from the design capacity can be obtained.

  The third and fourth internal electrodes 19 and 20 only need to be alternately arranged in plural, and for example, three or more may be arranged alternately.

In the second reference example , not only the third lead portion 26 of the third internal electrode 19 but also the fourth lead portion 28 of the fourth internal electrode 20 has a relatively width dimension. When the width direction dimension of the fourth lead portion 28 of the fourth internal electrode 20 is not relatively shortened, for example, when the shape is the same as that of the second internal electrode 28, In particular, the internal electrodes 20 may not be arranged continuously in the stacking direction.

In the third reference example shown in FIG. 6, in the third and fourth internal electrodes 19 and 20, the third and fourth lead portions 26 and 28 are respectively connected to the third and fourth capacitor portions 25 and It is pulled out from the end, not from the center of 27. Thus, by changing the positions of the drawer portions 26 and 28 to, for example, the center portion, the end portion, or the intermediate portion of the third and fourth capacitor portions 25 and 27, the mounting surface 16 ( The current path from the land formed above to the lead portions 26 and 28 via the external terminal electrodes 9 and 10 can be changed. Thereby, the ESR can be finely adjusted by utilizing the resistance component of the external terminal electrodes 9 and 10 themselves.

In the fourth reference example shown in FIG. 7, in the third and fourth internal electrodes 19 and 20, the third and fourth lead portions 26 and 28 are respectively connected to the third and fourth capacitor portions 25 and 27 extends in a tapered manner toward the first and second end faces 6 and 7. By adopting such a configuration, the current paths from the third and fourth lead portions 26 and 28 to the third and fourth capacitor portions 25 and 27 are more easily dispersed, so that ESL is lowered. be able to.

In the fifth reference example shown in FIG. 8, the first and second lead portions 22 and 24 of the first and second internal electrodes 17 and 18 in the first capacitor portion 12 are notched, respectively. It is formed in a state where it is divided into two places with 22a and 24a therebetween. When this first capacitor portion 12 is combined with, for example, the second capacitor portion 13 shown in FIG. 4, the first lead portion 22 and the second lead portion 22 are projected when projected in the stacking direction of the capacitor body 8 (see FIG. 1). The third drawer portion 26 does not overlap with each other, and the second drawer portion 24 and the fourth drawer portion 28 do not overlap each other. By adopting such a configuration, it is possible to reduce a difference in thickness that can be locally generated in the capacitor body 8, and thus it is possible to suppress the occurrence of structural defects in the capacitor body 8.

In the fifth reference example , the dimension corresponding to the width direction dimension L1 of the first drawer portion 22 shown in FIG. 3 (1) is as shown in FIG. 8 (1). It is the sum of the width direction dimensions L11 and L12 of each part divided by the notch 22a.

In relation to the fifth reference example shown in FIG. 8, depending on the formation positions of the third and fourth lead portions 26 and 28 in the second capacitor portion 13 combined with the first capacitor portion 12. The positions of the notches 22a and 24a formed in the first and second drawer portions 22 and 24 can be changed.

In the sixth reference example shown in FIG. 9, as shown in FIG. 9 (1), the third lead portion 26 of the third internal electrode 19 in the second capacitor portion 13 is intermediate in the lead direction. The portion has a narrow portion 26a. As a matter of course, the width direction dimension of the narrow portion 26a is shorter than the width direction dimension of the first lead portion 22 (see FIG. 3). The width direction dimension of the edge of the third drawer portion 26 exposed at the first end face 6 is preferably equal to the width direction dimension L1 of the first drawer portion 22. On the other hand, as shown in FIG. 9 (2), in the fourth internal electrode 20, as in the case of the second internal electrode 18 shown in FIG. The four lead portions 28 are formed with a uniform width direction dimension.

In the sixth reference example , the narrow portion 26 a formed in the third lead portion 26 acts to increase the ESR per layer in the second capacitor portion 13.

In the seventh reference example shown in FIG. 10, dummy electrodes 74 and 75 are formed in the first capacitor unit 12. More specifically, the dummy electrode 74 is formed so as to be exposed to the second end face 7 on the same plane as the first internal electrode 17 as shown in FIG. On the other hand, as shown in FIG. 10B, the dummy electrode 75 is formed so as to be exposed on the first end face 6 on the same plane as the second internal electrode 18. The width direction dimension of the dummy electrode 74 is the same as the width direction dimension of the exposed edge of the first lead portion 22 of the first internal electrode 17 on the same plane, and the width direction dimension of the dummy electrode 75 is It is preferable that the width direction dimension of the exposed edge of the second lead portion 24 of the second inner electrode 18 on the same plane is the same.

By forming the dummy electrodes 74 and 75 as in the seventh reference example , not only the internal electrodes 17 and 18 but also the dummy electrodes 74 and 75 are joined to the external terminal electrodes 9 and 10. As a result, the bonding location of the external terminal electrodes 9 and 10 to the capacitor body 8 can be improved. Further, the external terminal electrodes 9 and 10, when formed by directly plating on the surface of the capacitor body 8, since the core portion serving of plating deposition increases, with adhesive force is improved, it is also possible to shorten the plating time.

In the eighth reference example shown in FIG. 11, dummy electrodes 76 and 77 are formed in the second capacitor portion 13. More specifically, as shown in FIG. 11A, the dummy electrode 76 is formed so as to be exposed to the second end face 7 on the same plane as the third internal electrode 19. On the other hand, the dummy electrode 77 is formed so as to be exposed to the first end face 6 on the same plane as the fourth internal electrode 20, as shown in FIG. The width direction dimension of the dummy electrode 76 is the same as the width direction dimension of the exposed edge of the third lead portion 26 of the third internal electrode 19 on the same plane, and the width direction dimension of the dummy electrode 77 is It is preferable that the width direction dimension of the exposed edge of the fourth lead portion 28 of the fourth inner electrode 20 on the same plane is the same.

According to the eighth reference example , the same effect as in the case of the seventh reference example described above can be obtained.

In the ninth reference example shown in FIG. 12, dummy electrodes 78 to 85 are formed in the second capacitor unit 13 in addition to the dummy electrodes 76 and 77 formed in the eighth reference example . More specifically, as shown in FIG. 12A, the dummy electrodes 78 to 81 are formed on the same surface as the third internal electrode 19, like the dummy electrode 76. The dummy electrodes 78 and 79 are exposed at the first end face 6, and the dummy electrodes 80 and 81 are exposed at the second end face 7, as with the dummy electrode 76. On the other hand, as shown in FIG. 12B, the dummy electrodes 82 to 85 are formed on the same surface as the fourth internal electrode 20, as with the dummy electrode 77. The dummy electrodes 82 and 83 are exposed on the first end face 6 and the dummy electrodes 84 and 85 are exposed on the second end face 7, similarly to the dummy electrode 77.

According to the ninth reference example , the effect of improving the fixing force of the external terminal electrodes 9 and 10 and the shortening of the plating time can be achieved more effectively than in the case of the above eighth reference example .

13 to 16 are for explaining a first embodiment of the present invention. Here, FIG. 13 corresponds to FIG. 1 and is a perspective view showing an appearance of the multilayer capacitor 31 according to the first embodiment .

  The multilayer capacitor 31 has first and second main surfaces 32 and 33 facing each other, first and second side surfaces 34 and 35 facing each other, and first and second end surfaces 36 and 37 facing each other. A capacitor main body 38 having a rectangular parallelepiped shape is provided. Similarly to the multilayer capacitor 1 described above, the multilayer capacitor 31 is also of the LW reverse type, and the longitudinal dimension Le of each of the first and second end faces 36 and 37 is the first and second side faces 34. And 35 are longer than the longitudinal dimension Ls.

  The multilayer capacitor 31 also includes first and second external terminal electrodes 39 and 40 that are formed on at least the second main surface 33 of the capacitor body 38 so as to be electrically insulated from each other. In this embodiment, the first external terminal electrode 39 is formed on the second main surface 33 to the first end surface 36, on each of the first and second side surfaces 34 and 35, and the first main surface. The second external terminal electrode 40 is formed on the second main surface 33, on the second end surface 37, on each of the first and second side surfaces 34 and 35. It is formed so as to wrap around a part and part of the first main surface 32.

The capacitor body 38 has a laminated structure including a plurality of laminated dielectric layers 41 (see FIGS. 15 and 16). The first embodiment is characterized in that the first and second side surfaces 34 and 35 extend in the surface direction of the dielectric layer 41.

FIG. 14 corresponds to FIG. 2 described above. The arrangement state of the first and second capacitor portions 42 and 43 formed in the capacitor body 38 is shown along the line BB in FIG. It is a block diagram shown with the section which follows. As shown in FIG. 14, the capacitor main body 38 includes a first capacitor portion 42 and a second capacitor portion 43 that are arranged along the stacking direction of the dielectric layers 41. In this embodiment, one second capacitor part 43 is arranged so as to be sandwiched between two first capacitor parts 42, and capacitance is formed at both ends in the stacking direction of the capacitor body 38. A non-contributing outer layer portion 45 is provided. In the first embodiment, the arrangement state of the first and second capacitor portions 42 and 43 can be arbitrarily changed.

  The multilayer capacitor 31 is mounted with the second main surface 33 of the capacitor body 38 facing the mounting surface 46 provided by the surface of the mounting substrate 44. Therefore, the first and second external terminal electrodes 39 and 40 need only be formed on at least the second main surface 33 of the capacitor body 38 as described above.

  As shown in FIG. 15, the first capacitor portion 42 is provided with first and second internal electrodes 47 and 48. The first and second internal electrodes 47 and 48 are opposed to each other through a predetermined dielectric layer 41 so as to form a capacitance. As shown in FIG. 16, the second capacitor portion 43 is provided with third and fourth internal electrodes 49 and 50. The third and fourth internal electrodes 49 and 50 are opposed to each other via a predetermined dielectric layer 41 so as to form a capacitance.

  As shown in FIG. 15 (1), the first internal electrode 47 is drawn out from the first capacitor 51 and the first capacitor 51 to at least the second main surface 33 and the first external terminal electrode 39. And a first drawer portion 52 that is electrically connected to each other. As shown in FIG. 15 (2), the second internal electrode 48 includes a second capacitor 53 and a second capacitor 53 that are opposed to the first capacitor 51 via a predetermined dielectric layer 41. At least a second lead portion 54 that is drawn to the second main surface 33 and is electrically connected to the second external terminal electrode 40 is provided.

  As shown in FIG. 16 (1), the third internal electrode 49 is drawn out from the third capacitor portion 55 and the third capacitor portion 55 to the second main surface 33 and is connected to the first external terminal electrode 39. It has the 3rd drawer | drawing-out part 56 electrically connected. As shown in FIG. 16 (2), the fourth internal electrode 50 includes a fourth capacitor portion 57 and a fourth capacitor portion 57 that face the third capacitor portion 55 through a predetermined dielectric layer 41. It has a fourth lead portion 58 that is drawn to the second main surface 33 and is electrically connected to the second external terminal electrode 40.

  As can be seen from both FIG. 15 (1) and FIG. 16 (1), in this embodiment, the first lead portion 52 and the third lead portion 56 are projected in the stacking direction of the capacitor body 38. In some cases, they are arranged so as to partially overlap each other. When compared in the same direction, that is, in the left-right direction in FIGS. 15 and 16, the third drawer portion 56 has a narrower portion than the first drawer portion 52. More specifically, the width direction dimension L1 of the first lead portion 52 exposed on the second main surface 33 is larger than the width direction dimension L2 of the third lead portion 56 exposed on the second main surface 33. It is getting longer.

As described above, in the multilayer capacitor 31 according to the first embodiment, the third lead portion 56 has a narrower portion than the first lead portion 52 when compared in the same direction. Moreover, since the contact area between the first internal electrode 47 and the first external terminal electrode 39 is larger than the contact area between the third internal electrode 49 and the second external terminal electrode 40, the second The ESR per layer directed to the capacitor portion 43 is higher than the ESR per layer in the first capacitor portion 42. Further, in the first capacitor unit 42, the current path from the first internal electrode 47 to the first external terminal electrode 39 is more dispersed, so the ESL of the first capacitor unit 42 becomes relatively low. The resonance frequency becomes relatively high.

  As a result, the characteristic of the multilayer capacitor 31 is a combination of the low ESL characteristic of the first capacitor unit 42 and the high ESR characteristic of the second capacitor unit 43, as in the case of the multilayer capacitor 1 described above. Capacitor 31 can be of low ESL and high ESR.

  Further, as described above, since the third lead portion 56 and the fourth lead portion 58 are drawn to the second main surface 33, the path from the mounting surface 46 (see FIG. 14) to the second capacitor portion 43. Also in this respect, the ESL of the multilayer capacitor 31 can be lowered as a whole.

  In this embodiment, as shown in FIG. 15 (1), the first drawer portion 52 is pulled out not only to the second main surface 33 but also to the first end surface 36 and the first main surface 32. ing. That is, the first internal electrode 47 has a T shape. When comparing the width direction dimension L1 of the first drawer part 52 with the width direction dimension L2 of the third drawer part 56, the first drawer part 52 exposed on the first end face 36 or the first main surface 32 is compared. Although it is possible to consider the dimension in the width direction, as described above, particularly in the high frequency band, the current loop between the mounting surface 46 and the multilayer capacitor 31 becomes dominant. It is sufficient that only the width direction dimension L1 of the first lead portion 52 exposed at 33 is used as a comparison target.

  As described above, the fact that the first lead portion 52 is also drawn out to the first end surface 36 and the first main surface 32 is rather significant in terms of mechanical aspects, that is, the first internal electrode. Since the bondability between the first external terminal electrode 39 and the first external terminal electrode 39 can be improved, the adhesion of the first external terminal electrode 39 to the capacitor body 38 can be improved.

  In this embodiment, the second and fourth lead portions 56 and 58 have the same relationship as that of the first and third lead portions 52 and 56. Is not necessarily required. As in this embodiment, the second and fourth lead portions 54 and 58 have the same relationship as that of the first and third lead portions 52 and 56. Since the arrangement of the lead portions 52, 54, 56 and 58 is balanced, for example, an effect that the laminated state of the capacitor body 38 is stabilized can be expected.

17 to 21 are for explaining second to sixth embodiments of the present invention, respectively. 17, 19, and 20 correspond to FIG. 16, and in each of FIGS. 17, 19, and 20, elements corresponding to the elements shown in FIG. In addition, overlapping explanation is omitted. 18 is a diagram corresponding to FIG. 15. In FIG. 18, elements corresponding to the elements shown in FIG. 15 are denoted by the same reference numerals, and redundant description is omitted. FIG. 21 is a diagram corresponding to FIG. 13. In FIG. 21, elements corresponding to the elements shown in FIG.

The multilayer capacitor according to the second embodiment shown in FIG. 17 has the appearance, the arrangement state of the first and second capacitor portions 42 and 43, and the first and second internal electrodes 47 in the first capacitor portion 42. The forms of and 48 are the same as those of the multilayer capacitor 31 according to the first embodiment described above.

In the second embodiment, as shown sequentially in FIGS. 17 (1) to (4), two third internal electrodes 49 and two fourth internal electrodes 50 are alternately arranged in the stacking direction. . According to the second embodiment, the same effects as in the case of the second reference example shown in FIG.

In the second embodiment, as shown in FIGS. 17 (3) and (4), the width direction dimension of the fourth drawer portion 58 is the same as that of the second drawer portion 54 (see FIG. 15 (2)). The fourth internal electrode 50 has the same form as the second internal electrode 48, for example, and the width direction dimension of the fourth lead portion 58 is the width direction dimension of the second lead portion 54. , Only the third inner electrode 49 may be continuously arranged in the stacking direction.

In the third embodiment shown in FIG. 18, dummy electrodes 86 and 87 are formed in the first capacitor unit 42. More specifically, as shown in FIG. 18A, the dummy electrode 86 is formed on the same surface as the first internal electrode 47, the second end surface 37 and each part of the first and second main surfaces 32. It is formed so as to be exposed. On the other hand, as shown in FIG. 18B, the dummy electrode 87 is exposed on each of the first end surface 36 and the first and second main surfaces 32 on the same plane as the second internal electrode 48. It is formed as follows.

By forming the dummy electrodes 86 and 87 as in the third embodiment, the internal electrodes 47 and 48 with respect to the external terminal electrodes 39 and 40 are the same as in the case of the seventh reference example shown in FIG. In addition, since the dummy electrodes 86 and 87 are also joined, the number of joined portions is increased, and as a result, the fixing force of the external terminal electrodes 39 and 40 to the capacitor body 38 can be improved. Further, the external terminal electrodes 39 and 40, when formed by directly plating on the surface of the capacitor body 38, since the core portion serving of plating deposition increases, with adhesive force is improved, it is also possible to shorten the plating time.

In the fourth embodiment shown in FIG. 19, dummy electrodes 88 and 89 are formed in the second capacitor unit 43. More specifically, the dummy electrode 88 is formed so as to be exposed to the first main surface 32 on the same plane as the third internal electrode 49 as shown in FIG. On the other hand, the dummy electrode 89 is formed so as to be exposed to the first main surface 32 on the same plane as the fourth internal electrode 50 as shown in FIG. The width direction dimension of the dummy electrode 88 is the same as the width direction dimension of the exposed edge of the third lead portion 56 of the third internal electrode 49 on the same plane, and the width direction dimension of the dummy electrode 89 is It is preferable that the width direction dimension of the exposed edge of the fourth lead portion 58 of the fourth inner electrode 50 on the same plane is the same.

According to the fourth embodiment, the same effect as in the case of the third embodiment described above is achieved.

In the tenth reference example shown in FIG. 20, in the second capacitor portion 43, as shown in FIG. 20 (1), the third lead portion 56 of the third internal electrode 49 is connected to the first external terminal. As shown in FIG. 20 (2), the fourth lead portion 58 of the fourth inner electrode 50 is pulled out to the second end face 36 so as to be electrically connected to the electrode 39. It is drawn out to the second end face 37 so as to be electrically connected to the external terminal electrode 40. When such a configuration is adopted, the path from the mounting surface 46 (see FIG. 14) to the second capacitor unit 43 can be lengthened, and as a result, the ESR of the second capacitor unit 43 can be increased. it can.

The multilayer capacitor 31a according to the fifth embodiment shown in FIG. 21 is not a so-called LW inversion type as compared with the multilayer capacitor 31 according to the first embodiment shown in FIG. The longitudinal dimension Le of each of the two end faces 36 and 37 is shorter than the longitudinal dimension Ls of each of the first and second side faces 34 and 35. Further, the areas of the first and second external terminal electrodes 39 and 40 extending on the first and second main surfaces 32 and 33 are relatively wide. Further, external terminal electrodes 39 and 40 are not formed on the first and second side surfaces 34 and 35. The fifth embodiment has the significance of clearly indicating that various modifications can be made with respect to the shape of the capacitor body 38.

  Next, experimental examples carried out to confirm the effects of the present invention will be described.

In this experimental example, although not within the scope of the present invention, the first reference example described with reference to FIGS. 1 to 4, the second reference example described with reference to FIG. 5, and FIG. Based on the third reference example described with reference and the fourth reference example described with reference to FIG. 7, multilayer capacitors according to Samples 1, 2, 3, and 4 were produced.

  In addition, as a comparative example, a multilayer capacitor 61 according to the sample 5 including only one type of capacitor portion including the first and second internal electrodes 66 and 67 shown in FIGS. Produced. The multilayer capacitor 61 includes a capacitor body 62, and first and second external terminal electrodes 63 and 64 are formed on the first and second end faces of the capacitor body 62, respectively. The capacitor body 62 has a laminated structure including a plurality of laminated dielectric layers 65, and first and second internal electrodes 66 and 67 facing each other with a predetermined dielectric layer 65 interposed therebetween. Provided. The first internal electrode 66 includes a first capacitor portion 68 and a first lead portion 69 that is drawn from the first capacitor portion 68 and is electrically connected to the first external terminal electrode 63. The internal electrode 67 is drawn out from the second capacitor 70 and the second capacitor 70 facing the first capacitor 68 via the predetermined dielectric layer 65, and the second external terminal electrode 64. It has the 2nd drawer | drawing-out part 71 electrically connected.

  For the multilayer capacitor according to each sample, the dimensions of the capacitor body are 1.6 mm (corresponding to the longitudinal dimension Le of the end face) × 0.8 mm (corresponding to the longitudinal dimension Ls of the side surface) × 0.5 mm (dimension in the thickness direction) ). The conditions such as the thickness of the dielectric layer and the thickness of the internal electrode of the multilayer capacitor according to each sample were made common.

  The width direction dimension L1 of the first and second lead portions is 1.24 mm in the samples 1 to 4, and the width direction dimension L2 of the third and fourth lead portions is 0 in the samples 1 to 3. 18 mm, and in sample 4, 0.3 mm. In Sample 5, the width direction dimension of the drawer portion was set to 1.24 mm, similar to the width direction dimension L1 of the first and second drawer portions in Samples 1 to 4.

  Regarding the number of first and second internal electrodes stacked in the first capacitor unit, in samples 1 to 4, one first internal electrode and one second internal electrode, a total of two did. Regarding the number of stacked third and fourth internal electrodes in the second capacitor unit, in Samples 1, 3 and 4, 16 third internal electrodes and 16 fourth internal electrodes, a total of 32, are provided. In Sample 2, the number of the third internal electrodes was 32 and the number of the fourth internal electrodes was 32, for a total of 64, and 16 pairs were opposed as capacitors. In Sample 5, there were 17 first internal electrodes and 17 second internal electrodes, for a total of 34 sheets.

  With respect to the multilayer capacitor according to each sample, the overall capacitance, the synthesized ESR, and the impedance frequency characteristic were obtained. The overall capacity and synthetic ESR are shown in Table 1 below.

  For impedance frequency characteristics, each sample was shunt-connected to a coplanar substrate having a characteristic impedance of 50Ω, and S parameters were measured at a measurement frequency of 300 kHz to 3 GHz using a network analyzer (manufactured by Agilent). From the above, L, C and R are calculated. FIG. 23, FIG. 24, FIG. 25, FIG. 26, and FIG. 27 show the impedance frequency characteristics of samples 1, 2, 3, 4, and 5, respectively. 23 to 27, the horizontal axis indicating the frequency and the vertical axis indicating the impedance are both based on a logarithmic scale, and the frequency value on the horizontal axis and the impedance value on the vertical axis are shown in FIG. 23 to 27 are common.

  From Table 1, it can be seen that, according to Samples 1 to 4 as examples of the present invention, a higher ESR was obtained compared to Sample 5 as a comparative example. Comparing between samples 1 to 4, it can be seen that the ESR can be controlled by changing the width direction dimension L2 of the third and fourth lead portions or changing the positions of the third and fourth lead portions. .

  Further, comparing FIGS. 23 to 27, it can be seen that the waveforms of the impedance frequency characteristics of the samples 1 to 4 are duller than that of the sample 5 in the vicinity of the resonance frequency.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing an appearance of a multilayer capacitor 1 as a first reference example that is of interest to the present invention. The arrangement state of the first and second capacitor parts 12 and 13 configured in the capacitor body 8 provided in the multilayer capacitor 1 shown in FIG. 1 is shown with a cross section along the line AA in FIG. It is a block diagram. It is a figure which shows the 1st capacitor | condenser part 12 comprised in the capacitor | condenser main body 8 with which the multilayer capacitor | condenser 1 shown in FIG. 1 is provided with the cross section which the 1st and 2nd internal electrodes 17 and 18 each pass. It is a figure which shows the 2nd capacitor | condenser part 13 comprised in the capacitor | condenser main body 8 with which the multilayer capacitor | condenser 1 shown in FIG. 1 is provided with the cross section which the 3rd and 4th internal electrodes 19 and 20 each pass. It is a figure corresponding to FIG. 4 for demonstrating the 2nd reference example interested for this invention. It is a figure corresponding to FIG. 4 for demonstrating the 3rd reference example interested for this invention. It is a figure corresponding to FIG. 4 for demonstrating the 4th reference example interested for this invention. It is a figure corresponding to FIG. 3 for demonstrating the 5th reference example interested for this invention. It is a figure corresponding to FIG. 4 for demonstrating the 6th reference example interested for this invention. It is a figure corresponding to FIG. 3 for demonstrating the 7th reference example interested for this invention. It is a figure corresponding to FIG. 4 for demonstrating the 8th reference example interested for this invention. It is a figure corresponding to FIG. 4 for demonstrating the 9th reference example interested for this invention. 1 is a perspective view showing an appearance of a multilayer capacitor 31 according to a first embodiment of the present invention. The arrangement state of the first and second capacitor portions 42 and 43 configured in the capacitor main body 38 provided in the multilayer capacitor 31 shown in FIG. 13 is shown with a cross section along the line BB in FIG. It is a block diagram. It is a figure which shows the 1st capacitor | condenser part 42 comprised in the capacitor | condenser main body 38 with which the multilayer capacitor | condenser 31 shown in FIG. 13 is provided with the cross section through which the 1st and 2nd internal electrodes 47 and 48 each pass. It is a figure which shows the 2nd capacitor | condenser part 43 comprised in the capacitor | condenser main body 38 with which the multilayer capacitor | condenser 31 shown in FIG. 13 is provided with the cross section through which the 3rd and 4th internal electrodes 49 and 50 each pass. It is a figure corresponding to FIG. 16 for demonstrating the 2nd Embodiment of this invention. It is a figure corresponding to FIG. 15 for demonstrating the 3rd Embodiment of this invention. It is a figure corresponding to FIG. 16 for demonstrating the 4th Embodiment of this invention. It is a figure corresponding to FIG. 16 for demonstrating the 10th reference example interested for this invention. It is a figure corresponding to FIG. 13 for demonstrating the 5th Embodiment of this invention. It is a figure which shows the multilayer capacitor 61 which concerns on the sample 5 produced as a comparative example in an experiment example with the cross section which the 1st and 2nd internal electrodes 66 and 67 each pass. It is a figure which shows the impedance frequency characteristic about the sample 1 produced in the said experiment example. It is a figure which shows the impedance frequency characteristic about the sample 2 produced in the said experiment example. It is a figure which shows the impedance frequency characteristic about the sample 3 produced in the said experiment example. It is a figure which shows the impedance frequency characteristic about the sample 4 produced in the said experiment example. It is a figure which shows the impedance frequency characteristic about the sample 5 produced in the said experiment example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,31,31a Multilayer capacitor | condenser 2,32 1st main surface 3,33 2nd main surface 4,34 1st side surface 5,35 2nd side surface 6,36 1st end surface 7,37 2nd End face 8, 38 Capacitor body 9, 39 First external terminal electrode 10, 40 Second external terminal electrode 11, 41 Dielectric layer 12, 42 First capacitor part 13, 43 Second capacitor part 16, 46 Mounting Surface 17, 47 1st internal electrode 18, 48 2nd internal electrode 19, 49 3rd internal electrode 20, 50 4th internal electrode 21, 51 1st capacity | capacitance part 22, 52 1st extraction part 23 , 53 2nd capacity part 24, 54 2nd drawer part 25, 55 3rd capacity part 26, 56 3rd drawer part 26a Narrow part 27, 57 4th capacity part 28, 58 4th drawer Part Le End face longitudinal dimension Ls Side Longitudinal dimension L1, L11, L12 first width dimension in the width direction dimension L2 third lead portion of the lead-out portion

Claims (5)

First and second main surfaces having a laminated structure composed of a plurality of laminated dielectric layers, and extending in the surface direction of the dielectric layer and facing each other, and first and second side surfaces facing each other And a capacitor body having a rectangular parallelepiped shape having first and second end faces facing each other;
A first external terminal electrode formed on at least a second main surface and a first end surface of the capacitor body ;
A second external terminal electrode formed on at least the second main surface and the second end surface of the capacitor body in a state of being electrically insulated from the first external terminal electrode ;
The capacitor body includes a first capacitor portion and a second capacitor portion, which are arranged along the stacking direction of the dielectric layers,
The first capacitor portion is provided with first and second internal electrodes facing each other through the predetermined dielectric layer so as to form a capacitance,
The second capacitor portion is provided with third and fourth internal electrodes facing each other through the predetermined dielectric layer so as to form a capacitance,
The first internal electrode is drawn out from the first capacitor portion and the first capacitor portion to at least the first end face and is electrically connected to the first external terminal electrode. And
The second internal electrode is led out to at least the second end face from the second capacitor portion and the second capacitor portion facing the first capacitor portion via the predetermined dielectric layer, and A second lead portion electrically connected to the second external terminal electrode,
The third internal electrode is drawn out from the third capacitor and the third capacitor to the second main surface and electrically connected to the first external terminal electrode. And
The fourth internal electrode is led to the second main surface from the fourth capacitor portion and the fourth capacitor portion facing the third capacitor portion via the predetermined dielectric layer, and A fourth lead portion electrically connected to the second external terminal electrode,
When compared at the same direction, the third lead portion, said first have a narrow portion as compared to the lead-out portion, the fourth lead portion, compared to the second lead-out portion Having a narrow part,
Multilayer capacitor. The multilayer capacitor according to claim 1, wherein the multilayer capacitor is mounted with the second main surface facing the mounting surface. The first external terminal electrode further includes a portion formed on the first main surface, and on the same surface as the third internal electrode, at a position facing the third lead portion, A dummy electrode is further formed so as to be exposed to the first main surface and bonded to the first external terminal electrode;
The second external terminal electrode further has a portion formed on the first main surface, and on the same plane as the fourth internal electrode, at a position facing the fourth lead portion, The multilayer capacitor according to claim 1, wherein a dummy electrode is further formed so as to be exposed to the first main surface and to be joined to the second external terminal electrode. 4. The multilayer capacitor according to claim 1, wherein a plurality of the third internal electrodes are continuously arranged in the lamination direction in the second capacitor unit. 5. In the capacitor body, two of said second capacitor section by the first capacitor portion is arranged so as to be sandwiched, laminated capacitor according to any one of claims 1 to 4.

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