JP5022093B2 - Implementation method - Google Patents

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JP5022093B2
JP5022093B2 JP2007114686A JP2007114686A JP5022093B2 JP 5022093 B2 JP5022093 B2 JP 5022093B2 JP 2007114686 A JP2007114686 A JP 2007114686A JP 2007114686 A JP2007114686 A JP 2007114686A JP 5022093 B2 JP5022093 B2 JP 5022093B2
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chip
mounting
electrode
substrate
bonding
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JP2008270672A (en
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威 中筋
健一郎 田中
將有 鎌倉
和司 吉田
昌男 桐原
久徳 城石
巧 田浦
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Panasonic Corp
Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

本発明は、複数個のチップを１枚の実装基板に実装する実装方法に関するものである。   The present invention relates to a mounting method for mounting a plurality of chips on a single mounting board.

従来から、複数個のチップを１枚のウェハからなる実装基板に実装する実装方法として、実装基板における各チップそれぞれの搭載領域の所定位置にボンディングパッド部を形成してから、ボンディングパッド部にフラックスを塗布し、その後、半田バンプを形成した各チップ（半導体チップ）を半田バンプがボンディングパッド部に重なるように実装基板に対して１個ずつ位置合わせしてから、リフローを行うことによりチップと実装基板とを接合し、続いて、フラックス残渣を除去するようにした実装方法が提案されている（例えば、特許文献１参照）。
特開平６−１５１７０１号公報（段落〔００１３〕−〔００１６〕および図１） Conventionally, as a mounting method for mounting a plurality of chips on a mounting substrate made of a single wafer, a bonding pad portion is formed at a predetermined position in a mounting area of each chip on the mounting substrate, and then flux is applied to the bonding pad portion. After that, each chip (semiconductor chip) on which solder bumps are formed is aligned with the mounting substrate so that the solder bumps overlap the bonding pad portions, and then reflowed to mount the chips. There has been proposed a mounting method in which a substrate is bonded and subsequently a flux residue is removed (see, for example, Patent Document 1).
JP-A-6-151701 (paragraphs [0013]-[0016] and FIG. 1)

上記特許文献１に開示された実装方法では、１枚の実装基板に複数個のチップを１個ずつ位置合わせしているので、例えばチップの小型化などに伴って１枚の実装基板に実装するチップの個数が増えるにつれて１枚の実装基板当たりの実装タクトタイムが増大してしまう。また、上述の実装方法では、半田バンプをリフローにより加熱する必要があるので、チップと実装基板との線膨張率差に起因して実装後にチップと実装基板との接合部に残留応力が生じ、チップの特性劣化を招く可能性がある。   In the mounting method disclosed in Patent Document 1, since a plurality of chips are aligned one by one on one mounting substrate, for example, mounting is performed on one mounting substrate in accordance with downsizing of the chip or the like. As the number of chips increases, the mounting tact time per mounting board increases. Further, in the above mounting method, since it is necessary to heat the solder bumps by reflow, residual stress occurs at the joint between the chip and the mounting substrate after mounting due to the difference in linear expansion coefficient between the chip and the mounting substrate, There is a possibility of deteriorating the characteristics of the chip.

本発明は上記事由に鑑みて為されたものであり、その目的は、実装タクトタイムを短縮でき、且つ、チップの特性劣化を防止できる実装方法を提供することにある。   The present invention has been made in view of the above-described reasons, and an object of the present invention is to provide a mounting method capable of shortening the mounting tact time and preventing the deterioration of chip characteristics.

請求項１の発明は、複数個のチップを１枚の実装基板に実装する実装方法であって、実装基板における各チップそれぞれの搭載位置にチップ接続用電極を形成するチップ接続用電極形成工程および実装基板への搭載前の複数個のチップを載置するチップ支持用基板において前記搭載位置に対応する各位置にチップを当該チップの実装用電極を上面側として載置するチップ載置工程を含む接合準備工程と、接合準備工程の後にチップ支持用基板と実装基板とを対応する実装用電極とチップ接続用電極とが離間して向かい合うように対向配置してから各チップの実装用電極および実装基板の各チップ接続用電極それぞれの表面を一括して活性化させる活性化工程と、活性化工程の後にチップ支持用基板と実装基板とを近づけて対応する実装用電極とチップ接続用電極とを常温下で接合する接合工程と、接合工程の後にチップ支持用基板を各チップから引き離す引離工程とを備え、チップ載置工程では、チップ支持用基板として各チップそれぞれを位置決めする位置決め凹所を一面側に有する基板を用いるようにし、基板として位置決め凹所の内側面がテーパ状であり且つ内底面の面積がチップのチップ面積よりも小さなものを用いることを特徴とする。 The invention according to claim 1 is a mounting method for mounting a plurality of chips on a single mounting substrate, wherein a chip connecting electrode forming step for forming a chip connecting electrode at a mounting position of each chip on the mounting substrate, and A chip mounting step of mounting a chip at each position corresponding to the mounting position on the chip support substrate on which a plurality of chips before mounting on the mounting substrate are mounted with the mounting electrode of the chip as the upper surface side; After the bonding preparation step, and after the bonding preparation step, the chip supporting substrate and the mounting substrate are arranged to face each other so that the corresponding mounting electrode and the chip connecting electrode are spaced apart from each other, and then the mounting electrode and mounting of each chip An activation process for activating the surfaces of the respective chip connection electrodes on the substrate in a lump, and a mounting electrode for which the chip support substrate and the mounting substrate are brought close to each other after the activation process E Bei a bonding step of bonding the chip connecting electrodes at room temperature, and引離step of separating the chip supporting substrate after the bonding step from the chip, the higher the chip mounting step, each chip respectively as the chip supporting substrate A substrate having a positioning recess on one side for positioning is used, and the inner surface of the positioning recess is tapered and the area of the inner bottom surface is smaller than the chip area of the chip. To do.

この発明によれば、実装基板における各チップそれぞれの搭載位置にチップ接続用電極を形成するチップ接続用電極形成工程および実装基板への搭載前の複数個のチップを載置するチップ支持用基板において前記搭載位置に対応する各位置にチップを当該チップの実装用電極を上面側として載置するチップ載置工程を含む接合準備工程の後に、チップ支持用基板と実装基板とを対応する実装用電極とチップ接続用電極とが離間して向かい合うように対向配置してから各チップの実装用電極および実装基板の各チップ接続用電極それぞれの表面を一括して活性化させる活性化工程を行い、その後、チップ支持用基板と実装基板とを近づけて対応する実装用電極とチップ接続用電極とを常温下で接合する接合工程を行い、続いて、チップ支持用基板を各チップから引き離す引離工程を行うので、チップ支持用基板に載置した複数個のチップを一括して１枚の実装基板に実装することができるから、実装タクトタイムを短縮でき、しかも、接合工程では、表面が活性化された実装用電極と表面が活性化されたチップ接続用電極とを常温下で接合するので、リフローのような加熱処理を行うことなく実装用電極とチップ接続用電極とを接合することができ、実装基板とチップとの線膨張率差に起因したチップの特性劣化を防止できる。   According to the present invention, in the chip connection electrode forming step of forming the chip connection electrode at the mounting position of each chip on the mounting substrate and the chip support substrate for mounting the plurality of chips before mounting on the mounting substrate Mounting electrodes corresponding to the chip support substrate and the mounting substrate after the bonding preparation step including the chip mounting step of mounting the chip at each position corresponding to the mounting position with the mounting electrode of the chip as the upper surface side And the chip connection electrode are arranged so as to face each other at a distance, and then an activation process is performed to collectively activate the surfaces of the mounting electrodes of each chip and the respective chip connection electrodes of the mounting substrate. Then, the chip supporting substrate and the mounting substrate are brought close to each other and a corresponding mounting electrode and chip connecting electrode are bonded at room temperature, followed by the chip supporting substrate. Since the separation process of separating each chip from each chip is performed, a plurality of chips mounted on the chip support substrate can be mounted on one mounting substrate at a time, so that the mounting tact time can be shortened, In the bonding process, the mounting electrode whose surface has been activated and the chip connection electrode whose surface has been activated are bonded at room temperature, so that the mounting electrode and chip connection can be performed without heat treatment such as reflow. The electrodes can be bonded to each other, and deterioration of the characteristics of the chip due to the difference in linear expansion coefficient between the mounting substrate and the chip can be prevented.

また、この発明によれば、チップ載置工程では、チップ支持用基板として各チップそれぞれを位置決めする位置決め凹所を一面側に有する基板を用いるので、チップ支持基板への各チップの位置合わせが容易になるとともに、実装基板に対する各チップの位置精度を高めることが可能になる。 Further, according to this invention, as in the chip mounting step, since a substrate having a positioning recess for positioning the respective chips as a chip supporting board on one side, the position of each chip to Chi-up support substrate together suit is facilitated, it is possible to improve the positional accuracy of each chip against the implementation substrate.

また、この発明によれば、チップ載置工程では、基板として位置決め凹所の内側面がテーパ状であり且つ内底面の面積がチップのチップ面積よりも小さなものを用いるので、位置決め凹所の内底面の表面あらさや位置決め凹所の深さ寸法のばらつきに起因したチップの高さばらつきを小さくすることができる。 Further, according to this invention, in about the chip mounting step, since the area inside surface of the inner bottom surface and a tapered positioning recess as a substrate is used as smaller than the chip area of the chip, position-decided Me concave it is possible to reduce the height variation of resulting from the switch-up to variations in the depth of the surface roughness and position-decided Me recess of the inner bottom surface of the place.

請求項２の発明は、請求項１の発明において、前記チップにおける前記実装用電極がＡｕにより形成されており、前記チップ接続用電極形成工程では、前記チップ接続用電極をＡｕにより形成することを特徴とする。 According to a second aspect of the present invention, in the first aspect of the invention, the mounting electrode in the chip is formed of Au, and in the chip connection electrode forming step, the chip connection electrode is formed of Au. Features.

この発明によれば、前記チップ接続用電極と前記実装用電極とを常温下で容易に接合することができる。   According to this invention, the chip connection electrode and the mounting electrode can be easily joined at room temperature.

請求項３の発明は、請求項１または請求項２の発明において、前記チップ接続用電極形成工程では、前記チップ接続用電極の外形寸法を、前記チップの外周縁よりも内側に前記チップ接続用電極の外周縁が位置するように設定することを特徴とする。 According to a third aspect of the present invention, in the first or second aspect of the present invention, in the chip connecting electrode forming step, the outer dimensions of the chip connecting electrode are set to be inside the outer peripheral edge of the chip. The outer peripheral edge of the electrode is set so as to be positioned.

この発明によれば、前記チップの外周部にダイシングに起因したバリが存在する場合でも前記チップ接続用電極と前記チップの前記実装用電極とを接合することが可能となる。   According to the present invention, it is possible to bond the chip connection electrode and the mounting electrode of the chip even when burrs caused by dicing exist on the outer peripheral portion of the chip.

請求項４の発明は、請求項１ないし請求項３の発明において、前記チップ接続用電極形成工程では、前記チップ接続用電極としてバンプを形成することを特徴とする。 According to a fourth aspect of the present invention, in the first to third aspects of the present invention, the chip connecting electrode forming step forms a bump as the chip connecting electrode.

この発明によれば、前記実装基板への実装後の前記各チップの高さばらつきを低減できる。   According to the present invention, it is possible to reduce the variation in height of each chip after being mounted on the mounting substrate.

請求項１の発明は、実装タクトタイムを短縮でき、且つ、チップの特性劣化を防止できるという効果がある。   According to the first aspect of the present invention, the mounting tact time can be shortened and the deterioration of the chip characteristics can be prevented.

（実施形態１）
以下、本実施形態の実装方法は、複数個のチップ１０を１枚の実装基板２０に実装する実装方法であって、図１（ａ）の右側に示すように実装基板２０における各チップ１０それぞれの搭載位置にチップ接続用電極２１を形成するチップ接続用電極形成工程および図１（ａ）の左側に示すように実装基板２０への搭載前の複数個のチップ１０を載置するチップ支持用基板３０において上記搭載位置に対応する各位置にチップ１０を当該チップ１０の実装用電極１１を上面側として載置するチップ載置工程を含む接合準備工程と、接合準備工程の後に図１（ｂ）に示すようにチップ支持用基板３０と実装基板２０とを対応する実装用電極１１とチップ接続用電極２１とが離間して向かい合うように対向配置してから各チップ１０の実装用電極１１および実装基板２０の各チップ接続用電極２１それぞれの表面を一括して活性化させる活性化工程と、活性化工程の後に図１（ｃ）に示すようにチップ支持用基板３０と実装基板２０とを近づけて対応する実装用電極１１とチップ接続用電極２１との全部を常温下で接合する接合工程と、接合工程の後に図１（ｄ）に示すようにチップ支持用基板３０を各チップ１０から引き離す引離工程とを備えている。 (Embodiment 1)
Hereinafter, the mounting method of the present embodiment is a mounting method in which a plurality of chips 10 are mounted on a single mounting substrate 20, and each chip 10 on the mounting substrate 20 is shown on the right side of FIG. The chip connection electrode forming step for forming the chip connection electrode 21 at the mounting position of the chip and the chip support for mounting the plurality of chips 10 before mounting on the mounting substrate 20 as shown on the left side of FIG. A bonding preparation step including a chip mounting step of mounting the chip 10 at each position corresponding to the mounting position on the substrate 30 with the mounting electrode 11 of the chip 10 as the upper surface side, and after the bonding preparation step, FIG. ), The chip support substrate 30 and the mounting substrate 20 are arranged to face each other so that the corresponding mounting electrode 11 and the chip connection electrode 21 are spaced apart from each other, and then the mounting electrode 1 of each chip 10 is disposed. And an activation step of activating the respective surfaces of the chip connection electrodes 21 of the mounting substrate 20 at a time, and a chip support substrate 30 and a mounting substrate 20 as shown in FIG. 1 and the chip mounting substrate 30 and the chip connecting electrode 21 are bonded together at room temperature, and after the bonding process, the chip supporting substrate 30 is attached to each chip 10 as shown in FIG. And a separation step of separating from.

ところで、本実施形態では、上述のチップ１０として、チップサイズが０．３ｍｍ□で青色光を放射する発光ダイオードチップ（以下、ＬＥＤチップと称す）を用いており、チップ１０は、厚み方向の一表面側に形成されたアノード電極が実装用電極１１を構成するとともに、他表面側に形成されたカソード電極が表面側電極１２を構成しており、実装用電極１１および表面側電極１２が、下層側のＮｉ膜と上層側のＡｕ膜との積層膜により構成されている。   By the way, in the present embodiment, a light emitting diode chip (hereinafter referred to as an LED chip) that emits blue light with a chip size of 0.3 mm □ is used as the chip 10 described above. The anode electrode formed on the surface side constitutes the mounting electrode 11, and the cathode electrode formed on the other surface side constitutes the surface side electrode 12, and the mounting electrode 11 and the surface side electrode 12 are the lower layer It is constituted by a laminated film of a Ni film on the side and an Au film on the upper layer side.

なお、チップ１０として用いるＬＥＤチップは、青色光を放射するＬＥＤチップに限らず、赤色光を放射するＬＥＤチップ、緑色光を放射するＬＥＤチップ、紫外光を放射するＬＥＤチップなどでもよい。また、チップ１０としては、チップサイズが１ｍｍ□のＬＥＤチップを用いてもよい。また、上述のチップ１０は、ＬＥＤチップに限らず、例えば、レーザダイオードチップ、フォトダイオードチップ、ＭＥＭＳチップ（例えば、加速度センサチップ、圧力センサチップなど）、半導体チップ（例えば、ＩＣチップなど）などでもよく、チップサイズも特に限定するものではなく、例えば０．３ｍｍ□〜５ｍｍ□程度のものを用いればよい。また、チップ１０の厚みも特に限定するものではなく、例えば０．１〜０．５ｍｍ程度のものを用いればよい。   The LED chip used as the chip 10 is not limited to an LED chip that emits blue light, but may be an LED chip that emits red light, an LED chip that emits green light, an LED chip that emits ultraviolet light, or the like. Further, as the chip 10, an LED chip having a chip size of 1 mm □ may be used. The chip 10 is not limited to an LED chip, and may be a laser diode chip, a photodiode chip, a MEMS chip (for example, an acceleration sensor chip or a pressure sensor chip), a semiconductor chip (for example, an IC chip), or the like. The chip size is not particularly limited, and for example, a chip having a size of about 0.3 mm □ to 5 mm □ may be used. Further, the thickness of the chip 10 is not particularly limited, and for example, a chip having a thickness of about 0.1 to 0.5 mm may be used.

実装基板２０としては、直径が１００〜１５０ｍｍ、厚みが２００〜５２５μｍ程度のＳｉ基板（Ｓｉウェハ）の表面にＳｉＯ２膜からなる絶縁膜を形成したものを用い、チップ支持用基板３０としては、直径が１００〜１５０ｍｍ、厚みが２００〜５２５μｍ程度でサイズが実装基板２０と同じサイズのＳｉ基板（Ｓｉウェハ）を用いるが、実装基板２０およびチップ支持用基板３０それぞれの材料は特に限定するものではなく、実装基板２０の基板材料とチップ支持用基板３０の基板材料とが異種材料でもよい。 As the mounting substrate 20, a Si substrate (Si wafer) having a diameter of 100 to 150 mm and a thickness of about 200 to 525 μm is used in which an insulating film made of a SiO 2 film is formed. A Si substrate (Si wafer) having a diameter of 100 to 150 mm and a thickness of about 200 to 525 μm and the same size as the mounting substrate 20 is used, but the materials of the mounting substrate 20 and the chip support substrate 30 are not particularly limited. Alternatively, the substrate material of the mounting substrate 20 and the substrate material of the chip support substrate 30 may be different materials.

以下、上述の各工程について詳細に説明する。   Hereinafter, each process described above will be described in detail.

接合準備工程のチップ接続用電極形成工程では、実装基板２０の一表面側の全面にＴｉ膜とＡｕ膜との積層膜を例えばスパッタ法などにより成膜し、その後、フォトリソグラフィ技術およびエッチング技術を利用して上記積層膜をパターニングすることにより、各チップ１０それぞれの搭載位置に上記積層膜の一部からなるチップ接続用電極２１を形成する。ここにおいて、チップ接続用電極２１は、接合用のＡｕ膜と絶縁膜との間に密着性改善用のＴｉ膜を介在させてある。言い換えれば、チップ接続用電極２１は、絶縁膜上に形成されたＴｉ膜と当該Ｔｉ膜上に形成されたＡｕ膜との積層構造を有している。なお、チップ接続用電極２１は、Ｔｉ膜の膜厚を１５〜５０ｎｍ、Ａｕ膜の膜厚を５００ｎｍに設定してあるが、これらの数値は一例であって特に限定するものではない。また、本実施形態では、Ａｕ膜と絶縁膜との間に密着性改善用の密着層としてＴｉ膜を介在させてあるが、密着層の材料はＴｉに限らず、例えば、Ｃｒ、Ｎｂ、Ｚｒ、ＴｉＮ、ＴａＮなどでもよい。   In the chip connection electrode forming step of the bonding preparation step, a laminated film of a Ti film and an Au film is formed on the entire surface of one surface side of the mounting substrate 20 by, for example, a sputtering method, and then a photolithography technique and an etching technique are performed. By patterning the laminated film using this, the chip connection electrode 21 made of a part of the laminated film is formed at the mounting position of each chip 10. Here, in the chip connection electrode 21, a Ti film for improving adhesion is interposed between the bonding Au film and the insulating film. In other words, the chip connection electrode 21 has a laminated structure of a Ti film formed on the insulating film and an Au film formed on the Ti film. In the chip connection electrode 21, the thickness of the Ti film is set to 15 to 50 nm and the thickness of the Au film is set to 500 nm. However, these numerical values are merely examples and are not particularly limited. In this embodiment, a Ti film is interposed between the Au film and the insulating film as an adhesion layer for improving adhesion. However, the material of the adhesion layer is not limited to Ti. For example, Cr, Nb, Zr TiN, TaN, etc. may be used.

接合準備工程のチップ載置工程で用いるチップ支持用基板３０には、上記搭載位置に対応する各位置に位置決めマーク３１が形成されている。ここにおいて、各位置決めマーク３１の形成にあたっては、例えば、チップ支持用基板３０の基礎となるＳｉ基板の一表面側の全面にＡｕ膜を例えばスパッタ法などにより成膜し、その後、フォトリソグラフィ技術およびエッチング技術を利用してＡｕ膜をパターニングすることにより、それぞれ上記Ａｕ膜の一部からなる位置決めマーク３１を形成すればよい。なお、位置決めマーク３１の材料はＡｕに限らず、成膜方法もスパッタ法に限らず、例えば、蒸着法などの表面平滑性の良い膜の成膜が可能な成膜方法であればよい。   A positioning mark 31 is formed at each position corresponding to the mounting position on the chip support substrate 30 used in the chip mounting process of the bonding preparation process. Here, in forming each positioning mark 31, for example, an Au film is formed on the entire surface of one surface side of the Si substrate that is the basis of the chip support substrate 30 by, for example, a sputtering method, and thereafter, photolithography technique and By patterning the Au film using an etching technique, the positioning marks 31 each formed of a part of the Au film may be formed. The material of the positioning mark 31 is not limited to Au, and the film forming method is not limited to the sputtering method. For example, any film forming method capable of forming a film with good surface smoothness such as an evaporation method may be used.

チップ載置工程では、各チップ１０を各位置決めマーク３１上に直接載置しているが、各チップ１０をグリースや接着剤などにより各位置決めマーク３１上に仮止めしてもよい。なお、チップ支持用基板３０の各位置に形成された位置決めマーク３１上に各チップ１０を載置するにあたっては、ダイボンド装置を利用しているが、ピックアップツールなどを用いて手作業で載置するようにしてもよい。また、位置決めマーク３１の平面サイズは、チップ１０のチップサイズと同じに設定してあるが、チップ１０のチップサイズよりも小さく設定してもよい。   In the chip placement step, each chip 10 is placed directly on each positioning mark 31, but each chip 10 may be temporarily fixed on each positioning mark 31 with grease or an adhesive. It should be noted that a die-bonding device is used to place each chip 10 on the positioning mark 31 formed at each position of the chip support substrate 30, but it is manually placed using a pick-up tool or the like. You may do it. The planar size of the positioning mark 31 is set to be the same as the chip size of the chip 10, but may be set smaller than the chip size of the chip 10.

なお、接合準備工程では、チップ接続用電極形成工程とチップ載置工程との順番は特に限定するものではなく、例えば、チップ接続用電極形成工程とチップ載置工程とを並行して行うようにしてもよい。ただし、チップ接続用電極形成工程については、複数の実装基板２０に対して上記積層膜の成膜工程や、上記積層膜のエッチング工程をバッチ処理することで実装タクトタイムの大幅な短縮を図れる。   In the bonding preparation step, the order of the chip connection electrode formation step and the chip placement step is not particularly limited. For example, the chip connection electrode formation step and the chip placement step are performed in parallel. May be. However, with regard to the chip connection electrode forming process, the mounting tact time can be significantly shortened by batch-processing the stacked film forming process and the stacked film etching process on the plurality of mounting substrates 20.

活性化工程では、チャンバ内においてチップ支持用基板３０と実装基板２０とを実装基板２０が上側となるように対向配置してから、チャンバ内を規定真空度（例えば、１×１０−５Ｐａ）以下となるように真空排気し、その後、真空中で、チップ支持用基板３０に支持されている各チップ１０の実装用電極１１の表面および実装基板２０の各チップ接続用電極２１の表面をスパッタエッチングすることで清浄・活性化する。ここにおいて、活性化工程では、各実装用電極１１の表面および各チップ接続用電極２１の表面に対してイオン源４０からＡｒのイオンビームを所定時間（例えば、３００秒）だけ照射して各表面を清浄・活性化する。なお、活性化工程では、Ａｒのイオンビームに限らず、Ａｒのプラズマ若しくは原子ビームを照射するようにしてもよい。また、イオン源４０から照射するイオンもＡｒのイオンに限らず、例えば、Ｈｅ、Ｎｅなどのイオンでもよい。同様に、Ａｒのプラズマや原子ビームに限らず、Ｈｅ、Ｎｅなどのプラズマや原子ビームを利用してもよい。 In the activation step, the chip support substrate 30 and the mounting substrate 20 are disposed to face each other in the chamber so that the mounting substrate 20 is on the upper side, and then the inside of the chamber has a specified vacuum (for example, 1 × 10 −5 Pa). After evacuating to the following, the surface of the mounting electrode 11 of each chip 10 supported on the chip supporting substrate 30 and the surface of each chip connecting electrode 21 of the mounting substrate 20 are sputtered in vacuum. It is cleaned and activated by etching. Here, in the activation step, the surface of each mounting electrode 11 and the surface of each chip connection electrode 21 are irradiated with an ion beam of Ar from the ion source 40 for a predetermined time (for example, 300 seconds), and then each surface. Clean and activate. In the activation process, not only an Ar ion beam but also an Ar plasma or an atomic beam may be irradiated. The ions irradiated from the ion source 40 are not limited to Ar ions, and may be ions such as He and Ne. Similarly, not only Ar plasma and atomic beams, but plasmas and atomic beams such as He and Ne may be used.

接合工程では、活性化工程の後に上記チャンバ内でチップ支持用基板３０と実装基板２０とを近づけて対応する実装用電極１１とチップ接続用電極２１との全部を常温（例えば、２５℃）下で接合する。ここにおいて、接合工程では、表面が活性化された実装用電極１１と表面が活性化されたチップ接続用電極２１との表面同士を突き合わせてから、実装基板２０の他表面側から適宜の荷重（例えば、２〜５０ｋｇ／ｃｍ２）を規定時間（例えば、１０秒〜２分）だけ印加することにより、厚み方向において重なり合っている実装用電極１１とチップ接続用電極２１との全部がＡｕ−Ａｕの組み合わせの常温接合により接合される。ここにおいて、上述のようにチップ１０としてＬＥＤチップを採用している場合には、実装用電極１１とチップ接続用電極２１とがＡｕ−Ａｕの組み合わせで接合されているので、実装用電極１１１およびチップ接続用電極２１それぞれの膜厚を５００ｎｍ以下としても安定して常温接合することができ、実装用電極１１およびチップ接続用電極２１を薄くすることによりチップ１０と実装基板２０との間の熱抵抗を小さくすることができるから、放熱性を向上させることができ、チップ１０への投入電力を大きくすることができて光出力を大きくすることができる。 In the bonding process, after the activation process, the chip support substrate 30 and the mounting substrate 20 are brought close to each other in the chamber, and the corresponding mounting electrode 11 and chip connection electrode 21 are all kept at room temperature (for example, 25 ° C.). Join with. Here, in the bonding step, after the surfaces of the mounting electrode 11 whose surface is activated and the chip connection electrode 21 whose surface is activated are brought into contact with each other, an appropriate load (from the other surface side of the mounting substrate 20 ( For example, by applying 2 to 50 kg / cm 2 ) for a specified time (for example, 10 seconds to 2 minutes), all of the mounting electrode 11 and the chip connection electrode 21 overlapping in the thickness direction are Au—Au. It is joined by room temperature joining of the combination. Here, when the LED chip is adopted as the chip 10 as described above, the mounting electrode 11 and the chip connection electrode 21 are joined by a combination of Au—Au. Even if the film thickness of each of the chip connection electrodes 21 is 500 nm or less, the room temperature bonding can be stably performed, and the heat between the chip 10 and the mounting substrate 20 can be achieved by thinning the mounting electrodes 11 and the chip connection electrodes 21. Since the resistance can be reduced, the heat dissipation can be improved, the input power to the chip 10 can be increased, and the light output can be increased.

引離工程では、上記チャンバ内においてチップ支持用基板３０と実装基板２０とを遠ざけることによりチップ支持用基板３０を各チップ１０から引き離す。   In the separation step, the chip support substrate 30 is separated from each chip 10 by moving the chip support substrate 30 and the mounting substrate 20 away from each other in the chamber.

なお、チップ１０の種類などによっては、実装用電極１１の材料がＡｕに限らず、例えばＡｌ、Ｃｕなどの場合もあるので、このような場合には、実装用電極１１とチップ接続用電極２１とを、Ａｌ−Ａｌの組み合わせやＣｕ−Ｃｕの組み合わせの常温接合により接合すればよい。   Depending on the type of the chip 10 and the like, the material of the mounting electrode 11 is not limited to Au, but may be, for example, Al or Cu. In such a case, the mounting electrode 11 and the chip connection electrode 21 are used. Are bonded by room temperature bonding of a combination of Al—Al and a combination of Cu—Cu.

なお、上述の活性化工程、接合工程および引離工程は、例えば、ウェハレベルでの常温接合が可能な常温接合装置を利用して同一チャンバ内で連続的に行えばよい。   The above-described activation process, bonding process, and separation process may be performed continuously in the same chamber using, for example, a room temperature bonding apparatus capable of room temperature bonding at the wafer level.

以上説明した本実施形態の実装方法によれば、実装基板２０における各チップ１０それぞれの搭載位置にチップ接続用電極２１を形成するチップ接続用電極形成工程および実装基板２０への搭載前の複数個のチップ１０を載置するチップ支持用基板３０において上記搭載位置に対応する各位置にチップ１０を当該チップ１０の実装用電極１１を上面側として載置するチップ載置工程を含む接合準備工程の後に、チップ支持用基板３０と実装基板２０とを対応する実装用電極１１とチップ接続用電極２１とが離間して向かい合うように対向配置してから各チップ１０の実装用電極１１および実装基板２０の各チップ接続用電極２１それぞれの表面を一括して活性化させる活性化工程を行い、その後、チップ支持用基板３０と実装基板２０とを近づけて対応する実装用電極１１とチップ接続用電極２１との全部を常温下で接合する接合工程を行い、続いて、チップ支持用基板３０を各チップ１０から引き離す引離工程を行うので、チップ支持用基板３０に載置した複数個のチップ１０を一括して１枚の実装基板２０に実装することができるから、実装タクトタイムを短縮でき、しかも、接合工程では、表面が活性化された実装用電極１１と表面が活性化されたチップ接続用電極２１とを常温下で接合するので、リフローのような加熱処理を行うことなく実装用電極１１とチップ接続用電極２１とを接合することができ、実装基板２０とチップ１０との線膨張率差に起因したチップ１０の特性劣化を防止できる。また、本実施形態では、チップ１０における実装用電極１１がＡｕにより形成されており、チップ接続用電極形成工程では、チップ接続用電極２１をＡｕにより形成しているので、チップ接続用電極２１と実装用電極１１とを常温下で容易に接合することができる。   According to the mounting method of the present embodiment described above, a chip connection electrode forming step for forming the chip connection electrodes 21 at the mounting positions of the respective chips 10 on the mounting substrate 20 and a plurality before mounting on the mounting substrate 20. In a bonding preparation step including a chip mounting step of mounting the chip 10 with the mounting electrode 11 of the chip 10 on the upper surface side at each position corresponding to the mounting position in the chip support substrate 30 on which the chip 10 is mounted. Thereafter, the mounting electrode 11 and the mounting substrate 20 of each chip 10 are disposed after the chip supporting substrate 30 and the mounting substrate 20 are arranged to face each other so that the corresponding mounting electrodes 11 and the chip connection electrodes 21 face each other. An activation process is performed in which the surfaces of the chip connection electrodes 21 are activated collectively, and then the chip support substrate 30 and the mounting substrate 20 are moved closer together. Therefore, since the corresponding mounting electrode 11 and chip connection electrode 21 are all bonded at room temperature, the chip supporting substrate 30 is separated from each chip 10. Since a plurality of chips 10 placed on the supporting substrate 30 can be mounted together on one mounting substrate 20, the mounting tact time can be shortened, and the surface is activated in the bonding process. Since the mounting electrode 11 and the chip connection electrode 21 whose surface is activated are bonded at room temperature, the mounting electrode 11 and the chip connection electrode 21 are bonded without performing a heat treatment such as reflow. It is possible to prevent deterioration of the characteristics of the chip 10 due to the difference in linear expansion coefficient between the mounting substrate 20 and the chip 10. In the present embodiment, the mounting electrode 11 in the chip 10 is formed of Au, and in the chip connection electrode forming step, the chip connection electrode 21 is formed of Au. The mounting electrode 11 can be easily joined at room temperature.

ところで、チップ接続用電極形成工程において、チップ接続用電極２１の外形寸法を、チップ１０の外周縁よりも内側にチップ接続用電極２１の外周縁が位置するように設定すれば、つまり、チップ接続用電極２１の平面サイズをチップ１０のチップサイズよりも小さく設定すれば、チップ１０の外周部にダイシングに起因したバリが存在する場合でもチップ接続用電極２１とチップ１０の実装用電極１１とを安定して接合することが可能となる。また、チップ支持用基板３０における位置決めマーク３１の外形寸法についても、チップ１０の外周縁よりも内側に位置決めマーク３１の外周縁が位置するように設定すれば、つまり、位置決めマーク３１の平面サイズをチップ１０のチップサイズよりも小さく設定すれば、チップ１０の外周部にダイシングに起因したバリが存在する場合でもチップ接続用電極２１とチップ１０の実装用電極１１とを安定して接合することが可能となる。   By the way, in the chip connecting electrode forming step, if the outer dimensions of the chip connecting electrode 21 are set so that the outer peripheral edge of the chip connecting electrode 21 is located inside the outer peripheral edge of the chip 10, that is, chip connecting. If the planar size of the electrode 21 is set to be smaller than the chip size of the chip 10, the chip connection electrode 21 and the mounting electrode 11 of the chip 10 can be connected even when burrs caused by dicing exist on the outer periphery of the chip 10. It becomes possible to join stably. Further, the outer dimension of the positioning mark 31 on the chip support substrate 30 is also set so that the outer peripheral edge of the positioning mark 31 is positioned inside the outer peripheral edge of the chip 10, that is, the planar size of the positioning mark 31 is set. If the chip size is set to be smaller than the chip size of the chip 10, the chip connection electrode 21 and the mounting electrode 11 of the chip 10 can be stably bonded even when a burr caused by dicing exists on the outer periphery of the chip 10. It becomes possible.

（実施形態２）
本実施形態の実装方法は実施形態１と略同じであり、図２（ａ）の右側に示すように実装基板２０における各チップ１０それぞれの搭載位置にチップ接続用電極２１を形成するチップ接続用電極形成工程および図２（ａ）の左側に示すように実装基板２０への搭載前の複数個のチップ１０を載置するチップ支持用基板３０において上記搭載位置に対応する各位置にチップ１０を当該チップ１０の実装用電極１１を上面側として載置するチップ載置工程を含む接合準備工程と、接合準備工程の後に図２（ｂ）に示すようにチップ支持用基板３０と実装基板２０とを対応する実装用電極１１とチップ接続用電極２１とが離間して向かい合うように対向配置してから各チップ１０の実装用電極１１および実装基板２０の各チップ接続用電極２１それぞれの表面を一括して活性化させる活性化工程と、活性化工程の後に図２（ｃ）に示すようにチップ支持用基板３０と実装基板２０とを近づけて対応する実装用電極１１とチップ接続用電極２１との全部を常温下で接合する接合工程と、接合工程の後に図２（ｄ）に示すようにチップ支持用基板３０を各チップ１０から引き離す引離工程とを備えており、チップ載置工程において、チップ支持用基板３０として各チップ１０それぞれを位置決めする位置決め凹所３２を一面側に有する基板を用いており、当該位置決め凹所３２の内底面が上記搭載位置に対応する位置を構成している点が相違する。 (Embodiment 2)
The mounting method of the present embodiment is substantially the same as that of the first embodiment. As shown on the right side of FIG. 2A, the chip connection electrode 21 is formed at the mounting position of each chip 10 on the mounting substrate 20. As shown on the left side of the electrode forming step and FIG. 2A, the chip 10 is placed at each position corresponding to the mounting position in the chip support substrate 30 on which the plurality of chips 10 before mounting on the mounting substrate 20 are placed. As shown in FIG. 2B, a chip preparing process including a chip mounting process for mounting the mounting electrode 11 of the chip 10 on the upper surface side, and a chip supporting board 30 and a mounting board 20 as shown in FIG. Are arranged so that the corresponding mounting electrode 11 and the chip connection electrode 21 are spaced apart from each other, and then the mounting electrode 11 of each chip 10 and each chip connection electrode 21 of the mounting substrate 20 An activation process for activating the surfaces collectively, and a mounting electrode 11 and a chip corresponding to each other by bringing the chip support substrate 30 and the mounting substrate 20 close to each other as shown in FIG. 2C after the activation process. A joining step for joining all of the connection electrodes 21 at room temperature, and a separation step for separating the chip support substrate 30 from each chip 10 as shown in FIG. 2 (d) after the joining step; In the chip mounting step, a substrate having a positioning recess 32 for positioning each chip 10 on one side is used as the chip support substrate 30, and the inner bottom surface of the positioning recess 32 corresponds to the mounting position. Is different.

接合準備工程のチップ載置工程で用いるチップ支持用基板３０は、Ｓｉ基板を用いて形成されており、Ｓｉ基板の一表面側に位置決め凹所３２が形成されている。ここにおいて、位置決め凹所３２は、矩形状（チップ１０の外周形状と相似形であり、例えば、正方形状）の内底面と当該内底面に隣り合う内側面とが略垂直となる形状（つまり、チップ支持用基板３０の厚み方向において開口面積が一様となる形状）に設計してあり、各位置決め凹所３２の形成にあたっては、例えば、チップ支持用基板３０の基礎となるＳｉ基板の一表面側に、位置決め凹所３２形成用にパターニングされたレジスト層を形成し、当該レジスト層をマスクとして、Ｓｉ基板を上記一表面側から所定深さまでエッチングし、その後、レジスト層を除去すればよい。なお、位置決め凹所３２の開口寸法（図１（ａ）における左右方向の寸法）はチップ１０の幅（図１（ａ）における左右方向の寸法）よりも１００μｍ程度大きな値に設定し、位置決め凹所３２の深さ寸法は、チップ１０の厚み寸法よりも小さくチップ支持用基板３０の上記一表面を含む平面よりもチップ１０が５０μｍ以上突出するように設定することが望ましい。また、チップ支持用基板３０の基礎となるＳｉ基板を上記一表面側から所定深さまでエッチングする際には、例えば、誘導結合プラズマ型のドライエッチング装置を用いればよいが、形成される位置決め凹所３２の内底面の平滑性が良ければ、エッチング装置やエッチング条件は特に限定するものではない。また、Ｓｉ基板の上記一表面が（１１０）面の場合には、例えばシリコン酸化膜をマスクとして、アルカリ系溶液（例えば、ＫＯＨ水溶液、ＴＭＡＨ水溶液など）を用いた異方性エッチングにより位置決め凹所３２を形成するようにしてもよい。   The chip support substrate 30 used in the chip placement process of the bonding preparation process is formed using a Si substrate, and a positioning recess 32 is formed on one surface side of the Si substrate. Here, the positioning recess 32 has a rectangular shape (similar to the outer peripheral shape of the chip 10, for example, a square shape) and a shape in which the inner side surface adjacent to the inner bottom surface is substantially vertical (that is, The shape is such that the opening area is uniform in the thickness direction of the chip support substrate 30). In forming each positioning recess 32, for example, one surface of the Si substrate that is the basis of the chip support substrate 30 A resist layer patterned for forming the positioning recess 32 is formed on the side, the Si substrate is etched from the one surface side to a predetermined depth using the resist layer as a mask, and then the resist layer is removed. The opening size of the positioning recess 32 (the horizontal dimension in FIG. 1A) is set to a value about 100 μm larger than the width of the chip 10 (the horizontal dimension in FIG. 1A). The depth dimension of the location 32 is preferably set so that the chip 10 protrudes by 50 μm or more from the plane including the one surface of the chip support substrate 30 smaller than the thickness dimension of the chip 10. Further, when etching the Si substrate serving as the basis of the chip support substrate 30 from the one surface side to a predetermined depth, for example, an inductively coupled plasma type dry etching apparatus may be used. If the smoothness of the inner bottom surface of 32 is good, the etching apparatus and etching conditions are not particularly limited. When the one surface of the Si substrate is a (110) plane, for example, a positioning recess is formed by anisotropic etching using an alkaline solution (for example, KOH aqueous solution, TMAH aqueous solution, etc.) using a silicon oxide film as a mask. 32 may be formed.

チップ載置工程では、各位置決め凹所３２それぞれの内底面上に、チップ１０を実装用電極１１が上側となるように直接載置している。なお、チップ支持用基板３０の各位置決め凹所３２の内底面上に各チップ１０を載置するにあたっては、ダイボンド装置を利用しているが、ピックアップツールなどを用いて手作業で載置するようにしてもよい。   In the chip mounting step, the chip 10 is directly mounted on the inner bottom surface of each positioning recess 32 so that the mounting electrode 11 is on the upper side. In order to place each chip 10 on the inner bottom surface of each positioning recess 32 of the chip support substrate 30, a die bonding apparatus is used. However, the chip 10 is placed manually by using a pickup tool or the like. It may be.

しかして、本実施形態の実装方法では、実施形態１と同様に、実装タクトタイムを短縮できるとともにチップ１０の特性劣化を防止でき、しかも、チップ支持基板３０への各チップ１０の位置合わせが容易になるとともに、実装基板２０に対する各チップ１０の位置精度を高めることが可能になる。   Thus, in the mounting method of the present embodiment, as in the first embodiment, the mounting tact time can be shortened, the characteristic deterioration of the chip 10 can be prevented, and the alignment of each chip 10 to the chip support substrate 30 is easy. In addition, the positional accuracy of each chip 10 with respect to the mounting substrate 20 can be increased.

（実施形態３）
本実施形態の実装方法は実施形態２と略同じであり、図３（ａ）の右側に示すように実装基板２０における各チップ１０それぞれの搭載位置にチップ接続用電極２１を形成するチップ接続用電極形成工程および図３（ａ）の左側に示すように実装基板２０への搭載前の複数個のチップ１０を載置するチップ支持用基板３０において上記搭載位置に対応する各位置にチップ１０を当該チップ１０の実装用電極１１を上面側として載置するチップ載置工程を含む接合準備工程と、接合準備工程の後に図３（ｂ）に示すようにチップ支持用基板３０と実装基板２０とを対応する実装用電極１１とチップ接続用電極２１とが離間して向かい合うように対向配置してから各チップ１０の実装用電極１１および実装基板２０の各チップ接続用電極２１それぞれの表面を一括して活性化させる活性化工程と、活性化工程の後に図３（ｃ）に示すようにチップ支持用基板３０と実装基板２０とを近づけて対応する実装用電極１１とチップ接続用電極２１との全部を常温下で接合する接合工程と、接合工程の後に図３（ｄ）に示すようにチップ支持用基板３０を各チップ１０から引き離す引離工程とを備えており、チップ載置工程において、チップ支持用基板３０として位置決め凹所３２の内側面がテーパ状であり且つ内底面の面積がチップ１０のチップ面積よりも小さなものを用いる点が相違する。 (Embodiment 3)
The mounting method of the present embodiment is substantially the same as that of the second embodiment. As shown on the right side of FIG. 3A, the chip connection electrode 21 is formed at the mounting position of each chip 10 on the mounting substrate 20. As shown on the left side of the electrode forming step and FIG. 3A, the chip 10 is placed at each position corresponding to the mounting position in the chip support substrate 30 on which the plurality of chips 10 before mounting on the mounting substrate 20 are placed. As shown in FIG. 3B, a chip preparing process including a chip mounting process for mounting the mounting electrode 11 of the chip 10 on the upper surface side, and a chip supporting board 30 and a mounting board 20 as shown in FIG. Are arranged so that the corresponding mounting electrode 11 and the chip connection electrode 21 are spaced apart from each other, and then the mounting electrode 11 of each chip 10 and each chip connection electrode 21 of the mounting substrate 20 An activation process for activating the surfaces collectively, and a mounting electrode 11 and a chip corresponding to each other by bringing the chip support substrate 30 and the mounting substrate 20 close to each other as shown in FIG. 3C after the activation process. A joining step for joining all of the connection electrodes 21 at room temperature, and a separation step for separating the chip support substrate 30 from each chip 10 as shown in FIG. 3 (d) after the joining step; In the chip mounting process, the chip support substrate 30 is different in that the inner surface of the positioning recess 32 is tapered and the area of the inner bottom surface is smaller than the chip area of the chip 10.

本実施形態において用いるチップ支持用基板３０は、一表面が（１００）面のＳｉ基板の上記一表面側からアルカリ系溶液（例えば、ＴＭＡＨ水溶液、ＫＯＨ水溶液など）を用いた異方性エッチングを行うことにより位置決め凹所３２を形成している。なお、位置決め凹所３２の上記一表面での開口幅および深さ寸法は、上記一表面を含む平面からチップ１０が５０μｍ以上突出するように設計してある。また、位置決め凹所３２は、アルカリ系溶液を用いた異方性エッチングのようなウェットエッチングに限らず、内側面のテーパ角の再現性が高く且つ内側面の平滑性が良いエッチング条件の設定が可能であればドライエッチングにより形成してもよい。   The chip support substrate 30 used in the present embodiment performs anisotropic etching using an alkaline solution (for example, TMAH aqueous solution, KOH aqueous solution, etc.) from the one surface side of the (100) Si substrate. Thus, the positioning recess 32 is formed. The opening width and depth dimension of the positioning recess 32 on the one surface are designed so that the chip 10 protrudes by 50 μm or more from a plane including the one surface. The positioning recess 32 is not limited to wet etching such as anisotropic etching using an alkaline solution, and the etching conditions are set so that the taper angle of the inner surface is highly reproducible and the inner surface is smooth. If possible, it may be formed by dry etching.

チップ載置工程では、各位置決め凹所３２の内底面にチップ１０が接触せずに、各位置決め凹所３２それぞれの内側面にチップ１０の実装用基板１１側とは反対の表面側の外周部が当接し実装用電極１１が上側となるように直接載置している。なお、チップ支持用基板３０の各位置決め凹所３２に各チップ１０を載置するにあたっては、ダイボンド装置を利用しているが、ピックアップツールなどを用いて手作業で載置するようにしてもよい。いずれにしても、チップ支持用基板３０の上記一表面とチップ１０における実装用電極１１の表面とが平行となるように載置する。   In the chip mounting step, the chip 10 does not contact the inner bottom surface of each positioning recess 32, and the outer peripheral portion on the surface side opposite to the mounting substrate 11 side of the chip 10 on each inner surface of each positioning recess 32. Are mounted directly so that the mounting electrode 11 is on the upper side. In addition, when mounting each chip | tip 10 in each positioning recess 32 of the chip | tip support board | substrate 30, although the die-bonding apparatus is utilized, you may make it mount manually by using a pick-up tool etc. . In any case, the chip is mounted so that the one surface of the chip support substrate 30 is parallel to the surface of the mounting electrode 11 in the chip 10.

しかして、本実施形態の実装方法では、実施形態１と同様に、実装タクトタイムを短縮できるとともにチップ１０の特性劣化を防止でき、しかも、位置決め凹所３２の内底面の表面あらさや位置決め凹所３２の深さ寸法のばらつきに起因したチップ１０の高さばらつきを小さくすることができる。   Thus, in the mounting method of the present embodiment, as in the first embodiment, the mounting tact time can be shortened, the characteristic deterioration of the chip 10 can be prevented, and the surface roughness of the inner bottom surface of the positioning recess 32 and the positioning recess. The variation in the height of the chip 10 caused by the variation in the depth dimension of 32 can be reduced.

（実施形態４）
本実施形態の実装方法は実施形態３と略同じであり、図４（ａ）の右側に示すように実装基板２０における各チップ１０それぞれの搭載位置にチップ接続用電極２１ｂを形成するチップ接続用電極形成工程および図４（ａ）の左側に示すように実装基板２０への搭載前の複数個のチップ１０を載置するチップ支持用基板３０において上記搭載位置に対応する各位置にチップ１０を当該チップ１０の実装用電極１１を上面側として載置するチップ載置工程を含む接合準備工程と、接合準備工程の後に図４（ｂ）に示すようにチップ支持用基板３０と実装基板２０とを対応する実装用電極１１とチップ接続用電極２１とが離間して向かい合うように対向配置してから各チップ１０の実装用電極１１および実装基板２０の各チップ接続用電極２１それぞれの表面を一括して活性化させる活性化工程と、活性化工程の後に図４（ｃ）に示すようにチップ支持用基板３０と実装基板２０とを近づけて対応する実装用電極１１とチップ接続用電極２１との全部を常温下で接合する接合工程と、接合工程の後に図４（ｄ）に示すようにチップ支持用基板３０を各チップ１０から引き離す引離工程とを備えており、チップ接続用電極形成工程において、チップ接続用電極２１ｂとしてスタッドバンプからなるバンプを実装基板２０の金属層２１ａ上に形成している点が相違する。 (Embodiment 4)
The mounting method of the present embodiment is substantially the same as that of the third embodiment. As shown on the right side of FIG. 4A, the chip connection electrode 21b is formed at the mounting position of each chip 10 on the mounting substrate 20. As shown on the left side of the electrode forming step and FIG. 4A, the chip 10 is placed at each position corresponding to the mounting position in the chip support substrate 30 on which the plurality of chips 10 before mounting on the mounting substrate 20 are placed. As shown in FIG. 4B, a bonding preparation process including a chip mounting process for mounting the mounting electrode 11 of the chip 10 on the upper surface side, and a chip supporting board 30 and a mounting board 20 as shown in FIG. Are mounted so that the corresponding mounting electrode 11 and the chip connection electrode 21 are spaced apart from each other, and then the mounting electrode 11 of each chip 10 and each chip connection electrode 21 of the mounting substrate 20 are arranged. An activation step for activating the respective surfaces collectively, and a mounting electrode 11 corresponding to the chip support substrate 30 and the mounting substrate 20 as shown in FIG. 4C after the activation step. A joining step for joining all of the chip connection electrodes 21 at room temperature and a separation step for separating the chip support substrate 30 from each chip 10 as shown in FIG. 4D after the joining step are provided. In the chip connection electrode forming step, a bump made of a stud bump is formed on the metal layer 21a of the mounting substrate 20 as the chip connection electrode 21b.

接合準備工程のチップ接続用電極形成工程では、実装基板２０の一表面側の全面にＴｉ膜とＡｕ膜との積層膜を例えばスパッタ法などにより成膜し、その後、フォトリソグラフィ技術およびエッチング技術を利用して上記積層膜をパターニングすることにより、各チップ１０それぞれの搭載位置に上記積層膜の一部からなる金属層２１ａを形成してから、スタッドバンプ法によってチップ接続用電極２１ｂを形成する。ここにおいて、金属層２１ａは、Ａｕ膜と絶縁膜との間に密着性改善用のＴｉ膜を介在させてある。言い換えれば、金属層２１ａは、絶縁膜上に形成されたＴｉ膜と当該Ｔｉ膜上に形成されたＡｕ膜との積層構造を有している。なお、金属層２１ａは、Ｔｉ膜の膜厚を１５〜５０ｎｍ、Ａｕ膜の膜厚を５００ｎｍに設定してあるが、これらの数値は一例であって特に限定するものではない。また、本実施形態では、Ａｕ膜と絶縁膜との間に密着性改善用の密着層としてＴｉ膜を介在させてあるが、密着層の材料はＴｉに限らず、例えば、Ｃｒ、Ｎｂ、Ｚｒ、ＴｉＮ、ＴａＮなどでもよい。また、Ａｕ膜の代わりに、Ａｌ膜を採用してもよい。   In the chip connection electrode forming step of the bonding preparation step, a laminated film of a Ti film and an Au film is formed on the entire surface of one surface side of the mounting substrate 20 by, for example, a sputtering method, and then photolithography technology and etching technology are used. By patterning the laminated film using this, the metal layer 21a made of a part of the laminated film is formed at the mounting position of each chip 10, and then the chip connecting electrode 21b is formed by the stud bump method. Here, in the metal layer 21a, a Ti film for improving adhesion is interposed between the Au film and the insulating film. In other words, the metal layer 21a has a laminated structure of a Ti film formed on the insulating film and an Au film formed on the Ti film. In the metal layer 21a, the thickness of the Ti film is set to 15 to 50 nm, and the thickness of the Au film is set to 500 nm. However, these numerical values are merely examples and are not particularly limited. In this embodiment, a Ti film is interposed between the Au film and the insulating film as an adhesion layer for improving adhesion. However, the material of the adhesion layer is not limited to Ti. For example, Cr, Nb, Zr TiN, TaN, etc. may be used. Further, an Al film may be employed instead of the Au film.

また、チップ接続用電極２１ｂを構成するバンプのサイズは、例えばφ３０μｍ〜φ９０μｍ程度で、１つの金属層２１ａ上に形成するバンプの個数はチップ１０のチップサイズに応じて適宜設定すればよい。なお、金属層２１ａの平面サイズはチップ１０のチップサイズと同じサイズか、やや大きなサイズに設定することが望ましい。チップ接続用電極２１ｂの材料としてはＡｕを採用しているが、Ａｕに限らず、Ａｌでもよいが、チップ接続用電極２１ｂと実装用電極１１とは同じ材料により形成することが望ましい。また、チップ接続用電極２１ｂを構成するバンプはスタッドバンプに限らず、接合工程において荷重を印加した時にチップ１０の高さばらつきを吸収できるような凸型の形状であればよい。   The size of the bumps constituting the chip connection electrode 21b is, for example, about φ30 μm to φ90 μm, and the number of bumps formed on one metal layer 21a may be appropriately set according to the chip size of the chip 10. The planar size of the metal layer 21a is preferably set to the same size as the chip size of the chip 10 or slightly larger. Although Au is adopted as the material of the chip connection electrode 21b, it is not limited to Au, and Al may be used, but it is desirable that the chip connection electrode 21b and the mounting electrode 11 are formed of the same material. The bumps constituting the chip connection electrode 21b are not limited to stud bumps, but may be any convex shape that can absorb the height variation of the chip 10 when a load is applied in the bonding process.

しかして、本実施形態の実装方法では、実施形態１と同様に、実装タクトタイムを短縮できるとともにチップ１０の特性劣化を防止でき、しかも、実装基板２０への実装後の各チップ１０の高さばらつきを低減できる。   Thus, in the mounting method of the present embodiment, as in the first embodiment, the mounting tact time can be shortened, the characteristic deterioration of the chip 10 can be prevented, and the height of each chip 10 after mounting on the mounting substrate 20 can be prevented. Variations can be reduced.

なお、本実施形態におけるチップ接続用電極形成工程を他の実施形態において適用してもよい。   Note that the chip connection electrode forming step in this embodiment may be applied to other embodiments.

実施形態１の実装方法の説明図である。It is explanatory drawing of the mounting method of Embodiment 1. FIG. 実施形態２の実装方法の説明図である。It is explanatory drawing of the mounting method of Embodiment 2. FIG. 実施形態３の実装方法の説明図である。It is explanatory drawing of the mounting method of Embodiment 3. FIG. 実施形態４の実装方法の説明図である。It is explanatory drawing of the mounting method of Embodiment 4.

符号の説明Explanation of symbols

１０ チップ
１１ 実装用電極
１２ 表面側電極
２０ 実装基板
２１ チップ接続用電極
２１ｂ チップ接続用電極（バンプ）
３０ チップ支持用基板
３１ 位置決めマーク DESCRIPTION OF SYMBOLS 10 Chip 11 Mounting electrode 12 Surface side electrode 20 Mounting board 21 Chip connection electrode 21b Chip connection electrode (bump)
30 Chip support substrate 31 Positioning mark

Claims (4)

複数個のチップを１枚の実装基板に実装する実装方法であって、実装基板における各チップそれぞれの搭載位置にチップ接続用電極を形成するチップ接続用電極形成工程および実装基板への搭載前の複数個のチップを載置するチップ支持用基板において前記搭載位置に対応する各位置にチップを当該チップの実装用電極を上面側として載置するチップ載置工程を含む接合準備工程と、接合準備工程の後にチップ支持用基板と実装基板とを対応する実装用電極とチップ接続用電極とが離間して向かい合うように対向配置してから各チップの実装用電極および実装基板の各チップ接続用電極それぞれの表面を一括して活性化させる活性化工程と、活性化工程の後にチップ支持用基板と実装基板とを近づけて対応する実装用電極とチップ接続用電極とを常温下で接合する接合工程と、接合工程の後にチップ支持用基板を各チップから引き離す引離工程とを備え、チップ載置工程では、チップ支持用基板として各チップそれぞれを位置決めする位置決め凹所を一面側に有する基板を用いるようにし、基板として位置決め凹所の内側面がテーパ状であり且つ内底面の面積がチップのチップ面積よりも小さなものを用いることを特徴とする実装方法。 A mounting method for mounting a plurality of chips on a single mounting board, in which a chip connecting electrode is formed at a mounting position of each chip on the mounting board and before mounting on the mounting board. A bonding preparation step including a chip mounting step in which a chip is mounted on each chip corresponding to the mounting position on a chip support substrate on which a plurality of chips are mounted with the mounting electrode of the chip as an upper surface side, and a bonding preparation After the step, the chip support substrate and the mounting substrate are arranged to face each other so that the corresponding mounting electrode and the chip connection electrode are spaced apart from each other, and then the mounting electrode of each chip and each chip connection electrode of the mounting substrate An activation process for activating each surface in a lump, and a mounting electrode and a chip connection electrode corresponding to each other by bringing the chip support substrate and the mounting substrate close to each other after the activation process A bonding step of bonding at a room temperature, and Bei example a引離step of separating the chip supporting substrate from the chip after the bonding step, as in the chip mounting step, the positioning concave positioning each respective chip as the chip supporting substrate A mounting method characterized in that a substrate having a surface on one side is used, and the inner surface of the positioning recess is tapered and the area of the inner bottom surface is smaller than the chip area of the chip . 前記チップにおける前記実装用電極がＡｕにより形成されており、前記チップ接続用電極形成工程では、前記チップ接続用電極をＡｕにより形成することを特徴とする請求項１記載の実装方法。 Wherein the mounting electrodes in the chip are formed by Au, in the chip connecting electrode forming step, mounting method of claim 1, wherein the forming the chip connecting electrodes by Au. 前記チップ接続用電極形成工程では、前記チップ接続用電極の外形寸法を、前記チップの外周縁よりも内側に前記チップ接続用電極の外周縁が位置するように設定することを特徴とする請求項１または請求項２記載の実装方法。 Claims and in the chip connection electrodes forming step, the outer dimensions of the chip connecting electrodes, the outer peripheral edge of said chip connection electrodes on the inner side of the outer peripheral edge of the chip and sets to be located The mounting method according to claim 1 or 2 . 前記チップ接続用電極形成工程では、前記チップ接続用電極としてバンプを形成することを特徴とする請求項１ないし請求項３のいずれか１項に記載の実装方法。 Wherein the chip connection electrodes forming step, mounting method according to any one of claims 1 to 3, characterized in that that form the bump as the chip connecting electrodes.
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