JP4973157B2 - Semiconductor evaluation circuit - Google Patents

Description

  The present invention relates to a semiconductor evaluation circuit, and more particularly to a technique for evaluating characteristics of a large number of semiconductor elements.

  When developing micro processes for semiconductors, TEG (Test Element Group) consisting of elements of various dimensions is fabricated in a semiconductor wafer to evaluate and analyze the characteristics of micro elements (transistors, resistor elements, etc.). We are developing devices that can withstand mass production by setting process conditions based on analysis results.

In the process development so far, the optimum process conditions and transistor structure could be set by evaluating and analyzing the characteristics of individual transistors fabricated in the TEG. Can no longer be ignored.
In addition, the phenomenon that the stress applied to the transistor changes depending on the state of the transistor and the characteristics of the transistor change cannot be ignored.

  From such a situation, for example, in a fine process with a processing level of 45 nm, the characteristics of both transistors vary even if they are adjacent transistors. Therefore, a small signal such as SRAM (Static Random Access Memory) is transferred to a pair transistor (adjacent 2 It is predicted that the detection circuit and the amplification circuit that detect with two transistors) have a reduced operating margin or become inoperable.

  In this case, sufficient data cannot be obtained only by evaluating individual transistors. Therefore, the characteristics of a large number of transistors are evaluated, analyzed by statistical processing, and systematic characteristic differences and characteristic differences due to variations are separated. A large-scale TEG that can be analyzed is required.

  Conventionally, as a TEG for performing large-scale element evaluation, for example, there is a DMA (Device Matrix Array) -TEG in which a plurality of transistors are arranged in a matrix as shown in FIG. reference).

  The configuration of the DMA-TEG according to the prior art will be described below with reference to FIG. DUT11 to DUTnm are transistors to be measured. The drains of the transistors under measurement DUT11 to DUT1m are connected to the common drain line D1, and the sources are connected to the common source line S1. The common drain line D1 is connected via a switch SW2 to a common drain force line (Drain Force) to which a drain voltage is supplied. In order to monitor the voltage of the common drain line D1, the drain voltage sense line DS1 is connected to the drain sense line (Drain Sense) via the switch SW1.

  The common source line S1 is connected to a common source power source (Source Force). Further, in order to monitor the voltage of the common source line S1, the common source line S1 is connected to the source sense line (Source Sense) via the switch SW3. The switches SW1 to SW3 are controlled by an output signal of a decoder (not shown).

  With these sets as one set, the transistors to be measured DUTn1 to DUTnm which are the n-th set are provided with the same connection as described above. The gates of the transistors under test DUT11 to DUTn1 are connected to the common gate line G1, and the gates of the transistors under test DUT1m to DUTnm are connected to the common gate line Gm.

Further, either the gate voltage VG1 or the gate non-selection voltage VGX is supplied to the common gate line G1 through the gate selection circuit 100. When the selection signal EN1 becomes high level (selected), the gate voltage VG1 is supplied to the gate line G1, and when the selection signal EN1 becomes low level (non-selected), the gate non-selection voltage VGX is supplied to the gate line G1. The gate non-selection voltage VGX is normally zero volts, but a negative voltage can be set as required.
With the DMA-TEG having such a configuration, the characteristics of m × n transistors DUT11 to DUTnm can be evaluated.

Here, since the m measured transistors DUT11 to DUT1m are connected in parallel to the common drain line D1, if each of the measured transistors has an off-leak current (current that flows without the transistor being completely turned off), Since a leak current flows through the non-selected transistor under measurement, the characteristics of the transistor under measurement to be measured cannot be accurately evaluated. In this case, for example, the gate non-selection voltage VGX is set to about −0.2 V so as to suppress the off-leak current.
FIG. 1B is a circuit diagram of the switches SW1 to SW3.
Yoshiyuki Shimizu, Mitsuo Nakamura, Toshimasa Matsuoka, and Kenji Taniguchi, `` Test structure for precise statistical characteristics measurement of MOSFETs, '' IEEE 2002 Int. Conference on Microelectronic Test Structure (ICMTS 2002), pp. 49-54, April 2002

  However, according to the above-described conventional DMA-TEG, when a large-scale DMA-TEG (for example, m = n = 512, that is, a TEG that can evaluate 512K transistors) is formed, the common drain line D1 has 512 transistors are connected. Here, when an off-leakage current of about 10 pA flows through the fine transistor, the total of the leakage currents flowing through the non-selected transistors is 10 pA × 511 = 5.1 nA, and cannot be ignored with respect to the drain current flowing through the selected transistor. Therefore, there was a problem that high-precision measurement could not be performed.

  In this case, when −0.3 V is applied to the non-selection gate voltage VGX, the leakage current decreases by one to two digits, which is effective as a countermeasure against leakage current. However, for example, when the drain voltage is 1.0 V, the voltage difference between the drain and the gate is 1.3 V, and a leak current called GiDL (Gate induced Drain Leakage) is generated. That is, the depletion layer near the drain is modulated by the gate voltage, a high electric field is applied to the depletion layer near the surface, and a band-to-band (between energy bands) leak current flows from the drain to the substrate, resulting in measurement accuracy. There was a problem of getting worse.

  The common source lines S1 to Sn are provided with source voltage sense terminals (Source Sense), and the voltages of the common source lines S1 to Sn can be measured. However, one common source line S1 to Sn is provided. Only. Accordingly, for example, the potential difference between the source potentials of DUT 11 and DUT 1m located at both ends of the TEG is caused by the resistances of the common source lines S1 to Sn, so that there is a problem that high-precision measurement cannot be performed.

  Further, since the oxide film of the fine transistor is very thin, gate leakage current flows to the drain and source. Here, since the gates of 512 transistors are connected in parallel to each of the common gate lines G1 to Gm, there is a problem that the gate leakage current cannot be ignored and high-precision measurement cannot be performed.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor evaluation circuit capable of measuring a large-scale semiconductor element with high accuracy.

The present invention has been made to solve the above problems, and a semiconductor evaluation circuit according to the present invention is a semiconductor evaluation circuit including one or a plurality of evaluation cell arrays for evaluating transistor characteristics. The evaluation cell array includes n rows and m columns of evaluation cells arranged in a matrix, m common gate lines for the evaluation cells belonging to each column, and m common sources for the evaluation cells belonging to each column. A line, m common source sense lines for the evaluation cells belonging to each column, n common drain lines for the evaluation cells belonging to each row, and the common drain line is connected to a drain voltage according to a control signal. Alternatively, the third control means for setting the first voltage, the fourth control means for connecting and releasing the common drain line and the drain sense terminal according to the control signal, and the common according to the control signal. Fifth control means for setting the source line to the source voltage or source bias voltage, sixth control means for setting the common gate line to the gate voltage or the first voltage according to the control signal, and the control signal And a seventh control means for connecting and opening the common source sense line and the source sense terminal. The evaluation cell has a drain connected to the common drain line and a source connected to the common source line. A transistor to be measured, a first control means for switching a gate connection destination of the transistor to be measured between the common gate line and the first voltage according to a gate selection signal, and the transistor to be measured The source of the transistor under test is connected to the common source sense line when the gate of the transistor under test is connected to the common gate line; Gate is characterized in that is composed of a second control means for opening the source of 該被 measuring transistor when it is connected to the first voltage.
According to the present invention, a source bias voltage different from the source voltage applied to the source of the transistor under measurement can be applied to the source of the transistor under measurement belonging to a column other than the column to which the transistor under measurement to be evaluated belongs. Further, since the source sense terminal and the drain sense terminal are respectively connected to the source and drain of the transistor under measurement to be evaluated, the source voltage and the drain voltage can be accurately measured. Thereby, the measurement accuracy is increased.
In addition, since a plurality of evaluation cell arrays can be provided, the transistors under measurement belonging to a plurality of sets of evaluation cell arrays can be measured simultaneously, and the measurement speed is improved.

  In the semiconductor evaluation circuit, the first control means has a first end connected to the gate of the transistor under measurement, the other end connected to the common gate line, and a first open / closed state controlled according to a gate selection signal. A second switch that has one end connected to the gate of the transistor under measurement and the other end to which the first voltage is applied and is controlled to be in an open / closed state different from the first switch. The means includes a third switch having one end connected to the source of the transistor under measurement and the other end connected to the common source sense line and controlled to be in the same open / close state as the first switch. Has one end connected to each of the common drain lines, the other end connected to a drain voltage application terminal to which the drain voltage is applied, and one end connected to each of the fourth switches. A plurality of fifth switches connected to the common drain line and applied to the other end with the first voltage, and the fourth control means has one end connected to each common drain line and the other end Includes a plurality of sixth switches connected to the drain sense terminal, and the fifth control means has one end connected to each of the common source lines and the other end to which the source voltage is applied. A plurality of seventh switches connected to the terminals, and a plurality of eighth switches having one end connected to each of the common source lines and the other end connected to a source bias voltage application terminal to which the source bias voltage is applied. A plurality of ninth switches having one end connected to each of the common gate lines and the other end connected to a gate voltage application terminal to which the gate voltage is applied; one end A plurality of tenth switches connected to each of the common gate lines and applied with the first voltage to the other end, and the seventh control means has one end connected to each of the common source sense lines. And a plurality of eleventh switches having the other end connected to the source sense terminal.

In the semiconductor evaluation circuit, the plurality of fourth switches and the plurality of sixth switches are respectively connected to both ends of the common drain line.
In the present invention, the voltage can be measured at a position where no current flows through the common drain line, regardless of which of the transistors under measurement is selected. Therefore, the measurement accuracy is increased.

In the semiconductor evaluation circuit, the plurality of first to eleventh switches are constituted by transistors having a higher withstand voltage than the transistor under measurement.
According to the present invention, the leakage current caused by the transistors constituting the switch can be reduced.

In the semiconductor evaluation circuit, the plurality of first to eleventh switches are NMOS transistors.
In the present invention, the area of the switch can be reduced.

In the semiconductor evaluation circuit, the first voltage is a ground voltage, and the source bias voltage is higher than the ground voltage.
In the present invention, the source bias voltage higher than the ground voltage is applied to the source of the non-selected transistor under measurement belonging to a column other than the column to which the transistor under measurement to be evaluated belongs, and the gate is grounded. The off-leakage current of the measurement transistor can be reduced. Further, since it is not necessary to increase the voltage difference between the gate and the drain of these non-selected transistors under measurement, the leakage current GiDL and the gate leakage current can also be reduced.

In the semiconductor evaluation circuit, the gate voltage, the source voltage, and the drain voltage are applied to a transistor to be measured belonging to the evaluation cell array.
In the present invention, evaluation can be performed by applying a voltage only to the transistor under measurement to be evaluated.

In the semiconductor evaluation circuit, the gate voltage, the source voltage, and the drain voltage are simultaneously applied to all the transistors under measurement belonging to the evaluation cell array.
In the present invention, since a voltage can be simultaneously applied to all the transistors under measurement, a stress test can be performed.

In the semiconductor evaluation circuit, all the eleventh switches from the plurality of first switches are opened, and the leakage currents of the eleventh switches from the plurality of first switches are measured.
In the present invention, since no voltage is applied to all the transistors under measurement, only the leakage current of the switch can be measured.

  According to the present invention, the minute source bias voltage is applied to the source of the non-selected transistor belonging to the column other than the column to which the transistor to be evaluated belongs, and the ground voltage is applied to the gate. The off-leak current, leak current GiDL, and gate leak current of the transistor can be reduced. Therefore, a semiconductor evaluation circuit capable of measuring a large-scale semiconductor element with high accuracy can be realized.

<First Embodiment>
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
FIG. 2 is a circuit diagram of the DMA-TEG according to the embodiment of the present invention.
In the figure, 1-1-1, 21-1, 3-11, 1-1m, 2-1m, 3-1m, 1-n1, 2-n1, 3-n1, 1-nm, 2-nm, 3- nm, 5-1, 5-n, 7-1, 7-m are transistors, 4-1, 4-n, 6-1, 6-n, 8-1, 8-m, 9-1, 9- n, 10-1, 10-n, 11-1, 11-n are switches, DUT11, DUT1m, DUTn1, DUTnm are transistors to be measured, and 30-1, 30-n are inverters.

  In this DMA-TEG, a basic unit including a transistor to be measured forms a matrix of n rows and m columns (m and n are positive integers), but only evaluation cells at four corners of the matrix are provided for easy understanding. It is shown. The transistors under test DUT11 to DUTnm are, for example, 1V type fine transistors with low breakdown voltage, and the other switches are composed of, for example, 3V type transistors with high breakdown voltage.

  The drains of the transistors DUT11 and DUT1m to be measured are commonly connected to the common drain line D1. Further, the drains of the transistors under test DUTn1 and DUTnm are commonly connected to the common drain line Dn.

  The source of the transistor under test DUT11 is connected to the common source line S1 orthogonal to the drain lines D1 and Dn, and is connected to the common source sense line Ss1 via the transistor 3-11 (third switch). Similarly, the source of the transistor under test DUTn1 is connected to the common source line S1, and is also connected to the common source sense line Ss1 via the transistor 3-n1 (third switch).

  The source of the transistor under test DUT1m is connected to the common source line Sm orthogonal to the drain lines D1 and Dn, and is connected to the common source sense line Ssm via the transistor 3-1m. Similarly, the source of the transistor under test DUTnm is connected to the common source line Sm and also connected to the common source sense line Ssm via the transistor 3-nm.

  Further, the gate of the transistor under test DUT11 is connected to the common gate line G1 via the transistor 1-11 (first switch) which is turned on when selected, and the transistor 2-11 (second switch which is turned on when not selected). ) To ground. Similarly, the gate of the transistor DUTn1 to be measured is connected to the common gate line G1 via the transistor 1-n1 (first switch) that is turned on when selected, and the transistor 2-n1 (second transistor) that is turned on when not selected. It is grounded via a switch.

  Similarly, the gate of the transistor DUT1m to be measured is connected to the common gate line Gm via the transistor 1-1m that is turned on when selected, and is grounded via the transistor 2-1m that is turned on when not selected. Further, the gate of the transistor DUTnm to be measured is connected to the common gate line Gm via the transistor 1-nm which is turned on when selected, and is grounded via the transistor 2-nm which is turned on when not selected.

  Furthermore, the gates of the transistors 1-11, 3-11, 1-1m, and 3-1m are commonly connected to a gate selection signal (Gate Sel-1). The gate selection signal (Gate Sel-1) is input to the inverter 30-1, and the output of the inverter 30-1 is commonly connected to the gates of the transistors 2-11 and 2-1m.

  Similarly, the gates of the transistors 1-n1, 3-n1, 1-nm, and 3-nm are commonly connected to a gate selection signal (Gate Sel-n). The gate selection signal (Gate Sel-n) is input to the inverter 30-n, and the output of the inverter 30-n is commonly connected to the gates of the transistors 2-n1 and 2-nm.

The above-described measured transistor DUT11 and transistors 1-11, 21-11, and 3-11 constitute a basic unit (evaluation cell) Unit1-1. The basic units Unit1-1 are arranged in a matrix of n rows and m columns to constitute an evaluation cell array. Further, the transistors 1-11, 11-11 and 3-11 functioning as switches are composed of only NMOS transistors in order to reduce the area of the basic unit Unit1-1 as much as possible.
The evaluation cell array further includes the following configuration to configure the DMA-TEG according to the present embodiment.

  The common drain lines D1 and Dn are connected in common to the drain force line DF via switches 4-1 and 4-n (fourth switches) on the evaluated transistor DUT11 side, and the drain force line DF is connected to the drain force terminal (Drain). Force; drain voltage application terminal). A drain voltage is applied to the drain force terminal (Drain Force).

  The common drain lines D1 and Dn are grounded via the transistors 5-1 and 5-n (fifth switch) on the transistor under test DUT1m side, and the switches 6-1 and 6-n (sixth switch). The drain sense line DS is commonly connected via a switch), and the drain sense line DS is commonly connected to a drain sense terminal (Drain Sense).

  The common source lines S1 and Sn are connected in common to the source force line SF via switches 11-1 and 11-m (seventh switch), respectively, and the source force line SF is connected to one end of the ammeter 20. . The other end of the ammeter 20 is connected to a source force terminal (Source Force; source voltage application terminal). A source voltage is applied to the source force terminal (Source Force).

  The common source lines S1 and Sn are connected in common to the source bias line SB via switches 8-1 and 8-m (eighth switches), respectively. The source bias line SB is a source bias terminal (Source Bias). Common terminal). A source bias voltage is applied to the source bias terminal (Source Bias).

  Further, the common source sense lines Ss1 and Ssm are connected in common to the source sense line SS via switches 9-1 and 9-m (11th switch), respectively, and the source sense line SS is connected to the source sense terminal (Source Sense). Commonly connected.

  The common gate lines G1 and Gm are connected in common to the gate force line GF via switches 10-1 and 10-m (9th switch), respectively. The gate force line GF is a gate force terminal (Gate Force). Application terminal). A gate voltage is applied to the gate force terminal (Gate Force). The common gate lines G1 and Gm are grounded via transistors 7-1 and 7-m (tenth switch), respectively.

  Connections similar to the above are also made for evaluation cells not shown in the figure, and this DMA-TEG has m common gate lines for evaluation cells belonging to each column of the evaluation cell array, and evaluation cells belonging to each column. m common source lines, m common source sense lines for evaluation cells belonging to each column, and n common drain lines for evaluation cells belonging to each row.

  The transistors 1-11 to 1-nm, 2-11 to 2-nm, 3-11 to 3-nm, 5-1 to 5-n, 7-1 to 7-m, and switches 4-1 to 4 are used. -N, 6-1 to 6-n, 8-1 to 8-m, 9-1 to 9-n, 10-1 to 10-n, and 11-1 to 11-n are output from a decoder (not shown). The open / close state is controlled by the control signal. The overall configuration including the decoder will be described later.

Here, the transistors 1-11 to 1-nm, 2-11 to 2-nm and the decoder function as the first control means in the present invention, and the transistors 3-11 to 3-nm and the decoder are the present invention. Functions as the second control means.
The transistor switches 4-1 to 4-n, 5-1 to 5-n and the decoder function as third control means in the present invention, and the switches 6-1 to 6-n and the decoder are connected to the present invention. Functions as the fourth control means. Further, the switches 8-1 to 8-m and 11-1 to 11-m function as fifth control means in the present invention, and the switches 10-1 to 10-m and the transistors 7-1 to 7-m. And the decoder function as sixth control means in the present invention. The switches 9-1 to 9-m and the decoder function as seventh control means in the present invention.

Next, the operation of this DMA-TEG will be described with reference to FIG.
Hereinafter, a case where the transistor under test DUT11 is selected as an evaluation target will be considered. First, the switches 4-1, 9-1, 10-1, and 11-1 are selected and turned on by a decoder (not shown). Further, the gate selection signal (Gate Sel-1) is set to the high level (“1” shown in the figure), the transistors 1-11 and 3-11 are turned on, and the low level “0” is applied to the gate. The transistor 2-11 is turned off. The switches 7-1 and 8-1 are controlled to be off.

  Further, 1 V is applied to the drain force terminal (Drain Force) by a power source (not shown), 1 V is applied to the gate force terminal (Gate Force) by a power source (not shown), and a power source (not shown) is applied to the source force terminal (Source Force). Thus, 0V is applied. As a result, 1 V is applied to the common gate line G1, 1 V is applied to the common drain line D1, and Vss (0 V; first voltage) is applied to the common source line S1.

Even if the voltage applied to the source force terminal (Source Force) is 0V, the source of the transistor DUT11 to be measured (Source Force terminal (Source) via the resistance component of the common source line S1 and the switch 11-1). Force) causes the source voltage of the transistor under test DUT11 to float from 0V. Here, since the source voltage of the transistor under test DUT11 is applied to the common source sense line Ss1 via the transistor 3-11, the source voltage is connected to a source sense terminal (Source Sense) by a voltmeter (not shown). The voltage of a power source (not shown) connected to the source force terminal (Source Force) is adjusted based on the detected voltage, and the source voltage of the transistor DUT 11 to be measured can be accurately set to 0 V (Kelvin measurement).
Then, the current flowing through the transistor under test DUT 11 is measured using the ammeter 20.

  In the same way, the drain voltage of the transistor under test DUT11 is detected by a voltmeter (not shown) connected to the drain sense terminal (Drain Sense) and connected to the drain force terminal (Drain Force) based on the detected voltage. The drain voltage of the transistor DUT 11 to be measured can be accurately set to 1V by adjusting the voltage of the power source (not shown).

  The drain sense terminal (Drain Sense) is a drain force terminal (Drain Force) in order to accurately detect the drain voltage of the transistor under test DUT11 even if a voltage drop occurs due to the wiring resistance of the common drain line D1. It is arranged on the opposite side. With this arrangement, the drain voltage can be accurately detected regardless of which of the transistors under measurement DUT11 to DUT1m is selected.

  Next, the transistor DUT1m that is not selected will be described. Since the switch 10-m is turned off and the switch 7-m is turned on by a decoder (not shown), the common gate line Gm becomes 0V. Further, since the transistor 1-1m is turned on and the transistor 2-1m is turned off by the gate selection signal (Gate Sel-1), 0V is applied to the gate of the transistor DUT1m to be measured, and the transistor is turned off.

Here, since the switch 11-m is off and the switch 8-m is on, 0.3 V is applied to the common source line Sm by a power source (not shown) connected to the source bias terminal (Source Bias). The voltage difference between the gate and the source of the transistor DUT1m becomes −0.3V, and off-leakage is reduced.
Note that the voltage applied to the source bias terminal (Source Bias) is adjusted to a voltage at which no leakage current occurs.
Further, although the transistor 3-1m is on, the switch 9-m is off, so that the source sense terminal (Source Sense) is not affected.

  Next, the transistor DUTn1 that is not selected will be described. Since the gate selection signal (Gate Sel-n) is controlled to a low level “0” by a decoder (not shown), the transistor 1-n1 is turned off and the transistor 2-n1 is turned on. Accordingly, 0 V is applied to the gate of the transistor under test DUTn1. Further, since the switch 4-n is turned off, the switch 6-n is turned off, and the transistor 5-n is turned on, the common drain line Dn becomes 0V. Therefore, the transistor under test DUTn1 is completely turned off and no leakage current is generated.

  Next, the transistor DUTnm that is not selected will be described. Since the transistors 1-nm and 3-nm are off, the transistor 2-nm is on, the switch 4-n is off, the switches 6-n and 8-m are on, and the transistor 5-n is on, the measured transistor DUTnm The gate is 0V, the drain is 0V, and the source is 0.3V. Under this condition, there is a possibility that off-leakage flows backward along the path 300 indicated by an arrow in the figure. However, when the drain voltage is about 0.3 V, the off-leakage is very small. Since it flows to VSS via -n, it does not flow to the drain sense terminal (Drain Sense) and does not affect the measurement accuracy.

In the above-described configuration, the source of the transistors under measurement belonging to the same row is configured to perform Kelvin measurement for each source, and the drain is configured to perform Kelvin measurement using a common drain line (4-terminal Kelvin measurement). The gate does not perform Kelvin measurement, but the current flowing through the common gate line is only the gate leakage current, and its magnitude can be ignored, so there is no particular problem. In addition, when a large current flows through the drain, the layout depends on the location. However, when measuring static characteristics, the pentode characteristics (characteristics in the saturation region) depend on the drain voltage due to the characteristics of the MOS transistor. Therefore, the measurement error is small and not a big problem.
Since the drain voltage and the source voltage of the transistor DUT 11 to be measured can be accurately set using the above-described 4-terminal Kelvin measurement, the measurement accuracy is improved.

  By using the DMA-TEG having such a configuration, it is possible to take measures against off-leakage of a fine transistor, perform three-terminal Kelvin measurement, and take measures against gate leakage current and leakage current GiDL. DMA-TEG can be provided.

FIG. 4 shows an overall circuit diagram of the DMA-TEG including the decoder.
The DMA-TEG includes an address buffer (Address Buffer), an X address predecoder (Pre Dec (X)), a Y address predecoder (Pre Dec (Y)), and a circuit shown in FIG. X address main decoder (Main Dec (X)), Y address main decoder (Main Dec (Y)), pads (AX0 to AX8, AY0 to AY8, Drain Force, Drain Source, Source Force, Source Sense, Gate, GND, Source Bias, DUT Sub, 3V Tr Sub, VDD (3V), VSS (3V)). The X address main decoder (Main Dec (X)) is composed of decoders MDX1 to MDX512, and the Y address main decoder (Main Dec (Y)) is composed of decoders MDY1 to MDU512. The DMA-TEG constitutes a 512 × 512 evaluation cell array composed of basic units Unit1-1 to Unit512-512.

Nine X address signals AX0 to AX8 and nine Y address signals AY0 to AY8 from the pad are respectively sent to an X address predecoder (Pre Dec (X)) and a Y address via an address buffer (Address Buffer). It is input to the predecoder (Pre Dec (Y)). The signal output from the X address predecoder (Pre Dec (X)) is input to the X address main decoder (Main Dec (X)) and output from the X address main decoder (Main Dec (X)). The control signal to be controlled controls each switch. Similarly, the signal output from the Y address predecoder (Pre Dec (Y)) is input to the Y address main decoder (Main Dec (Y)), and the Y address main decoder (Main Dec (Y)). A control signal output from each controls each switch.
Although this DMA-TEG is composed of 512K transistors to be measured and is large-scale, there is little leakage current from the transistors to be measured that are not to be evaluated, and 4-terminal Kelvin measurement is possible, so high-precision measurement can be performed. .

<Second Embodiment>
Next, a second embodiment of the present invention will be described with reference to FIGS.
FIG. 5 is a circuit for adding a test mode to the DMA-TEG of FIG.
The address buffer circuit corresponding to the test mode shown in FIG. 4A is replaced with an address buffer to which X address signals AX0 to AX8 and AY0 to AY8 are input in the DMA-TEG of FIG.
In addition, two test signal input circuits shown in FIG.

  Test signals TEST1 and TEST2 are input to two test signal input circuits, respectively, and inverted test signals TEST1B and TEST2B are output, respectively. The inverted test signals TEST1B and TEST2B are input to all the address buffer circuits corresponding to the test mode described above.

Next, the operation of the DMA-TEG to which this test circuit is added will be described with reference to Tables 1 and 2.
First, as shown in Table 1, when the test signal TEST1 = TEST2 = '0', it is in the normal mode and operates as the normal DMA-TEG described in the first embodiment.
When the test signals TEST1 = "1" and TEST2 = "0", the address buffer output signals axi and axib are both "1", and the DMA-TEG evaluated transistors shown in FIG. Become.

  On the other hand, when the test signal TEST2 = “1”, the address buffer outputs axi and axib are both “0” regardless of the state of the test signal TEST1, and the DMA-TEG evaluated transistors shown in FIG. Selected state.

  Here, in the fully selected state, a voltage is applied to the transistor under measurement via the gate force pad (Gate Force), drain force pad (Drain Force), and source force pad (Source Force) shown in FIG. It is possible to perform a stress test.

Table 2 shows the relationship between the voltage applied to the gate of the transistor under measurement, GF, the drain DF, and the source SF, and the stress test mode. Specifically, when any one of the gate stress mode, the drain stress mode 1 and the drain stress mode 2 is selected and a voltage is applied as shown in Table 2, the voltage is simultaneously applied to all the transistors under test DUT, A stress test can be performed in a short time.
Further, when TEST2 = '1', the switches connected to all the transistors under measurement are turned off, so that all the transistors under measurement are all unselected and no voltage is applied, and the off-leak current of the switches is measured. I can do it.

Next, the switch off-leak will be described. For example, according to the calculation described later, the size of the switch is required to be L (gate length) / W (gate width) = 0.6 μm / 20 μm in the case of an NMOS transistor, for example. At this time, considering the switches connected to the drain force line DF, for example, since there are 512 switches, the total W (gate width) of the switches is 10240 um, which is a huge transistor. In an ordinary 3V transistor, the off-leakage current is about 10 ⁻¹⁴ A (0.01 pA) to 10 ⁻¹³ A (0.1 pA) per unit W (gate width) (that is, per W = 1 μm), so W = 10240 μm. The off-leakage current of this transistor is about 100 pA to 1 nA.

Normally, when measuring the threshold value of the transistor under measurement, the current value of about 100 nA to 1 μA is used. In this case, the off-leakage current of the switch is negligible. When the off-leakage current is deteriorated to about 10 ⁻¹² (1 pA), the off-leakage current flows as much as 10 nA, and the transistor under measurement cannot be evaluated with high accuracy. In this case, it is necessary to determine the off-leakage current in the above-described all non-selection test mode.

Next, switch optimization will be described.
In the example described above, the CMOS type is used as the switch. Here, a comparison is made between the CMOS type switch and the NMOS only switch.
FIG. 6A shows a CMOS type switch, and FIG. 6B shows an NMOS type switch. In order to compare the two types of switches, first, the load characteristics of the PMOS transistor and the NMOS transistor are compared.

  FIG. 7 shows load characteristics of the PMOS transistor and the NMOS transistor. This figure shows the relationship between the drain current Id (vertical axis) and the output voltage Vout (horizontal axis) when the drain voltage Vd of the PMOS transistor and NMOS transistor in a certain manufacturing process is used as a parameter. The size of the PMOS transistor whose characteristics are shown in the figure is L / W = 0.6 / 20 μm, and the size of the NMOS transistor is L / W = 0.6 / 10 μm.

  The characteristic of the PMOS transistor is that almost no current flows regardless of the output voltage Vout when the drain voltage Vd = 1.2V. This is because the current drive capability is lowered because the threshold value of the PMOS transistor is high. That is, since the current flowing through the PMOS transistor is proportional to the square of | (Vg−Vd−Vthp) | in the saturation region, if the threshold Vthp = 0.8V, | Vg−Vd−Vthp | = | 0−1.2. It can be seen that −0.8 | = 0.4V and the current driving capability is small. Note that the current drive capability increases as the drain voltage Vd is increased.

  On the other hand, since the gate voltage of the NMOS transistor is 3.3V, it operates in the tripolar region even when the threshold Vthn = 0.8V, so that the load characteristic is almost linear. For example, when the output voltage Vout = 1.0V, the drain current Id = If a current of 500 μA is to be passed, the drain voltage Vd = 1.2V is sufficient. Accordingly, switches for evaluating the 1V system transistor DUT (for example, the switches 4-1 to 4-n, 6-1 to 6-n, 8-1 to 8-m, 9-1 shown in FIG. 2). ~ 9-n, 10-1 to 10-n, 11-1 to 11-n) can be seen that there is no problem with the configuration of only NMOS transistors. Thereby, the area of a switch and an evaluation unit can be made small.

Next, the size of the switch used for the DMA-TEG of the present invention is set.
FIG. 8 shows an equivalent circuit diagram of the transistor under measurement and the switch. First, the maximum current flowing through the transistor under test DUT is determined. If the dimension of the transistor DUT to be measured is an NMOS transistor having a maximum L / W = 0.06 / 2 μm, for example, in a certain manufacturing process, a drain current of about 1 mA under the condition of drain voltage Vd = gate voltage Vg = 1.0V. Flows.

  From the simulation results shown in FIG. 7, in order to set the drain voltage Vd of the transistor under test DUT to 1.0 V and to supply 1 mA to the drain switch (Drain SW), it is applied to the drain and source of the drain switch (Drain SW). Therefore, the drain switch (Drain SW) must have a dimension of W = 20 μm. Similarly, the size of the source switch (Source SW) may be set to W = 20 μm. At this time, the source voltage VSforce = −0.2V. That is, in this case, the resistance values of the drain switch (Drain SW) and the source switch (Source SW) are each set to 200Ω.

  The reason why the voltage difference between the drain force voltage VDforce (1.2 V) and the drain voltage Vd (1.0 V) of the transistor DUT to be measured is set to 0.2 V is to speed up the four-terminal Kelvin measurement using a tester described later. Because.

Next, measurement of this DMA-TEG will be described.
FIG. 9 shows a schematic diagram of a tester system at the time of four-terminal Kelvin measurement. In the figure, a drain force pad (Drain Force Pad) and a drain sense pad (Drain Sense Pad) connected to the transistor DUT to be measured are a force probe, a sense probe, and a coaxial cable 901. The path connected to the tester 900 via is shown. Further, the total resistance from the drain force pad (Drain Force Pad) and the measured transistor DUT in the DMA-TEG is a resistance Rforce, and the total resistance from the drain sense pad (Drain Sense Pad) to the measured transistor DUT is a resistance Rsense. .

Here, the time required for measurement in the tester 900 is basically determined depending on the resistance on the signal path from the drain terminal of the transistor under test DUT to the tester 900 and the parasitic capacitance. When performing four-terminal Kelvin measurement of a single transistor, the resistances Rforce and Rsense are almost zero, and the resistance and parasitic capacitance of the probe system of the tester 900 are not so large, so that the measurement time is not affected. However, in the case of DMA-TEG, the values of resistances Rforce and Rsense increase depending on the design method, and when the resistances Rforce and Rsense increase, the time constant of the measurement system increases and the measurement time increases. Problems arise.
Therefore, it is necessary to determine the values of the resistors Rforce and Rsense in consideration of the measurement time. The resistance values of the DMA-TEG wires and switches are shown below.

  FIG. 10 is a circuit diagram for explaining the resistance value of each DMA-TEG wiring. This DMA-TEG has a basic block (evaluation cell array) in which 512 basic units are arranged in a vertical direction (column direction) and 128 in the horizontal direction (row direction) as one block. By arranging four blocks horizontally (in the row direction), a DMA-TEG in which 512 transistors to be measured and 128 × 4 = 512 transistors in total are arranged. The size of one basic unit Unit is 9 μm in both length and width.

  Here, the basic unit Unit 512-128 is considered in order to estimate the maximum wiring resistance. The basic unit Unit 512-128 is connected to a drain force pad (Drain Force) via a common drain line D512, a switch 4-512, and a drain force line DF, and is connected to a drain sense pad via a switch 6-512 and a drain sense line DS. (Drain Sense), connected to the source force pad (Source Force) via the common source line S128, the switch 11-128, and the source force line SF, and the common source sense line SS128, the switch 9-128, and the source sense line. It is connected to the source sense pad (Source Sense) via SS.

  The resistances of these paths are mainly the resistances of the transistors constituting the switches 4-512, 6-512, 9-128, and 11-128 and the metal wiring resistance. In the figure, the metal wiring width and resistance values R1 to R4 are shown in the path wired by metal. For example, the drain force line DF connected to the drain force pad (Drain Force) is set to a wiring width of 20 μm that has a resistance value R1.

  FIG. 11 shows an equivalent circuit diagram in which the wiring resistance of the DMA-TEG is added. FIG. 4A shows the resistance value of the drain system of the transistor under measurement, and FIG. 4B shows the resistance value of the source system. With reference to FIG. 10, the process of estimating the wiring resistance will be described below. In the case of the drain system shown in FIG. 11A, the drain force line DF is a wiring in the vertical direction (column direction), and the wiring length per basic unit Unit is 9 μm. Therefore, the total wiring length is 9 μm × 512 = 4608 μm. Here, if the wiring distance to the drain force pad (Drain Force) is taken into consideration, the length of the drain force line DF is about 6000 μm. When the wiring width is set to 20 μm, since the resistance value ρs = 0.18Ω / □ per unit length of the metal wiring, the total resistance R1 of the drain force line DF is R1 = 6000 ÷ 20 × 0.18 = 54Ω. .

  Similarly, since the common drain line D512 has a wiring length of 9 μm in the basic unit, the total wiring length is 9 μm × 128 = 1152 μm. Since the wiring width is set to 3 μm, the resistance value R2 of the common drain line D512 is R2 = 11152/3 × 0.18 = 69Ω. Similarly, the resistance value R3 of the drain sense line DS is R3 = 108Ω.

  Next, the resistance of the switch is estimated. The transistor size of the switch 4-512 on the drain force pad (Drain Force) side is W = 20 μm, and the transistor size of the switch 6-512 on the drain sense pad (Drain Sense) side is W = 2 μm. Based on the estimation described with reference to FIG. Accordingly, as shown in FIG. 11A, the resistance from the drain force pad (Drain Force) to the drain of the transistor under test DUT is 323Ω, and the resistance from the drain of the transistor under test DUT to the drain sense pad (Drain Sense) is 2108Ω.

  Similarly, when the resistance value of the source system shown in FIG. 11B is calculated, the resistance value R1 of the source force line SF = 54Ω, the resistance value R2 of the common source line S128 = 276Ω, and the resistance value of the common source sense line Ss128 R3 = 2700Ω, and the resistance value of the source sense line SS R4 = 108Ω. Therefore, the resistance from the source force pad (Source Force) to the source of the measured transistor DUT is 430Ω, and the resistance value from the measured transistor DUT to the source sense pad (Source Sense) is 3808Ω. Here, the resistance value from each pad to each terminal of the transistor DUT to be measured was set to 500Ω or less in consideration of the measurement time from the consideration of the tester measurement system described with reference to FIG.

Next, FIG. 12 shows an overall block diagram of the DMA-TEG. In the figure, input pads such as address inputs and test terminals are not shown.
In the figure, 1200 is a column address buffer, 1201 is a row address buffer, 1202 is a column predecoder, 1203 is a row predecoder, 1210-1 to 1210-4 are column decoder & SW, and 1220-1 to 1220-4 are row decoders. & SWs 1230-1 to 1230-4 are evaluation cell arrays.

  The evaluation cell arrays 1230-1 to 1230-4 are divided into four parts, and the drain wiring resistance is reduced as described above. In this configuration, the four terminals of the drain force pad (Drain Force), the drain sense pad (Drain Sense), the source force pad (Source Force), and the source sense pad (Source Sense) are divided into four evaluation cell arrays 1230. Wiring resistance is reduced as much as possible by providing each of -1 to 1230-4.

  Gate pad (DUT Gate), Sub voltage pad (DUT Sub), source bias input pad (Source Bias), 3V transistor Vcc (3V Tr Vcc), GND (3V Tr GND), etc. connected to the transistor DUT to be measured Since the resistance value is hardly a problem, it may be common to each array. Of course, when there is a margin in the total number of terminals, there is a degree of freedom such as providing a gate pad (DUT Gate) for each evaluation cell array.

  If the number of terminals is limited and the wiring resistance can be relaxed somewhat, the drain force pad (Drain Force), drain sense pad (Drain Sense), and source provided separately in the four evaluation cell arrays The four terminals of the force pad (Source Force) and the source sense pad (Source Sense) may be shared.

Next, the operation of this DMA-TEG will be described.
First, an address is input to a column address buffer 1200 and a row address buffer 1201 from an address input pad (not shown). The column address buffer 1200 outputs a signal corresponding to the input address to the column predecoder 1202, and the column predecoder 1202 decodes the signal and outputs it to the column decoders & SWs 1210-1 to 1210-4. The column decoders & SWs 1210-1 to 1210-4 control the open / close state of the internal switches in accordance with the input signals, and control each of the transistors under measurement in the evaluation cell arrays 1230-1 to 1230-4 corresponding to the addresses. Connect the source force pad (Source Force) and the source sense pad (Source Sense).

  Similarly, the row decoders & SWs 1220-1 to 1220-4 control the open / close state of the internal switches according to the input signals, and each of the evaluation cell arrays 1230-1 to 1230-4 corresponding to the addresses. Connect Drain Force, Drain Sense, and DUT Gate to the transistor under test.

Then, by applying a voltage to each pad, the transistor under measurement can be evaluated as in the first embodiment. Here, in this DMA-TEG, four transistors under measurement belonging to each of the four evaluation cell arrays 1230-1 to 1230-4 can be measured simultaneously, so that the evaluation speed is improved fourfold.
Also, the test mode described above can be set.

Next, a schematic diagram of the layout of the basic unit is shown in FIG. This schematic diagram shows a basic unit Unitn-m belonging to n rows and m columns. In order to facilitate understanding, contact holes, via holes and the like are omitted, and a schematic arrangement of each component is shown.
In the figure, 1300 represents the layout of the transistor under test DUTnm, and 1310 represents the layout of the transistors 1-nm, 2-nm, and 3-nm.

As shown in the figure, the transistor DUTnm to be measured is located at the lower right of the basic unit Unitn-m, and the three 1-V, 2-nm, and 3-nm transistors for the 3V switch are located on the left side. . The 1V system measured transistor DUTnm and the 3V system switch transistors 1-nm, 2-nm, and 3-nm separate the wells in which they are arranged, and the potentials of the wells are set respectively. The
Thus, the transistor under test DUTnm and the transistors 1-nm, 2-nm, and 3-nm belonging to one basic unit Unitn-m are arranged adjacent to each other.

As mentioned above, although embodiment of this invention was explained in full detail, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included.
For example, the number of transistors to be measured is not limited to the above example. In addition, the relationship between rows and columns may be interchanged.
Further, the switch used in the DMA-TEG described in the first embodiment may be an NMOS transistor.

It is a circuit diagram of DMA-TEG which concerns on a prior art. 1 is a circuit diagram of a DMA-TEG according to a first embodiment of the present invention. It is a circuit diagram for demonstrating operation | movement of DMA-TEG same as the above. It is a whole circuit diagram of DMA-TEG including a decoder same as the above. It is a circuit for adding a test mode to the DMA-TEG according to the second embodiment of the present invention. It is a circuit diagram which shows a CMOS type switch and NMOS type switch same as the above. It is a load characteristic view of the same PMOS transistor and NMOS transistor. It is an equivalent circuit diagram of a transistor under measurement and a switch same as the above. It is the schematic of the tester system at the time of the four terminal Kelvin measurement same as the above. It is a circuit diagram for demonstrating the resistance value which each wiring of DMA-TEG same as the above has. It is the equivalent circuit diagram which added the wiring resistance of DMA-TEG same as the above. It is a whole block diagram of DMA-TEG same as the above. It is a layout figure of a DUT unit same as the above.

Explanation of symbols

  1-1-1, 21-1, 3-11, 1-1m, 2-1m, 3-1m, 1-n1, 2-n1, 3-n1, 1-nm, 2-nm, 3-nm, 5- 1,5-n, 7-1,7-m transistor, 4-1,4-n, 5-1,5-n, 6-1,6-n, 8-1,8-n, 9-1 , 9-n, 10-1, 10-n, 11-1, 11-n switch, DUT11, DUT1m, DUTn1, DUTnm measured transistor, 30-1, 30-n inverter

Claims (9)

A semiconductor evaluation circuit including one or a plurality of evaluation cell arrays for evaluating transistor characteristics,
The evaluation cell array includes:
Evaluation cells of n rows and m columns (n and m are positive integers) arranged in a matrix,
M common gate lines for the evaluation cells belonging to each column;
M common source lines for the evaluation cells belonging to each column;
M common source sense lines for the evaluation cells belonging to each column;
N common drain lines for the evaluation cells belonging to each row;
Third control means for setting the common drain line to a drain voltage or a first voltage according to a control signal;
Fourth control means for connecting and opening the common drain line and the drain sense terminal in response to the control signal;
Fifth control means for setting the common source line to a source voltage or a source bias voltage according to the control signal;
Sixth control means for setting the common gate line to a gate voltage or the first voltage according to the control signal;
A seventh control means for connecting and opening the common source sense line and the source sense terminal according to the control signal;
The evaluation cell is
A transistor under test having a drain connected to the common drain line and a source connected to the common source line;
First control means for switching a connection destination of the gate of the transistor under measurement between the common gate line and the first voltage in response to a gate selection signal;
When the gate of the measured transistor is connected to the common gate line, the source of the measured transistor is connected to the common source sense line, and when the gate of the measured transistor is connected to the first voltage And second control means for opening the source of the transistor under measurement. A first switch having one end connected to the gate of the transistor under measurement, the other end connected to the common gate line, and an open / closed state controlled according to a gate selection signal;
A second switch that has one end connected to the gate of the transistor under measurement and the other end to which the first voltage is applied and is controlled to be in an open / closed state different from the first switch;
The second control means includes a third switch having one end connected to the source of the transistor under measurement and the other end connected to the common source sense line and controlled to be in the same open / close state as the first switch,
A plurality of fourth switches having one end connected to each of the common drain lines and the other end connected to a drain voltage application terminal to which the drain voltage is applied;
A plurality of fifth switches having one end connected to each of the common drain lines and the other end to which the first voltage is applied;
The fourth control means includes a plurality of sixth switches having one end connected to each of the common drain lines and the other end connected to the drain sense terminal,
A plurality of seventh switches having one end connected to each of the common source lines and the other end connected to a source voltage application terminal to which the source voltage is applied;
A plurality of eighth switches having one end connected to each of the common source lines and the other end connected to a source bias voltage application terminal to which the source bias voltage is applied;
A plurality of ninth switches having one end connected to each of the common gate lines and the other end connected to a gate voltage application terminal to which the gate voltage is applied;
A plurality of tenth switches having one end connected to each of the common gate lines and the other end to which the first voltage is applied;
2. The semiconductor evaluation according to claim 1, wherein the seventh control unit includes a plurality of eleventh switches having one end connected to each of the common source sense lines and the other end connected to a source sense terminal. circuit.   The semiconductor evaluation circuit according to claim 2, wherein the plurality of fourth switches and the plurality of sixth switches are respectively connected to both ends of the common drain line.   4. The semiconductor evaluation circuit according to claim 2, wherein the plurality of first to eleventh switches are constituted by transistors having a higher breakdown voltage than the transistor under measurement. 5.   5. The semiconductor evaluation circuit according to claim 2, wherein the plurality of first to eleventh switches are NMOS transistors. 6. The first voltage is a ground voltage;
6. The semiconductor evaluation circuit according to claim 1, wherein the source bias voltage is higher than the ground voltage.   7. The device according to claim 1, wherein the gate voltage, the source voltage, and the drain voltage are applied to a transistor under measurement to be evaluated belonging to the evaluation cell array. 8. Semiconductor evaluation circuit.   The gate voltage, the source voltage, and the drain voltage are simultaneously applied to all the transistors under measurement belonging to the evaluation cell array. Semiconductor evaluation circuit.   The eleventh switch is opened from the plurality of first switches, and the leakage current of the eleventh switch from the plurality of first switches is measured. The semiconductor evaluation circuit described in 1.

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