JP4961232B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention suppresses a step of a substrate such as a wafer that occurs in a manufacturing process (process) of a semiconductor device, and defocuses during defocusing (photofocusing). The present invention relates to a method for manufacturing a semiconductor device that prevents occurrence of pattern defects due to deviation.

  In the method for manufacturing a semiconductor device, the following processes (1) to (7) are performed, for example, in a photoetching process for forming a wiring pattern on a substrate such as wear via an insulating film.

(1) Formation of metal film A metal film for wiring pattern is deposited on the entire surface of the insulating film formed on the substrate.

(2) Photoresist application A photoresist is applied to the entire surface of the metal film.

(3) Positioning / Exposure In the manufacturing process of a semiconductor device, since the photoetching process is performed several times, it is necessary to match the relative positions of the pattern of the photomask and the pattern on the substrate. This is called mask alignment. Thereafter, the photoresist is irradiated with ultraviolet light (hereinafter referred to as “UV light”) through a photomask (exposure).

(4) Development After exposure, a development resist pattern is obtained with an organic solvent or the like (development).

(5) Etching Using the resist pattern as a mask, the metal film is etched to form a wiring pattern.

(6) Resist removal After etching, an unnecessary resist pattern is removed (resist removal).

(7) Insulating film formation In order to protect the wiring pattern, an insulating film is formed on the wiring pattern.

  In order to suppress the step of the insulating film, chemical mechanical polishing (Chemical polishing) that planarizes the surface of the insulating film on the wafer using a rotatable polishing pad, for example, as described in the following documents, etc. Mechanical Polishing, hereinafter referred to as “CMP”) is used.

JP 2003-140319 A

  3A and 3B are partial manufacturing process diagrams in the conventional method for manufacturing a semiconductor device described in Patent Document 1 and the like.

  In the insulating film forming step of FIG. 3A, a high density plasma CVD (High Density Plasma-Chemical Vapor Deposition, hereinafter referred to as “HD”) is formed on the wiring pattern 2-1 formed on the substrate 1 such as a wafer via the insulating film. A film to be polished (for example, an oxide film such as silicon dioxide (SiO 2) or an interlayer insulating film) 3-1 is deposited by “-CVD”) or the like. The surface of the film to be polished 3-1 has local unevenness and steps depending on the unevenness of the wiring pattern 2-1. As a result, in a multi-layer wiring structure or the like for high integration, a defect such as a short circuit between layers, a short circuit between wirings, and an open occurs, resulting in a decrease in yield and reliability. Therefore, a flattening process is necessary.

  In the planarization step of FIG. 3B, when the polishing target film 3-1 is planarized using CMP, the underlying wiring pattern density (the wiring pattern on the substrate is changed) in the polished target film 3-1a. The polishing rate varies depending on the ratio of the area to be disposed to the total area of the substrate. For example, a region (sparse region) where the wiring pattern density on the right side is lower than the film thickness D1 of a region (dense region) where the wiring pattern density on the left side of the film 3-1a to be polished shown in FIG. The film thickness D2 becomes smaller (D1> D2), and a remaining film thickness difference (= D1-D2, the remaining film thickness difference after CMP is hereinafter referred to as “global step”) is generated. In order to suppress the occurrence of this global level difference, methods as shown in FIGS. 4A and 4B have been proposed.

  4A and 4B are partial manufacturing process diagrams in the conventional method for manufacturing a semiconductor device described in Patent Document 1 and the like. Elements common to those in FIG. The common code | symbol is attached | subjected.

  4A, when the wiring pattern 2-1 is formed on the substrate 1 such as a wafer via an insulating film, a dummy (for example, a sparse region on the right side of the wiring pattern 2-1 is formed. A pseudo) wiring pattern 4 is formed, and the surface of the film to be polished 3-1 deposited by HD-CVD or the like is flattened on the wiring pattern 2-1 and the dummy wiring pattern 4.

  4B, when the polishing target film 3-1 is flattened using CMP in the flattening step of FIG. 4B, the pattern density of the base is uniformized in the flattened polishing film 3-1a. Therefore, the film thickness D1 in the left region and the film thickness D2 in the right region in FIG. 4B are substantially equal, and the occurrence of a global step can be suppressed.

  FIG. 5 is a manufacturing process diagram for explaining a problem in the conventional method of manufacturing a semiconductor device, and common elements to those in FIGS. 3 and 4 are denoted by common reference numerals.

  In the conventional manufacturing method for forming the dummy wiring pattern 4 as shown in FIG. 4, for example, a substrate located below the portion where the light-shielding (non-transparent) dummy wiring pattern 4 such as a metal wiring is to be generated. When a photoelectric conversion element (for example, a light receiving element such as an optical sensor) 5 is formed on 1, a dummy wiring pattern 4 as shown by a broken line in FIG. Since the light incident through 3-1a does not reach the light receiving element 5, a portion where the dummy wiring pattern 4 cannot be arranged is generated, so the dummy wiring pattern method cannot be adopted.

  However, when the dummy wiring pattern method is not adopted, particularly in the multilayer wiring structure, for example, a second-layer wiring pattern 2-2 is formed on the first-layer polishing film 3-1a. In addition, a second layer of the polished film 3-2a, a third layer of the wiring pattern 2-3, and the like are sequentially stacked, and CMP is repeated for each of the layers of the polished film 3-1a, 3-2a,. It is. As a result, as shown by the solid line in FIG. 5, when CMP is repeated with multilayer wiring, the global step (= D11−D12) between the total film thickness D11 in the left region and the total film thickness D12 in the right region is significant. In the photoetching process, for example, there is a problem that the depth of focus at the time of exposure when the second layer of the polishing target film 3-2a in the right region is generated cannot be secured, and a pattern defect occurs.

In the method of manufacturing the semiconductor device of the present invention, the photoelectric conversion elements mounted on a substrate (e.g., light receiving element) a first step of forming a first insulating film you covering and the circuit section, by CMP, the first A second step of planarizing the surface of the insulating film; and a light-shielding property that is located on the circuit unit and electrically connected to the circuit unit on the first insulating film having a planarized surface. A third step of forming a wiring pattern and a dummy pattern for suppressing a global step located on the photoelectric conversion element and covering the photoelectric conversion element; and a second insulating film covering the wiring pattern and the dummy pattern Etching the fourth step of forming the fifth step, planarizing the surface of the second insulating film by CMP, etching the dummy pattern and the first insulating film and the second insulating film located therebelow Selectively And a sixth step of exposing the photoelectric conversion element removed by.

  According to the method for manufacturing a semiconductor device of the present invention, since the dummy step for suppressing the global level difference is arranged in the region covering the photoelectric conversion element, the photoelectric conversion element region is not excessively recessed in the upper layer process, and the global range is kept within a certain range. A step can be maintained. This makes it possible to prevent pattern defects due to defocusing in the photoetching exposure process when creating an upper layer hole, wiring pattern, or the like.

In the method of manufacturing a semiconductor device, the photoelectric conversion elements mounted on a substrate (e.g., light receiving element) a first step of forming a first insulating film you covering and the circuit section, by CMP, the first insulating film A second step of planarizing the surface, and a light-shielding wiring pattern located on the circuit unit and electrically connected to the circuit unit on the first insulating film having the planarized surface A third step of forming a global step suppressing dummy pattern located on the photoelectric conversion element and covering the photoelectric conversion element, and forming a second insulating film covering the wiring pattern and the dummy pattern A fourth step, a fifth step of planarizing the surface of the second insulating film by CMP, and selective etching of the dummy pattern and the first insulating film and the second insulating film located therebelow. To remove And a sixth step of exposing the serial photoelectric conversion element.

In the sixth step, for example, the dummy pattern and the first insulating film and the second insulating film located therebelow are removed by photo-etching using the resist pattern as a mask.

(Manufacturing method of Example 1)
FIGS. 2-1 (a) to (e), FIGS. 2-2 (f) to (i), and FIGS. 2-3 (j) to (l) are semiconductors in the multilayer wiring structure of Example 1 of the present invention. It is a manufacturing process figure of the general | schematic longitudinal cross-section which shows the manufacturing method of an apparatus. 1 (A) to 1 (C) are the same manufacturing process diagrams corresponding to FIGS. 2-3 (j) to (l).

  In the manufacturing method of the semiconductor device in the multilayer wiring structure of the first embodiment, for example, it is manufactured by the following steps (1) to (12).

(1) Metal film formation / resist coating process of FIG. 2-1 (a) A substrate 10 such as a Si wafer is prepared. The area of the substrate 10 is divided into a wiring part 11 and a photoelectric conversion part (for example, a light receiving element part) 12. A semiconductor element or the like (not shown) is formed on the wiring portion 11 of the substrate 10, and the light receiving element portion 12 of the substrate 10 has a light receiving element (for example, a planar length L 1 for converting incident light into electricity) (Photodiode, phototransistor, etc.) 13 is formed. On the wiring part 11 of the substrate 10, a first light-shielding metal film (metal film) 14-1 for a wiring pattern is formed via an insulating film (for example, SiO2) not shown. At this time, the metal film 14-1 is not formed on the light receiving element portion 12. A photoresist 15-1 is applied to the entire surface of the metal film 14-1, except for the light receiving element portion 12. After applying the resist, if necessary, heat treatment (pre-baking) is performed to remove the solvent remaining in the coating film.

(2) Alignment / Exposure Process in FIG. 2-1 (b) In the manufacturing process of the semiconductor device, since the photoetching process is performed several times, relative alignment between the pattern of the photomask 16 and the pattern on the substrate is performed. Perform (mask alignment). Thereafter, UV light 17 is irradiated (exposure).

(3) Development Step in FIG. 2-1 (c) After exposure, development is performed with an organic solvent or the like to obtain a resist pattern 15-1a of the photoresist 15-1 (development). After development, if necessary, heat treatment (post-bake) is performed to improve the adhesion between the resist pattern 15-1a and the first metal film 14-1 before etching.

(4) Etching Step in FIG. 2-1 (d) Using the resist pattern 15-1a as a mask, the first metal film 14-1 is etched.

(5) Resist Stripping Step in FIG. 2-1 (e) When the resist pattern 15-1a that is no longer needed is stripped and removed, a first-layer metal wiring pattern 14-1a is obtained on the wiring portion 11.

(6) Insulating film forming step in FIG. 2-2 (f) A film to be polished which is the first insulating film of the first layer (for example, an oxide film such as SiO 2 or an interlayer insulating film) is formed on the entire surface by using DP-CVD or the like. ) 20-1 is deposited to a predetermined thickness. Since the surface of the film to be polished 20-1 has local unevenness and steps depending on the unevenness of the wiring pattern 14-1a, a planarization process is required.

(7) Flattening Step in FIG. 2-2 (g) The surface of the first film to be polished 20-1 is flattened using CMP. In this flattening process, the polishing rate varies depending on the underlying wiring pattern density. For example, the light receiving element portion on the right side as compared with the film thickness d1 of the polished film 20-1a after polishing in the region (dense region) where the wiring pattern density is high in the wiring portion 11 on the left side in FIG. 12 and the thickness d2 of the polished film 20-1b after polishing in the region (sparse region) where the wiring pattern density is low in the wiring part 11 are reduced (d1> d2), and a global step (= d1-d2) is generated. .

(8) Resist pattern forming step in FIG. 2-2 (h) Photoresist is applied to the entire surfaces of the polished films 20-1a and 20-1b after polishing, and exposure and development using a photomask are performed in the same manner as described above. Then, a resist pattern 15-2a of the photoresist is formed.

(9) Conductor Embedding Step in FIG. 2-2 (i) Using the resist pattern 15-2a as a mask, the second-layer polished films 20-1a and 20-1b are etched to form the first-layer wiring pattern 14 A plurality of holes (openings) extending in a cylindrical shape in the vertical direction are formed on -1a, and these cylindrical holes are filled with a conductor 22-1, such as tungsten. Thereafter, if the resist pattern 15-2a is removed, a hole pattern made of a plurality of columnar conductors 22-1 electrically connected in the vertical direction to the first wiring pattern 14-1a is formed. Ru

(10) Wiring pattern / polished film forming step of FIGS. 2-3 (j) and 1 (A) Almost the same as the above (a), the entire surface of the first film to be polished 20-1a, 20-1b Then, a second light-shielding metal film is formed, and a photoresist is applied to the entire surface of the metal film. In substantially the same manner as in (b), mask alignment is performed, and after exposure, development is performed in substantially the same manner as in (c) to obtain a resist pattern. In substantially the same manner as in (d) above, after etching the second metal film using the resist pattern as a mask, the unnecessary resist pattern is peeled off and removed in the same manner as in (e) above. A second metal wiring pattern 14-2a is formed on the hole pattern made of -1 and a dummy for suppressing a global level difference is formed at the location of the first layer to be polished 20-1b on the light receiving element portion 12. A pattern (for example, a light shielding metal pattern) 23 is formed. The metal pattern 23 has a film thickness that is almost the same as the height of the peripheral wiring pattern 14-2a, and has a planar length L2 that is larger than the planar length L1 of the light receiving element 12. It is formed so as to cover the entire surface of the element 13.

In substantially the same manner as in (f) , a film to be polished (for example, an oxide film such as SiO 2 or an interlayer insulating film) 20-2, which is a second insulating film of the second layer, is formed on the entire surface using DP-CVD or the like. To a thickness of. Since the surface of the film to be polished 20-2 has local unevenness and steps depending on the unevenness of the wiring pattern 14-2a and the metal pattern 23, a flattening process is necessary.

(11) Planarization and conductor embedding step in FIGS. 2-3 (k) and 1 (B) In substantially the same manner as in (g), the surface of the second layer 20-2 to be polished is subjected to CMP. Flatten. In this flattening process, the polishing rate varies depending on the underlying wiring pattern density and the presence or absence of the metal pattern 23. For example, in the wiring portion 11 on the left side of FIGS. 2-3 (k) and 1 (B), since the wiring pattern density is a high region (dense region), the polished film 20-2a after polishing is a film. The thickness is d11. On the other hand, the wiring pattern density on the right wiring part 11 is low, but the metal pattern 23 covering the light receiving element part 12 is formed, so that the pattern density on the entire right side is almost the same as the pattern density on the left side. . Therefore, the film thickness of the polishing target film 20-2b after polishing the right wiring part 11 and the light receiving element part 12 is d12. Therefore, the magnitude relationship between the film thickness d11 of the entire polished film 20-1a and 20-2a on the left side after polishing and the film thickness d12 of the entire film to be polished 20-1b and 20-2b on the right side is the conventional relationship. Thus, not d11 >> d12 but d11> d12, d11 <d12, or d11 = d12, and even if a global step (= d11−d12) occurs, it is significantly smaller than the conventional case.

  After the planarization treatment, a photoresist is applied to the entire surface of the second polished films 20-2a and 20-2b after polishing, and exposure and development using a photomask are performed in substantially the same manner as in (h) above. A resist pattern of the photoresist is formed. Next, using the resist pattern as a mask, the second-layer polished films 20-1a and 20-1b are etched in substantially the same manner as in (i) above, and on the second-layer wiring pattern 14-2a, A plurality of holes extending in a cylindrical shape in the vertical direction are formed, and these cylindrical holes are filled with a conductor 22-2 such as tungsten. Thereafter, if the resist pattern that is no longer needed is removed, a hole pattern composed of a plurality of columnar conductors 22-2 electrically connected in the vertical direction to the second-layer wiring pattern 14-2a is formed. Is done. On the metal pattern 23, the conductor 22-2 is not formed.

(12) Wiring pattern formation / light-receiving element opening process in FIGS. 2-3 (l) and 1 (C) In substantially the same manner as in (j) above, the entire surfaces of the second polishing films 20-2a and 20-2b A third light-shielding metal film is formed, and a photoresist is applied to the entire surface of the metal film. Next, mask alignment is performed, exposure is performed, and development is performed to obtain a resist pattern. After etching the third layer metal film using this resist pattern as a mask, the unnecessary resist pattern is peeled and removed, and the third layer metal wiring is formed on the hole pattern made of a plurality of conductors 22-2. Pattern 14-3a is formed. At the same time, or thereafter, the second polishing film 20-2b, the metal pattern 23, and the first polishing film 20-1b stacked on the light receiving element 13 are sequentially masked from the top. Then, an opening 24 having a plane length L3 substantially the same as the plane length L1 of the light receiving element 13 is formed, and the light receiving element 13 is exposed. At this time, since the length L3 of the opening 24 is smaller than the length L2 of the metal pattern 23, both end portions 23a of the metal pattern 23 remain as residues, but it interferes with incident light from the outside to the light receiving element 13. Must not. Thereafter, if a protective film is coated on the third-layer wiring pattern 14-3a, the manufacture of the semiconductor device having the three-layer wiring structure having the light receiving element 13 is completed.

(Effect of Example 1)
According to the manufacturing method of Example 1, the following effects (a) to (c) are obtained.

  (A) Since the metal pattern 23 is disposed in a region covering the light receiving element 13, the light receiving element portion 12 is not excessively recessed in the upper layer process, and a global step (= d11−d12) can be maintained within a certain range. As a result, it is possible to prevent pattern defects due to defocusing in the exposure process of the photoetching process when creating the upper hole or the metal pattern 23.

  (B) Since the metal pattern 23 covering the entire surface of the light receiving element 12 is disposed, the etching depth can be kept constant when the metal pattern is removed by etching in a subsequent process. That is, by forming the metal pattern 23 that covers the entire surface, not a part of the light receiving element 12, when the metal pattern 23 is completely removed by etching in a later process, the etching depth progresses uniformly, and the light receiving element 13 is etched. Thus, it becomes easy to prevent the element from being destroyed.

(C) In the steps shown in FIGS. 2-3 (j) to (l) and FIGS. 1 (A) to (C),
Step 1: Create a metal wiring pattern 14-1a, but do not place a wiring pattern on the light receiving element 12 at this time.
Step 2: Laminating a polishing target film 20-1 that is an insulating film,
Step 3: The deposited polishing target film 20-1 is planarized by CMP.
Step 4: In the planarized polished surfaces 20-1a and 20-1b, a plurality of holes are formed on the wiring pattern 14-1a, and these holes are filled with the conductor 22-1.

  Thereafter, the n-layer wiring is stacked by repeating steps 1 to 4 n times, and the metal pattern 23 covering the entire surface of the light receiving element 13 is formed in the middle x-th (1 ≦ x ≦ n). In FIGS. 2-3 (j) to (l) and FIGS. 1 (A) to (C), an example of n = 2 is shown. In the multilayer wiring structure thus formed, the metal pattern 23 covering the entire surface of the light receiving element is removed by etching. Therefore, a multilayer wiring structure having an arbitrary number of layers can be easily formed, and the effects (a) and (b) can be easily obtained.

(Production method of Example 2)
A method for manufacturing a semiconductor device according to Example 2 of the present invention will be described below with reference to FIGS.

  A metal pattern 23 covering the entire surface of the light receiving element 13 having a planar length L1 is created by enlarging the light receiving element portion 12 to the outside. Although not shown, the plane length of the metal pattern 23 at this time is L4. In the step of forming a resist pattern that serves as a photo-etching mask for removing the metal pattern 23 covering the entire surface of the light receiving element, the region of the resist pattern that is used to form the opening 24 is larger than that of the light receiving element portion 12, It is assumed that the metal pattern 23 covering the entire surface of the element is smaller than the length L4. According to such a manufacturing method, the metal pattern 23 finally disappears immediately above the light receiving element portion 12, and both end portions 23 a of the metal pattern 23 remain around the light receiving element portion 12.

(Effect of Example 2)
According to the second embodiment, since the plane length of the resist pattern is shorter than the plane length L4 of the metal pattern 23, the overlay of the exposure machine is generated, and as a result, the portion without the metal pattern 23 is excessive. It is possible to prevent the circuit near the light receiving element from being damaged by deep etching. Moreover, since the light-shielding metal pattern 23 can be removed in a larger area than the light receiving element 13, it is possible to prevent the light shielding material from being left immediately above the light receiving element due to misalignment.

(Modification)
The present invention is not limited to the first and second embodiments, and various usage forms and modifications are possible. For example, the following forms (a) to (c) are available as usage forms and modifications.

  (A) Instead of metal wiring patterns 14-1a, 14-2a, 14-3a, metal pattern 23, and metal conductors 22-1, 22-2, these may be polysilicon other than metal, etc. Alternatively, a conductive non-light-transmitting material may be used.

  (B) Although the metal pattern 23 covering the non-light-transmitting film has been described as an example of only one layer, it can be applied to a plurality of layers. Although the multilayer wiring structure has been described, the present invention can also be applied to a single-layer wiring structure.

  (C) Instead of the light receiving element 12, the present invention can also be applied to other photoelectric conversion elements such as light emitting elements such as light emitting diodes.

It is the same manufacturing process figure corresponding to the manufacturing process of FIGS. 2-3 which shows the manufacturing method of the semiconductor device in Example 1 of this invention. It is a manufacturing process figure of the general | schematic longitudinal cross-section which shows the manufacturing method of the semiconductor device in the multilayer wiring structure of Example 1 of this invention. It is a manufacturing process figure of the general | schematic longitudinal cross-section which shows the manufacturing method of the semiconductor device in the multilayer wiring structure of Example 1 of this invention. It is a manufacturing process figure of the general | schematic longitudinal cross-section which shows the manufacturing method of the semiconductor device in the multilayer wiring structure of Example 1 of this invention. It is a part manufacturing process figure in the manufacturing method of the conventional semiconductor device. It is a part manufacturing process figure in the manufacturing method of the conventional semiconductor device. It is a manufacturing process figure for demonstrating the subject in the manufacturing method of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Board | substrate 11 Wiring part 12 Light receiving element part 13 Light receiving element 14-1 Metal film 14-1a, 14-2a, 14-3a Wiring pattern 15 Photoresist 15-1a, 15-2a Resist pattern 16 Photomask 20-1, 20-2 Films to be polished 20-1a, 20-1b, 20-2a, 20-2b Films to be polished after polishing 22-1 and 22-2 Conductor 23 Metal pattern 24 Opening

Claims (6)

A first step of forming a first insulating film you cover the photoelectric conversion element and a circuit portion mounted on the substrate,
A second step of planarizing the surface of the first insulating film by chemical mechanical polishing;
A light-shielding wiring pattern located on the circuit portion and electrically connected to the circuit portion on the first insulating film having a planarized surface, and located on the photoelectric conversion element A third step of forming a residual film thickness difference dummy pattern covering the photoelectric conversion element;
A fourth step of forming a second insulating film covering the wiring pattern and the dummy pattern;
A fifth step of planarizing the surface of the second insulating film by chemical mechanical polishing;
A sixth step of exposing the photoelectric conversion element by selectively removing the dummy pattern and the first insulating film and the second insulating film located thereunder by etching;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the third step, the dummy pattern is formed so as to cover the entire surface of the photoelectric conversion element. In the sixth step, an opening is formed by removing the dummy pattern and the first insulating film and the second insulating film located therebelow by photoetching using the resist pattern as a mask. A method for manufacturing a semiconductor device according to claim 2. 4. The method of manufacturing a semiconductor device according to claim 3, wherein a length of the plane of the opening is smaller than a length of the plane of the dummy pattern and is substantially the same as a length of the plane of the photoelectric conversion element.   The method for manufacturing a semiconductor device according to claim 1, wherein the photoelectric conversion element is a light receiving element.   The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device has a single-layer wiring structure or a multilayer wiring structure.

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