JP4887202B2 - Plasma processing apparatus and high-frequency current short circuit - Google Patents

Plasma processing apparatus and high-frequency current short circuit Download PDF

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JP4887202B2
JP4887202B2 JP2007108421A JP2007108421A JP4887202B2 JP 4887202 B2 JP4887202 B2 JP 4887202B2 JP 2007108421 A JP2007108421 A JP 2007108421A JP 2007108421 A JP2007108421 A JP 2007108421A JP 4887202 B2 JP4887202 B2 JP 4887202B2
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和男 佐々木
充一 中村
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Tokyo Electron Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • H01J37/32174Circuits specially adapted for controlling the RF discharge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32458Vessel
    • H01J37/32477Vessel characterised by the means for protecting vessels or internal parts, e.g. coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32532Electrodes
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    • H05HPLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
    • H05H1/00Generating plasma; Handling plasma
    • H05H1/24Generating plasma
    • H05H1/46Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05HPLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
    • H05H1/00Generating plasma; Handling plasma
    • H05H1/24Generating plasma
    • H05H1/46Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
    • H05H1/4645Radiofrequency discharges
    • H05H1/4652Radiofrequency discharges using inductive coupling means, e.g. coils
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05HPLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
    • H05H2242/00Auxiliary systems
    • H05H2242/20Power circuits

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  • Engineering & Computer Science (AREA)
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Description

本発明は、プラズマ処理装置及び高周波電流の短絡回路に関し、特に、基板にプラズマ処理を施すプラズマ処理装置に関する。   The present invention relates to a plasma processing apparatus and a high-frequency current short circuit, and more particularly to a plasma processing apparatus for performing plasma processing on a substrate.

第7世代や第8世代の液晶パネル用のガラス基板にエッチング処理を施すプラズマ処理装置50は、図6に示すように、ガラス基板(以下、単に「基板」という。)Gを収容するチャンバ51と、該基板Gを載置する下部電極52と、該下部電極52と対向するシャワーヘッド53の上部電極54とを備える。このプラズマ処理装置50では、上部電極54及び下部電極52の間の空間(以下、「処理空間」という。)に供給された処理ガスを高周波電界によって励起してプラズマを発生させ、該プラズマによって基板Gにエッチング処理を施す。   As shown in FIG. 6, a plasma processing apparatus 50 that performs an etching process on a glass substrate for a seventh-generation or eighth-generation liquid crystal panel includes a chamber 51 that houses a glass substrate (hereinafter simply referred to as “substrate”) G. And a lower electrode 52 on which the substrate G is placed, and an upper electrode 54 of the shower head 53 facing the lower electrode 52. In this plasma processing apparatus 50, a processing gas supplied to a space between the upper electrode 54 and the lower electrode 52 (hereinafter referred to as “processing space”) is excited by a high-frequency electric field to generate plasma, and the plasma generates a substrate. G is etched.

プラズマ処理装置50では、下部電極52が接地基板55によって支持され、該接地基板55は上下方向に移動可能なピラー56及びベローズ57を介してチャンバ51に接続されている。チャンバ51は接地されているため、エッチング処理の際、上部電極54→処理空間のプラズマ→下部電極52→接地基板55→ピラー56→ベローズ57→チャンバ51の経路で高周波電流が流れる。ここで、ピラー56やベローズ57は導電体からなるため、接地基板55はチャンバ51と直流的に同電位であるが、ピラー56やベローズ57によってリアクタンスが発生するため交流的には同電位とならない。   In the plasma processing apparatus 50, the lower electrode 52 is supported by a ground substrate 55, and the ground substrate 55 is connected to the chamber 51 via a pillar 56 and a bellows 57 that are movable in the vertical direction. Since the chamber 51 is grounded, a high-frequency current flows through the path of the upper electrode 54 → the plasma in the processing space → the lower electrode 52 → the ground substrate 55 → the pillar 56 → the bellows 57 → the chamber 51 during the etching process. Here, since the pillar 56 and the bellows 57 are made of a conductor, the ground substrate 55 has the same potential as the chamber 51 in terms of direct current. .

また、第7世代や第8世代の液晶パネルは非常に大きいため、下部電極52や接地基板55も非常に大きく、その結果、接地基板55及びチャンバ51の壁面の間における空間(以下、「下部空間」という。)も非常に大きくなる。そして、交流的に同電位とならない接地基板55及びチャンバ51の壁面の間には電位差が生じるため、下部空間にも高周波電流が流れて容量結合プラズマや異常放電が発生することがある。このプラズマによって処理空間におけるプラズマの密度が低下し、均一性が悪化する。また、異常放電によってパワー効率が低下し、さらには接地基板55が削れてパーティクルが発生する。   Further, since the 7th generation and 8th generation liquid crystal panels are very large, the lower electrode 52 and the ground substrate 55 are also very large. As a result, the space between the ground substrate 55 and the wall surface of the chamber 51 (hereinafter referred to as “lower portion”). The space is also very large. Since a potential difference is generated between the ground substrate 55 and the wall surface of the chamber 51 that do not have the same potential in terms of alternating current, a high-frequency current may flow in the lower space to generate capacitively coupled plasma or abnormal discharge. This plasma reduces the density of the plasma in the processing space and deteriorates the uniformity. In addition, power efficiency is reduced due to abnormal discharge, and the ground substrate 55 is scraped to generate particles.

そこで、プラズマ処理装置50では、接地基板55及びチャンバ51の壁面を交流的に短絡する導電性材料からなる薄板状の短絡板58が設けられている(例えば、特許文献1参照。)。
特許3710081号公報
Therefore, the plasma processing apparatus 50 is provided with a thin plate-like short-circuit plate 58 made of a conductive material that short-circuits the ground substrate 55 and the wall surface of the chamber 51 in an alternating manner (see, for example, Patent Document 1).
Japanese Patent No. 3710081

しかしながら、第7世代や第8世代の液晶パネル用の基板Gにエッチング処理を施すには高パワー、例えば、10kW以上の高周波電力を処理空間に供給する必要がある。このとき、処理空間や接地基板55を流れる高周波電流は100A以上になる。また、短絡板58は自己インダクタンスを有し、高周波電流に対応して誘導性リアクタンス(インピーダンス)が発生する。その結果、接地基板55の電位は数100Vの高周波電圧を呈する。   However, in order to perform the etching process on the substrate G for the 7th generation or 8th generation liquid crystal panels, it is necessary to supply high power, for example, high frequency power of 10 kW or more to the processing space. At this time, the high-frequency current flowing through the processing space and the ground substrate 55 is 100 A or more. Further, the short-circuit plate 58 has a self-inductance, and inductive reactance (impedance) is generated corresponding to the high-frequency current. As a result, the potential of the ground substrate 55 exhibits a high frequency voltage of several hundred volts.

接地基板55の電位を低下させるためには、短絡板58の数を増やすのが最も効果的であるが、下部空間にはリフターピンホルダ(図示しない)等の構成部品が配置されているため、空間的な余裕が無く、短絡板58の数を増やすのは困難である。   In order to lower the potential of the ground substrate 55, it is most effective to increase the number of short-circuit plates 58, but since components such as a lifter pin holder (not shown) are arranged in the lower space, It is difficult to increase the number of short-circuit plates 58 because there is no space.

したがって、依然として接地基板55及びチャンバ51の壁面の間における電位差は解消せず、該電位差によって下部空間には容量結合プラズマや異常放電が発生する虞がある。   Therefore, the potential difference between the ground substrate 55 and the wall surface of the chamber 51 is still not eliminated, and capacitive coupling plasma and abnormal discharge may occur in the lower space due to the potential difference.

本発明の目的は、下部電極又は上部電極の少なくとも一方を支持する接地基板及び収容容器の内壁の間における電位差を低減することができるプラズマ処理装置及び高周波電流の短絡回路を提供することにある。   An object of the present invention is to provide a plasma processing apparatus and a high-frequency current short circuit capable of reducing a potential difference between a ground substrate supporting at least one of a lower electrode and an upper electrode and an inner wall of a container.

上記目的を達成するために、請求項1記載のプラズマ処理装置は、基板を収容する収容容器と、該収容容器内に配置されて前記基板を載置する載置台としての下部電極と、該下部電極に対向して配置され且つ前記収容容器内に処理ガスを供給する上部電極と、前記下部電極又は前記上部電極の少なくとも一方に接続された高周波電源と、前記下部電極又は前記上部電極の少なくとも一方を絶縁部を介して支持すると共に前記収容容器の内壁から離間して配置される接地基板と、該接地基板及び前記収容容器の内壁を短絡する短絡板とを備えるプラズマ処理装置において、前記短絡板及び前記収容容器の内壁の間にコンデンサが介在し、該コンデンサは前記収容容器の内壁に設けられ、前記短絡板は断面が矩形の直線導体からなり、途中で少なくとも2つに分岐していることを特徴とする。 In order to achieve the above object, a plasma processing apparatus according to claim 1 includes a storage container that stores a substrate, a lower electrode that is disposed in the storage container and mounts the substrate, and the lower part An upper electrode disposed opposite to the electrode and supplying a processing gas into the container; a high-frequency power source connected to at least one of the lower electrode or the upper electrode; and at least one of the lower electrode or the upper electrode In the plasma processing apparatus, comprising: a grounding substrate that is supported via an insulating portion and spaced apart from the inner wall of the housing container; and a shorting plate that short-circuits the grounding substrate and the inner wall of the housing container. and a capacitor is interposed between the inner wall of the container, the capacitor is provided on an inner wall of the container, the short-circuiting plate in cross-section consists of a rectangular straight conductors, small in the middle Both features that you have branched into two.

請求項2記載のプラズマ処理装置は、請求項1記載のプラズマ処理装置において、前記コンデンサの容量性リアクタンスをXとし、前記短絡板の誘導性リアクタンスをXとした場合、X=−X/2が成立することを特徴とする。 If the claims 2 plasma processing apparatus, wherein in the plasma processing apparatus according to claim 1, in which the capacitive reactance of the capacitor and X C, the inductive reactance of the short-circuiting plate was X L, X C = -X It is characterized in that L / 2 is established.

請求項3記載のプラズマ処理装置は、請求項1又は2記載のプラズマ処理装置において、前記コンデンサは絶縁層と、該絶縁層を狭持する2つの導電体とからなり、前記絶縁層はセラミックシート、溶射セラミック層及びフッ素樹脂層からなる群から選択された1つであることを特徴とする。   The plasma processing apparatus according to claim 3 is the plasma processing apparatus according to claim 1 or 2, wherein the capacitor includes an insulating layer and two conductors sandwiching the insulating layer, and the insulating layer is a ceramic sheet. And one selected from the group consisting of a thermal sprayed ceramic layer and a fluororesin layer.

請求項4記載のプラズマ処理装置は、請求項1記載のプラズマ処理装置において、前記短絡板及び前記接地基板の間に他のコンデンサが介在し、該他のコンデンサは前記接地基板に設けられ、前記コンデンサの静電容量をC1とし、前記短絡板の自己インダクタンスをLとし、前記他のコンデンサの静電容量をC2とし、前記高周波電源が供給する高周波電力の周波数をfとし、角周波数ωを2πfとした場合、C1=C2=2/(ω×L)が成立することを特徴とする。 The plasma processing apparatus according to claim 4 is the plasma processing apparatus according to claim 1, wherein another capacitor is interposed between the short-circuit plate and the ground substrate, and the other capacitor is provided on the ground substrate. The capacitance of the capacitor is C1, the self-inductance of the short-circuit plate is L, the capacitance of the other capacitor is C2, the frequency of the high-frequency power supplied from the high-frequency power source is f, and the angular frequency ω is 2πf. In this case, C1 = C2 = 2 / (ω 2 × L) is established.

上記目的を達成するために、請求項記載の高周波電流の短絡回路は、基板を収容する収容容器と、該収容容器内に配置されて前記基板を載置する載置台としての下部電極と、該下部電極に対向して配置され且つ前記収容容器内に処理ガスを供給する上部電極と、前記下部電極又は前記上部電極の少なくとも一方に接続された高周波電源と、前記下部電極又は前記上部電極の少なくとも一方を絶縁部を介して支持すると共に前記収容容器の内壁から離間して配置される接地基板とを備えるプラズマ処理装置における前記接地基板及び前記収容容器の内壁を短絡する高周波電流の短絡回路であって、前記接地基板及び前記収容容器の内壁を短絡する短絡板と、該短絡板及び前記収容容器の内壁の間に介在するコンデンサとを有し、該コンデンサは前記収容容器の内壁に設けられ、前記短絡板は断面が矩形の直線導体からなり、途中で少なくとも2つに分岐していることを特徴とする。 In order to achieve the above object, a high-frequency current short-circuit circuit according to claim 5, a storage container for storing a substrate, a lower electrode as a mounting table disposed in the storage container and mounting the substrate, An upper electrode disposed opposite to the lower electrode and supplying a processing gas into the container; a high-frequency power source connected to at least one of the lower electrode or the upper electrode; and the lower electrode or the upper electrode A high-frequency current short circuit for short-circuiting the grounding substrate and the inner wall of the housing container in a plasma processing apparatus comprising: a grounding substrate disposed at a distance from the inner wall of the housing container while supporting at least one through an insulating portion A short-circuit plate that short-circuits the inner wall of the grounding substrate and the storage container, and a capacitor interposed between the short-circuit plate and the inner wall of the storage container. Provided on an inner wall of the container, the short-circuiting plate in cross-section consists of a rectangular straight conductors, characterized that you have branched into at least two in the middle.

請求項1記載のプラズマ処理装置及び請求項記載の高周波電流の短絡回路によれば、接地基板及び収容容器の内壁を短絡する短絡板及び該収容容器の内壁の間にコンデンサが介在するので、接地基板及び収容容器の内壁の間における電位差を短絡板及びコンデンサで分担することができる。また、コンデンサは収容容器の内壁に設けられるので、接地基板及び収容容器の内壁の間における電位差は、実質的に接地基板及びコンデンサの間における電位差であり、該電位差は短絡板が分担する電位差に他ならない。また、短絡板は断面が矩形の直線導体からなり、途中で少なくとも2つに分岐している。短絡板を分岐すると各分岐路の断面積は減少するが、高周波電流の経路を増やすことができ、結果として短絡板全体のインダクタンスを低下させることができる。これにより、接地基板の電位を低下させることができる。その結果、下部電極又は上部電極の少なくとも一方を支持する接地基板及び収容容器の内壁の間における電位差を低減することができるAccording to the plasma processing apparatus of claim 1 and the short-circuit of the high-frequency current of claim 5 , since the capacitor is interposed between the grounding substrate and the short-circuit plate that short-circuits the inner wall of the container, and the inner wall of the container, The potential difference between the ground substrate and the inner wall of the container can be shared by the short-circuit plate and the capacitor. Further, since the capacitor is provided on the inner wall of the container, the potential difference between the ground substrate and the inner wall of the container is substantially the potential difference between the ground substrate and the capacitor, and the potential difference is a potential difference shared by the short-circuit plate. There is nothing else. The short-circuit plate is made of a straight conductor having a rectangular cross section, and is branched into at least two parts along the way. When the short-circuit plate is branched, the cross-sectional area of each branch path decreases, but the number of high-frequency current paths can be increased. As a result, the inductance of the entire short-circuit plate can be reduced. As a result, the potential of the ground substrate can be lowered. As a result, the potential difference between the ground substrate that supports at least one of the lower electrode and the upper electrode and the inner wall of the container can be reduced .

請求項2記載のプラズマ処理装置によれば、コンデンサの容量性リアクタンスX及び短絡板の誘導性リアクタンスXがX=−X/2を満たす。高周波電流をIとすると、短絡板及び該収容容器の内壁の間にコンデンサが介在しない場合の接地基板の電位Vは、V≒X×Iで示され、短絡板及び該収容容器の内壁の間にコンデンサが介在する場合の接地基板の電位Vは、V≒(X+X)×Iで示される。ここで、X=−X/2が成立するので、V≒1/2×X×Iとなる。すなわち、VをVの1/2にすることができ、短絡板が分担する電位差を確実に低減することができる。また、このとき、コンデンサが分担する電位差もVの1/2となるため、接地基板及びコンデンサの間、並びにコンデンサ及び収容容器の内壁の間における電位差をいずれも適切に低減することができ、もって、接地基板及びコンデンサの間やコンデンサ及び収容容器の内壁の間において容量結合プラズマや異常放電が発生するのを抑制することができる。 According to the plasma processing apparatus of the second aspect, the capacitive reactance X C of the capacitor and the inductive reactance X L of the short-circuit plate satisfy X C = −X L / 2. Assuming that the high-frequency current is I, the potential V 1 of the ground substrate when no capacitor is interposed between the short-circuit plate and the inner wall of the storage container is represented by V 1 ≈X L × I. The potential V 2 of the ground substrate when a capacitor is interposed between the inner walls is represented by V 2 ≈ (X L + X C ) × I. Here, since X C = −X L / 2 holds, V 2 ≈½ × X L × I. That is, the V 2 can be 1/2 of V 1, it is possible to short-circuit plate is reliably reduced potential to share. At this time, since the potential difference capacitor share also becomes half of V 1, both between the ground substrate and the capacitor, and a potential difference between the inner wall of the condenser and container can be suitably reduced, Accordingly, it is possible to suppress the generation of capacitively coupled plasma and abnormal discharge between the ground substrate and the capacitor or between the capacitor and the inner wall of the container.

請求項4記載のプラズマ処理装置によれば、短絡板及び接地基板の間に他のコンデンサが介在し、該他のコンデンサは接地基板に設けられ、コンデンサの静電容量C1、短絡板の自己インダクタンスL、他のコンデンサの静電容量C2、及び高周波電力の周波数をfとしたときの角周波数ω(=2πf)が、C1=C2=2/(ω×L)を満たす。高周波電流をIとすると、短絡板及び該収容容器の内壁の間にコンデンサが介在し、且つ短絡板及び接地基板の間に他のコンデンサが介在する場合の接地基板の電位Vは、コンデンサの容量性リアクタンスをXC1とし、他のコンデンサの容量性リアクタンスをXC2とし、短絡板の誘導性リアクタンスをXとすると、V≒(XC1+X+XC2)×Iで示され、さらに展開すると、電位Vは、V≒(−1/(ω×C1)+ω×L−1/(ω×C2))で示される。ここでC1=C2=2/(ω×L)が成立するので、V≒0となる。すなわち、接地基板の電位を0にすることができるため、接地基板の近傍において容量結合プラズマや異常放電が発生するのを防止することができる。 According to the plasma processing apparatus of claim 4, another capacitor is interposed between the short-circuit plate and the ground substrate, and the other capacitor is provided on the ground substrate, and the capacitance C1 of the capacitor and the self-inductance of the short-circuit plate. L, the capacitance C2 of the other capacitor, and the angular frequency ω (= 2πf) where f is the frequency of the high-frequency power satisfy C1 = C2 = 2 / (ω 2 × L). Assuming that the high-frequency current is I, the potential V 3 of the ground substrate when a capacitor is interposed between the short-circuit plate and the inner wall of the container and another capacitor is interposed between the short-circuit plate and the ground substrate is the capacitive reactance and X C1, the capacitive reactance of the other capacitor and X C2, the inductive reactance of the short-circuiting plate to X L, indicated by V 3 ≒ (X C1 + X L + X C2) × I, further When developed, the potential V 3 is represented by V 3 ≈ (−1 / (ω × C1) + ω × L−1 / (ω × C2)). Here, since C1 = C2 = 2 / (ω 2 × L) holds, V 3 ≈0. That is, since the potential of the ground substrate can be set to 0, it is possible to prevent the occurrence of capacitively coupled plasma and abnormal discharge in the vicinity of the ground substrate.

以下、本発明の実施の形態について図面を参照しながら説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

まず、本発明の第1の実施の形態に係るプラズマ処理装置について説明する。   First, the plasma processing apparatus according to the first embodiment of the present invention will be described.

図1は、本実施の形態に係るプラズマ処理装置の構成を概略的に示す断面図である。このプラズマ処理装置は液晶ディスプレイ(LCD)用のガラス基板にエッチング処理を施すように構成されている。   FIG. 1 is a cross-sectional view schematically showing a configuration of a plasma processing apparatus according to the present embodiment. This plasma processing apparatus is configured to perform an etching process on a glass substrate for a liquid crystal display (LCD).

図1において、プラズマ処理装置10は、例えば、一辺が約1mである矩形のガラス基板(以下、単に「基板」という。)Gを収容する角筒形状のチャンバ11(収容容器)を有する。該チャンバ11はアルミニウムからなり、チャンバ11の内壁の殆どはアルマイトによって被覆されている。   In FIG. 1, the plasma processing apparatus 10 includes a rectangular tube-shaped chamber 11 (accommodating container) that accommodates a rectangular glass substrate (hereinafter simply referred to as “substrate”) G having a side of about 1 m, for example. The chamber 11 is made of aluminum, and most of the inner wall of the chamber 11 is covered with alumite.

チャンバ11の天井部にはシャワーヘッド12(上部電極)が配置され、該シャワーヘッド12は、矩形の導電性平板である上部電極板13と、該上部電極板13を着脱可能に釣支する導電体からなる上部電極基部14とを有する。上部電極基部14の内部にはバッファ室15が設けられ、このバッファ室15には処理ガス導入管16が接続されている。また、上部電極板13はバッファ室15内及びチャンバ11内を連通する多数のガス穴17を有する。処理ガス導入管16は処理ガス供給装置(図示しない)に接続され、該処理ガス供給装置は処理ガス導入管16を介してバッファ室15へ処理ガスを導入する。シャワーヘッド12は、バッファ室15へ導入された処理ガスをガス穴17を介して上部電極板13及び後述の下部電極板23の間の空間(以下、「処理空間S」という。)へ供給する。ここで、シャワーヘッド12は上部絶縁部22を介してチャンバ11の天井部から釣支されているので、シャワーヘッド12はチャンバ11から十分電気的にフローティングしている。   A shower head 12 (upper electrode) is disposed on the ceiling portion of the chamber 11. The shower head 12 has an upper electrode plate 13 that is a rectangular conductive plate and a conductive member that supports the upper electrode plate 13 in a detachable manner. And an upper electrode base 14 made of a body. A buffer chamber 15 is provided inside the upper electrode base 14, and a processing gas introduction pipe 16 is connected to the buffer chamber 15. The upper electrode plate 13 has a large number of gas holes 17 communicating with the buffer chamber 15 and the chamber 11. The processing gas introduction pipe 16 is connected to a processing gas supply apparatus (not shown), and the processing gas supply apparatus introduces the processing gas into the buffer chamber 15 through the processing gas introduction pipe 16. The shower head 12 supplies the processing gas introduced into the buffer chamber 15 to the space between the upper electrode plate 13 and the lower electrode plate 23 described later (hereinafter referred to as “processing space S”) through the gas hole 17. . Here, since the shower head 12 is supported from the ceiling portion of the chamber 11 via the upper insulating portion 22, the shower head 12 is sufficiently electrically floating from the chamber 11.

上部電極板13は上部電極基部14、整合回路18及び導電路19を介して高周波電源20に接続されている。また、チャンバ11の天井部上には、整合回路18を包有するようにマッチングボックス21が設けられている。該マッチングボックス21は接地されているため、整合回路18の接地筐体として機能する。高周波電源20は所定の高周波電力、例えば、13.56MHzの高周波電力を上部電極板13に供給する。そして、上部電極板13は処理空間Sに高周波電圧を印加して、高周波電界を発生させる。該高周波電界は処理空間Sに供給された処理ガスを励起してプラズマを発生させる。なお、処理ガスとしては、例えばハロゲンを含むガス、具体的には、ハロゲン化合物からなるガス、酸素ガス及びアルゴンガス等が用いられる。   The upper electrode plate 13 is connected to the high-frequency power source 20 through the upper electrode base portion 14, the matching circuit 18 and the conductive path 19. A matching box 21 is provided on the ceiling of the chamber 11 so as to include the matching circuit 18. Since the matching box 21 is grounded, it functions as a grounding housing for the matching circuit 18. The high frequency power supply 20 supplies a predetermined high frequency power, for example, a high frequency power of 13.56 MHz to the upper electrode plate 13. The upper electrode plate 13 applies a high frequency voltage to the processing space S to generate a high frequency electric field. The high frequency electric field excites the processing gas supplied to the processing space S to generate plasma. As the processing gas, for example, a gas containing halogen, specifically, a gas composed of a halogen compound, oxygen gas, argon gas, or the like is used.

チャンバ11の底部には基板Gを載置する載置台を兼ねる矩形の下部電極板23が配置されている。該下部電極板23は、上部電極板13と対向するとともに、下部絶縁部25を介してアルミニウムからなる接地基板26によって支持されている。また、接地基板26はチャンバ11の底部から離間して配置されており、円筒状のピラー27によって支持されている。該ピラー27は図示しない駆動機構によって上下方向(図中矢印方向)に移動する支持板28上に配置される。したがって、支持板28の上下動に伴い接地基板26や下部電極板23も上下動する。支持板28はベローズ29を介してチャンバ11の底部と接続され、該ベローズ29はチャンバ11内及びチャンバ11外を気密に区画する。なお、ピラー27、支持板28及びベローズ29は全て導電体からなる。   A rectangular lower electrode plate 23 also serving as a mounting table on which the substrate G is mounted is disposed at the bottom of the chamber 11. The lower electrode plate 23 faces the upper electrode plate 13 and is supported by a ground substrate 26 made of aluminum via a lower insulating portion 25. The ground substrate 26 is disposed away from the bottom of the chamber 11 and is supported by a cylindrical pillar 27. The pillar 27 is disposed on a support plate 28 that moves in the vertical direction (in the direction of the arrow in the figure) by a drive mechanism (not shown). Therefore, as the support plate 28 moves up and down, the ground substrate 26 and the lower electrode plate 23 also move up and down. The support plate 28 is connected to the bottom of the chamber 11 via a bellows 29, and the bellows 29 partitions the inside of the chamber 11 and the outside of the chamber 11 in an airtight manner. The pillar 27, the support plate 28, and the bellows 29 are all made of a conductor.

下部電極板23内にはチラー流路(図示しない)が設けられ、該チラー流路を流れる冷媒によって下部電極板23上に載置された基板Gが冷却される。下部絶縁部25は誘電体や大気層からなり、下部電極板23を接地基板26、引いてはチャンバ11から十分電気的にフローティングさせる。   A chiller channel (not shown) is provided in the lower electrode plate 23, and the substrate G placed on the lower electrode plate 23 is cooled by the refrigerant flowing through the chiller channel. The lower insulating portion 25 is made of a dielectric material or an atmospheric layer, and causes the lower electrode plate 23 to be sufficiently electrically floated from the ground substrate 26 and then from the chamber 11.

下部電極板23にはピラー27内に設けられた導電路30の一端が接続され、この導電路30にはインピーダンス調整部31が介設されている。導電路30の他端は、支持板28及びベローズ29を介してチャンバ11の底部に接続されている。本実施の形態では、上部電極板13及び下部電極板23が夫々カソード電極及びアノード電極に相当する。   One end of a conductive path 30 provided in the pillar 27 is connected to the lower electrode plate 23, and an impedance adjusting unit 31 is interposed in the conductive path 30. The other end of the conductive path 30 is connected to the bottom of the chamber 11 through a support plate 28 and a bellows 29. In the present embodiment, the upper electrode plate 13 and the lower electrode plate 23 correspond to a cathode electrode and an anode electrode, respectively.

チャンバ11の底部には排気路32が接続され、該排気路32には図示しない排気装置、例えば、ターボ分子ポンプやドライポンプが接続されている。排気装置は排気路32を介してチャンバ11内を排気する。さらに、チャンバ11の側壁には、基板Gの搬送口33を開閉するゲートバルブ34が設けられている。   An exhaust passage 32 is connected to the bottom of the chamber 11, and an exhaust device (not shown) such as a turbo molecular pump or a dry pump is connected to the exhaust passage 32. The exhaust device exhausts the inside of the chamber 11 through the exhaust path 32. Furthermore, a gate valve 34 for opening and closing the transfer port 33 for the substrate G is provided on the side wall of the chamber 11.

プラズマ処理装置10では、高周波電源20→整合回路18→シャワーヘッド12→処理空間Sのプラズマ→下部電極板23→インピーダンス調整部31→チャンバ11→マッチングボックス21→接地の経路で高周波電流が流れるが、シャワーヘッド12からプラズマを介してチャンバ11の壁部に短絡的に高周波電流が流れるおそれがあるため、下部電極板23からマッチングボックス21に至るまでの経路(リターン経路)のインピーダンスをインピーダンス調整部31により調整してチャンバ11の壁部に短絡的に高周波電流が流れるのを防止する。   In the plasma processing apparatus 10, a high frequency current flows through a high frequency power source 20 → a matching circuit 18 → a shower head 12 → a plasma in the processing space S → a lower electrode plate 23 → an impedance adjusting unit 31 → a chamber 11 → a matching box 21 → a ground path. Since the high-frequency current may flow in a short circuit from the shower head 12 to the wall portion of the chamber 11 via plasma, the impedance of the path (return path) from the lower electrode plate 23 to the matching box 21 is changed to the impedance adjusting section. The high frequency current is prevented from flowing in a short-circuit manner on the wall portion of the chamber 11 by adjusting by 31.

また、プラズマ処理装置10では、処理空間Sに高周波電力を供給して高周波電界を発生させることにより、該処理空間Sにおいてシャワーヘッド12から供給された処理ガスを励起して高密度のプラズマを発生させ、該プラズマによって基板Gにエッチング処理を施す。   Further, in the plasma processing apparatus 10, high-frequency electric power is generated in the processing space S to generate a high-frequency electric field, thereby exciting the processing gas supplied from the shower head 12 in the processing space S and generating high-density plasma. The substrate G is etched by the plasma.

なお、プラズマ処理装置10の各構成部品の動作は、プラズマ処理装置10が備える制御部(図示しない)のCPUがエッチング処理に対応するプログラムに応じて制御する。   The operation of each component of the plasma processing apparatus 10 is controlled by a CPU of a control unit (not shown) provided in the plasma processing apparatus 10 according to a program corresponding to the etching process.

さらに、プラズマ処理装置10は、接地基板26及びチャンバ11の内壁を短絡する短絡板36と、該短絡板36及びチャンバ11の内壁の間に介在するコンデンサ37とを備える。短絡板36は、金属等の導電性材料、例えば、ステンレスやハステロイ(登録商標)からなる、断面矩形の薄板状導体である。   Further, the plasma processing apparatus 10 includes a short-circuit plate 36 that short-circuits the ground substrate 26 and the inner wall of the chamber 11, and a capacitor 37 interposed between the short-circuit plate 36 and the inner wall of the chamber 11. The short-circuit plate 36 is a thin plate-like conductor having a rectangular cross section made of a conductive material such as metal, for example, stainless steel or Hastelloy (registered trademark).

短絡板36の一端は接地基板26の下面に接続部38を介して接続され、短絡板36の他端はチャンバ11の内壁、具体的にはチャンバ11の底部に設けられたコンデンサ37に接続されている。   One end of the short-circuit plate 36 is connected to the lower surface of the ground substrate 26 via a connection portion 38, and the other end of the short-circuit plate 36 is connected to an inner wall of the chamber 11, specifically, a capacitor 37 provided on the bottom portion of the chamber 11. ing.

コンデンサ37は、絶縁層37aと、該絶縁層37aを狭持する、アルミニウム板等の2つの金属板37b,37cとからなり、プラズマと接触する可能性のある部分がアルマイト等の絶縁膜によって被覆されている。また、絶縁層37aは、例えば、セラミックシート、溶射セラミック層やフッ素樹脂層(テフロン(登録商標)層)からなる。このコンデンサ37として、上述した仕様のものの他、耐プラズマ性を有する市販の真空コンデンサや可変容量コンデンサを用いることもできる。   The capacitor 37 is composed of an insulating layer 37a and two metal plates 37b and 37c such as an aluminum plate that sandwich the insulating layer 37a, and a portion that may come into contact with plasma is covered with an insulating film such as alumite. Has been. The insulating layer 37a is made of, for example, a ceramic sheet, a sprayed ceramic layer, or a fluororesin layer (Teflon (registered trademark) layer). As the capacitor 37, a commercially available vacuum capacitor or variable capacitor having plasma resistance can be used in addition to the above-described specification.

このプラズマ処理装置10では、短絡板36及びコンデンサ37が、接地基板26及びチャンバ11の内壁の間を短絡する短絡回路を構成する。   In the plasma processing apparatus 10, the short-circuit plate 36 and the capacitor 37 constitute a short circuit that short-circuits between the ground substrate 26 and the inner wall of the chamber 11.

また、プラズマ処理装置10では、接地基板26及びチャンバ11の内壁の間に高周波電流が流れると、短絡板36は自己インダクタンスを有するため、短絡板36には誘導性リアクタンスが発生し、また、コンデンサ37は静電容量を有するため、コンデンサ37には容量性リアクタンスが発生する。また、プラズマ処理装置10では、コンデンサ37が短絡板36及びチャンバ11の内壁の間に介在するので、短絡板36及びコンデンサ37は、接地基板26及びチャンバ11の内壁の間において直列回路を構成する。したがって、短絡板36及びコンデンサ37は、接地基板26及びチャンバ11の内壁の間を高周波電流が流れる際に生じる電位差を分担することができる。   In the plasma processing apparatus 10, when a high-frequency current flows between the ground substrate 26 and the inner wall of the chamber 11, the short-circuit plate 36 has a self-inductance, so that an inductive reactance is generated in the short-circuit plate 36. Since the capacitor 37 has a capacitance, a capacitive reactance is generated in the capacitor 37. In the plasma processing apparatus 10, the capacitor 37 is interposed between the short-circuit plate 36 and the inner wall of the chamber 11, so that the short-circuit plate 36 and the capacitor 37 constitute a series circuit between the ground substrate 26 and the inner wall of the chamber 11. . Therefore, the short-circuit plate 36 and the capacitor 37 can share a potential difference generated when a high-frequency current flows between the ground substrate 26 and the inner wall of the chamber 11.

ここで、接地基板26の電位Vは、チャンバ11の内壁を接地電位とし、短絡板36のインピーダンスをZとし、コンデンサ37のインピーダンスをZとし、接地基板26及びチャンバ11の内壁の間を流れる高周波電流をIとすると、下記式(1)で示される。
= (Z+Z)×I … (1)
通常、ZやZはR+jX(Xはリアクタンス)で示されるが、プラズマ処理装置10では、RはXに比べて非常に小さく、無視できる。したがって、本実施の形態では、短絡板36の誘導性リアクタンスをXとし、コンデンサ37の容量性リアクタンスをXとすると、接地基板26の電位Vは下記式(2)で示される。
≒ (X+X)×I … (2)
本実施の形態では、コンデンサ37の静電容量を調整することによって電位Vを低減する。具体的には、下記式(3)が成立するようにコンデンサ37の静電容量を調整する。
= −X/2 … (3)
その結果、接地基板26の電位Vは下記式(4)で示される。
≒ 1/2×X×I … (4)
一方、従来のプラズマ処理装置のように、接地基板及びチャンバの内壁が短絡板のみで短絡されている場合、接地基板の電位Vは下記式(5)で示される。
≒ X×I … (5)
上記式(4)及び(5)を比較すると、接地基板26の電位Vは従来のプラズマ処理装置における接地基板の電位Vの1/2である。したがって、コンデンサ37を短絡板36及びチャンバ11の内壁の間に介在させ、上記式(3)が成立するようにコンデンサ37の静電容量を調整することにより、接地基板26の電位Vを従来のプラズマ処理装置における接地基板の電位Vの1/2にすることができる。
Here, the potential V 2 of the ground substrate 26 is set such that the inner wall of the chamber 11 is a ground potential, the impedance of the short-circuit plate 36 is Z L , the impedance of the capacitor 37 is Z C, and between the ground substrate 26 and the inner wall of the chamber 11. Assuming that the high-frequency current flowing through is I, the following equation (1) is obtained.
V 2 = (Z L + Z C ) × I (1)
Normally, Z L and Z C are represented by R + jX (X is reactance), but in the plasma processing apparatus 10, R is very small compared to X and can be ignored. Thus, in this embodiment, the inductive reactance of the short-circuiting plate 36 and X L, the capacitive reactance of the capacitor 37 and X C, the potential V 2 of the ground substrate 26 is represented by the following formula (2).
V 2 ≈ ( XL + X C ) × I (2)
In the present embodiment, the potential V 2 is reduced by adjusting the capacitance of the capacitor 37. Specifically, the capacitance of the capacitor 37 is adjusted so that the following formula (3) is satisfied.
X C = −X L / 2 (3)
As a result, the potential V 2 of the ground substrate 26 is represented by the following formula (4).
V 2 ≒ 1/2 × XL × I (4)
On the other hand, when the ground substrate and the inner wall of the chamber are short-circuited only by the short-circuit plate as in the conventional plasma processing apparatus, the potential V 1 of the ground substrate is expressed by the following formula (5).
V 1XL × I (5)
Comparing the expressions (4) and (5), the potential V 2 of the ground substrate 26 is 1/2 of the potential V 1 of the ground substrate in a conventional plasma processing apparatus. Therefore, by interposing the capacitor 37 between the short-circuit plate 36 and the inner wall of the chamber 11 and adjusting the capacitance of the capacitor 37 so that the above equation (3) is satisfied, the potential V 2 of the ground substrate 26 is conventionally increased. it can be 1/2 of the potential V 1 of the ground substrate in the plasma processing apparatus.

また、このとき、コンデンサ37の電位Vは下記式(6)で示される。
≒ X×I … (6)
ここで、上記式(3)より、コンデンサ37の電位Vは下記式(7)で示される。
≒ −1/2×X×I … (7)
したがって、コンデンサ37の電位Vも従来のプラズマ処理装置における接地基板の電位Vの1/2にすることができる。すなわち、コンデンサ37が分担する電位差もVの1/2となる。
At this time, the potential V C of the capacitor 37 is expressed by the following formula (6).
V C ≈ X C × I (6)
Here, from the above equation (3), the potential V C of the capacitor 37 is expressed by the following equation (7).
V C ≈−1 / 2 × XL × I (7)
Therefore, the potential V C of the capacitor 37 can also be ½ of the potential V 1 of the ground substrate in the conventional plasma processing apparatus. That is, the potential difference shared by the capacitor 37 is also ½ of V 1 .

本実施の形態に係るプラズマ処理装置10によれば、短絡板36及びコンデンサ37は、接地基板26及びチャンバ11の内壁の間を高周波電流が流れる際に生じる電位差を分担することができる。また、コンデンサ37はチャンバ11の内壁に設けられるので、接地基板26及びチャンバ11の内壁の間における電位差は、実質的に接地基板26及びコンデンサ37の間における電位差であり、該電位差は短絡板36が分担する電位差に他ならない。したがって、下部電極板23を支持する接地基板26及びチャンバ11の内壁の間における電位差を低減することができる。   According to the plasma processing apparatus 10 according to the present embodiment, the short-circuit plate 36 and the capacitor 37 can share a potential difference generated when a high-frequency current flows between the ground substrate 26 and the inner wall of the chamber 11. Further, since the capacitor 37 is provided on the inner wall of the chamber 11, the potential difference between the ground substrate 26 and the inner wall of the chamber 11 is substantially a potential difference between the ground substrate 26 and the capacitor 37, and the potential difference is the short-circuit plate 36. Is nothing but the potential difference shared by Therefore, the potential difference between the ground substrate 26 that supports the lower electrode plate 23 and the inner wall of the chamber 11 can be reduced.

上述したプラズマ処理装置10では、コンデンサ37の静電容量を調整することによってX=−X/2(上記式(3))を成立させるので、接地基板26の電位VはV≒1/2×X×I(上記式(4))で示される。一方、従来のプラズマ処理装置の接地基板の電位VはV≒X×I(上記式(5))で示される。すなわち、VをVの1/2にすることができ、短絡板36が分担する電位差を確実に低減することができる。 In the plasma processing apparatus 10 described above, X C = −X L / 2 (the above formula (3)) is established by adjusting the capacitance of the capacitor 37, so that the potential V 2 of the ground substrate 26 is V 2 ≈ 1/2 × X L × I (the above formula (4)). On the other hand, the potential V 1 of the ground substrate of the conventional plasma processing apparatus is expressed by V 1 ≈X L × I (the above formula (5)). That is, the V 2 can be 1/2 of V 1, may be short-circuiting plate 36 is reliably reduced potential to share.

また、コンデンサ37が分担する電位差もVの1/2となるため、接地基板26及びコンデンサ37の間、並びにコンデンサ37及びチャンバ11の内壁の間における電位差をいずれも適切に低減することができ、もって、接地基板26及びコンデンサ37の間やコンデンサ37及びチャンバ11の内壁の間において容量結合プラズマや異常放電が発生するのを抑制することができる。 Further, since the potential difference shared by the capacitor 37 is also ½ of V 1 , the potential difference between the ground substrate 26 and the capacitor 37 and between the capacitor 37 and the inner wall of the chamber 11 can be appropriately reduced. Accordingly, it is possible to suppress the generation of capacitively coupled plasma and abnormal discharge between the ground substrate 26 and the capacitor 37 and between the capacitor 37 and the inner wall of the chamber 11.

上述したプラズマ処理装置10では、コンデンサ37の静電容量を調整することによって接地基板26の電位Vを従来のプラズマ処理装置における接地基板の電位Vの1/2にしたが、コンデンサ37の静電容量を調整することによって短絡板36が分担する電位差を変更し、接地基板26の電位Vをほぼ0にしてもよい。 In the plasma processing apparatus 10 described above, the potential V 2 of the ground substrate 26 is set to ½ of the potential V 1 of the ground substrate in the conventional plasma processing apparatus by adjusting the capacitance of the capacitor 37. change the potential difference is short-circuiting plate 36 is shared by adjusting the electrostatic capacitance may be substantially zero potential V 2 of the ground substrate 26.

次に、本発明の第2の実施の形態に係るプラズマ処理装置について説明する。   Next, a plasma processing apparatus according to the second embodiment of the present invention will be described.

本実施の形態は、その構成、作用が上述した第1の実施の形態と基本的に同じであり、接地基板26及びチャンバ11の壁面を短絡する短絡回路の構成が異なるのみであるので、重複した構成、作用については説明を省略し、以下に異なる構成、作用についての説明を行う。   The present embodiment is basically the same in configuration and operation as the first embodiment described above, and is different only in the configuration of the short circuit that short-circuits the ground substrate 26 and the wall surface of the chamber 11. The description of the configuration and operation will be omitted, and different configurations and operations will be described below.

図2は、本実施の形態に係るプラズマ処理装置の構成を概略的に示す断面図である。   FIG. 2 is a cross-sectional view schematically showing the configuration of the plasma processing apparatus according to the present embodiment.

図2において、プラズマ処理装置40は、接地基板26及びチャンバ11の内壁を短絡する短絡板41を備える。短絡板41も、金属等の導電性材料、例えば、ステンレスやハステロイ(登録商標)からなる、断面矩形の薄板状導体である。   In FIG. 2, the plasma processing apparatus 40 includes a short-circuit plate 41 that short-circuits the ground substrate 26 and the inner wall of the chamber 11. The short-circuit plate 41 is also a thin plate-like conductor having a rectangular cross section made of a conductive material such as metal, for example, stainless steel or Hastelloy (registered trademark).

短絡板41の一端は接続部38を介して接地基板26に接続され、短絡板41の他端はチャンバ11の内壁に接続部42を介して接続されている。このプラズマ処理装置40では、短絡板41が接地基板26及びチャンバ11の内壁の間を短絡する短絡回路を構成する。   One end of the short-circuit plate 41 is connected to the ground substrate 26 via the connection portion 38, and the other end of the short-circuit plate 41 is connected to the inner wall of the chamber 11 via the connection portion 42. In the plasma processing apparatus 40, the short-circuit plate 41 constitutes a short circuit that short-circuits between the ground substrate 26 and the inner wall of the chamber 11.

図3は、図2における短絡板を示す正面図であり、図3(A)は短絡板を2つに分岐した場合を示し、図3(B)は短絡板を3つに分岐した場合を示す。   3 is a front view showing the short-circuit plate in FIG. 2, FIG. 3 (A) shows a case where the short-circuit plate is branched into two, and FIG. 3 (B) shows a case where the short-circuit plate is branched into three. Show.

一般に、金属からなる断面矩形の直線導体のインダクタンスLは、該直線導体の長さをa(cm)、幅をb(cm)、厚さをc(cm)とすると、下記式(8)で示される。
L=0.002a×〔2.303×log{2a/(b+c)}+0.5+0.2235×(b+c)/a〕 … (8)
ここで、b≫cとすると、上記式(8)は下記式(8)’で示される。
L≒0.002a×{2.303×log(2a/b)+0.5+0.2235×b/a} … (8)’
このとき、上記式(8)’におけるLの値をAとし、直線導体における幅−長さ比をb/aとすると、該A及びb/aの関係は図4に示す通りとなる。なお、図4において、横軸は幅−長さ比b/aを示し、縦軸は、幅−長さ比b/aが0.5のときのAを1として各幅−長さ比b/aに対応するAを規格化した場合における規格化されたAを示す。
In general, the inductance L of a straight conductor having a rectangular cross section made of metal is expressed by the following formula (8), where a (cm) is a length of the straight conductor, b (cm) is a width, and c (cm) is a thickness. Indicated.
L = 0.002a × [2.3303 × log {2a / (b + c)} + 0.5 + 0.2235 × (b + c) / a] (8)
Here, if b >> c, the above equation (8) is expressed by the following equation (8) ′.
L≈0.002a × {2.3303 × log (2a / b) + 0.5 + 0.2235 × b / a} (8) ′
At this time, if the value of L in the above formula (8) ′ is A and the width-length ratio of the linear conductor is b / a, the relationship between A and b / a is as shown in FIG. In FIG. 4, the horizontal axis indicates the width-length ratio b / a, and the vertical axis indicates each width-length ratio b where A is 1 when the width-length ratio b / a is 0.5. A standardized A when A corresponding to / a is standardized is shown.

図4に示す関係から、幅−長さ比b/aを0.5から0.25へ半減(すなわち、直線導体の幅を半減)しても、インダクタンスLの値であるAは約1.3倍となるのみであり、b/aを0.5から0.1へ1/5減(すなわち、幅を1/5減)しても、Aは約1.8倍となるのみである。   From the relationship shown in FIG. 4, even if the width-length ratio b / a is halved from 0.5 to 0.25 (that is, the width of the straight conductor is halved), the value of inductance L is about 1. It is only 3 times, and even if b / a is reduced by 1/5 from 0.5 to 0.1 (ie, the width is reduced by 1/5), A is only about 1.8 times. .

一方、図3(A)に示す2つに分岐した短絡板41において、接続部38,42と接続される部分を除いた長さ(有効長さ)をlとし、各分岐路41aの幅をwとすると、該短絡板41では、幅w及び長さlの2つの分岐路41aが並列に配置されていることになる。このとき、短絡板41全体のインダクタンスをLallとし、分岐路41aにおけるインダクタンスをLdivとすると、下記式(9)が成立する。
1/Lall = 1/Ldiv+1/Ldiv … (9)
したがって、上記式(9)より、短絡板41全体のインダクタンスは分岐路41aのインダクタンスの半分となる。
On the other hand, in the short-circuit plate 41 branched into two shown in FIG. 3A, the length (effective length) excluding the portion connected to the connecting portions 38 and 42 is l, and the width of each branch path 41a is Assuming w, in the short-circuit plate 41, two branch paths 41a having a width w and a length l are arranged in parallel. At this time, if the inductance of the entire short-circuit plate 41 is L all and the inductance in the branch path 41a is L div , the following equation (9) is established.
1 / L all = 1 / L div + 1 / L div (9)
Therefore, from the above equation (9), the inductance of the entire short-circuit plate 41 is half of the inductance of the branch path 41a.

すなわち、短絡板41を分岐すると、1つの分岐路41aにおけるインダクタンスは増加するが、短絡板41では2つの分岐路41aが並列に配置されているため、高周波電流の経路を増やすことができ、結果として短絡板41全体のインダクタンスを低下させることができる。   That is, when the short circuit plate 41 is branched, the inductance in one branch path 41a increases, but in the short circuit board 41, since the two branch paths 41a are arranged in parallel, the path of the high-frequency current can be increased. As a result, the inductance of the entire short-circuit plate 41 can be reduced.

なお、短絡板41は、図3(B)に示すように、3つに分岐してもよい。すなわち、短絡板41における分岐路の数は限られていない。   The short-circuit plate 41 may be branched into three as shown in FIG. That is, the number of branch paths in the short-circuit plate 41 is not limited.

本実施の形態に係るプラズマ処理装置40によれば、断面が矩形の直線導体からなる短絡板41は途中で少なくとも2つに分岐している。短絡板41を分岐すると、結果として短絡板41全体のインダクタンスを低下させることができる。これにより、接地基板26の電位を低下させることができ、下部電極板23を支持する接地基板26及びチャンバ11の内壁の間における電位差を低減することができる。   According to the plasma processing apparatus 40 according to the present embodiment, the short-circuit plate 41 made of a straight conductor having a rectangular cross section is branched into at least two in the middle. If the short-circuit plate 41 is branched, the inductance of the entire short-circuit plate 41 can be reduced as a result. Thereby, the potential of the ground substrate 26 can be lowered, and the potential difference between the ground substrate 26 supporting the lower electrode plate 23 and the inner wall of the chamber 11 can be reduced.

次に、本発明の第3の実施の形態に係るプラズマ処理装置について説明する。   Next, a plasma processing apparatus according to a third embodiment of the present invention will be described.

本実施の形態は、その構成、作用が上述した第1の実施の形態と基本的に同じであり、接地基板26及びチャンバ11の壁面を短絡する短絡回路の構成が異なるのみであるので、重複した構成、作用については説明を省略し、以下に異なる構成、作用についての説明を行う。   The present embodiment is basically the same in configuration and operation as the first embodiment described above, and is different only in the configuration of the short circuit that short-circuits the ground substrate 26 and the wall surface of the chamber 11. The description of the configuration and operation will be omitted, and different configurations and operations will be described below.

図5は、本実施の形態に係るプラズマ処理装置の構成を概略的に示す断面図である。   FIG. 5 is a cross-sectional view schematically showing the configuration of the plasma processing apparatus according to the present embodiment.

図5において、プラズマ処理装置43は、接地基板26及びチャンバ11の内壁を短絡する短絡板44を備える。短絡板44も、金属等の導電性材料、例えば、ステンレスやハステロイ(登録商標)からなる、断面矩形の薄板状導体である。   In FIG. 5, the plasma processing apparatus 43 includes a short-circuit plate 44 that short-circuits the ground substrate 26 and the inner wall of the chamber 11. The short-circuit plate 44 is also a thin plate-like conductor having a rectangular cross section made of a conductive material such as metal, for example, stainless steel or Hastelloy (registered trademark).

短絡板44の一端は接地基板26の下面に設けられたコンデンサ45(他のコンデンサ)に接続され、短絡板44の他端はチャンバ11の底部に設けられたコンデンサ37に接続されている。コンデンサ45の構造はコンデンサ37の構造と同じである。   One end of the short-circuit plate 44 is connected to a capacitor 45 (another capacitor) provided on the lower surface of the ground substrate 26, and the other end of the short-circuit plate 44 is connected to a capacitor 37 provided at the bottom of the chamber 11. The structure of the capacitor 45 is the same as that of the capacitor 37.

このプラズマ処理装置43では、コンデンサ45、短絡板44及びコンデンサ37が、接地基板26及びチャンバ11の内壁の間を短絡する短絡回路を構成する。また、プラズマ処理装置43では、コンデンサ37が短絡板44及びチャンバ11の内壁の間に介在し、コンデンサ45が短絡板44及び接地基板26の間に介在するので、コンデンサ45、短絡板44及びコンデンサ37は、接地基板26及びチャンバ11の内壁の間において直列回路を構成する。   In this plasma processing apparatus 43, the capacitor 45, the short-circuit plate 44, and the capacitor 37 constitute a short circuit that short-circuits between the ground substrate 26 and the inner wall of the chamber 11. In the plasma processing apparatus 43, the capacitor 37 is interposed between the short-circuit plate 44 and the inner wall of the chamber 11, and the capacitor 45 is interposed between the short-circuit plate 44 and the ground substrate 26. 37 constitutes a series circuit between the ground substrate 26 and the inner wall of the chamber 11.

本実施の形態では、コンデンサ37,45の静電容量を調整することによって接地基板26の電位Vを0にする。具体的には、コンデンサ37の静電容量をC1とし、短絡板44の自己インダクタンスをLとし、コンデンサ45の静電容量をC2とし、高周波電源20が供給する高周波電力の周波数をfとし、高周波電力の角周波数ωを2πfとした場合、下記式(10)が成立するようにコンデンサ37,45の静電容量C1,C2を調整する。
C1 = C2 = 2/(ω×L) … (10)
ここで、コンデンサ37の容量性リアクタンスをXC1とし、コンデンサ45の容量性リアクタンスをXC2とし、短絡板44の誘導性リアクタンスをXとすると、接地基板26の電位Vは下記式(11)で示される。
≒ (XC1+X+XC2)×I = (−1/(ω×C1)+ω×L−1/(ω×C2))×I … (11)
ここで、上記式(10)より、接地基板26の電位Vは下記式(12)で示される。
≒ (−ω×L/2+ω×L−ω×L/2)×I … (12)
すなわち、接地基板26の電位Vは0となる。
In the present embodiment, the potential V 3 of the ground substrate 26 is set to 0 by adjusting the capacitances of the capacitors 37 and 45. Specifically, the capacitance of the capacitor 37 is C1, the self-inductance of the short-circuit plate 44 is L, the capacitance of the capacitor 45 is C2, the frequency of the high frequency power supplied from the high frequency power supply 20 is f, and the high frequency When the angular frequency ω of power is 2πf, the capacitances C1 and C2 of the capacitors 37 and 45 are adjusted so that the following formula (10) is satisfied.
C1 = C2 = 2 / (ω 2 × L) (10)
Here, the capacitive reactance of the capacitor 37 and X C1, the capacitive reactance of the capacitor 45 and X C2, the inductive reactance of the short-circuiting plate 44 and X L, the potential V 3 is of the formula of the ground substrate 26 (11 ).
V 3 ≈ (X C1 + XL + X C2 ) × I = (− 1 / (ω × C1) + ω × L−1 / (ω × C2)) × I (11)
Here, from the above equation (10), the potential V 3 of the ground substrate 26 is expressed by the following equation (12).
V 3 ≈ (−ω × L / 2 + ω × L−ω × L / 2) × I (12)
That is, the potential V 3 0 of the ground substrate 26.

また、このとき、コンデンサ45の電位VC2は下記式(13)で示される。
C2 ≒ (XC1+X)×I = (−1/(ω×C1)+ω×L))×I … (13)
ここで、上記式(10)より、コンデンサ45の電位VC2は下記式(14)で示される。
C2 ≒ 1/2×ω×L×I … (14)
一方、上記式(5)で示される従来のプラズマ処理装置の接地基板の電位Vは、上記式(10)より、下記式(15)で示される。
≒ X×I = ω×L×I … (15)
したがって、本実施の形態では、コンデンサ45の電位VC2を従来のプラズマ処理装置における接地基板の電位Vの1/2にすることができる。
At this time, the potential V C2 of the capacitor 45 is expressed by the following formula (13).
V C2 ≈ (X C1 + X L ) × I = (− 1 / (ω × C1) + ω × L)) × I (13)
Here, from the above equation (10), the potential V C2 of the capacitor 45 is represented by the following equation (14).
V C2 ≈ 1/2 × ω × L × I (14)
On the other hand, the potential V 1 of the ground substrate of the conventional plasma processing apparatus represented by the above formula (5) is represented by the following formula (15) from the above formula (10).
V 1XL × I = ω × L × I (15)
Therefore, in the present embodiment, the potential V C2 of the capacitor 45 can be ½ of the potential V 1 of the ground substrate in the conventional plasma processing apparatus.

また、コンデンサ37の電位VC1は下記式(16)で示される。
C1 ≒ XC1×I = −1/(ω×C1)×I … (16)
ここで、上記式(10)より、コンデンサ45の電位VC1は下記式(17)で示される。
C1 ≒ −1/2×ω×L×I … (17)
したがって、本実施の形態では、コンデンサ37の電位VC1も従来のプラズマ処理装置における接地基板の電位Vの1/2にすることができる。
The potential V C1 of the capacitor 37 is expressed by the following formula (16).
V C1 ≈ X C1 × I = −1 / (ω × C1) × I (16)
Here, from the above equation (10), the potential V C1 of the capacitor 45 is represented by the following equation (17).
V C1 ≈ −1 / 2 × ω × L × I (17)
Therefore, in the present embodiment, the potential V C1 of the capacitor 37 can also be ½ of the potential V 1 of the ground substrate in the conventional plasma processing apparatus.

本実施の形態に係るプラズマ処理装置43によれば、コンデンサ37に加え、短絡板44及び接地基板26の間にコンデンサ45が介在し、該コンデンサ45は接地基板26に設けられる。また、コンデンサ37,45の静電容量C1,C2を調整することによってC1=C2=2/(ω×L)(上記式(10))を成立させるので、V≒(−1/(ω×C1)+ω×L−1/(ω×C2))×I (上記式(11))で示される接地基板26の電位Vを0にすることができる。したがって、接地基板26の近傍において容量結合プラズマや異常放電が発生するのを防止することができる。 According to plasma processing apparatus 43 according to the present embodiment, capacitor 45 is interposed between short-circuit plate 44 and ground substrate 26 in addition to capacitor 37, and capacitor 45 is provided on ground substrate 26. Since C1 = C2 = 2 / (ω 2 × L) (the above formula (10)) is established by adjusting the capacitances C1 and C2 of the capacitors 37 and 45, V 3 ≈ (−1 / ( the ω × C1) + ω × L -1 / (ω × C2)) × I ( the potential V 3 of the ground substrate 26 represented by the above formula (11)) can be made zero. Therefore, it is possible to prevent the occurrence of capacitively coupled plasma or abnormal discharge in the vicinity of the ground substrate 26.

また、コンデンサ45の電位VC2及びコンデンサ37の電位VC1を従来のプラズマ処理装置における接地基板の電位Vの1/2にすることができるため、接地基板26及びコンデンサ45の間、並びにコンデンサ37及びチャンバ11の内壁の間における電位差をいずれも適切に低減することができ、もって、接地基板26及びコンデンサ45の間やコンデンサ37及びチャンバ11の内壁の間において容量結合プラズマや異常放電が発生するのを抑制することができる。 Moreover, since it is possible to set the potential V C2 and the potential V C1 of the capacitor 37 of the capacitor 45 to a half of the potential V 1 of the ground substrate in a conventional plasma processing apparatus, between the ground substrate 26 and a capacitor 45, and the capacitor 37 and the inner wall of the chamber 11 can be appropriately reduced, and capacitively coupled plasma and abnormal discharge are generated between the ground substrate 26 and the capacitor 45 and between the capacitor 37 and the inner wall of the chamber 11. Can be suppressed.

上述した各実施の形態は組み合わせてプラズマ処理装置に適用してもよい。例えば、プラズマ処理装置10において短絡板36の代わりに2つに分岐した短絡板41を用いてもよく、また、プラズマ処理装置43において短絡板44の代わりに短絡板41を用いてもよい。   The above-described embodiments may be combined and applied to the plasma processing apparatus. For example, the short-circuit plate 41 branched into two may be used instead of the short-circuit plate 36 in the plasma processing apparatus 10, and the short-circuit plate 41 may be used instead of the short-circuit plate 44 in the plasma processing apparatus 43.

上述した各実施の形態に係るプラズマ処理装置はインピーダンス調整部31を備えているが、本発明を適用できるプラズマ処理装置はこれに限られず、例えば、インピーダンス調整部を必要としないプラズマ処理装置であってもよい。   Although the plasma processing apparatus according to each of the embodiments described above includes the impedance adjustment unit 31, the plasma processing apparatus to which the present invention can be applied is not limited to this, for example, a plasma processing apparatus that does not require the impedance adjustment unit. May be.

上述した各実施の形態に係るプラズマ処理装置では、シャワーヘッド12の上部電極板13に高周波電源20が接続されているが、本発明を適用できるプラズマ処理装置はこれに限られない。例えば、下部電極板23にのみ高周波電源が接続されるプラズマ処理装置であってもよく、若しくは、上部電極板13及び下部電極板23のいずれにも別々の高周波電源が接続されるプラズマ処理装置であってもよい。   In the plasma processing apparatus according to each of the above-described embodiments, the high frequency power supply 20 is connected to the upper electrode plate 13 of the shower head 12, but the plasma processing apparatus to which the present invention can be applied is not limited thereto. For example, it may be a plasma processing apparatus in which a high frequency power source is connected only to the lower electrode plate 23, or a plasma processing apparatus in which a separate high frequency power source is connected to either the upper electrode plate 13 or the lower electrode plate 23. There may be.

また、上述した各実施の形態に係るプラズマ処理装置では、下部絶縁部25を介して下部電極板23を支持する接地基板26と、該接地基板26及びチャンバ11の内壁を短絡する短絡板とを備えたが、本発明を適用できるプラズマ処理装置はこれに限られない。例えば、上部絶縁部を介して上部電極板を支持し且つチャンバ11の内壁から離間して配置された接地基板と、該接地基板及びチャンバの内壁を短絡する短絡板とを備えるプラズマ処理装置であってもよい。   In the plasma processing apparatus according to each of the above-described embodiments, the ground substrate 26 that supports the lower electrode plate 23 via the lower insulating portion 25 and the short-circuit plate that short-circuits the ground substrate 26 and the inner wall of the chamber 11 are provided. Although provided, the plasma processing apparatus to which the present invention can be applied is not limited to this. For example, the plasma processing apparatus includes a grounding substrate that supports the upper electrode plate via the upper insulating portion and is spaced apart from the inner wall of the chamber 11, and a short-circuit plate that short-circuits the grounding substrate and the inner wall of the chamber. May be.

本発明の第1の実施の形態に係るプラズマ処理装置の構成を概略的に示す断面図である。It is sectional drawing which shows roughly the structure of the plasma processing apparatus which concerns on the 1st Embodiment of this invention. 本発明の第2の実施の形態に係るプラズマ処理装置の構成を概略的に示す断面図である。It is sectional drawing which shows schematically the structure of the plasma processing apparatus which concerns on the 2nd Embodiment of this invention. 図2における短絡板を示す正面図であり、図3(A)は短絡板を2つに分岐した場合を示し、図3(B)は短絡板を3つに分岐した場合を示す。FIG. 3A is a front view showing the short-circuit plate in FIG. 2, FIG. 3A shows a case where the short-circuit plate is branched into two, and FIG. 3B shows a case where the short-circuit plate is branched into three. 金属からなる断面矩形の直線導体のインダクタンスの値と、該直線導体における幅−長さ比との関係を示すグラフである。It is a graph which shows the relationship between the value of the inductance of the linear conductor of a cross-section rectangle which consists of metals, and the width-length ratio in this linear conductor. 本発明の第3の実施の形態に係るプラズマ処理装置の構成を概略的に示す断面図である。It is sectional drawing which shows schematically the structure of the plasma processing apparatus which concerns on the 3rd Embodiment of this invention. 従来のプラズマ処理装置の構成を概略的に示す断面図である。It is sectional drawing which shows the structure of the conventional plasma processing apparatus roughly.

符号の説明Explanation of symbols

G ガラス基板
S 処理空間
10,40,43 プラズマ処理装置
11 チャンバ
13 上部電極板
20 高周波電源
22 上部絶縁部
23 下部電極板
25 下部絶縁部
26 接地基板
36,41,44 短絡板
37,45 コンデンサ
37a,45a 絶縁層
41a 分岐路
G Glass substrate S Processing space 10, 40, 43 Plasma processing apparatus 11 Chamber 13 Upper electrode plate 20 High frequency power supply 22 Upper insulating part 23 Lower electrode plate 25 Lower insulating part 26 Grounding substrates 36, 41, 44 Shorting plates 37, 45 Capacitor 37a 45a Insulating layer 41a

Claims (5)

基板を収容する収容容器と、該収容容器内に配置されて前記基板を載置する載置台としての下部電極と、該下部電極に対向して配置され且つ前記収容容器内に処理ガスを供給する上部電極と、前記下部電極又は前記上部電極の少なくとも一方に接続された高周波電源と、前記下部電極又は前記上部電極の少なくとも一方を絶縁部を介して支持すると共に前記収容容器の内壁から離間して配置される接地基板と、該接地基板及び前記収容容器の内壁を短絡する短絡板とを備えるプラズマ処理装置において、
前記短絡板及び前記収容容器の内壁の間にコンデンサが介在し、該コンデンサは前記収容容器の内壁に設けられ
前記短絡板は断面が矩形の直線導体からなり、途中で少なくとも2つに分岐していることを特徴とするプラズマ処理装置。
A storage container for storing a substrate, a lower electrode as a mounting table disposed in the storage container for mounting the substrate, and a processing gas supplied to the storage container that is disposed to face the lower electrode An upper electrode, a high-frequency power source connected to at least one of the lower electrode or the upper electrode, and at least one of the lower electrode or the upper electrode are supported via an insulating portion and spaced apart from the inner wall of the container In a plasma processing apparatus comprising: a ground substrate to be disposed; and a short-circuit plate that short-circuits the ground substrate and the inner wall of the container,
A capacitor is interposed between the short-circuit plate and the inner wall of the container, and the capacitor is provided on the inner wall of the container .
The short-circuiting plate in cross-section consists of a rectangular straight conductor, a plasma processing apparatus characterized that you have branched into at least two in the middle.
前記コンデンサの容量性リアクタンスをXとし、前記短絡板の誘導性リアクタンスをXとした場合、
=−X/2
が成立することを特徴とする請求項1記載のプラズマ処理装置。
If the capacitive reactance of the capacitor and X C, the inductive reactance of the short-circuiting plate was X L,
X C = −X L / 2
The plasma processing apparatus according to claim 1, wherein:
前記コンデンサは絶縁層と、該絶縁層を狭持する2つの導電体とからなり、前記絶縁層はセラミックシート、溶射セラミック層及びフッ素樹脂層からなる群から選択された1つであることを特徴とする請求項1又は2記載のプラズマ処理装置。   The capacitor includes an insulating layer and two conductors sandwiching the insulating layer, and the insulating layer is one selected from the group consisting of a ceramic sheet, a sprayed ceramic layer, and a fluororesin layer. The plasma processing apparatus according to claim 1 or 2. 前記短絡板及び前記接地基板の間に他のコンデンサが介在し、該他のコンデンサは前記接地基板に設けられ、
前記コンデンサの静電容量をC1とし、前記短絡板の自己インダクタンスをLとし、前記他のコンデンサの静電容量をC2とし、前記高周波電源が供給する高周波電力の周波数をfとし、角周波数ωを2πfとした場合、
C1=C2=2/(ω×L)
が成立することを特徴とする請求項1記載のプラズマ処理装置。
Another capacitor is interposed between the short-circuit plate and the ground substrate, and the other capacitor is provided on the ground substrate,
The capacitance of the capacitor is C1, the self-inductance of the short-circuit plate is L, the capacitance of the other capacitor is C2, the frequency of the high-frequency power supplied by the high-frequency power source is f, and the angular frequency ω is If 2πf,
C1 = C2 = 2 / (ω 2 × L)
The plasma processing apparatus according to claim 1, wherein:
基板を収容する収容容器と、該収容容器内に配置されて前記基板を載置する載置台としての下部電極と、該下部電極に対向して配置され且つ前記収容容器内に処理ガスを供給する上部電極と、前記下部電極又は前記上部電極の少なくとも一方に接続された高周波電源と、前記下部電極又は前記上部電極の少なくとも一方を絶縁部を介して支持すると共に前記収容容器の内壁から離間して配置される接地基板とを備えるプラズマ処理装置における前記接地基板及び前記収容容器の内壁を短絡する高周波電流の短絡回路であって、
前記接地基板及び前記収容容器の内壁を短絡する短絡板と、該短絡板及び前記収容容器の内壁の間に介在するコンデンサとを有し、
該コンデンサは前記収容容器の内壁に設けられ
前記短絡板は断面が矩形の直線導体からなり、途中で少なくとも2つに分岐していることを特徴とする短絡回路。
A storage container for storing a substrate, a lower electrode as a mounting table disposed in the storage container for mounting the substrate, and a processing gas supplied to the storage container that is disposed to face the lower electrode An upper electrode, a high-frequency power source connected to at least one of the lower electrode or the upper electrode, and at least one of the lower electrode or the upper electrode are supported via an insulating portion and spaced apart from the inner wall of the container A short circuit of a high-frequency current for short-circuiting the ground substrate and the inner wall of the container in a plasma processing apparatus comprising a ground substrate disposed;
A short-circuit plate that short-circuits the grounding substrate and the inner wall of the storage container, and a capacitor interposed between the short-circuit plate and the inner wall of the storage container,
The capacitor is provided on the inner wall of the container ,
Short circuit and the short-circuiting plate is that cross section consists of a rectangular straight conductors, characterized that you have branched into at least two in the middle.
JP2007108421A 2007-04-17 2007-04-17 Plasma processing apparatus and high-frequency current short circuit Expired - Fee Related JP4887202B2 (en)

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