JP4820764B2 - Gain control filter device, gain control complex filter device, and reception device - Google Patents

Description

  The present invention relates to a gain control filter device and a gain control complex filter device having a gain control function, and further to a receiving device using the gain control complex filter device. In particular, the present invention relates to the field of a video reproduction apparatus including a low-IF (LOW-IF) receiving circuit, for example, a television receiver or a television tuner.

  In recent years, television receivers are shifting to digital broadcasting represented by 1seg and 13seg instead of conventional analog broadcasting. The Japanese system is called ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) and adopts the LOW-IF method. In general, in the superheterodyne wireless communication receiver system such as the LOW-IF method, In order to remove an image signal, a complex filter device has been used.

  First, the complex filter device will be described. The complex filter device is intended to realize the characteristics realized by the conventional SAW filter (surface acoustic wave filter) by an active filter composed of RC elements inside the semiconductor, and has a steep cutoff characteristic from the passband to the stopband. Furthermore, it is required that the group delay characteristic and the ripple characteristic are good. As a filter for realizing these characteristics, an inverse Chebyshev filter, an elliptic filter, and the like are conceivable, but any of these filters requires a higher-order filter of the 8th order or higher. come.

  This high-order filter is realized by a block cascading configuration (Biquad's polynomial) of a primary filter or a secondary filter, or a leapfrog filter to lower the element sensitivity, and is low for easy design. It is divided into the following filters.

  Further, when creating this complex filter device by an active filter using an RC element inside a semiconductor, the active filter configuration generally includes a filter network including an operational amplifier and a CR, a transconductance and a capacitance. A Gm-C filter network can be considered.

  When the complex filter device is configured by a filter network including the former operational amplifier and CR, the circuit area tends to be relatively large, but the distortion characteristics tend to be good. On the other hand, when the latter Gm-C filter network is used, the circuit area is relatively small, but the distortion characteristics tend to deteriorate.

  Further, as described in Japanese Patent Application Laid-Open No. 2006-157866, when there is a mismatch of elements between the in-phase (I) signal processing system and the quadrature (Q) signal processing system in the complex filter device, The gain IQ mismatch increases and the image rejection ratio of the complex filter device degrades.

  For this reason, it is necessary to establish an IQ mismatch reduction method focusing on element errors in the complex filter device. For example, in order to satisfy the 13seg filter characteristics shown in FIG. 7, although depending on the filter circuit design method, the allowable IQ mismatch is 1% or less for the gain difference and 0.5% for the phase difference. % Or less is required.

  Further, when these high-order filters are configured, the number of devices is large and the circuit current needs to be reduced, so that noise characteristics are also an issue. For this reason, generally a GCA (Gain Control Amp) circuit is provided as a gain control circuit before, between, and after the filter, and the S / N and distortion are best maintained during demodulation by the demodulation circuit. The points at which the gain distribution of each gain control circuit and automatic gain control start to function are set in advance.

  For example, when the signal level is small, there is no problem with distortion, so the gain may be increased to improve the S / N. On the other hand, when the signal level is high, there is no problem with the S / N, so the gain may be reduced to improve the distortion. Further, regarding the gain distribution of each gain control circuit, the S / N ratio is improved by setting the gain of the previous stage to be high and the gain of the subsequent stage to be low.

  Next, the tuner circuit 13 in the LOW-IF system will be described with reference to FIG.

  The LOW-IF type receiver built in the television receiver is roughly divided into a tuner circuit 13 that selects a desired channel frequency from the television high-frequency signal received by the antenna 10 and converts it into a LOW-IF signal; A demodulation circuit 14 that demodulates a video signal and an audio signal from a LOW-IF signal output from the tuner circuit 13 is configured. An RF filter circuit 11 and a low noise amplifier 12 are provided in front of the Chu circuit 13, and a television high frequency signal received by the antenna 10 is connected to the RF filter circuit 11 and the low noise amplifier 12. To the tuner circuit 13.

  The tuner circuit 13 includes an I signal mixer 20, a Q signal mixer 21, GCA circuits 22 and 23, an IF filter circuit 24, a GCA circuit 25 and 26, an IF filter circuit 27, a GCA circuit 28, a phase shifter 30, and a local oscillator. 31 and a GCA control circuit 32. Symbol S20 indicates an output signal of I signal mixer 20, symbol S21 indicates an output signal of Q signal mixer 21, symbols S22 and S23 indicate output signals of GCA circuits 22 and 23, respectively, and symbols S24I and S24Q indicate Symbols S25 and S26 indicate the output signals of the GCA circuits 25 and 26, symbol S27 indicates the I output signal of the IF filter circuit 27, and symbol S28 indicates the I output signal and Q output signal of the IF filter circuit 24, respectively. The output signal of the GCA circuit 28 is shown, and symbols S32a, S32b, and S32c show the output signal (gain control voltage) of the GCA control circuit 32, respectively. Symbol S14 indicates the output signal of the demodulation circuit 14.

  The operation of the tuner system configured as described above will be described. Here, a method called ISDB-T in Japan that employs the LOW-IF method will be described as an example. First, a television high-frequency signal received by the antenna 10 is filtered by an RF filter circuit 11 having bandpass characteristics, and then amplified by a low-noise amplifier 12 also called LNA (Low Noise Amp).

  The reception signal amplified by the low noise amplifier 12 is input to the I signal mixer 20 and the Q signal mixer 21. The I signal mixer 20 and the Q signal mixer 21 are provided with a zero phase shift signal and a 90 ° phase shift signal from a local oscillator 31 via a phase shifter 30, respectively.

  As a result, the received signal received by the antenna 10 is subjected to quadrature demodulation while being down-converted to an intermediate frequency signal of 4 MHz as shown in FIG. Signal) and quadrature signal (Q signal).

  Next, the I signal and the Q signal down-converted by the I signal mixer 20 and the Q signal mixer 21 are input to the GCA circuits 22 and 23, respectively, and the gain is controlled by the GCA circuits 22 and 23, respectively.

  Thereafter, the LOW-IF signal having the I and Q signals has the characteristics of a complex filter that is an image removal filter (IR filter) that removes any interference present within the image band of the desired signal (ie, 0 Hz or less). It is passed to the IF filter circuit 24. This complex filter can be realized by an active filter network or a Gm-C filter network composed of an operational amplifier and CR, and performs image removal.

  As a result, the IF filter circuit 24 having the complex filter characteristic attenuates the image signal and the adjacent interfering signal, and only the desired signal is in a band of 4 MHz ± 3 MHz (1 MHz to 7 MHz) as shown in FIG. Can pass.

  Thus, the signal from which any image interference has been removed can be handled as a real signal in the subsequent signal processing. That is, only one of the I signal and the Q signal needs to be processed.

  Here, if the noise characteristics can be sufficiently secured only by the GCA circuits 22 and 23 provided in the preceding stage of the IF filter circuit 24, the gain control is completed. However, if the noise characteristic is insufficient, the gain control must be performed again in the I signal processing system and the Q signal processing system by the GCA circuits 25 and 26 provided between the filter stages in consideration of the distortion characteristic. . Since the filter circuit is usually divided into several stages, it can be connected between the stages in this way.

  Thereafter, the signal is passed to the IF filter circuit 27 having complex filter characteristics, and the processing of the Q signal is completed. On the other hand, the I signal is passed through the GCA circuit 28 if the input level of the demodulator circuit 14 at the subsequent stage is insufficient and it is necessary to perform gain control.

  The output signal S28 of the GCA circuit 28 is output from the tuner circuit 13 and given to the demodulating circuit 14 having the AD converter at the subsequent stage, and various processes based on the data after digital conversion are subsequently performed. .

  The demodulation circuit 14 outputs a signal S14 corresponding to the intensity of the output signal S28 of the GCA circuit 28, which is an input signal, and this signal S14 is connected to the GCA of the tuner circuit 13 via the GCA control circuit 32. The feedback is supplied to the circuits 22 and 23, the GCA circuits 25 and 26, and the GCA circuit 28, and thereby the gain is controlled so that the level of the output signal S28 of the GCA circuit 28 that is the output signal of the tuner circuit 13 is made constant. It is operating.

  A conventional gain control circuit will be described with reference to a prior example of Japanese Patent No. 3598973.

  As a gain control circuit, a configuration using a Gilbert multiplier is common. An example of the conventional circuit is shown in FIG. In FIG. 4, for example, a GCA circuit 22 which is a gain control circuit according to a conventional example includes a differential amplifier circuit 101, two current dividing circuits 102 and 103, gain control voltage input terminals 104 and 105, and a circuit input. It has a configuration having terminals 106 and 107. The circuit input terminals 106 and 107 receive an output signal S20 of the I signal mixer 20, that is, signals S20 (P) and S20 (N) having the same amplitude but opposite signs. The input terminals 104 and 105 receive the output signal S32a of the GCA control circuit 32, that is, reverse gain control voltages S32a (P) and S32a (N) forming a differential signal.

  The differential amplifier circuit 101 includes an NPN-type differential pair transistor Q101, Q102, an emitter resistor R101 connected between the emitter electrodes of the differential pair transistor Q101, Q102, and a differential pair transistor Q101, The constant current sources I101 and I102 are connected between the emitter electrodes of Q102 and the ground. The base electrodes of the differential pair transistors Q101 and Q102 are connected to circuit input terminals 106 and 107, respectively.

  One current dividing circuit 102 is supplied with NPN-type differential pair transistors Q105 and Q104 each having an emitter electrode commonly connected to the collector electrode of the transistor Q101, and the collector electrode of one transistor Q103 and the power supply voltage (Vcc). The differential circuit configuration includes a resistor R102 connected between the power supply voltage terminal 1 to be connected. The collector electrode of the other transistor Q104 is directly connected to the power supply voltage terminal 1.

  The other current dividing circuit 103 includes NPN-type differential pair transistors Q105 and Q106 each having an emitter electrode commonly connected to the collector electrode of the transistor Q102, and between the collector electrode of one transistor Q103 and the power supply voltage terminal 1. The differential circuit configuration includes a resistor R103 connected to the. The collector electrode of the other transistor Q106 is directly connected to the power supply voltage terminal 1.

  In these current dividing circuits 102 and 103, the collector electrodes of the transistors Q103 and Q105 are output terminals via an HPF (high-pass filter) circuit 40 provided to perform DC cut with the IF filter circuit 24 at the subsequent stage. 108 and 109. From the output terminals 108 and 109, signals S22 (P) and S22 (N) which are differential signals are output.

  The base electrodes of the transistors Q104 and Q106 are commonly connected to the gain control voltage input terminal 104, and one of the signals S32a (P) is input thereto. The base electrodes of the transistors Q103 and Q105 are commonly connected to the gain control voltage input terminal 105, and the other signal S32a (N) is input thereto.

  In the GCA circuit 22 (gain control circuit) configured as described above, the output signal S32a of the GCA control circuit 32, that is, the voltage difference between the gain control voltages S32a (P) and S32a (N) forming a differential signal is represented by Vc. The thermal voltage Vt = kT / q, k is Boltzmann's constant, T is absolute temperature, and q is the charge amount of electrons.

  Details of the method for deriving the gain Av are described in Japanese Patent No. 3598973, and will be briefly described here. The input voltage is vi (potential difference between the input signal S20 (P) and the input signal S20 (N)), the output voltage is vo, the resistance value of the resistor R101 is RA, and the resistance values of the resistors 102 and R103 are RB. Then, the gain Av of the gain control circuit according to the conventional example is

(Equation 1)
Av = vo / vi = (2RB / RA). [1 / {1+ (exp (Vc / Vt))}]
Given in. As is clear from this (Equation 1), the gain Av is variable by the gain control voltage Vc (potential difference between S32a (P) and S32a (N)) generated from the GCA control circuit 32.

  The IF filter circuit (LPF) 24 includes an operational amplifier 50 that is a balanced amplifier having an inverting input terminal and a non-inverting input terminal, and an inverting output terminal and a non-inverting output terminal, and an inverting output terminal and a non-inverting input of the operational amplifier 50. A parallel circuit of a resistor R22 and a capacitor C20 inserted and connected in a feedback path between the terminals and a resistor R23 and a capacitor C21 inserted and connected in a feedback path between the non-inverting output terminal and the inverting input terminal of the operational amplifier 50 It consists of a parallel circuit. Then, the output signal S22 of the GCA circuit 22, that is, the signals S22 (P) and S22 (N) (differential signals) having the same amplitude and opposite signs are input to the IF filter circuit 24, whereby the IF filter The circuit 24 outputs a signal S24I. In FIG. 4, only the I signal is shown.

  The DC level (common-mode voltage) of the output voltage of the GCA circuit 22 is set to a desired common-mode voltage by a common-mode voltage feedback circuit (common-mode feedback circuit) built in the IF filter circuit 24 at the subsequent stage. Therefore, it is necessary to cut the DC voltage by the HPF circuit 40, and the circuit area such as the capacity is particularly large.

This gain control circuit is used for the I signal system and the Q signal system. However, the conventional GCA circuit 22 has a large circuit area due to the large number of elements, and this also causes an element variation factor. IQ mismatch may occur and the image removal ratio may deteriorate. Further, when the power supply voltage (VCC) is set to a low voltage, the dynamic range becomes narrow, which is not suitable for recent low voltage ICs. Furthermore, in order to improve the S / N, it is necessary to increase the circuit current. On the other hand, it is necessary to lower the junction temperature as much as possible to improve the reliability of the device.
Japanese Patent No. 3598973 Japanese Patent Publication No. 7-20042 JP 2006-157866 A

  In the configuration of the conventional GCA circuit 22 described in Japanese Patent No. 3598973, in particular, there are an I signal processing system and a Q signal processing system such as the complex filter of this time, and the GCA circuit 22 is also provided before and between the filters. If a plurality of GCA circuits 22 are provided, a plurality of GCA circuits 22 are required, and the number of circuit elements increases. Further, when the common-mode voltage of the GCA circuit 22 and the common-mode voltage of the operational amplifier 50 constituting the filter are different, the HPF circuit 40 having a low cutoff frequency is required, and the element area such as the capacitance is particularly large. As a result, there is a possibility that an increase in circuit area, a deterioration in noise, an increase in circuit current, an IQ mismatch due to an increase in variation, and an image removal ratio may be deteriorated.

  In order to solve such problems and reduce IQ mismatch to improve image removal ratio, improve SN, and reduce circuit area, it is required to provide a circuit with a reduced number of circuit elements.

  An object of the present invention is to solve the above-described conventional problems, and to reduce the number of circuit elements, thereby reducing circuit area, improving noise, reducing circuit current, and improving variation. That is, the present invention provides a gain control filter device, a gain control complex filter device, and a receiving device having a gain control circuit with a smaller number of elements in a gain control circuit provided to ensure the S / N of an active filter. It is intended to provide.

  In order to solve the above-described problem, a first gain control filter device of the present invention includes an active filter circuit having an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal, and a non-active filter circuit. An inverting input terminal, a variable resistance circuit that is inserted in the first and second input paths leading to the inverting input terminal, and whose resistance value is controlled by the first control voltage, and gain by changing the first control voltage Is controlling.

  According to this configuration, since the variable resistance circuit is provided at the input portion of the active filter circuit for gain control, the number of circuit elements is reduced, thereby reducing circuit area, improving noise, reducing circuit current, and variation. Can be improved.

In the above configuration, the variable resistance circuit includes a first fixed resistor inserted in the first input path and a first field effect transistor inserted in the first input path in series with the first fixed resistance. A second variable resistor comprising a first variable resistor, a second fixed resistor inserted in the second input path, and a second field effect transistor inserted in the second input path in series with the second fixed resistor. And a third field effect transistor connected in series between the connection point of the first fixed resistor and the first variable resistor and the connection point of the second fixed resistor and the second variable resistor. And a fourth variable resistor comprising a fourth field effect transistor,
The first control voltage includes a second control voltage and a third control voltage forming a differential signal. The resistance values of the first and second variable resistors are controlled according to the second control voltage, The resistance values of the third and fourth variable resistors are preferably controlled according to the third control voltage.

  In the above configuration, the active filter circuit is provided between the balanced amplifier having the inverting input terminal, the non-inverting input terminal, the inverting output terminal, and the non-inverting output terminal, and between the non-inverting input terminal and the inverting output terminal of the balanced amplifier. And a first CR circuit that forms a first feedback path, and a second CR circuit that is provided between the inverting input terminal and the non-inverting output terminal of the balanced amplifier to form a second feedback path. It is preferable to become.

  In the above configuration, the variable resistance circuit is preferably controlled by the first control signal so that the output level of the active filter circuit becomes constant.

  A second gain control filter device according to the present invention includes a first active filter circuit having an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal, and a non-inverting input terminal of the first active filter circuit. A first variable resistance circuit inserted in the first and second input paths leading to the inverting input terminal, the resistance value of which is controlled by the first control voltage, an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and A second active filter circuit having a non-inverting output terminal and cascade-connected to the first active filter circuit; and an inverting output terminal and a non-inverting output terminal of the first active filter circuit to the second active filter circuit A non-inverting input terminal, and a second variable resistance circuit inserted in third and fourth input paths reaching the inverting input terminal, the resistance value of which is controlled by a second control voltage. The gain is controlled by changing the control voltage, and the gain by the first active filter circuit and the first variable resistance circuit, and the gain by the second active filter circuit and the second variable resistance circuit are SN and distortion. Are allocated so as to keep them in good condition.

  This configuration has the same effect as the first gain control filter device.

  The gain control complex filter device of the present invention includes a first inverting input terminal corresponding to a first signal, a first non-inverting input terminal, a first inverting output terminal, a first non-inverting output terminal, A complex active filter circuit having a second inverting input terminal, a second non-inverting input terminal, a second inverting output terminal, and a second non-inverting output terminal corresponding to a second signal orthogonal to the first signal; First variable resistance circuit having a resistance value controlled by a first control voltage inserted into first and second input paths extending to the first non-inverting input terminal and the first inverting input terminal of the complex active filter circuit And a second variable whose resistance value is controlled by the first control voltage inserted into the third non-inverting input terminal and the third and fourth input paths leading to the second inverting input terminal of the complex active filter circuit. A resistance circuit and changing the first control voltage. And it controls the gain.

  This configuration has the same effect as the first gain control filter device.

  In the gain control complex filter device having the above configuration, the first variable resistance circuit is inserted in the first input path in series with the first fixed resistance inserted in the first input path and the first fixed resistance. A first variable resistor composed of the first field effect transistor, a second fixed resistor inserted into the second input path, and a second fixed resistor inserted in series with the second fixed resistor. A second variable resistor composed of a second field effect transistor, and a connection point between the first fixed resistor and the first variable resistor and a connection point between the second fixed resistor and the second variable resistor are connected in series. The third variable resistor is composed of a third variable resistor composed of a third field effect transistor and a fourth variable resistor composed of a fourth field effect transistor, and the second variable resistor circuit is inserted into the third input path. A third fixed resistor and a third fixed resistor in series with the third fixed resistor A fifth variable resistor comprising a fifth field effect transistor inserted in the force path, a fourth fixed resistor inserted in the fourth input path, and a fourth input path in series with the fourth fixed resistance. A sixth variable resistor composed of a sixth field effect transistor inserted into the third fixed resistor, a connection point of the third fixed resistor and the fifth variable resistor, and a connection point of the fourth fixed resistor and the sixth variable resistor A seventh variable resistor composed of a seventh field effect transistor and an eighth variable resistor composed of an eighth field effect transistor connected in series therebetween, and the first control voltage forms a differential signal. The first, second, fifth and sixth variable resistors are controlled in accordance with the second control voltage, and the resistance values of the first, second, fifth and sixth variable resistors are controlled according to the second control voltage, and the third, fourth, The resistance values of the seventh and eighth variable resistors are controlled according to the third control voltage. It is preferred.

  The gain control complex filter device having the above configuration includes a complex active filter circuit, a complex active filter circuit, a first inverting input terminal, a first non-inverting input terminal, a first inverting output terminal, and a first non-inverting output. And a first CR circuit provided between the first non-inverting input terminal and the first inverting output terminal of the first balanced amplifier to form a first feedback path. A second CR circuit provided between the first inverting input terminal and the first non-inverting output terminal of the first balanced amplifier to form a second feedback path, and a second inverting input terminal , A second balanced amplifier having a second non-inverting input, a second inverting output, and a second non-inverting output, and a second non-inverting input of the second balanced amplifier and a second inverting A third C that is provided between the output end and forms a third feedback path Circuit, a fourth CR circuit provided between the second inverting input terminal and the second non-inverting output terminal of the second balanced amplifier to form a fourth feedback path, and a first balanced amplifier A first resistor connected between the first inverting input terminal of the second balanced amplifier and a second inverting output terminal of the second balanced amplifier; a first non-inverting input terminal of the first balanced amplifier; A second resistor connected between the second non-inverting output terminal of the balanced amplifier, a second inverting input terminal of the second balanced amplifier, and a first non-inverting output terminal of the first balanced amplifier. And a fourth resistor connected between the second non-inverting input terminal of the second balanced amplifier and the first inverting output terminal of the first balanced amplifier. Preferably it consists of.

  The receiving device of the present invention is a receiving device that demodulates a received signal into a video signal and an audio signal, and selects a RF signal of a predetermined frequency band included in the received signal and converts it to a low IF (intermediate frequency) signal. A tuner circuit including a conversion means and the above gain control complex filter device for removing an image signal included in a low IF signal, and a video signal and an audio signal are demodulated from the low IF (intermediate frequency) signal and inputted. And a demodulating circuit that supplies a signal corresponding to the signal level of the low IF signal to the tuner circuit, and changes the first control voltage so that the output level of the tuner circuit becomes constant.

  According to this configuration, the same effect as the above-described gain control complex filter device can be obtained.

  The present invention provides a gain control circuit that reduces the number of circuit elements by using a variable resistance circuit as a gain control circuit. As a result, the circuit area is reduced, noise is improved, circuit current is reduced, and variation is reduced. The IQ mismatch can be reduced by the improvement, and the deterioration of the image removal ratio due to the IQ mismatch can be improved. Thus, the present invention provides a gain control filter device having a gain control circuit with a smaller number of elements in a gain control circuit provided to ensure S / N of a filter composed of an active filter or a complex filter, and gain control A complex filter device and a receiving device can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration of a gain control filter device having a gain control circuit according to Embodiment 1 of the present invention. The same reference numerals are used for the same parts as in the conventional example. This gain control filter device is used, for example, as an IF filter circuit in the receiving device shown in FIG. 3 and a gain control circuit in the preceding stage.

  As shown in FIG. 1, the gain control filter device includes an IF filter circuit 241 and a variable resistance circuit (substitute for the GCA circuit) 221 provided in the preceding stage.

  The IF filter circuit 241 includes an operational amplifier 50 that is a balanced amplifier having an inverting input terminal and a non-inverting input terminal, and an inverting output terminal and a non-inverting output terminal, and a non-inverting input terminal and an inverting output terminal of the operational amplifier 50. A parallel circuit of a resistor R22 and a capacitor C20 inserted and connected to the feedback path between them, and a parallel circuit of a resistor R23 and a capacitor C21 inserted and connected to the feedback path between the inverting input terminal and the non-inverting output terminal of the operational amplifier 50 It consists of

  Then, the output signal S22 of the variable resistance circuit 221, that is, the signals S22 (P) and S22 (N) (differential signals) having the same amplitude and opposite signs are input to the IF filter circuit 241. The filter circuit 241 outputs a signal S24I. In FIG. 1, only the I signal is shown.

  The variable resistance circuit 221 includes a series circuit of a resistor R20 inserted in the input path to the non-inverting input terminal of the operational amplifier 50 of the IF filter circuit 241 and a MOS transistor Q22 constituting the variable resistance, and an inversion of the operational amplifier 50. Between the resistor R21 inserted in the input path leading to the input terminal and the MOS transistor Q23 constituting the variable resistor, the connection point between the resistor R20 and the MOS transistor Q22, and the connection point between the resistor R21 and the MOS transistor Q23 And a series circuit of MOS transistors Q20 and Q21 constituting a variable resistor connected to the. The MOS transistors Q20 and Q21 are controlled by a gain control voltage S32a (P), and the MOS transistors Q22 and Q23 are controlled by a gain control voltage S32a (N).

  FIG. 2 is a circuit diagram showing a configuration of a gain control complex filter device having a gain control circuit according to Embodiment 1 of the present invention. The same reference numerals are used for the same parts as in the conventional example. This gain control complex filter device is used, for example, as an IF filter circuit in the receiving device shown in FIG.

  As shown in FIG. 2, the gain control filter device includes an IF filter circuit 242 and variable resistance circuits (replacement of the GCA circuit) 222 and 232 provided in the preceding stage.

  The IF filter circuit 242 includes an operational amplifier 50 that is a balanced amplifier having an inverting input terminal and a non-inverting input terminal, and an inverting output terminal and a non-inverting output terminal, and a non-inverting input terminal and an inverting output terminal of the operational amplifier 50. A parallel circuit of a resistor R22 and a capacitor C20 inserted and connected to the feedback path between them, and a parallel circuit of a resistor R23 and a capacitor C21 inserted and connected to the feedback path between the inverting input terminal and the non-inverting output terminal of the operational amplifier 50 An operational amplifier 51 which is a balanced amplifier having an inverting input terminal and a non-inverting input terminal, and an inverting output terminal and a non-inverting output terminal, and a feedback path between the non-inverting input terminal and the inverting output terminal of the operational amplifier 51 The parallel circuit of the inserted resistor R32 and capacitor C30, and the resistor R33 and capacitor connected to the feedback path between the inverting input terminal and the non-inverting output terminal of the operational amplifier 51 are connected. A parallel circuit of the circuit C31, a resistor R40 connected between the inverting input terminal of the operational amplifier 50 and the inverting output terminal of the operational amplifier 51, the non-inverting input terminal of the operational amplifier 50, and the non-inverting output terminal of the operational amplifier 51 A resistor R41 connected between the inverting input terminal of the operational amplifier 51 and the non-inverting output terminal of the operational amplifier 50, a non-inverting input terminal of the operational amplifier 51, and an inverting output of the operational amplifier 50. It is comprised by resistance R43 connected between the ends.

  The variable resistance circuit 222 includes a series circuit of a resistor R20 inserted in the input path leading to the non-inverting input terminal of the operational amplifier 50 of the IF filter circuit 242 and a MOS transistor Q22 constituting the variable resistance, and an inversion of the operational amplifier 50. Between the resistor R21 inserted in the input path leading to the input terminal and the MOS transistor Q23 constituting the variable resistor, the connection point between the resistor R20 and the MOS transistor Q22, and the connection point between the resistor R21 and the MOS transistor Q23 And a series circuit of MOS transistors Q20 and Q21 constituting a variable resistor connected to the. The MOS transistors Q20 and Q21 are controlled by a gain control voltage S32a (P), and the MOS transistors Q22 and Q23 are controlled by a gain control voltage S32a (N).

  The variable resistance circuit 232 includes a series circuit of a resistor R30 inserted in the input path to the non-inverting input terminal of the operational amplifier 51 of the IF filter circuit 242, and a MOS transistor Q32 constituting the variable resistance, and an inversion of the operational amplifier 51. Between the resistor R31 inserted in the input path leading to the input terminal and the MOS transistor Q33 constituting the variable resistor, the connection point between the resistor R30 and the MOS transistor Q32, and the connection point between the resistor R31 and the MOS transistor Q33 And a series circuit of MOS transistors Q30 and Q31 constituting a variable resistor connected to the. The MOS transistors Q30 and Q31 are controlled by a gain control voltage S32a (P), and the MOS transistors Q32 and Q33 are controlled by a gain control voltage S32a (N).

  In the configuration of FIG. 1, the output signal S14 (see FIG. 3) of the demodulation circuit 14 is input to the variable resistance control circuit having the same configuration as the GCA control circuit 32 (see FIG. 3), and is variable by the variable resistance control circuit. The resistance value of the resistance circuit 221 is controlled.

  In the configuration of FIG. 2, the output signal S14 (see FIG. 3) of the demodulation circuit 14 is input to the variable resistance control circuit having the same configuration as the GCA control circuit 32 (see FIG. 3). The resistance values of the variable resistance circuits 222 and 232 having the same configuration are controlled. Although not shown, the variable resistance circuit used in place of the conventional GCA circuits 25 and 26 is also controlled by the output signal S14 of the demodulation circuit 14 via the variable resistance control circuit.

  The MOS transistors Q20 to Q23 and Q30 to Q33 in the variable resistance circuits 222 and 232 operate as variable resistances controlled by a gain control voltage, and gain control is performed. However, the configuration of the IF filter circuits 241 and 242 is an example. In this configuration, an active filter network including an operational amplifier and an RC is used. However, a Gm-C filter network including a transconductance and a capacitor may be used.

  FIG. 6 shows a conventional RC tuneable integrator described in Japanese Patent Publication No. 7-20042. Electronically controlled MOS transistors Q90 and Q91 are arranged on the input path of the operational amplifier. RC tuning is enabled by applying an appropriate gain control voltage Vc to the gates of the MOS transistors Q90 and Q91. However, there are some problems in this case.

  First, in this conventional type, since the resistor placed on the input path is composed of the MOS transistors Q90 and Q91, distortion occurs due to the square characteristic of the MOS device. . For this reason, in the first embodiment of the present invention, fixed resistors R20 and R21 are connected in series to the MOS transistors Q22 and Q23, respectively, to improve the distortion characteristics.

  Similarly, in the second embodiment, fixed resistances R20, R21, R30, and R31 are connected in series to the MOS transistors Q22, Q23, Q32, and Q33, respectively, to improve the distortion characteristics.

  Second, the variable range of the input resistance is narrow in a state where only one MOS transistor is connected to each input path. However, in the first embodiment of the present invention, the MOS transistor Q20, By arranging Q21, the variable range of the input resistance is expanded. As a result, the gain control range can be widened.

  Similarly, in the second embodiment of the present invention, the variable range of the input resistance is expanded by newly disposing MOS transistors Q20, Q21, Q30, and Q31. As a result, the gain control range can be widened.

Next, the transfer function H ₁ (s) of the IF filter 241 (LPF) including the variable resistance circuit 221 shown in FIG. Here, it is assumed that the resistance values of the resistor R20 and the MOS transistors Q20 and Q22 placed on the input path are Ri, Rm1, and Rm2, respectively. Also, let Rf be the resistance value of the resistor R22 placed in the feedback path, and Cf be the capacitance value of the capacitor C20. The input resistance Rin can be obtained by calculating a current flowing into the feedback path of the operational amplifier 50 with respect to a change in the input voltage. ωo is a normalized frequency. s is a Laplace operator.

(Equation 2)
H ₁ (s) = − (Rf / Rin) · (ωo / (s + ωo))

(Equation 3)
ωo = 1 / (Rf · Cf)

(Equation 4)
Rin = Ri · (1 + Rm2 / Rm1) + Rm2
As a feature, the normalized frequency ωo can be obtained by the parallel Rf · Cf constant of the feedback path, but does not depend on the input series resistance Rin.

Further, regarding the input resistance Rin, for example, when Ri >> Rm1, Rm2,
If Rm2 >> Rm1, then Rin≈∞,
If Rm2 = Rm1, then Rin≈2Ri,
If Rm2 << Rm1, then Rin≈Ri,
It can be seen that it has a very large gain variable range.

  With this configuration, the MOS transistor that operates as a resistor is arranged in the input path depending on the gate voltage to which the gain control voltage is applied, and is generated due to the square characteristic of the MOS transistor. The distortion characteristic to be improved can be improved by inserting a fixed resistor, and the gain of the filter can be greatly adjusted. Further, only six elements are required, and a gain control circuit can be realized very easily.

  For example, if the MOS transistor is an NMOS transistor, the gain control voltage (gate voltage) S32a (P) forming a differential signal increases, and if the gain control voltage (gate voltage) S32a (N) decreases, the resistance value Rm1 decreases. The resistance value Rm2 increases. As a result, the input resistance Rin increases and the filter gain decreases.

  Conversely, if the gate voltage S32a (P) forming the differential signal decreases and the gate voltage S32a (N) increases, the resistance value Rm1 increases and the resistance value Rm2 decreases. As a result, the input resistance Rin decreases and the gain of the filter increases.

  Any type of transfer function can be realized with a circuit including an integrator and an adder. For this reason, in the present invention, the first-order LPF has been described as an example. However, the present system can be applied to a filter circuit using only a differential input integrator such as a higher-order leapfrog circuit or biquad circuit. I understand.

  In the case of the Zero-IF method adopted in DVB-H (Digital Video Broadcasting for Handheld) for European mobile phones, a complex filter is not necessary, and the IF filter circuit 24 and the IF filter circuit 27 have a quadrature phase relationship. An IF filter circuit having an LPF similar to that shown in FIG. 1 may be disposed in each of the I signal processing system and the Q signal processing system.

  Regarding the gain control circuit, the GCA circuit 23 in front of the IF filter circuit 24 in FIG. 3, the GCA circuit 25 and the GCA circuit 26 connected between the stages of the IF filter circuit 24 and the IF filter circuit 27 are the variable resistance circuit 221 described above. You can replace it with something completely the same.

  On the other hand, when the LOW-IF method adopted in Japanese ISDB-T and European DVB-T is adopted, a complex filter circuit for image removal as shown in FIG. 2 is necessary.

  In the complex filter circuit, as described in Japanese Patent Application Laid-Open No. 2006-157866, as shown in FIG. The input is made through resistors R40, R41, R42, and R43.

  In this case as well, the gain control circuit may have the same configuration as that applied to the LPF in FIG. 1, and the GCA circuit 23, IF filter circuit 24 and IF filter circuit 27 in the previous stage of the IF filter circuit 24 in FIG. The GCA circuit 25 and the GCA circuit 26 connected between the stages may be exactly the same as the variable resistance circuit 221.

Next, the transfer function H ₂ (s) of the complex filter including the variable resistance circuit 222 and the variable resistance circuit 232 shown in FIG. 2 is obtained in the same manner as in (Expression 2) to (Expression 4).

(Equation 5)
H ₂ (s) = − (Rf / Rin) · {ωo / (j (ω−ω _C ) + ωo)}

(Equation 6)
ωo = 1 / (Rf · Cf)

(Equation 7)
ω _C = 1 / (R1 · Cf)

(Equation 8)
Rin = Ri · (1 + Rm2 / Rm1) + Rm2
As a feature, it can be seen that the normalization frequency ωo can be obtained by the parallel Rf · Cf constant of the feedback path, but does not depend on the input series resistance Rin in the complex filter as in the LPF described above.

  According to such a configuration, the gain of the filter can be adjusted by disposing the MOS transistor that operates as a resistor depending on the gate voltage that is the gain control voltage in the input path. Further, only six elements are required, and a gain control circuit can be realized very easily.

  Next, an example of the variable resistance control circuit will be described with reference to FIG. However, this variable resistance control circuit has the same configuration as that of the conventional GCA control circuit 32. FIG. 5 shows known differential amplifier circuits 70, 71 and 72. For example, in the differential amplifier circuit 70, the emitters are connected to each other through resistors R7 and R8, the reference voltage Vb1 and the signal S14 are applied to the respective bases, and the respective collectors are powered via the resistors R1 and R2. NPN transistors Q1 and Q2 forming a differential amplification pair connected to the voltage terminal 1, one end connected to the emitters of the NPN transistors Q1 and Q2 via resistors R7 and R8, and the other end connected to the ground GND It consists of a current source I1.

  Further, the differential amplifier circuit 71 and the differential amplifier circuit 72 have the same configuration. In FIG. 5, symbols Q3 to Q6 indicate NPN transistors, symbols R3 to R6 and R9 to R12 indicate resistors, and symbols I2 and I3 indicate current sources, respectively.

  Preset bias voltages Vb1, Vb2, and Vb3 are respectively applied to bases of NPN transistors Q2, Q4, and Q6 which are one input terminals of the differential amplifier circuits 70, 71, and 72. On the other hand, the output signal S14 of the demodulation circuit 14 is commonly input to the bases of NPN transistors Q1, Q3, and Q5 that are the other inputs of the differential amplifier circuits 70, 71, and 72. Then, it is amplified to an appropriate gain. The output voltages of the differential amplifier circuits 70, 71, 72 are output signals S32a, S32b, S32c, respectively, and a variable resistance circuit (corresponding to the GCA circuits 22, 23) and a variable resistance circuit (GCA circuits 25, 26), respectively. And the GCA circuit 28 are supplied as respective control voltages.

  Here, when the bias voltages of the differential amplifier circuits 70, 71, 72 are set to Vb1 <Vb2 <Vb3, for example, the differential output level is V1out (= S32a (P) −S32a (N))> V2out. (= S32b (P) -S32b (N))> V3out (= S32c (P) -S32c (N)). At this time, the gain of the first stage variable resistance circuit (corresponding to the GCA circuits 22 and 23) of the filter becomes the largest, the gain of the last stage GCA circuit 28 becomes the smallest, and the noise is improved. However, if the first stage gain is increased too much, the distortion characteristics may be deteriorated, so it is necessary to improve noise and distortion in a balanced manner.

  The point at which gain distribution and automatic gain control of each gain control circuit (variable resistance circuit) starts to be applied can be arbitrarily set by appropriately determining the gain of the amplifier and the bias voltages Vb1, Vb2, and Vb3.

  As described above, according to the present invention, the variable resistance circuits 221 and 222 and the variable resistance circuit 231 thus configured can realize a gain control circuit with a very small number of elements.

  In the present invention, the MOS transistor placed on the input path and operating as a variable resistor has been described as an NMOS transistor. However, for example, this transistor may be a PMOS transistor. In the present invention, a digital TV receiving apparatus has been described as an application example, but it goes without saying that any receiving apparatus having gain control may be used. In the present invention, the received signal is input from the antenna. However, it goes without saying that the present invention may be applied to broadcasting received from a cable.

  As described above, according to the present invention, the gain control circuit for adjusting the gain of the filter can be realized with a configuration having a very small number of elements. For example, a video playback device with a built-in television receiver or television tuner is provided. Applicable to any field.

It is a circuit diagram which shows the gain control filter apparatus (LPF) provided with the variable resistance circuit in embodiment of this invention. It is a circuit diagram which shows the gain control complex filter apparatus provided with the variable resistance circuit in embodiment of this invention. It is a block diagram which shows the receiver with which embodiment of this invention is applied. It is a circuit diagram which shows the gain control filter apparatus (LPF) provided with the conventional GCA circuit. It is a circuit diagram which shows the resistance value control circuit (GCA control circuit) with which embodiment of this invention is applied. It is a circuit diagram which shows the integrator which can perform conventional RC tuning. It is a characteristic view which shows the characteristic of an example of IF filter for 13seg of ISDB-T.

Explanation of symbols

1 Power supply voltage terminal 10 Antenna 11 RF filter 12 LNA
13 Tuner circuit 14 Demodulator 20 I signal mixer 21 Q signal mixer 22 GCA circuit 22 GCA circuit 23 GCA circuit 24 IF filter 25 GCA circuit 26 GCA circuit 27 IF filter 28 GCA circuit 30 Phase shifter 31 Local oscillator 32 GCA control Circuit 40 HPF circuits 50, 51, 90 Operational amplifiers 70-72, 102-103 with common mode feedback Differential amplifier circuits 221, 222, 232 Variable resistance circuits 241, 242 IF filter circuits Q1-Q6, Q90-Q91, Q101 to Q106 NPN transistors Q20 to Q23, Q30 to 33 MOS transistors R1 to R12, R20 to R23, R101 to R103 Resistors C20 to C21, C30 to 31, C90 to 91 Capacitors I1 to I3, I101 to I102 Current source Vb 1 to Vb3 reference voltage

Claims (7)

An active filter circuit having an inverting input terminal, a non-inverting input terminal, an inverting output terminal and a non-inverting output terminal, and inserted into first and second input paths reaching the non-inverting input terminal and the inverting input terminal of the active filter circuit. A variable resistance circuit whose resistance value is controlled by a first control voltage, and controlling the gain by changing the first control voltage;
The variable resistance circuit includes a first fixed resistor inserted in the first input path, and a first field effect transistor inserted in the first input path in series with the first fixed resistor. A first variable resistor, a second fixed resistor inserted in the second input path, and a second field effect transistor inserted in the second input path in series with the second fixed resistor. The second variable resistor is connected in series between the connection point of the first fixed resistor and the first variable resistor and the connection point of the second fixed resistor and the second variable resistor. A third variable resistor made of a third field effect transistor and a fourth variable resistor made of the fourth field effect transistor;
The first control voltage includes a second control voltage and a third control voltage that form a differential signal, and the resistance value of the first and second variable resistors is controlled according to the second control voltage. And a gain control filter device in which the third and fourth variable resistors have resistance values controlled in accordance with the third control voltage.   The active filter circuit is provided between a balanced amplifier having an inverting input terminal, a non-inverting input terminal, an inverting output terminal and a non-inverting output terminal, and between the non-inverting input terminal and the inverting output terminal of the balanced amplifier. And a second CR circuit provided between an inverting input terminal and a non-inverting output terminal of the balanced amplifier to form a second feedback path. The gain control filter device according to 1.   The gain control filter device according to claim 1, wherein the variable resistance circuit is controlled by the first control signal so that an output level of the active filter circuit becomes constant. A first active filter circuit having an inverting input terminal, a non-inverting input terminal, an inverting output terminal and a non-inverting output terminal, and first and second terminals reaching the non-inverting input terminal and the inverting input terminal of the first active filter circuit A first variable resistance circuit that is inserted in the input path and has a resistance value controlled by a first control voltage, an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal. the non-inverting output terminal of the non-inverting input terminal before Symbol first active filter circuits, the inverted output terminal is connected to the respective inverting output terminal, an inverting input terminal of the non-inverting output terminal of the first active filter circuit, inverting the second and active filter circuit formed by connecting the input terminal, respectively, before Symbol non-inverting input terminal of the second active filter circuit is inserted into the input path of the third and fourth leading to the inverting input terminal second Control power And a second variable resistance circuit whose resistance value is controlled by the control circuit, the gain is controlled by changing the first and second control voltages, and the first active filter circuit and the first variable circuit The gain by the resistance circuit and the gain by the second active filter circuit and the second variable resistance circuit are variable,
The first variable resistance circuit includes a first fixed resistor inserted in the first input path, and a first field effect inserted in the first input path in series with the first fixed resistance. A first variable resistor composed of a transistor; a second fixed resistor inserted into the second input path; and a second electric field inserted into the second input path in series with the second fixed resistor. A second variable resistor formed of an effect transistor; and a connection point between the first fixed resistor and the first variable resistor and a connection point between the second fixed resistor and the second variable resistor in series. A third variable resistor composed of a connected third field effect transistor and a fourth variable resistor composed of the fourth field effect transistor;
The second variable resistance circuit includes a third fixed resistor inserted in the third input path, and a fifth field effect inserted in the third input path in series with the third fixed resistor. A fifth variable resistor composed of a transistor; a fourth fixed resistor inserted in the fourth input path; and a sixth electric field inserted in the fourth input path in series with the fourth fixed resistor. A sixth variable resistor composed of an effect transistor, a connection point between the third fixed resistor and the fifth variable resistor, and a connection point between the fourth fixed resistor and the sixth variable resistor are connected in series. A seventh variable resistor composed of a connected seventh field effect transistor and an eighth variable resistor composed of the eighth field effect transistor;
Each of the first control voltage and the second control voltage includes a third control voltage and a fourth control voltage forming a differential signal, and the first, second, fifth, and sixth variable resistors are The resistance value is controlled according to the third control voltage, and the resistance values of the third, fourth, seventh and eighth variable resistors are controlled according to the fourth control voltage. Gain control filter device. A first inverting input terminal corresponding to the first signal, a first non-inverting input terminal, a first inverting output terminal and a first non-inverting output terminal, and a second signal orthogonal to the first signal A complex active filter circuit having a second inverting input terminal, a second non-inverting input terminal, a second inverting output terminal, and a second non-inverting output terminal corresponding to the first inverting input terminal, A first variable resistance circuit inserted in the first and second input paths leading to the non-inverting input terminal and the first inverting input terminal, the resistance value of which is controlled by a first control voltage, and the complex active filter circuit A second non-inverting input terminal, a second variable resistance circuit inserted in the third and fourth input paths leading to the second inverting input terminal, the resistance value of which is controlled by the first control voltage, Controlling the gain by changing the first control voltage;
The first variable resistance circuit includes a first fixed resistor inserted in the first input path, and a first field effect inserted in the first input path in series with the first fixed resistance. A first variable resistor composed of a transistor; a second fixed resistor inserted into the second input path; and a second electric field inserted into the second input path in series with the second fixed resistor. A second variable resistor formed of an effect transistor; and a connection point between the first fixed resistor and the first variable resistor and a connection point between the second fixed resistor and the second variable resistor in series. A third variable resistor composed of a connected third field effect transistor and a fourth variable resistor composed of the fourth field effect transistor;
The second variable resistance circuit includes a third fixed resistor inserted in the third input path, and a fifth field effect inserted in the third input path in series with the third fixed resistor. A fifth variable resistor composed of a transistor; a fourth fixed resistor inserted in the fourth input path; and a sixth electric field inserted in the fourth input path in series with the fourth fixed resistor. A sixth variable resistor composed of an effect transistor, a connection point between the third fixed resistor and the fifth variable resistor, and a connection point between the fourth fixed resistor and the sixth variable resistor are connected in series. A seventh variable resistor composed of a connected seventh field effect transistor and an eighth variable resistor composed of the eighth field effect transistor;
Each of the first control voltage and the second control voltage includes a third control voltage and a fourth control voltage forming a differential signal, and the first, second, fifth, and sixth variable resistors are The resistance value is controlled according to the third control voltage, and the resistance values of the third, fourth, seventh and eighth variable resistors are controlled according to the fourth control voltage. A gain control complex filter device.   The complex active filter circuit includes a first balanced amplifier having a first inverting input terminal, a first non-inverting input terminal, a first inverting output terminal, and a first non-inverting output terminal, and the first balanced amplifier. A first CR circuit provided between a first non-inverting input terminal and a first inverting output terminal of the amplifier to form a first feedback path; and a first inverting input of the first balanced amplifier A second CR circuit provided between the first non-inverting output terminal and the first non-inverting output terminal to form a second feedback path; a second inverting input terminal; a second non-inverting input terminal; A second balanced amplifier having an output end and a second non-inverting output end; and a third balanced amplifier provided between a second non-inverting input end and a second inverting output end of the second balanced amplifier. A third CR circuit forming a feedback path; a second inverting input terminal of the second balanced amplifier; A fourth CR circuit which is provided between the non-inverting output terminal of the first balanced amplifier and forms a fourth feedback path; a first inverting input terminal of the first balanced amplifier; and a second CR circuit of the second balanced amplifier. A first resistor connected between the inverting output terminal and a first non-inverting input terminal of the first balanced amplifier and a second non-inverting output terminal of the second balanced amplifier. A second resistor connected; a third resistor connected between a second inverting input terminal of the second balanced amplifier and a first non-inverting output terminal of the first balanced amplifier; 6. The gain control complex according to claim 5, comprising a fourth resistor connected between a second non-inverting input terminal of the second balanced amplifier and a first inverting output terminal of the first balanced amplifier. Filter device. A receiving device that demodulates a received signal into a video signal and an audio signal,
6. The frequency control means for selecting an RF signal in a predetermined frequency band included in the received signal and converting it to a low IF (intermediate frequency) signal, and gain control according to claim 5, wherein the image signal included in the low IF signal is removed. A tuner circuit comprising a complex filter device;
The video signal and the audio signal are demodulated from the low IF (intermediate frequency) signal, and a signal corresponding to the signal level of the input low IF signal is supplied to the tuner circuit so that the output level of the tuner circuit becomes constant. And a demodulating circuit for changing the first control voltage.

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