JP4806696B2 - Information processing device - Google Patents

Description

  The present invention relates to an information processing apparatus such as a POS (Point Of Sales) terminal.

  The POS terminal is an information processing apparatus specialized for processing customer purchase information. In recent years, a POS terminal is often configured using a versatile personal computer.

  A computer system such as a personal computer is equipped with a microprocessor mainly serving as the center thereof and a main memory in which a program is stored. The microprocessor and the main memory are connected via a memory controller called a north bridge or the like. A system bus is connected between the microprocessor and the memory controller, and between the memory controller and the main memory (see, for example, Patent Document 1).

  This type of computer system improves performance by increasing the processing speed of the microprocessor. However, the microprocessor reads necessary data from the main memory via the memory controller. For this reason, even if the processing speed of only the microprocessor is increased, if the speed at which the memory controller reads data from the memory is slow, the microprocessor waits for processing until the data is read. In order to improve performance, it is necessary to increase not only the microprocessor but also the memory controller.

In order to increase the speed of the microprocessor and the memory controller, the common operating frequency may be increased. However, when the operating frequency is increased, the signal exchanged between the memory controller and the microprocessor is attenuated. When the signal is attenuated, the receiving side cannot receive the signal and may cause an error. Signal attenuation can be improved by raising the system bus voltage.
JP-T-2006-505046

  As described above, in the case of an information processing apparatus mainly composed of a computer system, in order to improve the performance, it is necessary to increase the voltage of the system bus connecting the memory controller and the microprocessor. However, the value of the voltage supplied to the system bus is always constant. For this reason, when the value of the supply voltage to the system bus is increased in order to improve the performance, a high voltage is always supplied to the system bus, so that the power consumption of the entire system is greatly increased and the amount of heat generation is increased. When the amount of generated heat increases, a mechanism for heat dissipation is required, which leads to an increase in size and cost of the system. In addition, when the mechanism for heat dissipation is insufficient, there is a possibility that IC components such as a microprocessor and a memory controller are thermally runaway or thermally destroyed when used in a high temperature environment.

  In addition, when the system bus voltage is increased, the amplitude of the signal increases, so that radiation noise from the substrate increases. Since the level of noise radiated from the equipment is regulated by law, if it exceeds the regulation, measures are required at the time of design, and there is a concern of further cost increase.

  Such a problem can be solved by making the voltage supplied to the system bus variable and reducing the supply voltage when high-speed processing is not required, thereby suppressing unnecessary heat dissipation and radiation noise.

  The present invention has been made based on such circumstances, and an object of the present invention is to make it possible to suppress useless heat generation and radiation noise by making the voltage supplied to the system bus variable. A processing apparatus is to be provided.

The present invention relates to a power supply circuit that supplies power to a system bus that connects a microprocessor and a memory controller in an information processing apparatus that transfers data between the microprocessor and a memory via a memory controller. A clock generator for supplying a clock pulse having a frequency corresponding to a bus speed set by a bus speed selection signal output from the microprocessor to the microprocessor and the memory controller, and the bus speed output from the microprocessor A decoding circuit that receives a selection signal, decodes bit information corresponding to the bus speed included in the bus speed selection signal, obtains the bus speed, and determines a power supply voltage supplied to the system bus from the bus speed; The power supply voltage supplied to the system bus is decoded And a voltage varying means for changing the output value of the power supply circuit as in the determined value.

  According to the present invention in which such measures are taken, it is possible to provide an information processing apparatus that can vary the voltage supplied to the system bus and can suppress wasteful heat generation and radiation noise.

The best mode for carrying out the present invention will be described below with reference to the drawings.
The principal part structure of the information processing apparatus 1 in this Embodiment is shown with the block diagram of FIG. As illustrated, the information processing apparatus 1 includes a microprocessor 11, a main memory 12, a memory controller 13, an I / O (Input / Output) controller 14, a clock generator 15, a power supply circuit 16, and a decoding circuit 17. Yes.

  Between the microprocessor 11 and the memory controller 13, between the memory controller 13 and the main memory 12, between the memory controller 13 and the I / O controller 14, and between the microprocessor 11 and the clock generator 15, respectively. The system buses 21, 22, 23, and 24 are connected. Of the system buses 21 to 24, a front side bus is used for the system bus 21 that connects the microprocessor 11 and the memory controller 13. A system bus 24 connecting the microprocessor 11 and the clock generator 15 is also connected to the decode circuit 17.

  A microprocessor 11 mainly composed of a CPU (Central Processing Unit) plays a central role in the information processing apparatus 1. A main memory 12 composed of a ROM (Read Only Memory) and a RAM (Random Access Memory) stores programs and data.

  A memory controller 13 called a north bridge or the like reads data from the main memory 12 or writes data according to a command from the microprocessor 11. The memory controller 13 is connected to the display 2.

  An I / O controller 14 called a south bridge or the like is connected to the microprocessor 11 via the memory controller 13. The I / O controller 14 exchanges data with an auxiliary storage device such as a hard disk and an input / output device such as a keyboard, mouse, and printer under the control of the microprocessor 11.

  The clock generator 15 supplies a clock pulse CLK to the microprocessor 11 and the memory controller 13. The power supply circuit 16 supplies a power supply voltage to each part including the system buses 21 to 24 (power supply means). The decode circuit 17 will be described later.

  The information processing apparatus 1 having such a configuration has an active mode and a sleep mode as operation modes. The active mode is a mode in which processing is being executed. The sleep mode is a mode in which processing is suspended.

  The microprocessor 11 outputs a bus speed selection signal BSEL for setting the speed of the front side bus 21 to the clock generator 15 via the system bus 24 at the time of rising or changing the operation mode. Typical bus speeds include 68 MHz, 100 MHz, 133 MHz, 400 MHz, and 533 MHz.

  The clock generator 15 generates a clock pulse CLK having a frequency corresponding to the bus speed set by the bus speed selection signal BSEL. Then, this clock pulse CLK is supplied to the microprocessor 11 and the memory controller 13. The microprocessor 11 and the memory controller 13 that have received the clock pulse CLK operate at an operating frequency several times the bus speed.

For example, if the bus speed set by the bus speed selection signal BSEL is 133 MHz and the magnification is 23.0 times,
133 MHz × 23.0 = 306.699 MHz
= 3.06 GHz
It becomes. That is, the microprocessor 11 and the memory controller 13 operate at an operating frequency of 3.06 GHz.

  The function of the decoding circuit 17 will be described with reference to the flowchart of FIG. The decode circuit 17 waits for a bus speed selection signal BSEL output from the microprocessor 11 (P1). When receiving the bus speed selection signal BSEL, the decode circuit 17 decodes the value of the bus speed selection signal BSEL (P2). The bus speed selection signal BSEL includes several bits of information corresponding to the bus speed. The decode circuit 17 obtains the bus speed of the front side bus 21 by decoding several bits of information included in the bus speed selection signal BSEL. The bus speed relates to the operating frequency of the microprocessor 11 or the memory controller 13 (operating frequency acquisition means).

When the bus speed is obtained from the bus speed selection signal BSEL, the decode circuit 17 determines the power supply voltage for the front side bus 21 from the bus speed (P3).
For example, when the bus speed is 200 MHz, 1.2 V is selected as the power supply voltage, and when the bus speed is 133 MHz, 1.05 V is selected. Comparing the bus speed of 200 MHz and the bus speed of 133 MHz, the operating frequency of the microprocessor 11 or the memory controller 13 is higher in the former (200 MHz) than in the latter (133 MHz). That is, the decode circuit 17 selects a high value as the power supply voltage for the front side bus 21 when the bus speed selection signal BSEL for setting the operating frequency of the microprocessor 11 or the memory controller 13 to be high is input. When the bus speed selection signal BSEL whose operating frequency is set low is input, a low value is selected.

  When the power supply voltage for the front side bus 21 is thus determined, the decode circuit 17 changes the output voltage value of the power circuit 16 so that the power supply voltage for the front side bus 21 becomes the determined value. (P4: Voltage variable means).

  Thus, in this embodiment, when the operating frequency of the microprocessor 11 or the memory controller 13 is high, that is, when high-speed processing is required, the value is high, and when the operating frequency is low, that is, high-speed processing is required. The voltage of the power source supplied to the front side bus 21 is varied so that the value is low when not.

  Therefore, when the operating frequency is high, attenuation of a signal exchanged between the memory controller 13 and the microprocessor 11 is suppressed, so that stable operation can be performed. On the other hand, when the operating frequency is low, the voltage of the power supplied to the front side bus 21 is low, so that power consumption can be reduced. As a result, wasteful heat generation and radiation noise are suppressed, so that the cost for a mechanism for heat dissipation and a mechanism for suppressing radiation noise can be reduced, and the system can be downsized. Furthermore, even when used in a high temperature environment, the possibility of thermal runaway or thermal destruction of IC components such as the microprocessor 11 and the memory controller 13 can be extremely reduced.

  The present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage.

  For example, in the above-described embodiment, the information regarding the operating frequency of the microprocessor 11 or the memory controller 13 is acquired by outputting a bus speed selection signal output from the microprocessor. It is not limited. For example, the frequency of the clock pulse CLK generated from the clock generator 15 is detected, the operating frequency of the microprocessor 11 or the memory controller 13 is obtained from the frequency, and the power supply voltage supplied to the front side bus 21 May be made variable.

In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, the constituent elements over different embodiments may be combined.
Hereinafter, the invention described in the scope of claims of the present application will be appended.
[Appendix 1]
In an information processing apparatus that transfers data between a microprocessor and a memory via a memory controller,
Power supply means for supplying power to a system bus connecting between the microprocessor and the memory controller;
Operating frequency acquisition means for acquiring information on the operating frequency of the microprocessor or the memory controller;
Voltage variable means for varying the voltage of the power supplied to the system bus by the power supply means in accordance with the operating frequency based on the information obtained by the operating frequency acquisition means;
An information processing apparatus comprising:
[Appendix 2]
The information processing apparatus according to claim 1, wherein the voltage varying unit lowers a voltage of a power source supplied to the system bus when the operating frequency is lowered.
[Appendix 3]
In an information processing apparatus that transfers data between a microprocessor and a memory via a memory controller,
A power supply circuit for supplying power to a system bus connecting between the microprocessor and the memory controller;
A clock generator for commonly supplying a clock pulse having a frequency corresponding to a bus speed selection signal output from the microprocessor to the microprocessor and the memory controller;
A decode circuit that decodes the bus speed selection signal and varies the voltage of the power supplied from the power supply circuit to the system bus from the decoded value;
An information processing apparatus comprising:
[Appendix 4]
4. The information processing apparatus according to claim 3, wherein the decode circuit reduces the voltage of a power supply supplied to the system bus when a bus speed selection signal that decreases the frequency of the clock pulse is input. .

The block diagram which shows the principal part structure of the information processing apparatus which is one embodiment of this invention. 6 is a flowchart used for describing functions of a decoding circuit provided in the information processing apparatus according to the embodiment;

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Information processing apparatus, 2 ... Display, 11 ... Microprocessor, 12 ... Main memory, 13 ... Memory controller, 14 ... I / O controller, 15 ... Clock generator, 16 ... Power supply circuit, 17 ... Decode circuit, 21 -24 System bus.

Claims (2)

In an information processing apparatus that transfers data between a microprocessor and a memory via a memory controller,
A power supply circuit for supplying power to a system bus connecting between the microprocessor and the memory controller;
A clock generator for supplying a clock pulse having a frequency corresponding to a bus speed set by a bus speed selection signal output from the microprocessor to the microprocessor and the memory controller;
Receives the bus speed selection signal output from the microprocessor , decodes bit information corresponding to the bus speed included in the bus speed selection signal, acquires the bus speed, and supplies the bus speed from the bus speed to the system bus A decoding circuit for determining the power supply voltage to be
Voltage varying means for changing the output value of the power supply circuit so that the power supply voltage supplied to the system bus becomes a value determined by the decode circuit;
An information processing apparatus comprising: When the decode circuit receives a bus speed selection signal in which the frequency of the clock pulse is set higher than the previous setting , the decoding circuit selects a value higher than the previous power supply voltage supplied to the system bus, frequency information processing apparatus according to claim 1, wherein when receiving a bus speed selection signal and selects a lower than the previous value as the power supply voltage supplied to said system bus is set lower than the previous setting.

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