JP4787651B2 - Clock distribution circuit for digital processing equipment - Google Patents

Description

  The present invention relates to a clock distribution circuit of a digital processing apparatus composed of a large number of semiconductor devices, and more particularly to a noise reduction method in clock distribution.

  Examples of this type of digital processing device include a wireless communication device such as a mobile phone, a waveform analysis device, and a frequency synthesizer. For example, a digital frequency synthesizer converts an analog signal output from a divided voltage-controlled oscillator into a digital signal by an A / D converter and imports the digital signal into a digital processing device. The output frequency of the voltage-controlled oscillator of the PLL is controlled by performing phase comparison by digital filter processing using a semiconductor device and further by performing frequency division ratio switching processing.

  As described above, since a digital processing apparatus including a large number of semiconductor devices uses the same reference signal as that of other devices for digital processing in each semiconductor device, a clock distribution circuit is required.

As shown in FIG. 6, the clock distribution circuit generates a clock output source 1 that generates a clock pulse of several tens of MHz to several hundreds of MHz with a crystal oscillation circuit or the like, and generates N clock signals from this clock for distribution output. The distribution circuit (buffer) 2 for obtaining The distribution circuit 2 transmits each clock signal to each clock transmission destination circuit 3 _{1 to} 3 _N such as a digital processing device through a transmission line such as a strip line or a coaxial cable.

In this clock distribution circuit, reflection noise is generated due to a mismatch between the output impedance of the distribution circuit 2 and the input impedances of the clock transmission destination circuits 3 _{1 to} 3 _N , and the clock waveform is distorted (see FIG. 7). Also, by distributing to a plurality of transmission destination circuits, the length of the transmission line becomes long, it is easily affected by impedance mismatching, and causes ringing noise and jitter. In addition, the generated spurious component is radiated to peripheral circuits including other clock transmission paths and transmission destination circuits and becomes a factor that generates unnecessary waves (see FIG. 8).

  In order to reduce such noise, measures such as shortening the clock transmission path, parallel termination, and insertion of a damping resistor are taken, but it is necessary to simultaneously deal with problems such as isolation between circuits and level reduction. .

  Another clock distribution method uses a sine wave signal as a clock signal. In this method, a sine wave signal is generated as a reference clock, amplified by an analog amplifier, analog-transmitted to a plurality of transmission destination circuits, digitized by the transmission destination circuit, and used as a clock signal (see, for example, Patent Document 1). ).

  In this document, the clock distribution device has a configuration in which a plurality of couplers are connected in an etch tree structure, and the clock transmission destination circuit is provided with an impedance matching circuit for suppressing reflection of the RF signal.

JP 2001-166846 A

  In the device of Patent Document 1 using the conventional RF signal, the RF signal is distributed by the coupler, so that the reflected wave of the signal can be suppressed, but a loss of about 3 dB occurs. When it is necessary to compensate for a decrease in the signal level due to this loss, a standing wave is induced by locally mismatching, but a problem of reflection and radiation due to the standing wave occurs.

  An object of the present invention is to provide a clock distribution circuit of a digital processing apparatus that can reduce transmission loss of a clock signal and suppress noise intrusion into another signal processing circuit.

  In order to solve the above-described problems, the present invention has the following configuration.

(1) A clock distribution circuit of a digital processing device composed of a large number of semiconductor devices,
A clock generation source that generates a sine wave oscillation signal of a constant frequency as a clock signal;
A distribution circuit for branching out the clock signal to a plurality of output terminals, and
A plurality of impedance conversion circuits for impedance-converting the clock signal output from the distribution circuit by an emitter-follower type transistor circuit and outputting it to the transmission line side;
A plurality of waveform conversion circuits that respectively convert the waveform of the clock signal transmitted from each impedance conversion circuit through a transmission path and output it to a clock transmission destination circuit ,
The transistor circuit includes a resistor connected between a connection point between the emitter of the transistor constituting the emitter follower and the transmission path, and a ground, and the resistance value of the resistance is determined by the transmission path and the waveform conversion circuit. It is characterized by being matched to the input impedance of the output destination circuit consisting of

  (2) When the waveform converting circuit outputs a sine wave clock signal to the clock transmission destination circuit as it is, the amplitude of the clock signal transmitted compared to the amplitude of the clock signal required by the clock transmission destination circuit Is small, the configuration is such that the output is obtained by amplifying the clock signal using a grounded-emitter transistor amplifier circuit configuration. Conversely, when the amplitude of the input clock signal is larger than the amplitude required by the clock transmission destination circuit It is characterized by having an attenuator configuration.

  (3) When the waveform conversion circuit converts a rectangular wave (pulse waveform) clock signal to the clock transmission destination circuit and outputs the signal, a rectangular wave conversion circuit or a differential driver circuit configuration is used.

  (4) The waveform conversion circuit may be arranged closest to the clock transmission destination circuit.

  (5) The impedance conversion circuit, the transmission path, the waveform conversion circuit, and the clock transmission destination circuit are characterized in that a high frequency shield is mounted for each clock signal to be distributed or the entire transmission path of the clock signal is shielded.

  As described above, according to the present invention, it is possible to reduce the transmission loss of the clock signal and suppress noise intrusion into other signal processing circuits.

  Specifically, impedance matching is performed by using an impedance conversion circuit as an emitter follower transistor, thereby reducing the influence of the transmission path length and suppressing the generation of noise. Further, the level loss of the clock signal hardly occurs. In addition, isolation between the transmission circuits can be ensured.

  When the waveform conversion circuit outputs a sine wave signal as it is to the clock transmission destination circuit, it can suppress generation of unnecessary radiation while outputting a signal suitable for the amplitude of the clock signal required by the clock transmission destination circuit. In addition, when converting a sine wave clock signal to a rectangular wave clock signal, the rectangular wave conversion circuit is arranged in close proximity to the clock transmission destination circuit, thereby generating digital noise and radiating to peripheral circuits by rectangular wave conversion. Can be minimized.

  In addition, the impedance conversion circuit, transmission path, waveform conversion circuit, and clock transmission destination circuit are equipped with a high-frequency shield for each clock signal to be distributed, or by shielding the entire clock signal transmission path, between each transmission circuit and other peripherals. Radiation in the space to the circuit can be further reduced.

  FIG. 1 is a clock distribution circuit diagram showing an embodiment of the present invention. The clock generation source 11 obtains a sine wave oscillation signal having a constant frequency of several tens to several hundreds of MHz with a crystal oscillation circuit or the like, removes harmonic components with a filter circuit, and has an analog amplification circuit (buffer circuit). Generate a clock signal. The distribution circuit 12 branches out the clock signal to each of the N output terminals.

The impedance conversion circuits 13 _{1 to} 13 _N correspond to the clock signal transmission paths 14 _{1 to} 14 _N and the waveform conversion circuits 15 ₁ to 15 _N with respect to the output impedance of the clock signal output to each output terminal of the distribution circuit 12. Is subjected to impedance conversion matched to the input impedance exhibited by the signal, and a clock signal is output to the transmission lines 14 _{1 to} 14 _N.

By taking impedance matching by these impedance conversion circuits 13 _{1 to} 13 _{N, the} influence of the transmission path length is reduced and the generation of noise is suppressed. FIG. 2 shows a specific circuit diagram of the impedance conversion circuit, which is an emitter-follower type transistor circuit. With this configuration, the clock signal input from the distribution circuit exhibits a relatively high impedance. The clock signal output to the transmission line is matched with the resistance value of the resistor R3 in accordance with the input impedance of the output destination circuit and output with a relatively low impedance, thereby obtaining impedance matching with almost no level loss of the clock signal. At the same time, isolation between the transmission circuits can be ensured.

The waveform conversion circuits 15 ₁ to 15 _N convert the waveform of the clock signal input through the transmission lines 14 _{1 to} 14 _N , and output the clock signal to the clock transmission destination circuits 16 _{1 to} 16 _N.

Here, the waveform converting circuit ₁₅ 1 to 15 _N, when outputting a clock signal to clock transmission destination circuit ₁₆ 1 ~ 16 _N side remains sinusoidal clock signal, the clock transmission destination circuit ₁₆ 1 ~ 16 _N are required When the amplitude of the transmitted clock signal is smaller than the amplitude of the clock signal to be transmitted, an output obtained by amplifying the clock signal is obtained by using a grounded-emitter transistor amplifier circuit configuration. On the other hand, when the amplitude of the input clock signal is larger than the amplitude required by the clock transmission destination circuit, the level is adjusted by using an attenuator configuration.

In addition, the waveform conversion circuits 15 ₁ to 15 _N convert the rectangular wave (pulse waveform) clock signal to the clock transmission destination circuits 16 _{1 to} 16 _N and output the rectangular wave conversion circuit, ECL (emitter).・ A differential driver circuit configuration with coupled logic) is converted into a rectangular wave. In this case, the waveform conversion circuits 15 ₁ to 15 _N are arranged close to the clock transmission destination circuits 16 _{1 to} 16 _N , respectively, so that the generation of digital noise and the radiation to the peripheral circuits are minimized by the rectangular wave conversion. Keep it down.

When transmitting a clock signal to another digital processing device through a coaxial cable, the other digital processing device is provided with waveform conversion circuits 15 ₁ to 15 _N for converting the clock signal into a rectangular wave (pulse waveform) clock signal, The waveform converting circuits 15 ₁ to 15 _N can obtain the same operation and effect as arrangements close to the clock transmission destination circuits 16 _{1 to} 16 _N , respectively.

Further, the impedance conversion circuits 13 _{1 to} 13 _N , the transmission lines 14 _{1 to} 14 _N , the waveform conversion circuits 15 ₁ to 15 _N and the clock transmission destination circuits 16 _{1 to} 16 _N are shown as broken line blocks in FIG. A high frequency shield 17 is mounted for each clock signal to be distributed, or the entire clock distribution circuit for the clock signal is shielded. By mounting these shields, radiation in the space between the transmission circuits and to other peripheral circuits can be further reduced.

FIG. 3 shows a configuration example of the shield 17. A conductive high-frequency shield 17 having, for example, a flat rectangular parallelepiped shape is provided on the printed circuit board 18 so as to cover the entire clock distribution circuit including the clock generation source 11, the distribution circuit 12, and the transmission destination circuits 16 _{1 to} 16 _N. Connect one location to ground.

4 and 5 show experimental results based on this embodiment. 4A shows an output waveform (sine wave) of the clock generation source 11, and FIG. 4B shows a waveform conversion circuit 15 ₁ to 15 _N input and a clock transmission destination circuit 16 ₁ to 16 when rectangular wave conversion is performed. The clock waveform at 16 _N input is shown. 5 (a) shows the spurious and phase noise characteristics in the clock signal of the clock generator 11, FIG. 5 (b) shows the spurious and phase noise characteristics when the rectangular wave converted in waveform converting circuit 15 ₁ to 15 _N As a result, almost no deterioration was obtained in spurious and phase noise.

1 is an RF signal type clock distribution circuit diagram showing an embodiment of the present invention. The specific circuit diagram of the impedance conversion circuit in embodiment. The example of mounting of the electromagnetic shield in embodiment. The sine wave waveform and clock waveform in this invention. Spurious and phase noise characteristics converted from a clock signal and rectangular wave in the present invention. The conventional clock distribution circuit diagram. Waveform diagram of generation of reflected noise and clock waveform distortion in a conventional circuit. FIG. 6 is a waveform diagram of spurious and phase noise in a conventional circuit.

Explanation of symbols

11 clock generation source 12 distributing circuit 13 ₁ to 13 _N impedance conversion circuits 14 ₁ to 14 _N clock signal transmission path 15 ₁ to 15 _N waveform converting circuit 16 ₁ ~ 16 _N clock transmission destination circuit 17 electromagnetic shield 18 PCB 19 accumulation of Circuit element 20 Connector

Claims (4)

A clock distribution circuit of a digital processing apparatus composed of a large number of semiconductor devices,
A clock generation source that generates a sine wave oscillation signal of a constant frequency as a clock signal;
A distribution circuit for branching out the clock signal to a plurality of output terminals, and
A plurality of impedance conversion circuits for impedance-converting the clock signal output from the distribution circuit by an emitter-follower type transistor circuit and outputting it to the transmission line side;
A plurality of waveform conversion circuits that respectively convert the waveform of the clock signal transmitted from each impedance conversion circuit through a transmission path and output it to a clock transmission destination circuit ,
The transistor circuit includes a resistor connected between a connection point between the emitter of the transistor constituting the emitter follower and the transmission path, and a ground, and the resistance value of the resistance is determined by the transmission path and the waveform conversion circuit. A clock distribution circuit for a digital processing device, wherein the clock distribution circuit is adapted to the input impedance of an output destination circuit including   When the waveform conversion circuit outputs a sine wave clock signal to the clock transmission destination circuit, the amplitude of the clock signal transmitted is smaller than the amplitude of the clock signal required by the clock transmission destination circuit. Is configured to obtain an output obtained by amplifying the clock signal with a grounded-emitter transistor amplifier circuit configuration. Conversely, when the amplitude of the input clock signal is larger than the amplitude required by the clock transmission destination circuit, the attenuator configuration is used. The clock distribution circuit of the digital processing device according to claim 1, wherein:   The clock distribution circuit of the digital processing device according to claim 1, wherein the waveform conversion circuit is disposed closest to each of the clock transmission destination circuits.   4. The impedance conversion circuit, the transmission path, the waveform conversion circuit, and the clock transmission destination circuit are each mounted with a high-frequency shield for each clock signal to be distributed, or the entire transmission path of the clock signal is shielded. A clock distribution circuit of the digital processing device according to claim 1.

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