JP4778132B2 - Memory controller and system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to a controller of a semiconductor memory device and a system including the semiconductor memory device and the controller, and more particularly, to a controller of a semiconductor memory device that outputs double data rate data together with a strobe signal, and strobe data of a double data rate. The present invention relates to a signal controlled system.
[0002]
[Prior art]
A semiconductor memory device such as a DRAM that operates at a double data rate generally outputs a data strobe signal and a data signal in the same phase, and determines the data change timing of the data signal at both the rising edge and falling edge of the strobe signal. The timing is matched. The controller connected to the semiconductor memory device receives the strobe signal, delays it by an appropriate delay amount, and latches the data signal using this delayed strobe signal, thereby taking in the data therein.
[0003]
[Problems to be solved by the invention]
Conventionally, in the controller, a timing signal is generated so as to latch the data signal at an optimal timing by delaying the strobe signal using a delay circuit constituted by an inverter train or the like. However, if the delay amount of the delay circuit changes due to errors in the manufacturing process, fluctuations in operating temperature, power supply voltage, etc., it becomes difficult to maintain the optimum capture timing for the data. That is, it becomes difficult to ensure an appropriate data hold time and data setup time for data.
[0004]
Accordingly, an object of the present invention is to provide a controller connected to a semiconductor memory device, which can maintain an optimum data fetch timing even when various fluctuation factors exist.
[0005]
[Means for Solving the Problems]
According to another aspect of the present invention, a memory controller connected to a memory that outputs double data rate data together with a strobe signal controls the memory, a clock signal generation circuit that generates a clock signal to be supplied to the memory, and the clock signal As a reference signal and the clock signal Feedback control Delayed by a time corresponding to about 1/4 cycle The variable delay circuit for the strobe signal is controlled by the same signal as the signal to be controlled, and only for a time corresponding to approximately ¼ cycle of the clock signal. A data fetch circuit is included which delays the strobe signal and latches the data using the delayed strobe signal as a timing signal.
[0006]
According to a second aspect of the present invention, in the memory controller according to the first aspect, the data capturing circuit includes a variable delay circuit that delays the strobe signal by a time corresponding to approximately ¼ cycle of the clock signal, and the variable delay. A latch circuit that latches the data using the strobe signal delayed by the circuit as a timing signal is included.
[0007]
According to a third aspect of the present invention, in the memory controller according to the second aspect, the data fetch circuit is a variable delay circuit in which circuits controlled so as to have the same delay as the variable delay circuit are connected in one or more stages in series. And a phase comparison circuit that detects a delay amount of the variable delay circuit row using the clock signal as a reference signal, and the variable delay circuit and the variable delay circuit row based on a delay amount detection result of the phase comparison circuit Control the delay.
[0008]
According to a fourth aspect of the present invention, in the memory controller according to the third aspect, the data capturing circuit controls the delay of the variable delay circuit and the variable delay circuit array based on the delay amount detection result of the phase comparison circuit. A delay control circuit for generating the control signal is further included.
[0009]
According to a fifth aspect of the present invention, the memory controller according to the third aspect transmits the delay amount detection result of the phase comparison circuit to the outside of the memory controller, and controls the delay of the variable delay circuit and the variable delay circuit array. A control signal is received from outside the memory controller.
[0010]
According to a sixth aspect of the present invention, in the memory controller according to the third aspect, the variable delay circuit array has a configuration in which four stages of circuits controlled to have the same delay as the variable delay circuit are connected in series. The clock signal is received, the clock signal is delayed by a delay amount four times that of the variable delay circuit, and the phase comparison circuit compares the phase of the clock signal with the clock signal delayed by the variable delay circuit array. .
[0011]
According to a seventh aspect of the present invention, in the memory controller according to the third aspect, the variable delay circuit array has a configuration in which two stages of circuits controlled to have the same delay as the variable delay circuit are connected in series. The clock signal is received and the clock signal is delayed by a delay amount twice that of the variable delay circuit, and the phase comparison circuit compares the phase of the inverted signal of the clock signal and the clock signal delayed by the variable delay circuit array. Compare
[0012]
According to an eighth aspect of the present invention, in the memory controller according to the third aspect, the variable delay circuit array has a configuration in which two stages of circuits controlled to have the same delay as the variable delay circuit are connected in series. A signal having a frequency twice that of the clock signal is received and delayed by a delay amount twice that of the variable delay circuit, and the phase comparison circuit is delayed by a signal having a frequency twice that of the clock signal and the variable delay circuit array. The phase of the clock signal having a frequency twice that of the clock signal is compared.
[0013]
According to a ninth aspect of the present invention, in the memory controller according to the third aspect, the variable delay circuit array is configured such that a circuit controlled to have the same delay as the variable delay circuit is composed of one stage, and the clock A signal having a frequency twice that of the signal is received and delayed by an amount equal to that of the variable delay circuit, and the phase comparison circuit is delayed by an inverted signal of the signal having a frequency twice that of the clock signal and the variable delay circuit array. Further, the phase of the clock signal is compared with a signal having a frequency twice that of the clock signal.
[0014]
In the above invention, since the timing signal supplied to the latch circuit is a signal obtained by delaying the data strobe signal by 1/4 cycle of the clock signal CLK, the data signal is latched in the middle of the data change timing in the data signal. It will be. Therefore, the optimum data hold time and data setup time can be realized. Also, instead of setting the delay time to a predetermined value, the delay time is controlled to be ¼ cycle of the clock signal by feedback control, so various errors such as manufacturing process errors, fluctuations in operating temperature and power supply voltage, etc. Even if there is a fluctuation factor, it is possible to ensure the optimum data capture timing. In addition, the scale of the variable delay circuit array can be reduced by using an inverted signal of the clock signal or a signal having a frequency twice that of the clock signal as a reference signal in feedback control.
[0015]
Also in a system in which the above memory controller is combined with a double data rate memory, the same operation as described above can be realized.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a configuration of an example of a system to which the present invention is applied.
[0017]
The system of FIG. 1 includes a memory controller 10, a memory device 11, and a microprocessor 12. The memory controller 10 mediates control between the microprocessor 12 and the memory device 11 when performing a data read / write operation on the memory device 11. A data signal, an address signal, a control signal, and a clock signal are transmitted between the microprocessor 12 and the memory controller 10. A strobe signal, a data signal, an address signal, a control signal, and a clock signal are transmitted between the memory controller 10 and the memory device 11.
[0018]
In general, the role of the memory controller 10 is to change the bus width of the data bus between the microprocessor 12 and the memory device 11, execute a DMA (direct memory access) operation on the memory device 11, etc. Perform various control operations related to access.
[0019]
In the system to which the present invention is applied, the memory device 11 is a data double rate memory device that inputs and outputs data at both the rising edge and the rising edge of the strobe signal. At the time of data writing, a strobe signal is supplied from the memory controller 10 to the memory device 11 together with the data. At the time of data reading, a strobe signal is supplied from the memory device 11 to the memory controller 10 together with the data. The strobe signal supplied from the memory device 11 to the memory controller 10 when reading data is a signal whose rising edge and rising edge timing coincide with the timing of the data change point of the data signal.
[0020]
FIG. 2 shows a schematic configuration of an example of a memory controller according to the present invention.
[0021]
The memory controller 10 shown in FIG. 2 is arranged between the microprocessor 12 and the memory device 11 when the data bus width of the microprocessor 12 is 64 bits and the data bus width of the memory device 11 is 32 bits. It is an example of the controller which performs conversion of a data bus width.
[0022]
The memory controller 10 shown in FIG. 2 includes a clock generation circuit 21, a write control circuit 22, a read control circuit 23, an interface 24, an interface 25, a delay circuit 26, a latch circuit 27, a selector circuit 28, a selector circuit 29, and a latch circuit. 30 to 33 are included.
[0023]
The clock generation circuit 21 generates a clock signal CLK and supplies it to the write control circuit 22 and the read control circuit 23. The clock generation circuit 21 further supplies a clock signal CLK to the memory device 11 connected to the memory controller 10. For a double data rate memory device, not only the clock signal CLK but also a clock signal / CLK obtained by inverting the clock signal CLK is generally supplied. In some cases, the clock generation circuit 21 may generate a clock signal CLK2 having a frequency twice that of the clock signal CLK and its inverted clock / CLK2.
[0024]
At the time of data writing, 64-bit data from the microprocessor 12 is stored in the latch circuits 30 and 31 through the interface 25 by 32 bits. The selector circuit 28 alternately selects one of the latch circuits 30 and 31, and supplies 32-bit data of the selected latch circuit to the memory device 11 via the interface 24. The timing of these operations is controlled by the write control circuit 22. The write control circuit 22 supplies a data strobe signal to the memory device 11 via the interface 24.
[0025]
When reading data, 32-bit data from the memory device 11 is supplied to the latch circuit 27 via the interface 24. The strobe signal from the memory device 11 is supplied to the delay circuit 26 via the interface 24. The strobe signal is delayed by ¼ cycle of the clock signal CLK by the delay circuit 26 and supplied to the latch circuit 27 as a timing signal. The latch circuit 27 latches the data signal using the supplied timing signal. The selector circuit 29 alternately selects one of the latch circuits 32 and 33, and stores the data latched in the latch circuit 27 alternately in the selected latch circuit. A total of 64 bits of data stored in the latch circuits 32 and 33 are supplied to the microprocessor 12 via the interface 25.
[0026]
Here, the delay circuit 26 and the latch circuit 27 constitute a data capturing circuit 50 according to the present invention that captures the data signal by delaying the strobe signal by ¼ cycle of the clock signal CLK. The data capturing circuit 50 is supplied with the clock signal CLK from the clock generation circuit 21.
[0027]
FIG. 3 shows the configuration of a first embodiment of the data capturing circuit 50 according to the present invention.
[0028]
The data fetch circuit 50 includes five variable delay circuits 51-1 to 51-5, a delay control circuit 52, a phase comparator 53, and a latch circuit 27. The variable delay circuits 51-1 through 51-5 have the same circuit configuration and are controlled by the same control signal output from the delay control circuit 52. Therefore, the variable delay circuits 51-1 to 51-5 always have the same delay. In FIG. 2, the variable delay circuits 51-1 to 51-5, the delay control circuit 52, and the phase comparator 53 are collectively shown as the delay circuit 26 for simplification.
[0029]
The clock signal CLK is input to one input terminal of the phase comparator 53 as it is, and after being delayed by the four variable delay circuits 51-1 to 51-4, is delayed to the other input terminal of the phase comparator 53. Input as a clock signal DCLK. The phase comparator 53 compares the phases of the clock signal CLK and the delayed clock signal DCLK and supplies the phase comparison result to the delay control circuit 52.
[0030]
The delay control circuit 52 generates a control signal so that the phases of the clock signal CLK and the delayed clock signal DCLK are the same (precisely, the delayed clock signal DCLK is delayed by 360 degrees), and generates four variable delay circuits. The delay amount 51-1 to 51-4 is adjusted. That is, the edge timings of the clock signal CLK and the delayed clock signal DCLK are compared, and when the edge timing of the delayed clock signal DCLK is relatively early, the delay amount is controlled to increase, and the edge timing of the delayed clock signal DCLK is controlled. When is relatively slow, control is performed to reduce the delay amount.
[0031]
As a result of the above delay adjustment, the delayed clock signal DCLK is controlled to be 360 degrees behind the clock signal CLK. As described above, the variable delay circuits 51-1 to 51-4 have the same circuit configuration and the same delay amount. Therefore, when the delayed clock signal DCLK is 360 degrees behind the clock signal CLK, one variable delay circuit is provided. The circuit has a delay amount corresponding to a quarter cycle of the clock signal CLK.
[0032]
FIG. 4 is a diagram showing the relationship between the clock signal CLK, the delayed clock signal DCLK, and the output of the variable delay circuit 51-1.
[0033]
As shown in FIG. 4, the delayed clock signal DCLK is adjusted so that the phase is delayed by 360 degrees from the clock signal CLK. At this time, since the delay amounts of the four variable delay circuits 51-1 to 51-4 are equal to one cycle of the clock signal CLK, the output of the variable delay circuit 51-1 delays the clock signal CLK by 1/4 cycle. Signal. That is, the delay amount of the variable delay circuit 51-1 is set to a delay amount equal to ¼ cycle of the clock signal CLK.
[0034]
In FIG. 3, the variable delay circuit 51-5 is controlled so as to have the same delay amount with the same control signal as the other variable delay circuits, and therefore has a delay equal to ¼ cycle of the clock signal CLK. . As a result, the data strobe signal DS input to the variable delay circuit 51-5 is delayed by ¼ cycle of the clock signal CLK and supplied to the latch circuit 27 as a timing signal. The latch circuit 27 latches the data signal DQ using the supplied timing signal.
[0035]
The timing signal supplied to the latch circuit 27 is a signal obtained by delaying the data strobe signal DS by ¼ cycle of the clock signal CLK. The data change timing in the data signal DQ is the rising and falling edges of the data strobe signal DS. Therefore, the timing signal supplied to the latch circuit 27 latches the data signal DQ just in the middle of the data change timing in the data signal DQ. Therefore, the optimum data hold time and data setup time can be realized.
[0036]
Even if the delay of the variable delay circuit fluctuates due to various fluctuation factors such as errors in the manufacturing process, fluctuations in operating temperature, power supply voltage, etc., the variable delay circuit 51-5 is controlled by the delay amount control based on the phase comparison of the clock signals. Since the delay amount is adjusted to be ¼ cycle of the clock signal, the optimum data capture timing can be ensured even under conditions where various fluctuation factors exist.
[0037]
FIG. 5 is a circuit diagram showing an example of the circuit configuration of the phase comparator 53 and the delay control circuit 52. Signals S1 and S2 input to the circuit of FIG. 5 correspond to the clock signal CLK and the delayed clock signal DCLK.
[0038]
The circuit of FIG. 5 includes NAND circuits 141 to 145, inverters 146 to 149, NAND circuits 150 and 151, inverters 152 and 153, a binary counter 154, an inverter 155, NAND circuits 156 and 157, and inverters 158 and 159. For example, it can be considered that the NAND circuits 141 to 145 and the inverters 146 to 149 constitute the phase comparator 53 and the remaining part constitutes the delay control circuit 52.
[0039]
NAND circuits 144 and 145 constitute a latch, and as shown in FIG. 5, in the initial state, two inputs are LOW and two outputs are HIGH. When the rising edge of the signal S1 is earlier than the rising edge of the signal S2, the output of the NAND circuit 143 becomes HIGH before the output of the NAND circuit 142. Therefore, the output of the NAND circuit 145 becomes LOW, and the output of the NAND circuit 144 remains HIGH. Since this state is latched, the state does not change even if the output of the NAND circuit 142 becomes HIGH thereafter by the rising edge of the signal S2. Therefore, when the phase of the signal S1 is advanced, the output of the inverter 149 becomes HIGH. Conversely, when the phase of the signal S2 is advanced, the output of the inverter 155 becomes HIGH.
[0040]
Here, the signal from the inverter 148 serves to return the latch state to the initial state by simultaneously setting the outputs of the NAND circuits 142 and 143 to LOW at an appropriate timing. Without such a configuration, when the phase of the signal S1 is advanced, the output of the NAND circuit 143 becomes HIGH, and then the output of the NAND circuit 142 becomes HIGH, and then the signal S1 becomes higher than the signal S2. By returning to LOW first, the state of the latch is reversed, and the output of the NAND circuit 144 becomes LOW. In order to avoid this, the outputs of the NAND circuits 142 and 143 are simultaneously set to LOW.
[0041]
The output signal of the inverter 148 is supplied to the binary counter 154. The two outputs of the binary counter 154 are signals that alternately become HIGH every cycle of the input signals S1 and S2. The binary counter 154 includes NAND circuits 161 to 168 and inverters 169 to 171. Since the operation is within the range of the prior art, the description is omitted.
[0042]
Two outputs of the binary counter 154 are supplied to one input of the NAND circuits 150 and 151. The output from the inverter 149 is supplied to the other inputs of the NAND circuits 150 and 151. Further, the two outputs of the binary counter 154 are supplied to one input of the NAND circuits 156 and 157. The output from the inverter 155 is supplied to the other inputs of the NAND circuits 156 and 157.
[0043]
Therefore, when the phase of the signal S1 is ahead of that of the signal S2, HIGH pulses are alternately output from the inverters 152 and 153 that invert the outputs of the NAND circuits 150 and 151. Conversely, when the phase of the signal S2 is advanced, HIGH pulses are alternately output from the inverters 158 and 159 that invert the outputs of the NAND circuits 156 and 157.
[0044]
HIGH pulses alternately output from the inverters 152 and 153 or the inverters 158 and 159 are supplied to the variable delay circuit to adjust the delay amount of the variable delay circuit.
[0045]
FIG. 6 is a circuit diagram showing a part of the configuration of the variable delay circuit, and FIG. 7 is a circuit diagram showing the remaining part of the configuration of the variable delay circuit. 6 and 7 constitutes the entire variable delay circuit.
[0046]
The variable delay circuit includes NOR circuits 201-0 to 201-n, inverters 202-1 to 202-n, NAND circuits 203-1 to 203-n, NMOS transistors 204-1 to 204-n, and NMOS transistors 205-1 to 205-n. 205-n, NMOS transistors 206-1 to 206-n, and NMOS transistors 207-1 to 207-n. When the reset signal R is set to LOW, the circuit of FIG. 6 is reset. That is, when the reset signal R becomes LOW, the outputs of the NAND circuits 203-1 to 203-n become HIGH, and the outputs of the inverters 202-1 to 202-n become LOW. Each pair of the NAND circuits 203-1 to 203-n and the inverters 202-1 to 202-n forms a latch by using the outputs of each other as inputs. Therefore, the initial state set by the reset signal R is maintained even when the reset signal R returns to HIGH.
[0047]
In this initial state, as shown in FIG. 6, the output P (0) of the NOR circuit 201-0 is HIGH, and the outputs P (1) to P (n) of the NOR circuits 201-1 to 201-n are LOW. That is, only the output P (0) is HIGH.
[0048]
When it is necessary to increase the delay amount, HIGH pulses are alternately supplied to the signal lines A and B. First, when a HIGH pulse is supplied to the signal line B, the NMOS transistor 204-1 is turned on. At this time, since the NMOS transistor 206-1 is on, the output of the NAND circuit 203-1 is connected to the ground, and is forcibly changed from HIGH to LOW. Therefore, the output of the inverter 202-1 becomes HIGH, and this state is held in the latch composed of the NAND circuit 203-1 and the inverter 202-1. At this time, the output P (0) changes from HIGH to LOW, and the output P (1) changes from LOW to HIGH. Therefore, in this state, only the output P (1) becomes HIGH.
[0049]
Next, when a HIGH pulse is supplied to the signal line A, the NMOS transistor 204-2 is turned on. At this time, since the NMOS transistor 206-2 is turned on, the output of the NAND circuit 203-2 is connected to the ground and is forcibly changed from HIGH to LOW. Therefore, the output of the inverter 202-2 becomes HIGH, and this state is held in the latch composed of the NAND circuit 203-2 and the inverter 202-2. At this time, the output P (1) changes from HIGH to LOW, and the output P (2) changes from LOW to HIGH. Accordingly, in this state, only the output P (2) becomes HIGH.
[0050]
Thus, by supplying HIGH pulses alternately to the signal lines A and B, it is possible to shift only one HIGH output from the outputs P (0) to P (n) to the right one by one. I can do it.
[0051]
When it is necessary to reduce the delay amount, HIGH pulses are alternately supplied to the signal lines C and D. Since the operation in this case is the reverse of the above-described operation, a detailed description is omitted. However, by alternately supplying a HIGH pulse to the signal lines C and D, the outputs P (0) to P (n) Only one output that is HIGH can be shifted to the left one by one.
[0052]
By supplying these output signals P (1) to P (n) to the circuit portion of FIG. 7 of the variable delay circuit, the delay amount of the signal is adjusted.
[0053]
7 of the variable delay circuit includes an inverter 210, NAND circuits 211-1 to 211-n, NAND circuits 212-1 to 212-n, and inverters 213-1 to 213-n. Here, the NAND circuits 212-1 to 212-n and the inverters 213-1 to 213-n constitute a delay element array.
[0054]
An inverted signal of the input signal SI is supplied from the inverter 210 to one input of the NAND circuits 211-1 to 211-n, and signals P (1) to P (n) are supplied to the other input. Of the signals P (1) to P (n), a signal that is only HIGH is P (x).
[0055]
Among the NAND circuits 211-1 to 211-n, those other than the NAND circuit 211-x have a high level because one input is LOW. Of the NAND circuits 212-1 to 212-n that receive this HIGH level at one input, those other than the NAND circuit 212-x function as an inverter for the other input.
[0056]
Therefore, the delay element array on the left side of the NAND circuit 212-x transmits a fixed HIGH level applied to one input of the NAND circuit 212-n. Therefore, one input of the NAND circuit 212-x is HIGH. An input signal SI is supplied to the other input of the NAND circuit 212-x via the inverter 210 and the NAND circuit 211-x. Therefore, the delay element array from the NAND circuit 212-x to the inverter 213-1 propagates the input signal SI while delaying, and a delayed signal is obtained as the output signal SO. The output signal SO in this case is delayed from the input signal SI by a delay time corresponding to x delay elements.
[0057]
As described above, the phase comparator 53 and the delay control circuit 52 shown in FIG. 5 compare the phases of the clock signals, and output pulse signals that are alternately HIGH based on the phase comparison result. This pulse signal is supplied to the circuit portion shown in FIG. 6 of the variable delay circuit, and the position of the only HIGH signal among the output signals P (1) to P (n) is controlled. This signal P (1) Through P (n), the delay amount of the circuit portion shown in FIG. 7 of the variable delay circuit is set.
[0058]
FIG. 8 shows the configuration of a second embodiment of the data capturing circuit according to the present invention.
[0059]
8 includes three variable delay circuits 51-1, 51-2, and 51-5, a delay control circuit 52, a phase comparator 53, and a latch circuit 27.
[0060]
An inverted signal / CLK of the clock signal CLK is input to one input terminal of the phase comparator 53. The clock signal CLK is delayed by the two variable delay circuits 51-1 and 51-2 and then input to the other input terminal of the phase comparator 53 as the delayed clock signal DCLK. The phase comparator 53 compares the phases of the inverted clock signal / CLK and the delayed clock signal DCLK and supplies the phase comparison result to the delay control circuit 52.
[0061]
The delay control circuit 52 generates a control signal and adjusts the delay amounts of the two variable delay circuits 51-1 and 51-2 so that the phases of the inverted clock signal / CLK and the delayed clock signal DCLK are the same. . That is, the edge timings of the inverted clock signal / CLK and the delayed clock signal DCLK are compared, and when the edge timing of the delayed clock signal DCLK is relatively early, the delay amount is controlled to increase. When the edge timing is relatively late, control is performed to reduce the delay amount.
[0062]
As a result of the delay adjustment, the delayed clock signal DCLK is controlled to be in phase with the inverted clock signal / CLK. That is, the delayed clock signal DCLK is controlled to be 180 degrees out of phase with the clock signal CLK. Since the variable delay circuits 51-1 and 51-2 have the same circuit configuration and the same delay amount, in the state where the delayed clock signal DCLK is 180 degrees behind the clock signal CLK, one variable delay circuit is It has a delay amount corresponding to a quarter cycle of the signal CLK.
[0063]
Since the variable delay circuit 51-5 is controlled to have the same delay amount by the same control signal as the other variable delay circuits, it has a delay equal to ¼ cycle of the clock signal CLK. As a result, the data strobe signal DS input to the variable delay circuit 51-5 is delayed by ¼ cycle of the clock signal CLK and supplied to the latch circuit 27 as a timing signal. The latch circuit 27 latches the data signal DQ using the supplied timing signal.
[0064]
Therefore, the optimum data capture timing can be ensured even under conditions where there are various fluctuation factors such as manufacturing process errors, fluctuations in operating temperature and power supply voltage. In addition, the number of variable delay circuits can be reduced, the circuit scale can be reduced, and the cost can be reduced.
[0065]
FIG. 9 shows the configuration of a third embodiment of the data fetch circuit according to the present invention.
[0066]
9 includes three variable delay circuits 51-1, 51-2, and 51-5, a delay control circuit 52, a phase comparator 53, and a latch circuit 27.
[0067]
A clock signal CLK2 having a frequency twice that of the clock signal CLK is generated by the clock generation circuit 21 (see FIG. 2), is input to one input terminal of the phase comparator 53, and two variable delay circuits 51-1. And 51-2, it is input to the other input terminal of the phase comparator 53 as a delayed clock signal DCLK2. The phase comparator 53 compares the phases of the clock signal CLK2 and the delayed clock signal DCLK2, and supplies the phase comparison result to the delay control circuit 52.
[0068]
The delay control circuit 52 generates a control signal and generates two variable delay circuits so that the phases of the clock signal CLK2 and the delayed clock signal DCLK2 are the same (more precisely, the delayed clock signal DCLK2 is delayed by 360 degrees). The delay amount of 51-1 and 51-2 is adjusted. As a result of this delay adjustment, the delayed clock signal DCLK2 is controlled so that the phase is delayed 360 degrees from the clock signal CLK2. Since the variable delay circuits 51-1 and 51-2 have the same circuit configuration and the same delay amount, when the delayed clock signal DCLK2 is 360 degrees behind the clock signal CLK2, one variable delay circuit is It has a delay amount corresponding to 1/2 cycle of the signal CLK2. When considering a cycle of the clock signal CLK having a frequency twice that of the clock signal CLK2, one variable delay circuit has a delay amount corresponding to a quarter cycle.
[0069]
As a result, the variable delay circuit 51-5 has a delay equal to ¼ cycle of the clock signal CLK. The latch circuit 27 latches the data signal DQ with a timing signal delayed by 1/4 cycle of the clock signal CLK.
[0070]
Therefore, the optimum data capture timing can be ensured even under conditions where there are various fluctuation factors such as manufacturing process errors, fluctuations in operating temperature and power supply voltage. In addition, the number of variable delay circuits can be reduced, the circuit scale can be reduced, and the cost can be reduced.
[0071]
FIG. 10 shows the configuration of a fourth embodiment of the data fetch circuit according to the present invention.
[0072]
10 includes two variable delay circuits 51-1 and 51-5, a delay control circuit 52, a phase comparator 53, and a latch circuit 27.
[0073]
A clock signal CLK2 having a frequency twice that of the clock signal CLK and its inverted signal / CLK2 are generated by the clock generation circuit 21 (see FIG. 2). The inverted clock signal / CLK2 is input to one input terminal of the phase comparator 53. The clock signal CLK2 is delayed by the variable delay circuit 51-1, and then delayed to the other input terminal of the phase comparator 53. It is input as DCLK2. The phase comparator 53 compares the phases of the inverted clock signal / CLK2 and the delayed clock signal DCLK2, and supplies the phase comparison result to the delay control circuit 52.
[0074]
The delay control circuit 52 generates a control signal and adjusts the delay amount of the variable delay circuit 51-1 so that the phase of the inverted clock signal / CLK 2 and the delayed clock signal DCLK 2 are the same. As a result of this delay adjustment, the delayed clock signal DCLK2 is controlled to be 180 degrees out of phase with the clock signal CLK2. That is, the variable delay circuit 51-1 has a delay amount corresponding to a half cycle of the clock signal CLK2. When considering the cycle of the clock signal CLK having a frequency twice that of the clock signal CLK2, the variable delay circuit 51-1 has a delay amount corresponding to a quarter cycle.
[0075]
As a result, the variable delay circuit 51-5 has a delay equal to ¼ cycle of the clock signal CLK. The latch circuit 27 latches the data signal DQ with a timing signal delayed by 1/4 cycle of the clock signal CLK.
[0076]
Therefore, the optimum data capture timing can be ensured even under conditions where there are various fluctuation factors such as manufacturing process errors, fluctuations in operating temperature and power supply voltage. In addition, the number of variable delay circuits can be reduced, the circuit scale can be reduced, and the cost can be reduced.
[0077]
FIG. 11 shows the configuration of a fifth embodiment of the data fetch circuit according to the present invention. 11, the same components as those in FIG. 3 are referred to by the same reference numerals, and a description thereof will be omitted.
[0078]
The data fetch circuit 50D has the delay control circuit 52 removed as compared with the data fetch circuit 50 of FIG. The data capturing circuit 50D is connected to the microprocessor 12 via the interface 25 (see FIG. 2).
[0079]
The phase comparator 53 of the data capturing circuit 50D sends the phase comparison result to the microprocessor 12. The microprocessor 12 supplies a control signal as a response, and controls the delay amounts of the variable delay circuits 51-1 to 51-5 of the data fetch circuit 50D. Specifically, in the phase comparator 53 shown in FIG. 5, for example, the output of the inverter 149 is passed through the interface 25 as a signal indicating which rising edge of the input signals S1 and S2 precedes in time. What is necessary is just to supply to the microprocessor 12. In addition, the microprocessor 12 supplies a pulse signal that is alternately HIGH to be supplied to the signal lines A and B or the signal lines C and D according to whether the delay is increased or decreased in the variable delay circuit shown in FIG. May be supplied as a control signal.
[0080]
If the phase comparison result is sent from the phase comparator 53 to the microprocessor 12 and the control signal for adjusting the delay amount of the variable delay circuit is supplied from the microprocessor 12 to the variable delay circuit, the delay control circuit is Since the configuration can be eliminated, the circuit scale can be reduced. Further, since the delay time is adjusted not by hard-wired connection control but by software control as a program executed by the microprocessor 12, it is possible to easily cope with setting changes and configuration changes.
[0081]
The configuration in which the phase comparison result is sent from the phase comparator 53 to the microprocessor as described above and the control signal for adjusting the delay amount of the variable delay circuit is supplied from the microprocessor to the variable delay circuit is shown in FIGS. It is obvious that the present invention can be applied to the configurations of the second to fourth embodiments of the data capturing circuit to be used. It is not necessary for the microprocessor 12 to receive the phase comparison result and supply a control signal for delay control, but may be another microprocessor or a similar control processor.
[0082]
In the description of the above embodiment, the memory controller 10 is a controller that converts the data bus width when the data bus width of the microprocessor 12 is 64 bits and the data bus width of the memory device 11 is 32 bits. However, the present invention is not limited to such a configuration, and can be applied to various controllers having various control functions.
[0083]
As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.
[0084]
【The invention's effect】
In the present invention, the timing signal supplied to the latch circuit is a signal obtained by delaying the data strobe signal by approximately ¼ cycle of the clock signal CLK, so that the data signal is latched in the middle of the data change timing in the data signal. Will do. Therefore, the optimum data hold time and data setup time can be realized. Also, instead of setting the delay time to a predetermined value, the delay time is controlled to be ¼ cycle of the clock signal by feedback control, so various errors such as manufacturing process errors, fluctuations in operating temperature and power supply voltage, etc. Even if there is a fluctuation factor, it is possible to ensure the optimum data capture timing. This makes it possible to build a reliable memory system.
[0085]
In addition, by using an inverted signal of the clock signal or a signal having a frequency twice that of the clock signal as a reference signal in the feedback control, the scale of the variable delay circuit array can be reduced, and the optimum data capture timing is ensured. The cost for doing so can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of an example of a system to which the present invention is applied.
FIG. 2 is a configuration diagram showing a schematic configuration of an example of a memory controller according to the present invention.
FIG. 3 is a configuration diagram showing a configuration of a first embodiment of a data capturing circuit according to the present invention;
FIG. 4 is a diagram illustrating a relationship between a clock signal CLK, a delayed clock signal DCLK, and an output of a variable delay circuit.
FIG. 5 is a circuit diagram showing an example of a circuit configuration of a phase comparator and a delay control circuit.
FIG. 6 is a circuit diagram showing a part of the configuration of a variable delay circuit.
FIG. 7 is a circuit diagram showing the remaining part of the configuration of the variable delay circuit.
FIG. 8 is a configuration diagram showing a configuration of a second embodiment of the data capturing circuit according to the present invention;
FIG. 9 is a block diagram showing the configuration of a third embodiment of the data fetch circuit according to the present invention;
FIG. 10 is a configuration diagram showing a configuration of a fourth embodiment of the data capturing circuit according to the present invention;
FIG. 11 is a block diagram showing the configuration of a fifth embodiment of the data fetch circuit according to the present invention;
[Explanation of symbols]
10 Memory controller
11 Memory device
12 Microprocessor
27 Latch circuit
51-1, 51-2, 51-3, 51-4, 51-5 Variable delay circuit
52 Delay control circuit
53 Phase comparator

Claims (10)

A memory controller connected to a memory that outputs data at a double data rate together with a strobe signal and controls the memory,
A clock signal generation circuit for generating a clock signal to be supplied to the memory;
Controlling the variable delay circuit of the strobe signal with the same signal as the signal for controlling the clock signal to be delayed by a time corresponding to approximately ¼ cycle by using the clock signal as a reference signal , A memory controller, comprising: a data fetch circuit that delays the strobe signal by a time corresponding to approximately ¼ cycle of a clock signal, and latches the data using the delayed strobe signal as a timing signal. The data capturing circuit includes:
And said variable delay circuit for delaying the strobe signal by a time corresponding to approximately 1/4 cycle of the clock signal,
2. The memory controller according to claim 1, further comprising a latch circuit that latches the data using the strobe signal delayed by the variable delay circuit as a timing signal. The data capturing circuit includes:
A variable delay circuit array in which circuits controlled so as to have the same delay as the variable delay circuit are connected in one or more stages in series;
A phase comparison circuit that detects a delay amount of the variable delay circuit array using the clock signal as a reference signal, and delays the variable delay circuit and the variable delay circuit array based on a delay amount detection result of the phase comparison circuit; 3. The memory controller according to claim 2, wherein the memory controller is controlled.   The data capturing circuit further includes a delay control circuit that generates a control signal for controlling a delay of the variable delay circuit and the variable delay circuit array based on the delay amount detection result of the phase comparison circuit. The memory controller according to claim 3.   The delay amount detection result of the phase comparison circuit is transmitted to the outside of the memory controller, and a control signal for controlling the delay of the variable delay circuit and the variable delay circuit array is received from the outside of the memory controller. 3. The memory controller according to 3.   The variable delay circuit array has a configuration in which four stages of circuits controlled so as to have the same delay as the variable delay circuit are connected in series. 4. The memory controller according to claim 3, wherein the clock signal is delayed, and the phase comparison circuit compares the phases of the clock signal and the clock signal delayed by the variable delay circuit array.   The variable delay circuit array has a configuration in which two stages of circuits controlled so as to have the same delay as the variable delay circuit are connected in series, receives the clock signal, and has a delay amount that is twice that of the variable delay circuit. 4. The memory controller according to claim 3, wherein the clock signal is delayed, and the phase comparison circuit compares the phase of the inverted signal of the clock signal with the clock signal delayed by the variable delay circuit array.   The variable delay circuit array has a configuration in which two stages of circuits controlled so as to have the same delay as the variable delay circuit are connected in series, and receives a signal having a frequency twice that of the clock signal. The phase comparison circuit delays the phase of the signal having a frequency twice that of the clock signal and the signal having a frequency twice that of the clock signal delayed by the variable delay circuit array. 4. The memory controller according to claim 3, wherein the comparison is performed.   The variable delay circuit array has a configuration in which a circuit controlled to have the same delay as that of the variable delay circuit is composed of one stage, and receives a signal having a frequency twice that of the clock signal and is equal to the variable delay circuit The phase comparison circuit compares the phase of the inverted signal of the signal having a frequency twice that of the clock signal with the signal of the frequency twice that of the clock signal delayed by the variable delay circuit array. 4. The memory controller according to claim 3, wherein: A memory for outputting double data rate data together with a strobe signal;
A memory controller that receives the data and the strobe signal and controls the memory;
A clock signal generation circuit for generating a clock signal to be supplied to the memory;
Controlling the variable delay circuit of the strobe signal with the same signal as the signal for controlling the clock signal to be delayed by a time corresponding to approximately ¼ cycle by using the clock signal as a reference signal , And a data fetch circuit provided in the memory controller for delaying the strobe signal by a time corresponding to approximately ¼ cycle of the clock signal and latching the data using the delayed strobe signal as a timing signal. System.

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