JP4772210B2 - Arbitration control method and circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an arbitration control circuit used for arbitration such as switching equipment and bus access. More specifically, the present invention relates to a case where there are a plurality of request sources that should be treated basically equally, and in particular, an arbitration algorithm is used for each request source When selecting the maximum value or minimum value from the data values presented by and selecting the request source that presents the value as the selection result, the value corresponding to the maximum value or the minimum value is obtained from multiple request sources. The present invention relates to an arbitration control method and circuit that applies round-robin (rotation priority) control to finally determine one requester when presented.
[0002]
[Prior art]
The round robin method used for exchange devices and bus access arbitration has a long history, and many realization methods have been proposed. In the round robin method, arbitration is performed so as to give a right to access a shared resource such as a shared band and a bus fairly to a requester that should be treated basically equally.
[0003]
As a conventional technique for this type of round robin, there is JP-A-11-219335. This prior art uses a bit string of a 1-bit request signal indicating the presence / absence of a request and a search signal in which only 1 bit is 1, searches for a bit string of the request signal from a bit position where the search signal is 1, First, a round robin scan in which a permission signal corresponding to a bit whose request signal is 1 is set to 1 and a permission signal corresponding to another bit is set to 0 can be realized by a combinational logic circuit such as an adder circuit or a logic circuit. Since the round robin result can be uniquely obtained only by the combinational logic circuit, high-speed processing is possible.
[0004]
In this prior art, a 1-bit flag indicating whether it is 0 or 1 can be used as a search factor (request signal), and it is possible to process them in several layers. However, in this prior art, when the arbitration algorithm selects a request source by comparing numerical values consisting of a plurality of bits calculated from various factors, a circuit for comparison is prepared in the previous stage as a result. Must be flagged and input to the round robin control circuit. As described above, in this prior art, when the data presented by the request source is a plurality of bits, two or more stages of processing are eventually required until the arbitration result is obtained, and the circuit scale increases and the processing speed is increased. There is another problem that cannot be improved.
[0005]
On the other hand, Japanese Patent Laid-Open No. 1-296365 is known as a prior art that simultaneously performs a comparison using an arbitration algorithm and round robin. In this prior art, a counter is provided for each of a plurality of interface devices accessing the common bus, each interface device outputs a counter value, and each interface device outputs its own counter value and the counter value output from all devices. All interface devices that have a counter value smaller than the counter value of the device that has acquired the bus use right, and that has acquired the bus use right, It is shown that the interface device that has counted up the counter and acquired the right to use the bus sets the counter to the minimum value.
[0006]
The problem with this prior art is that the comparison value (counter value) must be different for each request source (each interface device) as a necessary condition for comparison.
[0007]
Further, in this prior art, it is disclosed that priority information is added to the most significant bit of the counter value and output, and the comparison is performed. In this prior art, the arbitration result is collectively displayed. In order to output, the priority order information must be able to output all different values for each request source, similarly to the original arbitration comparison value (counter value). If the values to be added to the higher order are not necessarily different for each request source, as shown in this prior art, two counters are prepared for each interface device. Step 2 for recognizing the comparison result of the output of the second counter), and as a result, only the request source permitted to participate in the second comparison outputs the contents of the second counter to the arbitration bus. It is necessary to follow the procedure.
[0008]
In this prior art, the first counter and the second counter are connected to a common bus. However, the buses of the respective counters are separated and the values of the first counter and the second counter are simultaneously transmitted by the interface devices. Assuming that For example, there is a request source A in which the first counter has the maximum value, the second counter has the second value, and the request source B in which the first counter has the second value and the second counter has the maximum value. At the request source A, the comparison result by the output of the first counter shows the maximum value, but the comparison result by the output of the second counter does not show the maximum value. Thus, in this prior art, when the outputs of the two counters are output simultaneously, it is not possible to determine whether or not one should be selected. That is, in this prior art, the request source B recognizes that it has dropped out at the selection stage in the first counter from the result of the first counter, and withdraws the output of the second counter for the first time. It is possible to recognize that the comparison result in the second counter is the maximum.
[0009]
In the end, the request source selection based on the specific factor corresponding to the first stage is first performed, and when a plurality of request sources are arranged side by side, it is always determined to be uniquely determined again in the second stage. It is not particularly different from the former prior art using a possible arbitration circuit.
[0010]
[Problems to be solved by the invention]
As described above, in the above-described prior art, when mediation is performed by comparing calculated values due to factors specific to the arbitration algorithm, the procedure for performing round robin at that time, that is, final unique selection is inevitably separated, and two steps are performed. The above procedure is required. For this reason, in the prior art, the circuit configuration is difficult to understand and becomes complicated and large-scale. In addition, the number of clock steps increases, high-speed processing cannot be performed, and a system that needs to perform arbitration at high speed becomes a speed bottleneck.
[0011]
The present invention has been made in view of the above. Arbitration that achieves simplification and speedup of a circuit by collectively selecting request source candidates by an arbitration algorithm and final request source selection by round robin. The purpose is to obtain a control circuit.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, the arbitration control method according to the present invention selects a maximum value or a minimum value among data values presented by a plurality of request sources, and selects a request source presenting the maximum value or the minimum value. Arbitration control method using round robin control to finally determine one request source when a value corresponding to the maximum value or minimum value is presented from a plurality of request sources, applied to the resulting arbitration algorithm , The upper M bits are the first comparison numerical data presented by each request source for the arbitration algorithm, and the lower N bits are all different by performing a different predetermined calculation for each request source on the previous arbitration result. The second comparison numerical data for round robin composed of integer values for N bits is used, and the first and second comparison numerical data for a plurality of request sources are M + N-bit unsigned integers. And obtaining the current arbitration results based on that search for maximum or minimum value of the data of the M + N bits by comparing Te.
[0013]
According to the present invention, the upper M bits are used as the first comparison numerical data presented by each request source for the arbitration algorithm, and the lower N bits are subjected to a predetermined calculation that is different for each request source in the previous arbitration result. The second comparison numerical data for round robin composed of all different N-bit integer values, and the first and second comparison numerical data for a plurality of request sources are compared as M + N-bit unsigned integers. Thus, the current arbitration result is obtained based on searching for the maximum value or the minimum value of the M + N-bit data. That is, by comparing the first and second comparison numerical data for a plurality of request sources as M + N-bit unsigned integers, request source selection by an arbitration algorithm for upper M bits and request source unique selection by lower N bits And in a single step.
[0014]
The arbitration control circuit according to the next invention is applied to an arbitration algorithm that selects a maximum value among data values presented by a plurality of request sources, and selects a request source that presents the maximum value as a selection result. In the arbitration control circuit that uses round-robin control to finally determine one request source when a value corresponding to is presented from a plurality of request sources, the N-bit arbitration result is latched using the clock signal as a trigger. And a plurality of first outputs of round robin comparison numerical data composed of integer values for all N bits by performing different unsigned integer operations on the previous arbitration result output from the latch circuit, respectively. And the N-bit output from each of the first arithmetic circuits as lower bits, and M-bit comparison numerical data presented by each requester for the arbitration algorithm Are compared with M + N-bit unsigned integers, and a value indicated by the lower-order N bits of the output of the comparator is compared. A second arithmetic circuit that performs unsigned subtraction from the previous arbitration result output from the latch circuit and inputs the subtraction result to the latch circuit as a current arbitration result, and has a maximum value in one clock cycle. The arbitration algorithm for searching and the round robin are collectively executed to derive a single arbitration result.
[0015]
According to this invention, the plurality of first arithmetic circuits perform different unsigned integer operations on the previous arbitration result output from the latch circuit, respectively, and perform comparison for round robin composed of integer values of N different bits. Output numerical data. The comparator uses the N-bit output from each of the first arithmetic circuits as the lower bits and combines the M bit comparison numerical data presented by each requester for the arbitration algorithm as the upper bits. The composite data is compared as an unsigned integer of M + N bits and the maximum value is output. The second arithmetic circuit subtracts the value indicated by the lower N bits of the output of the comparator from the previous arbitration result output from the latch circuit without a sign, and uses the subtraction result as the current arbitration result as the latch. Input to the circuit. In this way, the arbitration algorithm for searching for the maximum value and the round robin are collectively executed in one clock cycle to derive the only arbitration result.
[0016]
The arbitration control circuit according to the next invention is the above invention, wherein n = 2. ^N When −1 and L is an integer from 0 to n, each of the first arithmetic circuits corresponds to the Lth request source by adding (n−L + 1) to the output of the latch circuit. The comparison numerical data for round robin is output.
[0017]
According to the present invention, the first arithmetic circuit adds (n−L + 1) to the output of the latch circuit to output the comparison numerical data for round robin corresponding to the Lth request source.
[0018]
The arbitration control circuit according to the next invention is the arbitration control circuit according to the above invention, wherein a flag signal indicating the presence or absence of a request from each request source is input to the comparator as the most significant bit, and the most significant bit output of the comparator is input to the latch circuit. It is input as an enable signal.
[0019]
According to this invention, the flag signal indicating the presence / absence of the request of each request source is input as the most significant bit to the comparator, and the most significant bit output of the comparator is input as the enable signal to the latch circuit. If no request is issued from the request source, the arbitration operation is not executed.
[0020]
The arbitration control circuit according to the next invention is applied to an arbitration algorithm that selects a maximum value among data values presented by a plurality of request sources, and selects a request source that presents the maximum value as a selection result. In the arbitration control circuit that uses round-robin control to finally determine one request source when a value corresponding to is presented from a plurality of request sources, the N-bit arbitration result is latched using the clock signal as a trigger. And a plurality of arithmetic circuits that perform different unsigned integer operations on the previous arbitration result output from the latch circuit and output comparison numerical data for round robin composed of integer values of N bits that are all different. The N-bit output from each of these arithmetic circuits is used as the lower bit, and the M-bit comparison numerical data presented by each requester for the arbitration algorithm is used as the upper bit. As a result of the comparison, the combined data for a plurality of request sources combined as M + N-bit unsigned integers is output, and the number of the request source that is the maximum value is output by this comparison. And a comparator for inputting a maximum value in one clock cycle, and a round robin is collectively executed to derive a single arbitration result.
[0021]
According to the present invention, the plurality of arithmetic circuits perform different unsigned integer arithmetic operations on the previous arbitration result output from the latch circuit, respectively, and obtain comparison numerical data for round robin consisting of integer values of N different bits. Output. In the comparator, the N-bit output from each of these arithmetic circuits is used as the lower bits, and the combined data for a plurality of request sources, each of which is synthesized using the M-bit comparison numerical data presented by each request source for the arbitration algorithm as the upper bits. The number data corresponding to the maximum value is output as an M + N-bit unsigned integer. The output of the comparator, that is, the number data is input to the latch circuit as the current arbitration result.
[0022]
The arbitration control circuit according to the next invention is applied to an arbitration algorithm that selects a minimum value among data values presented by a plurality of request sources and uses the request source presenting the minimum value as a selection result. In the arbitration control circuit that uses round-robin control to finally determine one request source when a value corresponding to is presented from a plurality of request sources, the N-bit arbitration result is latched using the clock signal as a trigger. And a plurality of first outputs of round robin comparison numerical data composed of integer values for all N bits by performing different unsigned integer operations on the previous arbitration result output from the latch circuit, respectively. And the N-bit output from each of the first arithmetic circuits as lower bits, and M-bit comparison numerical data presented by each requester for the arbitration algorithm Comparing the combined data for a plurality of request sources as M + N bits unsigned integers, respectively, and a value indicated by the lower N bits of the output of the comparator, A second arithmetic circuit that obtains the current arbitration result based on unsigned addition of the previous arbitration result output from the latch circuit and inputs the current arbitration result to the latch circuit; An arbitration algorithm that searches for a minimum value in a clock cycle and a round robin are collectively executed to derive a single arbitration result.
[0023]
According to this invention, the plurality of first arithmetic circuits perform different unsigned integer operations on the previous arbitration result output from the latch circuit, respectively, and perform comparison for round robin composed of integer values of N different bits. Output numerical data. The comparator uses the N-bit output from each of the first arithmetic circuits as the lower bits and combines the M bit comparison numerical data presented by each requester for the arbitration algorithm as the upper bits. The composite data is compared as an unsigned integer of M + N bits and the minimum value is output. The second arithmetic circuit obtains the current arbitration result based on unsigned addition of the value indicated by the lower N bits of the output of the comparator and the previous arbitration result output from the latch circuit. The current arbitration result is input to the latch circuit. In this way, the arbitration algorithm for searching for the minimum value and the round robin are collectively executed in one clock cycle to derive the only arbitration result.
[0024]
The arbitration control circuit according to the next invention is the above invention, wherein n = 2. ^N When −1 is set and L is an integer from 0 to n, each of the first arithmetic circuits subtracts the output of the latch circuit from the value (L + n) to obtain a round corresponding to the Lth request source. And the second arithmetic circuit outputs a value indicated by the lower N bits of the output of the comparator, a previous arbitration result output from the latch circuit, a value of 1, The present arbitration result is obtained based on the unsigned addition of.
[0025]
According to the present invention, the first arithmetic circuit subtracts the output of the latch circuit from the value (L + n) to output round robin comparison numerical data corresponding to the Lth request source. The second arithmetic circuit adds the value indicated by the low-order N bits of the output of the comparator, the previous arbitration result output from the latch circuit, and the value 1 unsigned to the current arbitration result. Get.
[0026]
The arbitration control circuit according to the next invention is the arbitration control circuit according to the above invention, wherein a flag signal indicating the presence / absence of a request from each request source is input to the comparator as the most significant bit, and the most significant bit output of the comparator is logically inverted. Then, it is input to the latch circuit as an enable signal.
[0027]
According to the present invention, a flag signal indicating the presence / absence of a request from each request source is input to the comparator as the most significant bit, and the most significant bit output of the comparator is logically inverted and input to the latch circuit as an enable signal. Thus, when the request is not issued from all the request sources, the arbitration operation is not executed.
[0028]
The arbitration control circuit according to the next invention is applied to an arbitration algorithm that selects a minimum value among data values presented by a plurality of request sources and uses the request source presenting the minimum value as a selection result. In the arbitration control circuit that uses round-robin control to finally determine one request source when a value corresponding to is presented from a plurality of request sources, the N-bit arbitration result is latched using the clock signal as a trigger. And a plurality of arithmetic circuits that perform different unsigned integer operations on the previous arbitration result output from the latch circuit and output comparison numerical data for round robin composed of integer values of N bits that are all different. The N-bit output from each of these arithmetic circuits is used as the lower bit, and the M-bit comparison numerical data presented by each requester for the arbitration algorithm is used as the upper bit. As a result of the comparison, the combined data for a plurality of request sources synthesized as M + N bits are compared as unsigned integers, and the request source number that is the minimum value is output by this comparison. And an arbitration algorithm for searching for a minimum value and a round robin are collectively executed in one clock cycle to derive a single arbitration result.
[0029]
According to the present invention, the plurality of arithmetic circuits perform different unsigned integer arithmetic operations on the previous arbitration result output from the latch circuit, respectively, and obtain comparison numerical data for round robin consisting of integer values of N different bits. Output. In the comparator, the N-bit output from each of these arithmetic circuits is used as the lower bits, and the combined data for a plurality of request sources, each of which is synthesized using the M-bit comparison numerical data presented by each request source for the arbitration algorithm as the upper bits. The number data corresponding to the minimum value is output as an unsigned integer of M + N bits. The output of the comparator, that is, the number data is input to the latch circuit as the current arbitration result.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of an arbitration control circuit according to the present invention will be described below in detail with reference to the accompanying drawings.
[0031]
Embodiment 1.
Embodiment 1 of the present invention will be described with reference to FIGS. In the first embodiment, the round robin function is realized when the arbitration algorithm selects the one that outputs the maximum value among the numerical values presented by the request source. FIG. 1 is a diagram extracted and shown only in a portion particularly related to round robin.
[0032]
In FIG. 1, an N-bit DFF (latch circuit, D-type flip-flop circuit) 11 latches a round robin result (N bits) indicating a selected request source using a clock signal as a trigger. . The arithmetic circuit 21 subtracts the output b (N bits) of the comparator 31 from the previous round robin result a (N bits) held by the DFF 11 by an unsigned integer, and the subtraction result (ab) is obtained. Output to DFF11.
[0033]
Arithmetic circuits 40 to 4n (n = 2) ^N -1) outputs the comparison value for round robin by applying the operation shown in the frame to the output value of the DFF 11 input, that is, the previous round robin result a (N bits). For example, the arithmetic circuit 40 performs an N-bit unsigned addition corresponding to the request source “0” and +0 to the output value (N bits) of the DFF 11. The arithmetic circuit 41 performs an N-bit unsigned addition corresponding to the request source “1” and + n to the output value (N bits) of the DFF 11. The arithmetic circuit 42 executes an N-bit unsigned addition corresponding to the request source “2” and + (n−1) to the output value (N bits) of the DFF 11. That is, n = 2 ^N When L is set to −1 and L is an integer from 0 to n, the L-th arithmetic circuit counting from 0 corresponds to the request source “L”, and the output value of (DFF11) + (n−L + 1) N Bit unsigned addition is being performed. Hereinafter, similarly, the arithmetic circuit 4n performs N-bit unsigned addition corresponding to the request source “n” and adding +1 to the output value (N bits) of the DFF 11. The output values of these arithmetic circuits 40 to 4n are input to the comparator 31. The comparator 31 compares all these input values and outputs the maximum value among them to the arithmetic circuit 21.
[0034]
The calculation flow for N = 3 and n = 7 will be described. When the output value of the DFF 11 at a certain time is “5”, the calculation output results of the arithmetic circuits 40, 41, 42, 43, 44, 45, 46, and 47 are “5”, “4”, “ 3 ”,“ 2 ”,“ 1 ”,“ 0 ”,“ 7 ”,“ 6 ”. Here, the position of “5”, which is the previous round robin result, that is, the operation result of the arithmetic circuit of the sign 45 (corresponding to the request source “5”) is 0, and the priority in the next round robin processing is The calculation result of the calculation circuit of the code 46 (corresponding to the request source “6”) next to the code 45 indicates the maximum value “7” of the 3-bit integer, and the priority is the highest. Therefore, if all requesters have issued requests, the largest value among them is naturally “7”, and therefore “7” is output from the comparator 31 as a comparison result. In the arithmetic circuit 21, 5 [+8] −7 = 6 (in unsigned subtraction, when the solution becomes negative, borrowing is automatically generated, and the carry is automatically discarded) Is calculated, and the latest round robin result as its output is “6”. This round robin result “6” is latched by the DFF 11 at the next rising edge of the clock signal, and is output as a round robin result. It can be seen that the round robin result is correct even when compared with the calculation results of the calculation circuits 40 to 47.
[0035]
Thus, since the arithmetic circuit 21, the comparator 31, and the arithmetic circuits 40 to 4n for realizing the round robin are all composed of combinational circuits, and only the DFF 11 is a latch circuit that responds to the clock signal, the round robin processing is performed. It will be completed in 1 clock.
[0036]
Next, FIG. 3 shows the comparison value (N bits) for the round robin shown in FIG. 1, the comparison value (M bits) presented by each request source regarding the arbitration algorithm, and the presence / absence of a request from each request source. An arbitration control circuit for comparing flag signals (valid display bits) at once and outputting a selection result is shown.
[0037]
In FIG. 3, in addition to the comparison values for round robin from the plurality of arithmetic circuits 40 to 4n, the comparisons presented by the request sources “0” to “n” for the arbitration algorithm are shown for the comparator 31. A numerical value (each M bits) and an effective display bit (1 bit each) indicating whether or not there is a request from each request source are input. The valid indication bit is “1” when the request source has issued a request, and is “0” when the request source has not issued a request. That is, the comparison numerical value data synthesized into 1 + M + N bits corresponding to one request source is input to the comparator 31.
[0038]
As shown in FIG. 2, the effective bit (valid / invalid bit) is arranged in the most significant bit, the comparison numerical data of the M-bit arbitration algorithm is arranged in the next upper bit, and the bit configuration is shown in FIG. N bits of round robin (RR) are arranged.
[0039]
In the comparator 31, n + 1 (2) of (1 + M + N) bit width input corresponding to each request source. ^N ) Pieces of comparison numerical data (including valid display bits) are compared as unsigned integer values, the maximum value is searched, and the searched maximum value is output.
[0040]
The comparison process in the comparator 31 will be described with reference to FIG. The comparison part of the comparison value of the arbitration algorithm may have any number of stages as long as the bit width of the comparator 31 allows. Even if the choice is not uniquely determined by the comparison of the comparison value of the arbitration algorithm, The choice is always uniquely determined by comparing the comparison values. In the comparison of numerical values, naturally, the higher-order bits greatly influence the result, and the lower-order bits are referred to when the result is not determined by the higher order. Therefore, by assigning the most significant bit to the higher bit side, it is possible to compare a plurality of factors at once and derive a result.
[0041]
In FIG. 2, the valid / invalid bit is brought to the most significant bit, so that it can be first determined whether or not the request source is really issuing a request. In the case of FIG. 2, since it is a comparator for searching for the maximum value, if this bit is valid, the effective bit becomes smaller than the invalid bit. No side can be in any state. Similarly, among the ones whose effective bits are 1, the numerical values presented by the arbitration algorithm, which is the next lower-order bit, are compared, and if there are multiple values indicating the maximum value, the next lower-order bit is the last. The selection result is uniquely obtained by comparing the round robin numerical values. After all, even if numerical comparison is performed in a lump, it is the same value as such processing.
[0042]
Furthermore, it explains with a concrete example. FIG. 2 shows an example of a comparison numerical value state when N = 3, n = 7, that is, when there are eight (n + 1) request sources. First, 44 (corresponding to the request source “4”) and 46 (corresponding to the request source “6”) are dropped depending on whether the most significant bit is 1 or 0, and then presented to the arbitration algorithm When the numerical values thus obtained are compared, 41 (corresponding to the request source “1”) and 47 (corresponding to the request source “7”) are 11, indicating the maximum value. At this stage, since it is not yet decided uniquely, 41 (corresponding to the request source “1”) is 0 and 47 (corresponding to the request source “7”) is 2 when referring to the last few bits of the round robin. Finally, 47 (corresponding to the request source “7”) is selected.
[0043]
The right side of FIG. 2 shows these numbers actually displayed in binary. Here, since the maximum comparison value of the arbitration algorithm is 11, it is expressed as M = 4. In the batch numerical comparison, it is equivalent to searching for the largest bit by bit from the most significant bit, so if you follow this from the top,
Most significant bit: 40, 41, 42, 43, 45, 47
2nd bit: 41, 42, 47
3rd bit: 41, 42, 47
4th bit: 41, 47
5th bit: 41, 47
6th bit: 41, 47
7th bit: 47
8th bit:-
Naturally, it is the same as the previous result.
[0044]
Next, in FIG. 3, the lower N bits b of the output result (maximum value) of the comparator 31 are used by the next stage arithmetic circuit 21 to calculate the final selection result. The most significant bit of the output result (maximum value) of the comparator 31 is commonly input to an enable signal terminal of an N-bit latch circuit (DFF) 11 with an enable signal.
[0045]
As described with reference to FIG. 1, the arithmetic circuit 21 performs an operation of subtracting the lower N bits b of the output result (maximum value) of the comparator 31 from the output a of the DFF 11 by an unsigned integer, and the subtraction result (Ab) is output to the DFF 11 as the latest arbitration result.
[0046]
Since the most significant bit of the output result (maximum value) of the comparator 31 is input to the enable terminal of the DFF 11, the arbitration result is latched only when the output result is valid. Therefore, when the request is not issued from all the request sources, the arbitration operation is not performed and the arbitration result becomes an invalid value.
[0047]
As described above, in the first embodiment, in the arbitration including the arbitration algorithm for searching and selecting the maximum value and the round robin for finally narrowing down the selection result when the result becomes plural, The upper bits in the comparison numerical bits are the values presented by each requester in relation to the arbitration algorithm, and the lower bits are numerical values determined by round-robin control. This makes it possible to simultaneously execute the arbitration procedure by the arbitration algorithm by numerical comparison and the round-robin narrowing-down procedure without going through multiple stages such as multiple clock steps, thereby simplifying the circuit and simplifying the circuit. It is possible to realize high speed and the like. In addition, a flag signal indicating the presence / absence of each request source is input to the comparator 31 as the most significant bit, and the most significant bit output of the comparator 31 is input to the latch circuit 11 as an enable signal. If no request is issued from the request source, the arbitration operation is not executed, so that an incorrect arbitration result is not output.
[0048]
Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described with reference to FIG. In the second embodiment, the round robin function is realized in the case where the arbitration algorithm selects the one that outputs the minimum value among the numerical values presented by the request source. FIG. 4 shows a comparison value (N bits) for round robin, a comparison value (M bits) presented by each request source regarding the arbitration algorithm, and a flag signal (valid indication bit) indicating whether or not there is a request from each request source. 3 shows an arbitration control circuit for collectively comparing and outputting a selection result.
[0049]
In FIG. 4, an N-bit latch circuit (DFF) 11 is used to latch a round robin result (N bits) indicating a selected request source using a clock signal as a trigger. In this case, the latch circuit 11 has an enable signal terminal that is valid when the input enable signal is 1 and invalid when it is 0, as described above. The arithmetic circuit 22 adds the previous round robin result a (N bits) held by the DFF 11, the output b of the lower N bits of the comparator 32, and the value 1 as an unsigned integer, and the addition result (a + b + 1) ) To the DFF 11 as the latest arbitration result.
[0050]
Arithmetic circuits 50 to 5n (n = 2) ^N -1) outputs the comparison value for round robin by applying the operation shown in the frame to the output value of the DFF 11 input, that is, the previous round robin result a (N bits). For example, the arithmetic circuit 50 performs N-bit unsigned subtraction (na) corresponding to the request source “0” and subtracting the output value a (N bits) of the DFF 11 from n. The arithmetic circuit 51 executes N-bit unsigned subtraction (0-a) corresponding to the request source “1” and subtracting the output value a (N bits) of the DFF 11 from 0. The arithmetic circuit 52 executes N-bit unsigned subtraction (1-a) corresponding to the request source “2” and subtracting the output value a (N bits) of the DFF 11 from 1. That is, n = 2 ^N When L is set to −1 and L is an integer from 0 to n, the L-th arithmetic circuit counting from 0 corresponds to the request source “L” and performs an N-bit unsigned addition of (L + n−a). ing. Hereinafter, similarly, the arithmetic circuit 5n executes N-bit unsigned subtraction corresponding to the request source “n” and subtracting the output value (N bits) a of the DFF 11 from (n−1). The output values of these arithmetic circuits 50 to 5n are input to the comparator 32.
[0051]
For the comparator 32, in the same manner as in the first embodiment, in addition to the comparison values for round robin from the plurality of arithmetic circuits 50 to 5n, each request source “0” to “n” is used for the arbitration algorithm. A comparison numerical value to be presented (each M bits) and an effective display bit (1 bit each) indicating whether or not there is a request from each request source are input. However, in this case, since the minimum value is selected, the valid display bit is opposite to that of the first embodiment, and is “0” when the request source issues a request, and the request source issues the request. When it is not, it is “1”. In this way, the comparison numerical value data synthesized into 1 + M + N bits corresponding to one request source is input to the comparator 32.
[0052]
As shown in FIG. 2, the bit configuration is such that a valid display bit (valid / invalid bit) is arranged in the most significant bit, and comparison numerical data of an M-bit arbitration algorithm is arranged in the next higher bit. N bits of round robin (RR) are arranged in bits.
[0053]
In the comparator 32, n + 1 (2) of (1 + M + N) bit width inputted corresponding to each request source. ^N ) Pieces of comparison numerical data (including valid display bits) are compared as unsigned integer values, the minimum value is searched for, and the searched minimum value is output.
[0054]
Of the output result (maximum value) of the comparator 32, the lower N bits b are used to calculate the final selection result in the arithmetic circuit 22 in the next stage. In other words, the arithmetic circuit 22 adds the output a (N bits) of the DFF 11, the output b of the lower N bits of the comparator 32, and the value 1 as an unsigned integer, and the addition result (a + b + 1) is used as the latest arbitration result. To the DFF 11.
[0055]
The most significant bit of the output result (maximum value) of the comparator 32 is input to the inverter 23, and a value logically inverted by the inverter 23 is used as an enable signal of the N-bit latch circuit (DFF) 11 Common input to terminals. Thus, also in this case, since the most significant bit of the output result (minimum value) of the comparator 32 is input to the enable terminal of the DFF 11, the arbitration result is latched only when the output result is valid. The Therefore, when the request is not issued from all the request sources, the arbitration operation is not performed and the arbitration result becomes an invalid value.
[0056]
Next, a calculation flow in which the comparator 32 calculates the minimum value will be described. When N = 3 and n = 7, and the value currently latched in the DFF 11 is “4”, the operation outputs of the operation circuits 50 to 57 are “3”, “4”, “5”, respectively. ”,“ 6 ”,“ 7 ”,“ 0 ”,“ 1 ”,“ 2 ”. Here, the position of the previous round robin result “4”, that is, the calculation result of the calculation circuit of the code 54 (corresponding to the request source “4”) is the maximum value 7 of the 3-bit integer, and the minimum value is Since it is a circuit to be searched, the priority in the next round robin processing is the lowest, the calculation result of the arithmetic circuit of the code 55 next to the code 54 (corresponding to the request source “5”) indicates the minimum “0”, and the priority Is the best. Therefore, if all requesters have issued requests, the smallest numerical value is naturally “0”, and therefore, “0” is output from the comparator 32 as a comparison result. Then, the arithmetic circuit 22 calculates 4 + 0 + 1 = 5 (3-bit unsigned addition), and the latest round robin result as the output is “5”. The round robin result “5” is latched by the DFF 11 at the next rising edge of the clock signal, and is output as a round robin result. It can be seen that the round robin result is correct even when compared with the calculation results of the calculation circuits 50 to 57.
[0057]
As described above, in the second embodiment, in the arbitration including the arbitration algorithm for searching for and selecting the minimum value and the round robin for finally narrowing down the selection result when the result becomes plural, The high-order bits in the comparison numerical bits are the values presented by each requester in relation to the arbitration algorithm, and the low-order bits are numerical values determined by round-robin control. This makes it possible to simultaneously execute the arbitration procedure by the arbitration algorithm by numerical comparison and the round-robin narrowing-down procedure without going through multiple stages such as multiple clock steps, thereby simplifying the circuit and simplifying the circuit. It is possible to realize high speed and the like. Further, a flag signal indicating the presence / absence of a request from each request source is input to the comparator 32 as the most significant bit, and the most significant bit output of the comparator 32 is logically inverted and input to the latch circuit (DFF) 11 as an enable signal. By doing so, when the request is not issued from all the request sources, the arbitration operation is not executed, so that an incorrect arbitration result is not output.
[0058]
Embodiment 3 FIG.
Next, a third embodiment of the present invention will be described. Usually, in the comparator, a first type that outputs a comparison result of a plurality of input values and a second type that outputs number data corresponding to the input value selected as a result of comparison or a decoded version of the number. There are two types.
[0059]
For example, in a comparator that performs comparison at any time in the tournament format and searches for the maximum or minimum, it is necessary to compare again after one comparison, so the value output as the comparison result is the comparison value itself. In addition, the first type in which the comparison value is output as it is as the result of the comparison in the final stage is desirable.
[0060]
On the other hand, when all the values are compared and the comparison result is output all at once, there is no need to transmit the comparison value next, so the comparison result is displayed depending on whether the flag corresponding to the number data of the input value is valid or invalid. Will get. That is, in this case, for example, there are comparison targets from 0 to 7, and eight signals are prepared for output of the comparison result, and only the signal line corresponding to the comparison reference number indicating the maximum or minimum is provided. There will be 1 in each. In this case, by encoding the result into a numerical value, it is possible to realize a comparator that outputs number data (0 to n) corresponding to the maximum or minimum comparison value.
[0061]
If such a second type of comparator is used, the output of the comparator will be the final arbitration result. Therefore, when the maximum value selection method is adopted, the arithmetic circuit 21 of FIG. When the minimum value selection method is adopted, the arithmetic circuit 22 in FIG. 4 can be omitted. Then, the output of this comparator may be input to the DFF 11 as it is.
[0062]
Also in the third embodiment, as in the previous embodiment, the arbitration procedure by the arbitration algorithm by numerical comparison and the narrow-down procedure by the round robin can be executed simultaneously without performing a plurality of stages such as a plurality of clock steps. It becomes possible.
[0063]
【The invention's effect】
As described above, according to the arbitration control method according to the present invention, the arbitration algorithm for searching for and selecting the maximum value or the minimum value and finally selecting the selection result when there are a plurality of results. In the arbitration including round robin, the upper bits in the comparison numerical bits are the values presented by each requester in relation to the arbitration algorithm, and the lower bits are numerical values determined by the round robin control. By comparing, it becomes possible to simultaneously execute the arbitration procedure by the arbitration algorithm by numerical comparison and the round-robin narrowing-down procedure without going through multiple stages such as multiple clock steps, thereby simplifying the circuit, It becomes possible to increase the speed of the circuit.
[0064]
According to the next invention, in the arbitration control circuit that determines one request source that outputs the maximum value, the latch circuit that latches the N-bit arbitration result by the clock signal, and the previous arbitration output from the latch circuit A plurality of first arithmetic circuits that perform different unsigned integer operations on the results and output comparison numerical data for round robin, and N-bit output from each of the first arithmetic circuits is used as a lower bit for the arbitration algorithm A comparator that outputs a maximum value by comparing combined data for a plurality of request sources obtained by combining M-bit comparison numerical data presented by each request source as upper bits, and an M + N-bit unsigned integer, and this comparator The value indicated by the lower-order N bits of the output of the output is unsigned subtracted from the previous arbitration result output from the latch circuit, and this subtraction result is obtained as the current arbitration result And a second arithmetic circuit for inputting to the latch circuit, and the arbitration algorithm for searching for the maximum value and the round robin are collectively executed in one clock cycle to derive a single arbitration result. Therefore, an arbitration control circuit with a simple configuration and capable of high-speed processing can be realized.
[0065]
According to the arbitration control circuit of the next invention, the first arithmetic circuit adds (n−L + 1) to the output of the latch circuit, so that the comparison numerical data for round robin corresponding to the Lth request source Therefore, an arbitration control circuit capable of high-speed processing and capable of high-precision arbitration can be realized with a simple configuration.
[0066]
According to the arbitration control circuit of the next invention, a flag signal indicating the presence / absence of each request source is input to the comparator as the most significant bit, and the most significant bit output of the comparator is used as an enable signal to the latch circuit. By inputting, when the request is not issued from all the request sources, the arbitration operation is not executed, so that an incorrect arbitration result is not output.
[0067]
According to the arbitration control circuit according to the next invention, since the comparator outputs the request source number data corresponding to the maximum value as the arbitration result, the request source corresponding to the maximum value from the derived maximum value. Therefore, it is possible to achieve simpler circuit simplification, higher circuit speed, and the like.
[0068]
According to the arbitration control circuit of the next invention, in the arbitration control circuit that determines one request source that outputs the minimum value, a latch circuit that latches an N-bit arbitration result by a clock signal, and an output from the latch circuit A plurality of first arithmetic circuits that perform different unsigned integer operations on the previous arbitration result and output comparison numerical data for round robin, and N-bit output from each first arithmetic circuit as lower bits A comparator which outputs a minimum value by comparing combined data for a plurality of request sources, each of which is synthesized as Mbit comparison numerical data presented by each request source for the arbitration algorithm as upper bits, as an unsigned integer of M + N bits And unsigned addition of the value indicated by the lower N bits of the output of the comparator and the previous arbitration result output from the latch circuit. The second arithmetic circuit that outputs the arbitration result of this time is provided, and the arbitration algorithm that searches for the minimum value and the round robin are collectively executed in one clock cycle to derive the only arbitration result. Thus, an arbitration control circuit having a simple configuration and capable of high-speed processing can be realized.
[0069]
According to the arbitration control circuit according to the next invention, the first arithmetic circuit subtracts the output of the latch circuit from the value (L + n), whereby the comparison numerical data for round robin corresponding to the Lth request source. And the second arithmetic circuit adds the value indicated by the lower N bits of the output of the comparator, the previous arbitration result output from the latch circuit, and the value 1 without a sign. Since the current arbitration result is obtained, an arbitration control circuit capable of high-speed processing and high-precision arbitration can be realized with a simple configuration.
[0070]
According to the arbitration control circuit of the next invention, a flag signal indicating the presence / absence of a request from each request source is input to the comparator as the most significant bit, and the most significant bit output of the comparator is logically inverted to the latch circuit. By inputting as an enable signal, the arbitration operation is not executed when there is no request from all request sources, so that an incorrect arbitration result is not output.
[0071]
According to the arbitration control circuit of the next invention, since the comparator outputs the request source number data corresponding to the minimum value as the arbitration result, the request source corresponding to the minimum value from the derived minimum value. Therefore, it is possible to achieve simpler circuit simplification, higher circuit speed, and the like.
[Brief description of the drawings]
BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a diagram showing a first embodiment of an arbitration control circuit according to the present invention, and is a block diagram specifically showing only portions related to round robin.
FIG. 2 is a diagram showing comparison value data using a comparison value obtained by an arbitration algorithm for upper bits and a comparison value obtained by round robin for lower bits.
FIG. 3 is a block diagram showing a first embodiment of an arbitration control circuit according to the present invention;
FIG. 4 is a block diagram showing a second embodiment of an arbitration control circuit according to the present invention.
[Explanation of symbols]
11 latch circuit (D-type flip-flop), 21 arithmetic circuit (second arithmetic circuit), 22 arithmetic circuit (second arithmetic circuit), 31 comparator, 32 comparator, 40 to 4n arithmetic circuit (first arithmetic circuit) Circuit), 50 to 5n arithmetic circuit (first arithmetic circuit).

Claims (11)

This is applied to the arbitration algorithm that selects the maximum value or minimum value from the data values presented by multiple request sources and selects the request source that presents the maximum value or minimum value as the selection result. In an arbitration control method using round robin control to finally determine one request source when corresponding values are presented from a plurality of request sources,
A first comparison numerical data each requester presents for the M upper bits arbitration algorithm, the lower N bits, when the number of the plurality of requestor of 2 ^N, for the previous arbitration result A second comparison numerical data for round robin composed of integer values for all different N bits subjected to different unsigned integer operations for outputting different values from 0 to 2 ^N -1 for each request source, By comparing the first and second comparison numerical data for the request source as M + N-bit unsigned integers, the maximum or minimum value of the M + N-bit data is retrieved to obtain the current arbitration result. An arbitration control method characterized by the above. It is applied to the arbitration algorithm that selects the maximum value from the data values presented by multiple requesters and selects the requester presenting the maximum value as the selection result, and the value corresponding to the maximum value is obtained from the multiple requesters. In the arbitration control circuit that uses round-robin control to ultimately determine one requester, if present,
A latch circuit that latches an N-bit arbitration result using a clock signal as a trigger;
The same number as the plurality of request sources, each corresponding to a different request source, and each of the previous arbitration results output from the latch circuit are subjected to different unsigned integer operations to obtain all different N-bit integer values. A plurality of first arithmetic circuits that output comparison numerical data for round robin,
The N-bit output from each of these first arithmetic circuits is the lower bit, the M-bit comparison numerical data presented by each request source for the arbitration algorithm is the upper bit, and the M-bit comparison numerical data presented by each request source A comparator that compares combined data for a plurality of request sources , each of which combines N-bit outputs from the first arithmetic circuit corresponding to, as an M + N-bit unsigned integer, and outputs a maximum value;
The value indicated by the lower N bits of the output of the comparator is subtracted without sign from the previous arbitration result output from the latch circuit, and this subtraction result is input to the latch circuit as the current arbitration result. Arithmetic circuit of
And an arbitration algorithm that retrieves a maximum value in one clock cycle and a round robin collectively to derive an arbitration control circuit. When n = 2 ^N −1 and L is an integer from 0 to n, each of the first arithmetic circuits adds (n−L + 1) to the output of the latch circuit, so that the L th request The arbitration control circuit according to claim 2, wherein comparison numerical data for round robin corresponding to the original is output.   3. The flag signal indicating the presence or absence of a request from each request source is input to the comparator as the most significant bit, and the most significant bit output of the comparator is input to the latch circuit as an enable signal. 4. The arbitration control circuit according to 3. It is applied to the arbitration algorithm that selects the maximum value from the data values presented by multiple requesters and selects the requester presenting the maximum value as the selection result, and the value corresponding to the maximum value is obtained from the multiple requesters. In the arbitration control circuit that uses round-robin control to ultimately determine one requester, if present,
A latch circuit that latches an N-bit arbitration result using a clock signal as a trigger;
The same number as the plurality of request sources, each corresponding to a different request source, and each of the previous arbitration results output from the latch circuit are subjected to different unsigned integer operations to obtain all different N-bit integer values. A plurality of arithmetic circuits that output comparison numerical data for round robin,
The N-bit output from each of these arithmetic circuits is the lower bit, and the M-bit comparison numerical data presented by each request source for the arbitration algorithm is the upper bit , corresponding to the M-bit comparison numerical data presented by each request source. Compare the combined data for multiple request sources , each of which combines the N-bit output from the arithmetic circuit, as an M + N-bit unsigned integer, and output the request source number that is the maximum value by this comparison. A comparator that inputs to the latch circuit as an arbitration result of:
And an arbitration algorithm that retrieves a maximum value in one clock cycle and a round robin collectively to derive an arbitration control circuit. This is applied to an arbitration algorithm that selects a minimum value from data values presented by a plurality of request sources, and a request source that presents the minimum value is selected, and a value corresponding to the minimum value is obtained from a plurality of request sources. In the arbitration control circuit that uses round-robin control to ultimately determine one requester, if present,
A latch circuit that latches an N-bit arbitration result using a clock signal as a trigger;
The same number as the plurality of request sources, each corresponding to a different request source, and each of the previous arbitration results output from the latch circuit are subjected to different unsigned integer operations to obtain all different N-bit integer values. A plurality of first arithmetic circuits that output comparison numerical data for round robin,
The N-bit output from each of these first arithmetic circuits is the lower bit, the M-bit comparison numerical data presented by each request source for the arbitration algorithm is the upper bit, and the M-bit comparison numerical data presented by each request source A comparator that compares the combined data for a plurality of request sources , each of which combines the N-bit output from the first arithmetic circuit corresponding to, as an M + N-bit unsigned integer, and outputs a minimum value;
The current arbitration result is obtained based on the unsigned addition of the value indicated by the lower N bits of the output of the comparator and the previous arbitration result output from the latch circuit. A second arithmetic circuit that inputs to the latch circuit;
And an arbitration control circuit that derives a single arbitration result by collectively executing an arbitration algorithm that searches for a minimum value and a round robin in one clock cycle. When n = 2 ^N −1 and L is an integer from 0 to n, each of the first arithmetic circuits subtracts the output of the latch circuit from the value (L + n) to obtain an Lth request source. Output the comparison numerical data for round robin corresponding to
The second arithmetic circuit adds the value indicated by the lower N bits of the output of the comparator, the previous arbitration result output from the latch circuit, and the value 1 unsigned. The arbitration control circuit according to claim 6, wherein an arbitration result is obtained.   A flag signal indicating the presence / absence of a request from each request source is input to the comparator as the most significant bit, and the most significant bit output of the comparator is logically inverted and input to the latch circuit as an enable signal. The arbitration control circuit according to claim 6 or 7. This is applied to an arbitration algorithm that selects a minimum value from data values presented by a plurality of request sources, and a request source that presents the minimum value is selected, and a value corresponding to the minimum value is obtained from a plurality of request sources. In the arbitration control circuit that uses round-robin control to ultimately determine one requester, if present,
A latch circuit that latches an N-bit arbitration result using a clock signal as a trigger;
The same number as the plurality of request sources, each corresponding to a different request source, and each of the previous arbitration results output from the latch circuit are subjected to different unsigned integer operations to obtain all different N-bit integer values. A plurality of arithmetic circuits that output comparison numerical data for round robin,
The N-bit output from each of these arithmetic circuits is the lower bit, and the M-bit comparison numerical data presented by each request source for the arbitration algorithm is the upper bit , corresponding to the M-bit comparison numerical data presented by each request source. Compares the combined data for multiple request sources , each of which combines the N-bit output from the arithmetic circuit, as an M + N-bit unsigned integer, and outputs the request source number that is the minimum value by this comparison. A comparator that inputs to the latch circuit as an arbitration result of:
And an arbitration control circuit that derives a single arbitration result by collectively executing an arbitration algorithm that searches for a minimum value and a round robin in one clock cycle. It is applied to the arbitration algorithm that selects the maximum value from the data values presented by multiple requesters and selects the requester presenting the maximum value as the selection result, and the value corresponding to the maximum value is obtained from the multiple requesters. In the arbitration control method using round robin control to finally determine one requester, if present,
  The upper M bits are the first comparison numerical data presented by each request source for the arbitration algorithm, and the lower N bits are the number of the plurality of request sources being 2. ^N And L is changed from 0 to n = 2 ^N For round robin composed of all different N bits of integer values obtained by performing (n−L + 1) N-bit unsigned addition on the previous arbitration result at the L-th request source counting from 0 as an integer up to −1 Based on searching for the maximum value of the M + N bit data by comparing the first and second comparison numerical data for a plurality of request sources as unsigned integers of M + N bits as second comparison numerical data. An arbitration control method characterized in that the arbitration result of this time is obtained. This is applied to an arbitration algorithm that selects a minimum value from data values presented by a plurality of request sources, and a request source that presents the minimum value is selected, and a value corresponding to the minimum value is obtained from a plurality of request sources. In the arbitration control method using round robin control to finally determine one requester, if present,
  The upper M bits are the first comparison numerical data presented by each request source for the arbitration algorithm, and the lower N bits are the number of the plurality of request sources being 2. ^N And L is changed from 0 to n = 2 ^N The second round robin consisting of integer values for all N different bits obtained by performing N-bit unsigned subtraction on the previous arbitration result from (L + n) at the Lth request source counting from 0 as an integer up to -1. And the first and second comparison numerical data for a plurality of request sources are compared as M + N bit unsigned integers to search for the minimum value of the M + N bit data. An arbitration control method characterized by obtaining an arbitration result.

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