JP4689218B2 - Method for manufacturing semiconductor device - Google Patents

Description

    The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a conductive member having fine carbon fibers is formed in a contact hole.

Aluminum, copper, tungsten, or the like is used for the wiring of the semiconductor device. This is formed on an insulating film having a multilayer structure, and fine pattern wiring is formed by a photolithography process and an etching process.

  As the circuit is highly integrated, the wiring is also miniaturized, and the resistance of the wiring increases with this. This is one of the causes of increasing the power consumption of the integrated circuit, and the total extension distance of the wiring becomes longer as the integration progresses, which is a serious problem.

On the other hand, there is a material having a low work function or negative electron affinity, for example, a material formed using carbon, and typical examples thereof include carbon nanotubes (hereinafter referred to as CNT (Carbon Nanotube)), carbon nanofibers, Examples thereof include graphite nanofibers, tube-like graphite, carbon nanocones with a sharp tip, ultrafine carbon fibers such as cone-like graphite, fullerenes, and the like.

  CNT refers to nanometer-sized cylindrical graphite. Carbon nanotubes include carbon nanotubes and multi-wall nanotubes. A carbon-walled nanotube is a tube in which a single graphene sheet (carbon hexagonal mesh surface of a carbon atom layer) is closed in a cylindrical shape, and has a diameter of about 1 to 10 nm and a length of 1 to 100 μm. Multi-walled nanotubes are obtained by stacking cylindrical graphene sheets in multiple layers, and have an outer diameter of 5 to 50 nm, a central cavity diameter of 3 to 10 nm, and a length of 1 to 100 μm.

  CNTs have a sharp tip shape, are thermally and chemically stable, mechanically tough, and have properties such as electrical conductivity. Therefore, CNTs are used as microstructure vias (conductive members). , Attracting attention.

  However, the CNT has a fine structure, and a contact area is narrow when interconnects formed in different layers are connected. In addition, when a large number of CNTs are formed, it is difficult to form CNTs having a uniform height. For this reason, contact resistance increases and it is difficult to reliably connect different wirings. As a result, there is a problem that the yield of a semiconductor device using CNTs for connection wiring is lowered.

  Therefore, the present invention provides a semiconductor device with high reliability of connection between wirings. In addition, a method for manufacturing a semiconductor device capable of manufacturing a semiconductor device with high yield is provided.

  One feature of the present invention is that a conductive member formed in a contact hole such as a via or a plug is formed of an ultrafine carbon fiber and a conductive film. The conductive film is filled between ultrafine carbon fibers, and can be connected with high reliability while suppressing contact resistance with wirings formed on different layers.

    Further, according to one aspect of the present invention, after forming an ultrafine carbon fiber using a region containing a metal element as a catalyst, a conductive film is formed, the conductive film is fluidized, and the space between the ultrafine carbon fibers is filled with the conductive film. A conductive member is formed.

  Here, the region containing the metal element is formed of a nickel element, an iron element, a cobalt element, a platinum element, a germanium element, a titanium element, a palladium element, a zinc element, or a compound of these elements. Examples of the compound include silicides and oxides.

  The conductive film is formed of a conductive film having fluidity at a certain temperature or higher, such as aluminum, an alloy containing aluminum, or copper. In addition, a crystalline semiconductor film to which an impurity such as phosphorus, boron, or arsenic is added can also be used.

  Examples of the ultrafine carbon fiber formed in the present invention include CNT, carbon nanofiber, graphite nanofiber, tube-like graphite, carbon nanocone with a sharp tip, cone-like graphite, and the like.

    According to the present invention, a plurality of conductive layers formed through an insulating layer, typically, wiring can be connected by vias (conductive members) formed of ultrafine carbon fibers and a conductive layer filling between them. . For this reason, the via (conductive member) has a fine structure, and finely processed wiring can be connected to form a highly integrated circuit. In addition, since the via formed in the contact hole is filled with the conductive film, the connection area with the wiring can be increased, and the wiring can be connected with high reliability. Thus, a semiconductor device can be manufactured with high yield.

    The best mode for carrying out the invention will be described below with reference to the drawings. However, those skilled in the art can easily understand that the present invention can be implemented in many different modes, and that various modifications can be made without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the embodiment modes. In the drawings, common portions are denoted by the same reference numerals, and detailed description thereof is omitted.

(First embodiment)
A conductive member which is an embodiment of the connection wiring of the present invention will be described with reference to FIG. The conductive member includes general vias and plugs.

  FIG. 1A illustrates a conductive member 101 connected to part of a semiconductor region 100 (a source region or a drain region) of a semiconductor device. The conductive member 101 is located between the insulating films 102, and is an ultrafine carbon fiber 104 formed on the region 103 having a metal element, and a conductive layer 105 filled between the ultrafine carbon fibers 104. It is formed.

  The region 103 containing a metal element is formed of nickel element, iron element, cobalt element, platinum element, germanium element, titanium element, palladium element, zinc element, or a compound of these elements. Examples of the compound include silicides and oxides.

    The conductive layer 105 is formed using a conductive film having fluidity at a certain temperature or higher, such as aluminum, an alloy containing aluminum, or copper. In addition, a crystalline semiconductor film to which an impurity such as phosphorus, boron, or arsenic is added can also be used. The conductive member is connected to the wiring layer 106 formed on the insulating film 102.

    In FIG. 1A, the height of the ultrafine carbon fiber 104 is higher than the thickness of the insulating film 102, but is not limited to this structure, and is lower than the thickness of the insulating film 102. May be.

FIG. 1B illustrates a conductive member having a structure different from that in FIG. The conductive member 111 connects the first wiring layer 112 and the second wiring layer 113. The conductive member (via) 111 is located between the insulating films 114. In addition, a region 115 having a metal element formed on the first wiring layer 112, an ultrafine carbon fiber 116 formed thereon, and a conductive layer 117 filled between the ultrafine carbon fibers 116 are also included. Is formed.
The surface of the conductive member 111 shown in FIG. 1B is flattened and is almost the same height as the film thickness of the insulating film 114.

Since the conductive member (via) 111 formed in the contact hole is filled with the conductive film, the connection area with the wiring can be increased, and the wiring can be connected with high reliability. Thus, a semiconductor device can be manufactured with high yield.

(Second Embodiment)
In this embodiment, a manufacturing process of the conductive member shown in Embodiment 1 is shown. Hereinafter, description will be made using CNT as a representative example of the ultrafine carbon fiber.

  As shown in FIG. 2A, an interlayer insulating film is formed over the first wiring layer or the semiconductor region. In this embodiment, an interlayer insulating film 202 is formed on the semiconductor region 201. Next, a resist mask 203 is formed by a known photolithography process.

  Next, as shown in FIG. 2B, a portion of the interlayer insulating film not covered with the resist mask is etched to expose a part of the semiconductor region, thereby forming a contact hole 211. Next, after removing the resist mask with a stripping solution, the first conductive film 212 is formed by a known method such as a sputtering method or a CVD method. The first conductive film is formed using a nickel element, an iron element, a cobalt element, a platinum element, a germanium element, a titanium element, a palladium element, a zinc element, or a compound of these elements. Examples of the compound include silicides and oxides.

  Next, as illustrated in FIG. 2C, part of the first conductive film is removed by a lift-off method, an etching method, or the like, so that a region 221 containing an island-shaped metal element is formed over the semiconductor region. The region including an island-shaped metal element may be formed using a mask.

    Next, the CNT 222 is formed using the region containing the metal element as a catalyst. As a forming method, a catalytic CVD method using alcohol as a raw material gas, a thermal CVD method in which heating is performed at 100 to 1100 degrees, preferably 400 to 650 degrees in an atmosphere containing a hydrocarbon such as methane, ethylene, or acetylene, There is a plasma CVD method in which a hydrocarbon is used and formed under a reduced pressure of 0.1 to 10 torr. In the plasma CVD method, CNT grows in a direction perpendicular to the substrate by applying a negative voltage to the substrate side. Alternatively, CNTs can be formed by a plasma CVD method in which a pulse voltage is applied using a hydrocarbon as a raw material in an atmospheric pressure atmosphere.

  Next, as shown in FIG. 2D, a second conductive film 231 is formed. The second conductive film is formed using a conductive film having fluidity by heating at a certain temperature or higher, such as aluminum, an alloy containing aluminum, or copper. In addition, a crystalline semiconductor film to which an impurity such as phosphorus, boron, or arsenic is added can be used.

  Next, the second conductive film is fluidized by heating at 400 to 550 degrees, and the contact hole 211 is filled with the second conductive film. By this step, the surface of the second conductive film is substantially planarized. After that, the second conductive film is etched into a desired shape to form a conductive member 241 as shown in FIG.

  Thereafter, the surface of the conductive member 241 may be etched back so that the conductive member has a height similar to the film thickness of the interlayer insulating film 202. Further, instead of this step, the surface of the second conductive film may be polished by CMP to form a conductive member having a similar shape.

  According to the present invention, vias (conductive members) formed of ultrafine carbon fibers and a conductive layer filling between the fine carbon fibers can be formed in the contact holes on the wiring. Therefore, the via (conductive member) has a fine structure, and a finely processed wiring can be connected to form a highly integrated circuit. In addition, since the via formed in the contact hole is filled with the conductive film, the connection area with the wiring can be increased, and the wiring can be connected with high reliability. Thus, a semiconductor device can be manufactured with high yield.

(Third embodiment)
In this embodiment, a process different from that of the second embodiment is shown as a manufacturing process of the conductive member shown in the first embodiment.
As shown in FIG. 3A, as in the second embodiment, an interlayer insulating film 202 is formed on the first wiring layer or the semiconductor region 201 as shown in FIG.

  Next, as shown in FIG. 3B, as in the second embodiment, the part of the interlayer insulating film not covered with the resist mask is etched to expose a part of the semiconductor region, and the contact hole 211. Form. Next, after removing the resist mask with a stripping solution, the first conductive film 212 is formed.

  Next, as shown in FIG. 3C, as in the second embodiment, a region 221 containing an island-shaped metal element is formed over the semiconductor region. The region including the metal element is formed using a nickel element, an iron element, a cobalt element, a platinum element, a germanium element, a titanium element, a palladium element, a zinc element, or a compound of these elements. Examples of the compound include silicides and oxides.

  Next, using methanol as a source gas, CNTs are formed using a region containing a metal element as a catalyst. In addition, heating is performed at 100 to 1100 degrees, preferably 400 to 650 degrees in an atmosphere including hydrocarbon such as methane, ethylene, or acetylene at 1 to 760 torr to form CNTs using a region including a metal element as a catalyst. . Alternatively, a hydrocarbon such as methane, ethylene, or acetylene may be used as a raw material, and it may be formed by plasma CVD using 1 to 760 torr as a catalyst and a region containing a metal element. In this case, the CNT grows in a direction perpendicular to the substrate by applying a negative voltage to the substrate side. Alternatively, CNTs can be formed by a plasma CVD method in which a pulse voltage is applied using a hydrocarbon as a raw material in an atmospheric pressure atmosphere.

  Next, as shown in FIG. 3D, a second conductive film 231 is formed. In this embodiment, a crystalline semiconductor film to which an impurity such as phosphorus, boron, or arsenic is added is formed as the second conductive film.

  Next, continuous wave laser light 232 is irradiated to the second conductive film 231 to melt and fluidize the second conductive film, and the contact hole 211 is filled with the second conductive film. The second conductive film is solidified after melting and flowing to become a crystalline semiconductor film. Further, the surface is almost flattened. Thereafter, the second conductive film is etched into a desired shape to form a conductive member.

  After the second conductive film is melted and fluidized and the contact hole 211 is filled with the second conductive film 231, a third conductive film is formed, and the second conductive film and the third conductive film are formed. Etching is performed to form the second conductive layer 250 and the third conductive layer 251, respectively, and the second conductive layer 250, the CNT 222, and the third conductive layer 251 are formed as shown in FIG. The conductive member 252 to be formed may be formed.

  Thereafter, the surface of the conductive member 252 may be etched back to form a conductive member having a height similar to the thickness of the interlayer insulating film 202. Further, instead of this step, the surface of the second conductive film may be polished by CMP to form a conductive member having a similar shape.

  According to the present invention, vias (conductive members) formed of ultrafine carbon fibers and a conductive layer filling between the fine carbon fibers can be formed in the contact holes on the wiring. Therefore, the via (conductive member) has a fine structure, and a finely processed wiring can be connected to form a highly integrated circuit. In addition, since the via formed in the contact hole is filled with the conductive film, the connection area with the wiring can be increased, and the wiring can be connected with high reliability. Thus, a semiconductor device can be manufactured with high yield.

(Fourth embodiment)
In this embodiment, a region including metal is a metal compound, and a method for manufacturing a conductive member including CNTs formed using the compound as a catalyst and a semiconductor device including the conductive member will be described with reference to FIGS.

  First, the base insulating film 302 is formed over the substrate 301. As the substrate 301, a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature may be used.

  As the base insulating film 302, a base film made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. The base film is formed as a single layer film or a structure in which two or more layers are stacked.

  Next, a semiconductor film 303 is formed over the base insulating film. Here, as the semiconductor film, a semiconductor film having an amorphous structure is formed by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like). There is no limitation on the material of the semiconductor film, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy.

  Next, a metal element is added to the semiconductor film. As a method for adding the metal element, plasma treatment, vapor deposition, ion implantation, sputtering, or solution coating can be used. Here, a solution 304 containing 1 to 100 ppm, preferably 5 to 20 ppm of a metal element is applied. Thereafter, when the amorphous semiconductor film is heated in a nitrogen atmosphere at 400 to 600 degrees, a compound of a metal element and an element of the semiconductor film (typically nickel silicide, iron silicide, cobalt silicide, platinum silicide, palladium A crystallization reaction with suicide, titanium silicide, etc.) as a nucleus occurs, and a crystalline semiconductor film is formed.

  Next, as shown in FIG. 4B, a semiconductor region is formed by etching the semiconductor film into a desired shape using a resist mask. The semiconductor region is formed with a thickness of 25 to 80 nm (preferably 30 to 60 nm).

  Next, after removing the resist mask, an insulating film 312 is formed to cover the semiconductor region. The insulating film 312 is formed using a single layer or a stacked structure of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. This insulating film 312 becomes a gate insulating film of the TFT.

  Next, a conductive film with a thickness of 100 to 600 nm is formed over the insulating film 312. Here, a conductive film made of a W film is formed by sputtering. Note that although the conductive film is W, it is not particularly limited, and an element selected from Ta, W, Ti, Mo, Al, Cu, or a single layer of an alloy material or a compound material containing the element as a main component, or You may form by these laminated | stacked. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used.

    Next, after forming a resist mask, the conductive film is etched by a dry etching method or a wet etching method, so that the conductive layer 313 is obtained. Note that the conductive layer 313 serves as a gate electrode of the TFT.

  Note that the conductive layer 313 may be a conductive layer having a tapered portion (tapered portion) at an end portion using an ICP etching apparatus. The angle of the tapered portion (taper angle) is defined as the angle formed by the substrate surface (horizontal plane) and the inclined portion of the tapered portion. The taper angle of the conductive layer can be in the range of 5 to 45 degrees by appropriately selecting the etching conditions.

Next, an impurity element is doped into the semiconductor region using the conductive layer 313 as a mask, so that a channel formation region 315 covered with the gate electrode and an impurity region 314 doped with the impurity are formed. Note that the impurity region becomes a later source region and drain region. In the case of forming a p-channel TFT, doping is performed so that the concentration of an element imparting p-type in the impurity region, for example, boron (B) is 1 × 10 ^{19 to} 5 × 10 ²¹ / cm ³ . N
In the case of forming a channel type TFT, the concentration of an element imparting n-type in an impurity region, for example, phosphorus (P) is 5 × 10 ^{19 to} 5 × 10 ²¹ / cm ³ , and the concentration of a rare gas is 1 × 10 ¹⁹ to 1. × 10 ²² / c
Doping is performed to m ³ . Thereafter, heating is performed at 450 to 800 ° C. for 1 minute to 24 hours to activate the impurity element and move the metal element in the channel formation region to the impurity region. Here, since phosphorus or a rare gas is added to the semiconductor region, the metal element becomes a metal compound and moves to the impurity region by heat treatment. After the movement, segregation occurs in the impurity region as indicated by reference numeral 321 in FIG. In this embodiment, the semiconductor region is heated by a GRTA method in which a gas heated to 610 degrees is blown for 1 minute. Note that, as the heating step, a heat treatment using a furnace, an LRTA method, or a laser annealing method can be used instead of the GRTA method.

In this embodiment, a high concentration impurity is doped as the impurity region. In addition, the impurity concentration is low between the region doped with the high concentration impurity and the channel formation region. A region doped so as to be in the range of × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁹ / cm ³ (so-called LDD (Light Doped Drain) may be formed by a known method.

  Thereafter, after forming an insulating film (not shown) containing hydrogen, the semiconductor region is hydrogenated by heating to 400 to 550 ° C. to terminate dangling bonds in the semiconductor region.

  Next, as shown in FIG. 4C, an inorganic material (silicon oxide, silicon nitride, silicon oxynitride, or the like) or an organic material (polyimide, acrylic, polyamide, polyimideamide, benzocyclobutene, or siloxane polymer) is mainly used. An interlayer insulating film 322 is formed using raw materials as components.

Next, as illustrated in FIG. 4D, a part of the interlayer insulating film and the insulating film is etched using a resist mask to expose the impurity regions, thereby forming contact holes.
By this step, the metal compound 321 moved to the impurity region is exposed.

  Next, the CNT 331 is formed using the metal compound as a catalyst by using the process as in the second embodiment. Next, as shown in FIG. 4E, a first conductive film 341 is formed.

Next, as shown in FIG. 4F, after the first conductive film is fluidized using a process as in the second embodiment or the third embodiment, the first conductive film is formed between the CNTs 331. Fill with. Thereafter, the first conductive film is etched into a desired shape using a resist mask to form a conductive member 351 that fills the contact hole with the CNT 331 and the conductive film.

    In addition, a CMOS circuit can be manufactured by complementarily combining the obtained n-channel TFT and p-channel TFT. In this case, in order to control the threshold voltage of the TFT, it is desirable to make a depletion type TFT and an enhancement type TFT separately by doping a small amount of phosphorus or boron into a semiconductor region which becomes a channel formation region in advance. For example, an n-channel depletion type TFT may be doped with a small amount of phosphorus, and a p-channel type depletion type TFT may be doped with a small amount of boron.

  According to the present invention, vias (conductive members) formed of ultrafine carbon fibers and a conductive layer filling between the fine carbon fibers can be formed in the contact holes on the wiring. Therefore, the via (conductive member) has a fine structure and can be connected to a finely processed wiring, so that a circuit in which semiconductor elements having the via are highly integrated can be formed. In addition, since the via formed in the contact hole is filled with the conductive film, the connection area with the wiring can be increased, and the wiring can be connected with high reliability. Thus, a semiconductor device can be manufactured with high yield.

In this embodiment, a manufacturing process of a semiconductor element formed using the present invention and an active matrix substrate having the semiconductor element will be described with reference to FIGS. In this embodiment, a process of forming a conductive member by a method that does not require a high temperature treatment and a vacuum apparatus is shown. Note that in this embodiment, a thin film transistor is used as a typical example of a semiconductor element, but an organic thin film transistor, a thin film diode, a photoelectric conversion element, a resistor, and the like can also be used as a semiconductor element.

As shown in FIG. 5A, a base insulating film 402 is formed over a substrate 401. The size of the substrate is arbitrary but 600 mm × 720 mm, 680 mm × 880 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm, 1500 mm × 1800 mm, 1800 mm × 2000 mm, 2000 mm × 2100 mm, 2200 mm × 2600 mm, or 2600 mm × 3100 mm Such a large area substrate can be used. In this embodiment, a glass substrate is used. In addition, the base insulating film has a two-layer structure, and the first silicon oxynitride film formed using SiH ₄ , NH ₃ , and N ₂ O as a reaction gas reacts with 50 to 100 nm, SiH ₄ , and N ₂ O react. A second silicon oxynitride film formed as a gas is formed in a thickness of 100 to 1
Laminate to a thickness of 50 nm.

  Next, an amorphous silicon film is formed over the base insulating film by a known method such as a plasma CVD method, a low pressure CVD method, or a sputtering method, and heat treatment is performed for crystallization. In this case, in crystallization, silicide is formed in a portion of the semiconductor film in contact with a metal element that promotes crystallization of the semiconductor, and crystallization proceeds using the silicide as a nucleus. Here, after heat treatment for dehydrogenation (450 ° C., 1 hour), heat treatment for crystallization (500 ° C. to 650 ° C. for 1 to 24 hours) is performed.

  Thereafter, gettering of the metal element is performed from the crystalline silicon film by a known method, and the metal element in the crystalline silicon film is removed or the concentration is reduced. Next, it is preferable to irradiate the crystalline silicon film with a laser beam in order to increase the crystallization rate (the ratio of the crystal component in the entire volume of the film) and repair defects remaining in the crystal grains.

  Next, a TFT is formed by a known method using a crystalline silicon film. The crystalline silicon film is etched into a desired shape to form semiconductor regions 403a and 403b. 403a is an n-channel TFT semiconductor region, and 403b is a p-channel TFT semiconductor region. Next, after the surface of the crystalline silicon film is washed with an etchant containing hydrofluoric acid, an insulating film containing silicon as a main component and serving as the gate insulating film 404 is formed.

    Next, a known conductive film is formed and etched into a desired shape to form gate electrodes 405a and 405b. The gate electrode can have a single layer structure or a multilayer structure. The material of the gate electrode was selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), and neodymium (Nd). It can be formed of an element or an alloy material or a compound material containing these elements as main components. Alternatively, a silver-copper-palladium alloy (AgPdCu alloy) may be used.

Next, an n-type TFT is added by appropriately adding an impurity element imparting n-type (P, As, etc.) and an impurity element imparting P-type (B, etc.), here phosphorus and boron, to the semiconductor regions 403a and 403b. Source and drain regions 406a, and p-channel TFT source and drain regions 406b are formed.
Next, after a second insulating film (not shown) is formed over the substrate, heat treatment or intense light irradiation is performed to activate the added impurity element. This step can recover plasma damage to the gate insulating film and plasma damage to the interface between the gate insulating film and the semiconductor film simultaneously with activation.

  Next, an insulating film to be an interlayer insulating film is formed on the second insulating film. In this embodiment, a siloxane polymer is applied and baked, and a skeleton structure is formed by the bond of silicon (Si) and oxygen (O), and the substituent includes at least hydrogen, or the substituent includes fluorine and an alkyl group. Or an interlayer insulating film formed of a material having at least one of aromatic hydrocarbons. By using this material, an interlayer insulating film having heat resistance and flatness can be formed. In addition to this material, an organic material such as acrylic, polyimide, or polysilazane, or an inorganic material such as silicon oxide, silicon nitride oxide, or silicon oxynitride can be used. When an interlayer insulating film is formed of a photosensitive organic material as an organic material, since there is a contact hole having a curvature, there is an effect that the coverage (coverage) of electrodes to be formed later is increased.

Next, after applying a photoresist on the interlayer insulating film, resist masks 408a to 408e are formed by a known photolithography process. Thereafter, the regions not covered with the resist masks 408a to 408e are etched to form contact holes.
There is no limitation on the etching gas used in this etching step, but CF ₄ , O ₂ , He, and Ar are suitable here. Dry etching is performed with a CF ₄ flow rate of 380 sccm, an O ₂ flow rate of 290 sccm, a He flow rate of 500 sccm, an Ar flow rate of 500 sccm, an RF power of 3000 W, and a pressure of 25 Pa. In order to perform etching without leaving a residue on the semiconductor region, it is preferable to increase the etching time at a rate of about 10 to 20%. A taper shape may be formed by one etching, or a taper shape may be formed by a plurality of etchings. Here, CF ₄ , O ₂ and He are further used, the flow rate of CF ₄ is 550 sccm, the flow rate of O ₂ is 450 sccm, the flow rate of He is 350 sccm, R
The F power is 3000 W, the pressure is 25 Pa, and the second dry etching is performed to obtain a tapered shape.

  Next, as shown in FIG. 4B, a blocking film 411 is formed over the entire surface of the interlayer insulating film and the contact hole. This blocking film is for preventing a metal element such as aluminum or copper from penetrating into the semiconductor region when the first conductive film to be formed later is reflow-processed. The laminated structure of the titanium film and the titanium nitride film is preferable. Next, a first conductive film 412 is formed over the substrate by a known method such as a sputtering method or a CVD method. In this embodiment, a conductive film formed of nickel element is formed.

Next, as illustrated in FIG. 4C, part of the first conductive film 412 is removed by a lift-off method, so that a region 421 containing a metal element is formed. Next, the CNT 422 is formed. Here, a plasma CVD method using atmospheric pressure discharge is used. Specifically, the electric field is pulsed, the rising voltage is 10 μs or less, the electric field strength is 1 to 100 kV / cm, methane is used as the source gas, and this is diluted with hydrogen and helium to form CNTs.

  Next, a second conductive film 423 is formed. Here, an aluminum-germanium alloy is formed. Thereafter, the aluminum-germanium alloy flows into the contact holes by heating to 400 to 550 degrees. For this reason, the space between the CNTs 422 is filled with an aluminum-germanium alloy.

  Next, the second conductive film 423 is etched into a desired shape to form conductive members 431 and 432 as shown in FIG.

  In the present embodiment, the fourth embodiment has been described, but the first to third embodiments can also be used.

    According to the present invention, vias (conductive members) formed of ultrafine carbon fibers and a conductive layer filling between the fine carbon fibers can be formed in the contact holes on the wiring. Therefore, the via (conductive member) has a fine structure and can be connected to a finely processed wiring, so that a circuit in which semiconductor elements having the via are highly integrated can be formed. In addition, since the via formed in the contact hole is filled with the conductive film, the connection area with the wiring can be increased, and the wiring can be connected with high reliability. Thus, a semiconductor device can be manufactured with high yield. In addition, since CNTs can be formed under atmospheric pressure, an active matrix substrate having a large area can be manufactured, and throughput can be improved.

  In this embodiment, a process for manufacturing a MOS transistor using the present invention will be described with reference to FIGS. Note that the MOS transistor is formed using a single crystal silicon substrate or a compound semiconductor substrate. Typically, an N-type or P-type single crystal silicon substrate, a GaAs substrate, an InP substrate, a GaN substrate, a SiC substrate, It is a sapphire substrate or a ZnSe substrate.

  As shown in FIG. 6A, a p-type semiconductor substrate 601 made of, for example, single crystal silicon is prepared, and after forming a p-type well 602 and an n-type well 603 on the semiconductor substrate, a surface of the semiconductor substrate 601 is formed. The selective region is thermally oxidized to form a blocking isolation field insulating film 604 made of a silicon oxide film having a LOCOS (Local Oxidation of Silicon) structure.

  Next, the surface of the semiconductor substrate 601 is thermally oxidized to form a thin silicon oxide film (gate insulating film) having a thickness of about 50 nm or less, and a polycrystalline film having a thickness of about 300 nm is formed on the silicon oxide using a CVD method. A silicon film is deposited.

  Next, after applying a resist over the semiconductor substrate 601, exposure and development are performed using a photomask to form a gate electrode-shaped resist mask. Next, the polycrystalline silicon film is etched by dry etching using a resist mask to form gate electrodes 607 and 608.

  Next, an n-type semiconductor region 609 serving as a source and a drain is formed by ion-implanting an n-type impurity element such as phosphorus into the p-type well 602 on the semiconductor substrate 601. Further, a p-type semiconductor region 610 serving as a source and a drain is formed by ion implantation of a p-type impurity such as boron into the n-type well 603 of the semiconductor substrate 601.

Next, as illustrated in FIG. 6B, the silicon oxide film formed over the n-type semiconductor region 609 and the p-type semiconductor region 610 to be a source and a drain is removed, and a gate insulating film 605, 606 is formed.
Next, after forming an insulating film and planarizing the film, an interlayer insulating film 611 is formed. Note that an SiOx film formed by spin coating, a PSG (phosphorus silicate glass) film, a BSG (boron silicate glass) film or a BPSG (boron phosphorus silicate glass) film, an insulating film using a siloxane polymer, If an SOG (Spin on Glass) film such as the above is used, the planarization step is not necessary.

  Next, part of the interlayer insulating film 611 is etched to expose part of the n-type semiconductor region 609 and the p-type semiconductor region 610 to form contact holes.

  Next, a blocking film (not shown) is formed in the same manner as in Example 1. After that, as shown in FIG. 6B, a first conductive film 621 is formed. Here, a thin film formed of nickel element is formed as the first conductive film. After that, a part of the first conductive film is removed to form island-shaped metal element regions 631 and 632. Next, CNTs 633 and 634 are formed by a thermal CVD method by heating to 800 to 1100 degrees in an atmosphere containing acetylene.

  Next, a second conductive film 635 is formed as illustrated in FIG. Here, an aluminum-germanium film is formed as the second conductive film 635. Then, it heats at 400-550 degree | times and is made to fluidize, and the inside of a contact hole is filled with an aluminum-germanium film | membrane. By this step, the gap between the CNTs 633 and 634 is filled with the conductive film.

  Next, as shown in FIG. 6D, conductive members 641 and 642 are formed by etching back the second conductive film.

    In the present embodiment, the second embodiment has been described, but the first, third, or fourth embodiment can also be used.

    According to the present invention, vias (conductive members) formed of ultrafine carbon fibers and a conductive layer filling them can be formed in contact holes on the wiring. Since the via is filled with the conductive film, the connection area with the wiring can be increased, and the wiring can be connected with high reliability. Therefore, a semiconductor device can be manufactured with high yield. In addition, a via (conductive member) has a fine structure and can connect a finely processed wiring. Therefore, a circuit in which a semiconductor element having the via is highly integrated, typically a signal line driver circuit, a controller, A semiconductor device such as a CPU, a converter of a sound processing circuit, a power supply circuit, a transmission / reception circuit, a memory, an amplifier of a sound processing circuit can be formed. In addition, circuits that constitute a single system (functional circuit), such as an MPU (microcomputer), memory, and I / O interface, are monolithically mounted, enabling high speed, high reliability, and low power consumption. An on-chip can be formed.

In this embodiment, an example of a semiconductor device having a multilayer wiring structure in which wirings formed on different layers are connected by a conductive member formed by selectively formed CNTs and a conductive film filling them. Is shown in FIG.
By the process shown in Embodiment 1, an n-channel TFT 435 and a p-channel TFT 436 are formed on the substrate 401. In these TFTs, conductive members 431 and 432 connected to a semiconductor region are formed of CNTs and a conductive film that fills them.

    A second interlayer insulating film 701 is formed on the first interlayer insulating film 407 and the conductive members 431 and 432. The second interlayer insulating film 701 can be formed using a material similar to that of the first interlayer insulating film 407. Next, after etching a part of the second interlayer insulating film to open a contact hole, conductive members 702 and 703 to be vias are formed in the steps shown in the second to fourth embodiments. To do. Here, the conductive members 702 and 703 serving as vias have the structures shown in FIG. 1A of the first embodiment.

Next, a third interlayer insulating film 704 is formed. Thereafter, a part of the second interlayer insulating film 701 and the third interlayer insulating film 704 are etched to open a part of the contact hole. Thereafter, the conductive member 705 to be a via is formed by any one of the steps of the second embodiment to the fourth embodiment. Next, a wiring 706 is formed on the third interlayer insulating film 704. Thereafter, after forming a fourth interlayer insulating film 707, a part of the fourth interlayer insulating film 707 is etched to expose a part of the wiring 706 to form a contact hole. A conductive member 708 to be a via and a fifth interlayer insulating film 709 are formed.
In this embodiment, the conductive member whose surface is not flattened and polished is shown. However, the present invention is not limited to this structure, and the conductive member having a structure with a flattened surface as shown in FIG. A sex member can also be formed.

      In this embodiment, a multilayer semiconductor device having TFTs formed on a glass substrate is shown. However, the present invention is not limited to this, and the present invention can be applied to a semiconductor device having a MOS transistor using a single crystal semiconductor substrate. it can.

        According to the present invention, vias (conductive members) formed of ultrafine carbon fibers and a conductive layer filling between them can be formed in contact holes on the wiring. For this reason, the connection area with the wiring can be increased, and the wiring can be connected with high reliability. Thus, a semiconductor device can be manufactured with high yield. In addition, since the via (conductive member) has a fine structure and can be connected to a finely processed wiring, a circuit in which semiconductor elements having the via are highly integrated can be formed. Furthermore, by making the vias of the multilayer wiring have a fine structure, further integration of elements can be achieved.

In this embodiment, a package which is an example of a semiconductor device formed using the present invention will be described with reference to FIGS. FIG. 8A is a perspective view showing a cross-sectional structure of a package in which a chip is connected to an interposer by a wire bonding method. 1801 is an interposer, 1802 is a chip, and 1803 is a mold resin layer. The chip 1802 is mounted on the interposer 1801 with a mounting adhesive 1804.

      An interposer 1801 shown in FIG. 8A is a ball grid array type in which solder balls 1805 are provided. The solder ball 1805 is provided on the side opposite to the side where the chip 1802 of the interposer 1801 is mounted. A wiring 1806 provided in the interposer 1801 is electrically connected to the solder ball 1805 through a contact hole provided in the interposer 1805.

      In this embodiment, the wiring 1806 for electrically connecting the chip 1802 and the solder ball 1805 is provided on the surface of the interposer 1805 on which the chip is mounted. It is not limited to. For example, the wiring may be provided in multiple layers inside the interposer.

      In FIG. 8A, the chip 1802 and the wiring 1806 are electrically connected by a wire 1807. FIG. 8B shows a cross-sectional view of the package shown in FIG. The chip 1802 is provided with the semiconductor element 1809 shown in Embodiment 1 or 2, and a pad 1808 is provided on the side of the chip 1802 opposite to the side where the interposer 1801 is provided. The pad 1808 is electrically connected to the semiconductor element 1809. The pad 1808 is connected to a wiring 1806 provided in the interposer 1801 by a wire 1807.

      Reference numeral 1810 corresponds to a part of the printed wiring board, and 1811 corresponds to wirings or electrodes provided on the printed wiring board 1810. The wiring 1806 is connected to a wiring or electrode 1811 provided on the printed wiring board 1810 via a solder ball 1805. Note that various methods such as thermocompression bonding, thermocompression bonding with ultrasonic vibration, and the like can be used for connection between the solder ball 1805 and the wiring or the electrode 1811. It is also possible to fill the gaps between the solder balls after crimping with an underfill to increase the mechanical strength of the connection part and the efficiency of diffusion of heat generated in the package. Underfill is not necessarily used, but it can prevent poor connection due to stress caused by mismatch between thermal expansion coefficients of the interposer and the chip. When crimping with ultrasonic waves applied, poor connection can be suppressed compared to simply thermocompression bonding.

      In this embodiment, the package in which the chip is connected to the interposer by the wire bonding method is shown, but the present invention is not limited to this. These may be connected using a flip chip method. In this case, even if the number of pads to be connected is increased, a relatively wide pitch between pads can be secured as compared with the wire bonding method, which is suitable for connecting chips having a large number of terminals.

      Further, chips may be stacked in the package. In this case, since a plurality of chips can be provided in one package, there is an advantage that the size of the entire package can be suppressed.

      Furthermore, a plurality of packages may be stacked. This structure has the advantage that the yield can be increased because electrical inspection can be performed for each package and only good products can be selected and stacked.

      According to the present invention, a highly integrated semiconductor device with high yield can be manufactured.

    Various electronic devices can be manufactured by incorporating a semiconductor device obtained by implementing the present invention. Electronic devices include video cameras, digital cameras, goggles-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, audio components, etc.), notebook-type personal computers, game devices, and personal digital assistants (mobile A computer, a mobile phone, a portable game machine, an electronic book, or the like), an image playback device (specifically, Digital Versatile Disc (DVD)) provided with a recording medium, and the image can be displayed. Equipment with a display). A cellular phone which is one of the electronic devices is taken as an example, and FIG. 9A shows a state where a package which is one of the semiconductor devices of the present invention is actually mounted on the electronic device.

      The cellular phone module shown in FIG. 9A includes a printed wiring board 816, a CPU 802, a power supply circuit 803, a controller 801, a transmission / reception circuit 831, a memory 811, a sound processing circuit 829, and other resistors, buffers, capacitors. Elements such as elements are mounted. A panel 800 is mounted on the printed wiring board 816 by the FPC 808. The panel 800 includes a pixel portion 805 in which a light-emitting element or a liquid crystal display device is provided in each pixel, a scanning line driver circuit 806 for selecting a pixel included in the pixel portion 805, and a video signal to the selected pixel. A signal line driver circuit 807 to be supplied is provided.

      The power supply voltage to the printed circuit board 816 and various signals input from a keyboard or the like are supplied via a printed circuit board interface (I / F) 809 on which a plurality of input terminals are arranged. An antenna port 810 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 816.

      In this embodiment, the printed wiring board 816 is mounted on the panel 800 using the FPC, but it is not necessarily limited to this configuration. The controller 801, the audio processing circuit 829, the memory 811, the CPU 802, or the power supply circuit 803 may be directly mounted on the panel 800 by using a COG (Chip on Glass) method.

      Further, in the printed wiring board 816, noise may occur in the power supply voltage or the signal, or the rise of the signal may be slow due to the capacitance formed between the drawn wirings or the resistance of the wiring itself. Therefore, by providing various elements such as a capacitor and a buffer on the printed wiring board 816, it is possible to prevent noise from being applied to the power supply voltage and the signal and the rise of the signal from being slowed down.

      FIG. 9B shows a block diagram of the module shown in FIG.

      In this embodiment, the memory 811 includes a VRAM 832, a DRAM 825, a flash memory 826, and the like. The VRAM 832 stores image data to be displayed on the panel, the DRAM 825 stores image data or audio data, and the flash memory stores various programs. As the memory capacity increases, the mounting area also increases. For this reason, the memory is preferably manufactured using a single crystal silicon wafer.

      The power supply circuit 803 generates power supply voltages for the panel 800, the controller 801, the CPU 802, the sound processing circuit 829, the memory 811, and the transmission / reception circuit 831. Depending on the panel specifications, the power supply circuit 803 may be provided with a current source. The power supply circuit has a function of stably controlling the current supplied to the panel, controller, CPU, and the like. As an element for this purpose, a bipolar transistor capable of flowing a large amount of current is suitable. As a result, it is preferable that the power supply circuit is manufactured using a single crystal silicon wafer.

      The CPU 802 includes a control signal generation circuit 820, a decoder 821, a register 822, an arithmetic circuit 823, a RAM 824, an interface 835 for the CPU, and the like. Various signals input to the CPU 802 through the interface 835 are once held in the register 822 and then input to the arithmetic circuit 823, the decoder 821, and the like. The arithmetic circuit 823 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 821 is decoded and input to the control signal generation circuit 820. The control signal generation circuit 820 generates a signal including various instructions based on the input signal, and a location specified in the arithmetic circuit 823, specifically, a memory 811, a transmission / reception circuit 831, an audio processing circuit 829, a controller 801. Send to etc. The CPU can be thinned by manufacturing a TFT using a crystalline semiconductor film in a semiconductor region.

      The memory 811, the transmission / reception circuit 831, the audio processing circuit 829, and the controller 801 operate according to the received commands. The operation will be briefly described below.

      A signal input from the keyboard 804 is sent to the CPU 802 mounted on the printed wiring board 816 via the interface 809. The control signal generation circuit 820 converts the image data stored in the VRAM 832 into a predetermined format according to the signal sent from the keyboard 804 and sends it to the controller 801.

The controller 801 performs data processing on a signal including image data sent from the CPU 802 in accordance with the panel specifications, and supplies the processed signal to the panel 800. Further, the controller 801 generates an Hsync signal, a Vsync signal, a clock signal CLK, and an AC voltage (AC Cont) based on the power supply voltage input from the power supply circuit 803 and various signals input from the CPU. Supply to panel 800. The controller can be made of a TFT using a crystalline semiconductor film in the semiconductor region.

      The transmission / reception circuit 831 processes signals transmitted / received as radio waves in the antenna 833. Specifically, an isolator, a band-pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, a balun, and the like Includes high frequency circuit. Of the signals transmitted and received in the transmission / reception circuit 831, a signal including audio information is sent to the audio processing circuit 829 in accordance with a command from the CPU 802. Since the transmission / reception circuit includes a high-frequency circuit, it is made of a GaAs semiconductor substrate or a silicon wafer.

      A signal including audio information sent in accordance with a command from the CPU 802 is demodulated into an audio signal by the audio processing circuit 829 and sent to the speaker 828. The audio signal sent from the microphone 827 is modulated in the audio processing circuit 829 and sent to the transmission / reception circuit 831 in accordance with a command from the CPU 802. The audio processing circuit is composed of an amplifier and a converter. Since the variation in amplifier characteristics becomes conspicuous with respect to the sound quality output from the speaker, it is preferable to manufacture the amplifier with a silicon wafer with little variation. On the other hand, the converter can be manufactured with a TFT using a crystalline semiconductor film for a semiconductor region, and can be thinned.

      According to the present invention, an electronic device including a highly integrated semiconductor device can be manufactured. For this reason, the number of mounted components can be reduced, and the electronic device can be downsized.

Sectional drawing explaining the electroconductive member which concerns on this invention. Sectional drawing explaining the manufacturing process of the electroconductive member which concerns on this invention. Sectional drawing explaining the manufacturing process of the electroconductive member which concerns on this invention. Sectional drawing explaining the manufacturing process of the electroconductive member which concerns on this invention Sectional drawing explaining the manufacturing process of TFT which concerns on this invention. Sectional drawing explaining the manufacturing process of the MOS transistor which concerns on this invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device having a multilayer structure according to the present invention. FIG. 14 is a cross-sectional view illustrating a semiconductor device according to the invention. FIG. 14 is a cross-sectional view illustrating an electronic device according to the invention.

Claims (7)

Form a base film on the substrate,
Forming an amorphous semiconductor film on the base film;
A crystalline semiconductor film is formed by adding a metal element to the amorphous semiconductor film and heating the amorphous semiconductor film.
Etching the crystalline semiconductor film to form a semiconductor region;
Forming an insulating film covering the semiconductor region;
Forming a first conductive layer overlying a part of the semiconductor region on the insulating film;
Doping an impurity element into the semiconductor region using the first conductive layer as a mask to form a channel formation region overlapping with the first conductive layer, a source region and a drain region doped with the impurity element,
By performing heat treatment, the impurity element is activated, the metal element becomes a metal compound, and the metal compound in the channel formation region is moved to the source region or the drain region,
Forming an interlayer insulating film on the insulating film and the first conductive layer;
Etching part of the insulating film and the interlayer insulating film to form a contact hole reaching the source region or the drain region, exposing the metal compound moved to the source region or the drain region,
Forming ultrafine carbon fibers on the metal compound;
A second conductive layer is formed on the source or drain region and the interlayer insulating film exposed in the contact hole, and the second conductive layer is filled between the ultrafine carbon fibers by heating. A method for manufacturing a semiconductor device, wherein a conductive member is formed. In claim 1,
The method for manufacturing a semiconductor device, wherein the metal compound moved to the source region or the drain region is segregated on a surface of the source region or the drain region. In claim 1 or 2,
The method for manufacturing a semiconductor device, wherein the metal element is nickel, iron, cobalt, platinum, palladium, or titanium. In claim 1 or 2,
The method for manufacturing a semiconductor device, wherein the metal compound is nickel silicide, iron silicide, cobalt silicide, platinum silicide, palladium silicide, or titanium silicide. In any one of Claims 1 thru | or 4,
A method for manufacturing a semiconductor device, wherein the ultrafine carbon fiber is formed using a hydrocarbon or an alcohol. In any one of Claims 1 thru | or 5,
The method for manufacturing a semiconductor device, wherein the ultrafine carbon fiber is graphite nanofiber, carbon nanofiber, carbon nanotube, tube-like graphite, carbon nanocone, or cone-like graphite. In any one of Claims 1 thru | or 6,
The method for manufacturing a semiconductor device, wherein the second conductive layer is aluminum, an alloy containing aluminum, copper, or a crystalline semiconductor film to which an impurity is added.

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