JP4672753B2 - GaN-based nitride semiconductor free-standing substrate manufacturing method - Google Patents

GaN-based nitride semiconductor free-standing substrate manufacturing method Download PDF

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JP4672753B2
JP4672753B2 JP2008131183A JP2008131183A JP4672753B2 JP 4672753 B2 JP4672753 B2 JP 4672753B2 JP 2008131183 A JP2008131183 A JP 2008131183A JP 2008131183 A JP2008131183 A JP 2008131183A JP 4672753 B2 JP4672753 B2 JP 4672753B2
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隆文 八百
明煥 ▲チョ▼
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Description

本発明は、GaN系窒化物半導体自立基板の作製方法に関する。   The present invention relates to a method for manufacturing a GaN-based nitride semiconductor free-standing substrate.

青色、紫外線高出力レーザーダイオード、高輝度LED、高出力電子デバイスを実現するために窒化物半導体をベースにした素子の高性能化が進んでいる。現在、GaN系の光又は電子素子の製作において、結晶成長用基板としてサファイア基板が主に使われている。   In order to realize blue, ultraviolet high-power laser diodes, high-brightness LEDs, and high-power electronic devices, the performance of elements based on nitride semiconductors is increasing. Currently, sapphire substrates are mainly used as crystal growth substrates in the production of GaN-based optical or electronic devices.

しかし、サファイア基板の場合は、基板とGaN系窒化物半導体との間に大きい格子不整合と熱膨張係数の差によって、転位密度(dislocation density)が1010/cm程度となる。そしてこの大きい欠陥密度のために素子特性劣化等の問題がある。
転位密度を減少させるために多様なバッファ層を使い、LEO(lateral epitaxial overgrowth)、PENDEOエピタシーなどの選択成長や横方向成長技術を用いて低欠陥薄膜成長が可能になった。
However, in the case of a sapphire substrate, the dislocation density is about 10 10 / cm 2 due to a large lattice mismatch and a difference in thermal expansion coefficient between the substrate and the GaN-based nitride semiconductor. This large defect density causes problems such as deterioration of device characteristics.
Various buffer layers were used to reduce the dislocation density, and low-defect thin film growth became possible using selective growth such as LEO (lateral epitaxial overgrowth) and PENDEO epitaxy and lateral growth techniques.

しかし、このような成長技術は、成長前に多数プロセスによる基板製作工程が必要なことから生産単価を増加させる原因になり、また再現性と収率にも問題がある。基板からの結晶欠陥の問題を解決する対策を求めて、GaN基板に関する研究が進められている。素子の高性能化及び信頼性を確保するためには良質な単結晶膜の実現は必須条件である。   However, such a growth technique causes a production unit cost to increase because a substrate manufacturing process by a large number of processes is necessary before the growth, and there is a problem in reproducibility and yield. Research on a GaN substrate is underway in search of measures to solve the problem of crystal defects from the substrate. In order to ensure high performance and reliability of the element, it is essential to realize a high-quality single crystal film.

現実的に大口径GaNバルク成長は不可能であり、代わりに時間当たり数百ミクロンの高速成長速度を持つHVPE(Hydride Vapor Phase Epitaxy)法を用いたGaN系窒化物半導体自立基板が実用化されている。この方法はサファイア基板上に300ミクロン以上の厚膜GaN系窒化物半導体を成長した後、サファイア基板から厚膜GaN系窒化物半導体を分離するものである。   In reality, large-diameter GaN bulk growth is impossible. Instead, a GaN-based nitride semiconductor free-standing substrate using the HVPE (Hydride Vapor Phase Epitaxy) method with a high growth rate of several hundred microns per hour has been put into practical use. Yes. In this method, after a thick GaN-based nitride semiconductor having a thickness of 300 microns or more is grown on a sapphire substrate, the thick GaN-based nitride semiconductor is separated from the sapphire substrate.

薄膜の欠陥密度に非常に敏感な青紫色レーザーダイオードの場合、実用的にはこのようなGaN系窒化物半導体自立基板上に素子作製が行われている。今後、巨大な市場を持っている照明用高輝度LEDの場合もレーザーダイオードと同じ素子を動作させるためには高電流密度と素子信頼性を優先的に要求する状況となっている。   In the case of a blue-violet laser diode that is very sensitive to the defect density of the thin film, devices are practically produced on such a GaN-based nitride semiconductor free-standing substrate. In the future, even in the case of high-intensity LEDs for illumination having a huge market, in order to operate the same element as the laser diode, a high current density and element reliability are preferentially required.

良質なGaN系窒化物半導体自立基板を実現するために多様な方法が提案されている。自立基板を実現するには重要な二つの技術があり、これらはサファイア基板上にクラック及び反りが少ない厚膜GaN系窒化物半導体自立基板成長技術と成長後厚膜GaN系窒化物半導体をサファイア基板から分離するリフトオフプロセス技術である。サファイア基板上にクラック及び反りがない厚膜成長に成功しても、サファイア基板と厚膜GaN系窒化物半導体の界面には巨大なストレスが存在する。   Various methods have been proposed to realize a high-quality GaN-based nitride semiconductor free-standing substrate. There are two technologies that are important for realizing a free-standing substrate. These include a thick-film GaN-based nitride semiconductor free-standing substrate growth technology and a post-growth thick-film GaN-based nitride semiconductor on a sapphire substrate. Lift-off process technology that separates from Even if the thick film growth without cracks and warpage is successful on the sapphire substrate, a huge stress exists at the interface between the sapphire substrate and the thick film GaN-based nitride semiconductor.

一般的な機械研磨方法を用いてサファイア基板を除去する場合、界面に存在するストレスの緩和によって厚膜GaN系窒化物半導体の結晶内部にクラックが発生し易い。また、サファイア基板の除去後、表面研磨などのプロセスにも問題がある。   When the sapphire substrate is removed using a general mechanical polishing method, cracks are likely to occur inside the crystal of the thick GaN-based nitride semiconductor due to the relaxation of the stress present at the interface. In addition, after removing the sapphire substrate, there is also a problem in processes such as surface polishing.

このためサファイア基板を分離する色々なリフトオフ技術が提案されている。代表的な分離技術としては、レーザーリフトオフ技術、VAS(Void Assisted Separation)、エッチング技術が知られている。   For this reason, various lift-off techniques for separating the sapphire substrate have been proposed. As typical separation techniques, laser lift-off technique, VAS (Void Assisted Separation), and etching technique are known.

レーザーリフトオフ技術は、高出力レーザー照射による界面からの吸収によって基板を分離させるものであるが、大口径自立基板の作製は難しい。またVAS技術は、自然剥離現象に基づいて行うものあるが、GaNテンプレートの準備、金属層の蒸着などの複雑な工程を要求している。   Laser lift-off technology separates a substrate by absorption from an interface caused by high-power laser irradiation, but it is difficult to produce a large-diameter self-standing substrate. The VAS technique is based on the natural peeling phenomenon, but requires complicated processes such as preparation of a GaN template and vapor deposition of a metal layer.

GaAs基板上に厚膜GaNを成長してGaAs基板を化学エッチングにより除去する方法もあるが、高温成長中にGaAs基板の分解、界面での相互拡散などの問題があり、特別な成長技術が必要である。このような作製工程の複雑性と歩留まりの問題があるため汎用的に使われていない。
以上纏めると従来のGaN系の自立基板は複雑なプロセスによって、低歩留まりと高価という大きな問題がある。
特開2005−1928号公報 特開2005−119921号公報 特開2006−173147号公報 特表2006−527480号公報 特開2008−74671号公報
Although there is a method of growing thick GaN on a GaAs substrate and removing the GaAs substrate by chemical etching, there are problems such as decomposition of the GaAs substrate and interdiffusion at the interface during high temperature growth, and special growth techniques are required. It is. Due to the complexity of the manufacturing process and the problem of yield, it is not used for general purposes.
In summary, the conventional GaN-based free-standing substrate has a large problem of low yield and high cost due to a complicated process.
Japanese Patent Laid-Open No. 2005-1928 Japanese Patent Laid-Open No. 2005-119921 JP 2006-173147 A JP-T-2006-527480 JP 2008-74671 A

本発明は、簡単な工程により、安価でストレスフリーなGaN系窒化物半導体自立基板の作製方法を提供することを課題とする。   An object of the present invention is to provide an inexpensive and stress-free method for manufacturing a GaN-based nitride semiconductor free-standing substrate by a simple process.

(1)基板を準備する工程と、該基板上にGaNドット及びNHCl層を形成する工程と、GaNドット及びNHCl層上にIII-V族窒化物半導体からなる低温バッファ層を形成する工程と、低温バッファ層上にGaN系窒化物半導体層を形成する工程と、基板温度を常温に戻すことによりGaN系窒化物半導体層を基板より自然剥離させる工程とを含む、GaN系窒化物半導体自立基板の作製方法。
(2)上記基板は、サファイア基板であることを特徴とする(1)に記載のGaN系窒化物半導体自立基板の作製方法。
(3)上記基板上にGaNドット及びNHCl層を形成する工程の前に、基板表面を窒化しAlN1−X(0<X≦1)を局部的に形成する工程を含むことを特徴とする(2)に記載のGaN系窒化物半導体自立基板の作製方法。
(4)上記GaNドット及びNHCl層を形成する工程は、Gaガス雰囲気中でHCl及びNHをフローすることによりGaNドット及びNHCl層を形成する工程であることを特徴とする(1)乃至(3)のいずれかに記載のGaN系窒化物半導体自立基板の作製方法。
(5)上記GaNドットは、c軸方向に揃えられていることを特徴とする(1)乃至(4)のいずれかに記載のGaN系窒化物半導体自立基板の作製方法。
(6)上記低温バッファ層は、GaN、AlN、InN、BN、及びこれらの混晶半導体のうちのいずれかを構成材料とする層であることを特徴とする(1)乃至(5)のいずれかに記載のGaN系窒化物半導体自立基板の作製方法。
(7)上記低温バッファ層は、400℃以上800℃以下の温度で形成することを特徴とする(1)乃至(6)のいずれかに記載のGaN系窒化物半導体自立基板の作製方法。
(8)上記各工程は、単一のHVPE装置内で連続して行うことを特徴とする(1)乃至(7)のいずれかに記載のGaN系窒化物半導体自立基板の作製方法。
(1) forming a step of preparing a substrate, forming a GaN dot and NH 4 Cl layer on the substrate, a low temperature buffer layer made of a group III-V nitride semiconductor on the GaN dots and NH 4 Cl layer A step of forming a GaN-based nitride semiconductor layer on the low-temperature buffer layer, and a step of naturally peeling the GaN-based nitride semiconductor layer from the substrate by returning the substrate temperature to room temperature. A method for manufacturing a semiconductor free-standing substrate.
(2) The method for producing a GaN-based nitride semiconductor free-standing substrate according to (1), wherein the substrate is a sapphire substrate.
(3) including a step of nitriding the substrate surface and locally forming AlN X O 1-X (0 <X ≦ 1) before the step of forming the GaN dots and the NH 4 Cl layer on the substrate. (2) The manufacturing method of the GaN-based nitride semiconductor free-standing substrate according to (2).
(4) the step of forming the GaN dots and NH 4 Cl layer is characterized by a step of forming a GaN dot and NH 4 Cl layer by flow of HCl and NH 3 in Ga gas atmosphere ( 1) A method for manufacturing a GaN-based nitride semiconductor free-standing substrate according to any one of (3).
(5) The method for producing a GaN-based nitride semiconductor free-standing substrate according to any one of (1) to (4), wherein the GaN dots are aligned in the c-axis direction.
(6) The low-temperature buffer layer is a layer containing GaN, AlN, InN, BN, or any of these mixed crystal semiconductors as a constituent material. A method for producing a GaN-based nitride semiconductor free-standing substrate according to claim 1.
(7) The method for manufacturing a GaN-based nitride semiconductor free-standing substrate according to any one of (1) to (6), wherein the low-temperature buffer layer is formed at a temperature of 400 ° C. or higher and 800 ° C. or lower.
(8) The method for manufacturing a GaN-based nitride semiconductor free-standing substrate according to any one of (1) to (7), wherein each of the above steps is continuously performed in a single HVPE apparatus.

本発明によれば、NHCl層を用いることにより、安価でストレスフリーなGaN自立基板を作製することができる。 According to the present invention, an inexpensive and stress-free GaN free-standing substrate can be manufactured by using the NH 4 Cl layer.

本発明について、HVPE法を用いたGaN自立基板の作製方法を実施例として例示する。
本実施例では、次の1)から5)の工程を基本とする。
1)サファイア基板の高温窒化工程
2)NHCl層とGaNドット形成工程
3)低温GaNバッファ層の成長工程
4)高温厚膜GaN層の形成工程
5)GaN自立基板のセルフリフトオフ工程
そして本実施例では1)〜5)の工程を経て、c面成長したGaN自立基板が得られる。
以下上記1)〜5)の工程について詳細に説明する。
Regarding the present invention, a method for producing a GaN free-standing substrate using the HVPE method is illustrated as an example.
In this embodiment, the following steps 1) to 5) are basically used.
1) High-temperature nitridation process of sapphire substrate 2) NH 4 Cl layer and GaN dot formation process 3) Low-temperature GaN buffer layer growth process 4) High-temperature thick film GaN layer formation process 5) GaN free-standing substrate self-lift-off process and this implementation In the example, a c-plane-grown GaN free-standing substrate is obtained through the steps 1) to 5).
Hereinafter, the steps 1) to 5) will be described in detail.

1)サファイア基板の高温窒化工程
本工程は、HVPE反応炉でサファイア基板の高温窒化処理によってサファイア基板の表面に局部的に、AlN1−X(0<X≦1)を形成する工程である。
図1に、HVPE反応炉の中でサファイア基板をNHガス雰囲気で高温窒化処理によって局部的に形成されたAlN1−X(0<X≦1)の模式図を示す。AlN1−Xは次の工程で行われるGaNドット形成のシード層の役割を果たす。
1) High-temperature nitriding step of sapphire substrate This step is a step of forming AlN X O 1-X (0 <X ≦ 1) locally on the surface of the sapphire substrate by high-temperature nitriding treatment of the sapphire substrate in the HVPE reactor. is there.
FIG. 1 shows a schematic view of AlN X O 1-X (0 <X ≦ 1) in which an sapphire substrate is locally formed by high-temperature nitriding in an HVPE reactor in an NH 3 gas atmosphere. AlN X O 1-X serves as a seed layer for GaN dot formation performed in the next step.

NHの流量は、1L/min、基板温度は1080℃、窒化時間は30分間、キャリアガスとしては2.51L/minの水素を用いた。サファイア基板上に均一なAlN1−X(0<X≦1)層を形成するため窒化処理条件の最適化が必要である。本工程の窒化処理条件によってGaNドットの表面密度が決められ、最終的に自然セルフリフトオフ条件と緊密な関係を持つ。 The NH 3 flow rate was 1 L / min, the substrate temperature was 1080 ° C., the nitriding time was 30 minutes, and the carrier gas was 2.51 L / min hydrogen. In order to form a uniform AlN X O 1-X (0 <X ≦ 1) layer on the sapphire substrate, it is necessary to optimize nitriding conditions. The surface density of the GaN dots is determined by the nitriding conditions in this step, and finally has a close relationship with the natural self-lift-off conditions.

2)NHCl層とGaNドット形成工程
本工程は、工程1)により窒化処理したサファイア基板上にNHCl層とGaNドットを形成する工程である。図2に、形成されたGaNドット及びNHCl層を示す。本工程は、工程1)の窒化工程に連続して行われる。基板の温度を1080℃から500℃まで下げ、Gaボートの温度は450℃に設定した。
2) NH 4 Cl layer and GaN dot formation step This step is a step of forming an NH 4 Cl layer and a GaN dot on the sapphire substrate nitrided in step 1). FIG. 2 shows the formed GaN dots and the NH 4 Cl layer. This step is performed continuously to the nitriding step of step 1). The temperature of the substrate was lowered from 1080 ° C. to 500 ° C., and the temperature of the Ga boat was set to 450 ° C.

このような温度プロファイルは、HVPE反応炉の中で安定なガスフローを維持するためである。Gaボートを通過する大部のHClガスは、Gaと反応せず純粋なHClガス状態でサファイア基板表面上にNHガスと反応してNHCl層を形成する。しかし、一部のHClガスは少量のGaと反応してGaClを形成し、さらにサファイア基板の表面上でNHガスと反応してGaNを形成する。高温窒化工程によってサファイア基板上に局部的に形成されたAlN1−X(0<X≦1)層の上に選択的にGaNドットが形成される。GaNドットの表面密度は工程1)の窒化条件によって決められる。 Such a temperature profile is for maintaining a stable gas flow in the HVPE reactor. Most of the HCl gas passing through the Ga boat reacts with NH 3 gas on the surface of the sapphire substrate in a pure HCl gas state without reacting with Ga to form an NH 4 Cl layer. However, some HCl gas reacts with a small amount of Ga to form GaCl, and further reacts with NH 3 gas on the surface of the sapphire substrate to form GaN. GaN dots are selectively formed on the AlN X O 1-X (0 <X ≦ 1) layer locally formed on the sapphire substrate by the high temperature nitriding process. The surface density of GaN dots is determined by the nitriding conditions in step 1).

本発明では、GaNドットの表面密度を2〜4×10cm-2とした。NHCl層とGaNドットの比率は、HClの流量、NHの流量、Gaボートの温度、基板の温度など多様な成長条件で決められる。 In the present invention, the surface density of the GaN dots is 2 to 4 × 10 9 cm −2 . The ratio of the NH 4 Cl layer to the GaN dots is determined by various growth conditions such as HCl flow rate, NH 3 flow rate, Ga boat temperature, and substrate temperature.

本工程で作製した試料のSEM写真を図3に示す。NHCl層の厚さは800 nm、GaNドットの直径は200 nmである。写真の一部ではNHCl層が除去され、GaNドットが確実に観察された。NH4Cl層があるところでは平坦な表面が得られた。好ましい成長条件としては、HCl流量:40sccm、NH流量:1L/min、キャリア窒素ガスの流量:2.5L/minである。 An SEM photograph of the sample produced in this step is shown in FIG. The thickness of the NH 4 Cl layer is 800 nm, and the diameter of the GaN dot is 200 nm. In part of the photograph, the NH 4 Cl layer was removed and GaN dots were observed reliably. A flat surface was obtained where there was an NH 4 Cl layer. As preferable growth conditions, HCl flow rate: 40 sccm, NH 3 flow rate: 1 L / min, and carrier nitrogen gas flow rate: 2.5 L / min.

本工程で形成されたNH4Cl層の厚さは、高温窒化処理条件と共に最終的に界面に形成されるボイド密度を決める重要な要素である。
図4は、NH4Cl層のω−2θXRD結果を示す。図4から分かるように、多結晶状態の(100)、(110)、(200)、(220)のピークとGaNドットからの(0002)ピークが観察された。
The thickness of the NH 4 Cl layer formed in this step is an important factor that determines the density of voids finally formed at the interface together with the high-temperature nitriding conditions.
FIG. 4 shows the ω-2θXRD results for the NH 4 Cl layer. As can be seen from FIG. 4, the (100), (110), (200), and (220) peaks in the polycrystalline state and the (0002) peak from the GaN dots were observed.

GaNドットの形成有無と表面密度を確認するために本工程で作製した試料のHOエッチング実験を行った。NHClは、HOによって簡単に化学的エッチングが可能な物質である。
図5は、エッチング後のサファイア基板表面のSEM写真である。200 nmのGaNドットが均一に分布していることが分かった。このエッチング後のサファイア基板表面のXRD結果を図6に示す。エッチングによってNH4Clのピークが完全に消え、少量の単結晶状態のc軸に揃えたGaNによる(0002)ピークだけが観察された。
In order to confirm the presence or absence of GaN dots and the surface density, an H 2 O etching experiment was performed on the sample manufactured in this step. NH 4 Cl is a substance that can be easily chemically etched with H 2 O.
FIG. 5 is an SEM photograph of the surface of the sapphire substrate after etching. It was found that 200 nm GaN dots were uniformly distributed. The XRD result of the sapphire substrate surface after this etching is shown in FIG. The NH 4 Cl peak completely disappeared by etching, and only a (0002) peak due to GaN aligned with the c-axis in a small amount of single crystal was observed.

3)低温GaNバッファ層の成長工程
本工程は、工程2)で形成されたGaNドットを含めたNH4Cl層の上に低温バッファ層を成長する工程である。これはNHCl層の形成温度より高い温度で低温バッファ層を成長させることにより、基板温度の増加によるNH4Cl層の合成を抑え、高温GaN層のシード層を形成するものである。
図7に、NHCl層の上にNHCl層の形成温度より高い温度で形成された低温GaNバッファ層を模式的に示す。
3) Growth Step of Low Temperature GaN Buffer Layer This step is a step of growing a low temperature buffer layer on the NH 4 Cl layer including the GaN dots formed in step 2). This by growing a low-temperature buffer layer at a temperature higher than the formation temperature of the NH 4 Cl layer, suppressing the synthesis of NH 4 Cl layer due to an increase in the substrate temperature, and forms a seed layer of high-temperature GaN layer.
7 shows a low-temperature GaN buffer layer formed at a temperature higher than the formation temperature of the NH 4 Cl layer on the NH 4 Cl layer schematically.

Gaボートの温度は、工程2)と同じ450℃に設定し、基板温度は500℃から600℃へ増加した。基板温度が上昇する間低温バッファ層は連続的に成長する。
低温バッファ層は、400℃以上800℃以下の温度で形成することができる。
ただし、GaN低温バッファー層の形成温度に関しては、500℃〜600℃の温度範囲がより望ましい。
なおNH4Cl層の沸点(boiling temperature)は520℃であり、この温度以上では、NH4Clを合成する量が急激に減少し、サファイア基板上に形成するGaN成長比率が上がる。
The temperature of the Ga boat was set to 450 ° C. as in step 2), and the substrate temperature was increased from 500 ° C. to 600 ° C. The low temperature buffer layer grows continuously while the substrate temperature rises.
The low temperature buffer layer can be formed at a temperature of 400 ° C. or higher and 800 ° C. or lower.
However, regarding the formation temperature of the GaN low temperature buffer layer, a temperature range of 500 ° C. to 600 ° C. is more desirable.
The boiling temperature of the NH 4 Cl layer is 520 ° C. Above this temperature, the amount of NH 4 Cl synthesized is drastically reduced and the growth rate of GaN formed on the sapphire substrate is increased.

c軸で揃えたGaNドットが低温バッファ層のシードになり、低温バッファ層も同じようにc軸結晶方向を示した。
図8は、端面SEM写真を示している。低温バッファ層の厚さは2.3ミクロンであり、成長条件はHCl流量:40sccm、NH流量:1L/min、キャリア窒素ガスの流量: 2.5L/minである。写真の一部ではGaNドットが観察された。
図9は、低温GaNバッファ層のω−2θXRD結果を示している。多結晶状態のNH4Clピークと共にc軸に揃えたGaNドットを含めた低温GaNバッファ層の(0002)ピークを示している。
The GaN dots aligned on the c-axis became seeds for the low-temperature buffer layer, and the low-temperature buffer layer also showed the c-axis crystal direction in the same way.
FIG. 8 shows an end face SEM photograph. The thickness of the low temperature buffer layer is 2.3 microns, and the growth conditions are HCl flow rate: 40 sccm, NH 3 flow rate: 1 L / min, and carrier nitrogen gas flow rate: 2.5 L / min. GaN dots were observed in a part of the photograph.
FIG. 9 shows the ω-2θXRD result of the low temperature GaN buffer layer. The (0002) peak of the low-temperature GaN buffer layer including the GaN dots aligned with the c-axis is shown together with the NH 4 Cl peak in the polycrystalline state.

4)高温厚膜GaN層の形成工程
本工程は、工程2)と工程3)で形成されたバッファ層の上に厚膜高温GaN層を形成するために、成長温度を1040℃へ上げて厚膜GaN層を形成する工程である。この時1040℃の成長温度で熱処理効果があり、NH4Cl層の完全な分解に伴い、界面で多数のボイドが形成される。
図10は、低温バッファ層の上に高温厚膜GaN層が形成されるとともに、温度上昇中界面ではボイドが形成されていることを模式的に示す。
図11に好ましいボイドの写真を示す。これは、高温厚膜GaN層の形成前に低温バッファ層を550℃で180nm形成した場合のものである。
4) Formation process of high-temperature thick GaN layer In this process, in order to form a thick high-temperature GaN layer on the buffer layer formed in steps 2) and 3), the growth temperature is increased to 1040 ° C. to increase the thickness. This is a step of forming a film GaN layer. At this time, there is a heat treatment effect at a growth temperature of 1040 ° C., and with the complete decomposition of the NH 4 Cl layer, many voids are formed at the interface.
FIG. 10 schematically shows that a high-temperature thick GaN layer is formed on the low-temperature buffer layer, and voids are formed at the interface during the temperature rise.
FIG. 11 shows a photograph of a preferable void. This is a case where the low temperature buffer layer is formed at 180 ° C. and 180 nm before the high temperature thick GaN layer is formed.

本工程の目的は、ボイド形成によって高温厚膜GaN形成後に、成長温度を室温へ下げる時サファイア基板上に局部的に形成されたGaNドット層からストレスの緩和によって自然リフトオフを起させることである。
また熱処理効果によって工程2)と工程3)をとおして形成されたバッファ層の厚さは、1.2ミクロンまで減少した。
The purpose of this step is to cause natural lift-off by relaxation of stress from the GaN dot layer locally formed on the sapphire substrate when the growth temperature is lowered to room temperature after forming the high-temperature thick film GaN by void formation.
Also, due to the heat treatment effect, the thickness of the buffer layer formed through steps 2) and 3) was reduced to 1.2 microns.

図12は、熱処理後の端面SEM写真である。熱処理後界面に多数のボイド形成と厚さの減少を確認した。
図13は、この試料のω−2θXRD結果を示している。工程2)で形成されたNH4Cl層は完全に分解され、NH4Cl層のピークは観察されない、GaNバッファ層の(0002)ピークのみが観察された。即ち、熱処理によってNH4Cl層の分解が間接的に分かる。熱処理は、1040℃、NH雰囲気で10分間行われた。
FIG. 12 is an end face SEM photograph after the heat treatment. After the heat treatment, many voids were formed at the interface and the thickness decreased.
FIG. 13 shows the ω-2θXRD result of this sample. The NH 4 Cl layer formed in step 2) was completely decomposed, and the peak of the NH 4 Cl layer was not observed, and only the (0002) peak of the GaN buffer layer was observed. That is, the decomposition of the NH 4 Cl layer is indirectly known by the heat treatment. The heat treatment was performed at 1040 ° C. in an NH 3 atmosphere for 10 minutes.

5)GaN自立基板のセルフリフトオフ工程
図14は、基板温度を室温へ冷却中における界面からの分離によるセルフリフトオフを模式的に示している。
本工程は、高温厚膜GaNを成長し、基板温度を室温まで下げる時、界面でストレスの緩和に伴う自然剥離によりGaN自立基板を作製する工程である。
5) Self-lift-off process of GaN free-standing substrate FIG. 14 schematically shows self-lift-off due to separation from the interface while the substrate temperature is being cooled to room temperature.
This step is a step of producing a GaN free-standing substrate by natural exfoliation accompanying relaxation of stress at the interface when growing a high-temperature thick film GaN and lowering the substrate temperature to room temperature.

図15は、本工程によって得られた200ミクロンのGaN自立基板の端面SEM写真を示している。基板の冷却速度は、NH雰囲気で1時間当たり100℃に調整した。リフトオフ後、サファイア基板の表面側を観察したSEM写真を図16に示す。 FIG. 15 shows an end-surface SEM photograph of a 200-micron GaN free-standing substrate obtained by this process. The cooling rate of the substrate was adjusted to 100 ° C. per hour in an NH 3 atmosphere. FIG. 16 shows an SEM photograph of the surface side of the sapphire substrate observed after lift-off.

界面分離によってサファイア基板上に一部のGaN残留物が残っていることが分かった。この試料のXRD結果を図17に示す。サファイア基板上にGaN残留物からの(0002)ピークが観察された。リフトオフの結果、クラックと反りがなく良質な結晶を有するGaN自立基板を得ることができた。   It was found that a part of the GaN residue remained on the sapphire substrate by the interface separation. The XRD result of this sample is shown in FIG. A (0002) peak from the GaN residue was observed on the sapphire substrate. As a result of the lift-off, it was possible to obtain a GaN free-standing substrate having good quality crystals without cracks and warping.

XRD評価によるGaN自立基板のa軸とc軸の格子定数は、それぞれ3.189Åと5.185Åであり、これらはストレインフリーバルクの格子定数と一致する数値である。
また、図18はGaN自立基板のPL結果を示している。ドナー−アクセプター対発光(donor-bound exciton)ピーク(3.4718 eV)は、ストレインフリーバルク結晶の発光位置と同位置であることが分かった。
The a-axis and c-axis lattice constants of the GaN free-standing substrate by XRD evaluation are 3.1893.1 and 5.185Å, respectively, which are numerical values that coincide with the lattice constants of the strain-free bulk.
FIG. 18 shows a PL result of the GaN free-standing substrate. The donor-acceptor pair emission peak (3.4718 eV) was found to be the same as the emission position of the strain-free bulk crystal.

高温厚膜GaN層の成長後、ボイドは自然冷却中界面でストレスの緩和によって自然剥離を発生させる。自然剥離によってin situによるサファイア基板と厚膜GaNが分離される。
サファイア基板上のNHCl層の形成のみでは良質なGaN成長は難しくなる。このような問題を解決するためにはHVPEでは殆ど使われてないGaNドットと低温GaNバッファ層を用いることで良質なGaN結晶成長が可能になった。
After the growth of the high-temperature thick GaN layer, the voids cause spontaneous separation by relaxation of stress at the interface during natural cooling. The sapphire substrate and the thick GaN are separated in situ by natural peeling.
High-quality GaN growth becomes difficult only by forming the NH 4 Cl layer on the sapphire substrate. In order to solve such a problem, a high-quality GaN crystal can be grown by using a GaN dot and a low-temperature GaN buffer layer that are rarely used in HVPE.

低温で形成したNHCl層の使用目的は、基板温度上昇に伴いNHCl層が分解され、高温GaN層成長中にサファイア基板とGaNとの間に多数のボイドを形成させることである。このようなボイドが存在する界面上に成長した厚膜GaNは、クラックと反りがなく、大口径自立基板の作製が実現できる。
また、選択的に形成されたGaNドットはボイド形成によって自然冷却中サファイア基板と厚膜GaNが自然リフトオフされ、付加的なプロセスなしで簡単にサファイア基板を分離させることが可能となる。
The purpose of using the NH 4 Cl layer formed at a low temperature is to decompose the NH 4 Cl layer as the substrate temperature rises and to form a large number of voids between the sapphire substrate and GaN during the growth of the high-temperature GaN layer. Thick GaN grown on the interface where such voids are present is free from cracks and warpage, and a large-diameter self-standing substrate can be produced.
In addition, the selectively formed GaN dots cause the sapphire substrate and the thick film GaN to be naturally lifted off during the natural cooling by void formation, and the sapphire substrate can be easily separated without additional processes.

図19に低温バッファ層の形成を省略した比較例を示す。図19の右図から分かるように、本願発明と同様に基板を準備する工程と該基板上にGaNドット及びNHCl層を形成する工程とを備えていても低温バッファ層の形成を省略すると高温厚膜GaN層の成長後界面にボイドが形成されないため、自然冷却中界面での自然剥離が発生しない。 FIG. 19 shows a comparative example in which the formation of the low temperature buffer layer is omitted. As can be seen from the right side of FIG. 19, even if the substrate is prepared in the same manner as the present invention and the step of forming the GaN dots and the NH 4 Cl layer on the substrate is omitted, the formation of the low temperature buffer layer is omitted. Since no void is formed at the interface after the growth of the high-temperature thick GaN layer, natural peeling does not occur at the interface during natural cooling.

以上HVPE法を用いたGaN自立基板の作製方法を実施例として例示したが本発明はこれに限定されないことはいうまでもない。
例えば自立基板としてGaNを例示したが、AlGaN、InGaNといったGaN系窒化物半導体についても本発明は適用できる。
また低温バッファ層としてGaNバッファ層を例示したが、AlN、InN、BN、及びそれらの混晶半導体のうちのいずれかであってもよい。
As described above, the method for producing a GaN free-standing substrate using the HVPE method has been exemplified as an example, but the present invention is not limited to this.
For example, GaN is exemplified as a free-standing substrate, but the present invention can also be applied to GaN-based nitride semiconductors such as AlGaN and InGaN.
Moreover, although the GaN buffer layer was illustrated as a low temperature buffer layer, any of AlN, InN, BN, and those mixed crystal semiconductors may be sufficient.

次に実施例では、基板上にGaNドット及びNHCl層を形成するためにサファイア基板を準備し、予め高温窒化工程によってサファイア基板上に局部的にAlN1−X(0<X≦1)層を形成しているが、基板上に確実にGaNドット及びNHCl層が形成されるのであれば、基板は必ずしもサファイア基板である必要はない。また基板の高温窒化工程も省略できる。 Next, in an example, a sapphire substrate is prepared to form a GaN dot and NH 4 Cl layer on the substrate, and AlN X O 1-X (0 <X ≦) locally on the sapphire substrate by a high-temperature nitridation process in advance. 1) Although a layer is formed, the substrate is not necessarily a sapphire substrate if the GaN dots and the NH 4 Cl layer are reliably formed on the substrate. Further, the high temperature nitriding step of the substrate can be omitted.

サファイア基板の高温窒化処理によって局部的に形成されたAlN1−X(0<X≦1)の模式図Schematic diagram of AlN X O 1-X (0 <X ≦ 1) locally formed by high temperature nitriding treatment of sapphire substrate GaNドット及びNH4Cl層の形成模式図Schematic diagram of formation of GaN dots and NH 4 Cl layer NH4Cl層とGaNドットのSEM写真SEM photo of NH 4 Cl layer and GaN dots NH4Cl層とGaNドットを示すω−2θXRD結果Ω-2θXRD results showing NH 4 Cl layer and GaN dots Oエッチング後サファイア基板表面のSEM写真SEM photograph of sapphire substrate surface after H 2 O etching Oエッチング後サファイア基板表面のXRD結果XRD result of sapphire substrate surface after H 2 O etching 低温GaNバッファ層の形成模式図Schematic diagram of low-temperature GaN buffer layer formation 低温GaNバッファ層の端面SEM写真SEM photo of end face of low-temperature GaN buffer layer 低温GaNバッファ層のω−2θXRD結果Ω-2θXRD result of low-temperature GaN buffer layer 高温厚膜GaN層の形成模式図Schematic diagram of high-temperature thick GaN layer formation ボイドの写真Boyd Pictures 熱処理後の断面SEM写真Cross-sectional SEM photograph after heat treatment 熱処理後のω−2θXRD結果Ω-2θXRD result after heat treatment セルフリフトオフの模式図Schematic diagram of self-lift-off 自然剥離によるGaN自立基板の端面SEM写真SEM photo of end face of GaN free-standing substrate by natural peeling リフトオフ後のサファイア基板の表面側のSEM写真SEM photograph of the surface side of the sapphire substrate after lift-off リフトオフ後のサファイア基板表面のXRD結果XRD result of sapphire substrate surface after lift-off GaN自立基板のPL結果GaN free-standing substrate PL results 本発明の比較例Comparative example of the present invention

Claims (8)

基板を準備する工程と、該基板上にGaNドット及びNHCl層を形成する工程と、GaNドット及びNHCl層上にIII-V族窒化物半導体からなる低温バッファ層を形成する工程と、低温バッファ層上にGaN系窒化物半導体層を形成する工程と、基板温度を常温に戻すことによりGaN系窒化物半導体層を基板より自然剥離させる工程とを含む、GaN系窒化物半導体自立基板の作製方法。 A step of preparing a substrate, forming a step of forming a GaN dot and NH 4 Cl layer on the substrate, a low temperature buffer layer made of a group III-V nitride semiconductor on the GaN dots and NH 4 Cl layer A GaN-based nitride semiconductor free-standing substrate comprising: a step of forming a GaN-based nitride semiconductor layer on a low-temperature buffer layer; and a step of naturally peeling the GaN-based nitride semiconductor layer from the substrate by returning the substrate temperature to room temperature Manufacturing method. 上記基板は、サファイア基板であることを特徴とする請求項1に記載のGaN系窒化物半導体自立基板の作製方法。   The method for producing a GaN-based nitride semiconductor free-standing substrate according to claim 1, wherein the substrate is a sapphire substrate. 上記基板上にGaNドット及びNHCl層を形成する工程の前に、基板表面を窒化しAlN1−X(0<X≦1)を局部的に形成する工程を含むことを特徴とする請求項2に記載のGaN系窒化物半導体自立基板の作製方法。 The method includes a step of nitriding the substrate surface and locally forming AlN X O 1-X (0 <X ≦ 1) before the step of forming the GaN dots and the NH 4 Cl layer on the substrate. A method for producing a GaN-based nitride semiconductor free-standing substrate according to claim 2. 上記GaNドット及びNHCl層を形成する工程は、Gaガス雰囲気中でHCl及びNHをフローすることによりGaNドット及びNHCl層を形成する工程であることを特徴とする請求項1乃至3のいずれか1項に記載のGaN系窒化物半導体自立基板の作製方法。 The step of forming the GaN dots and NH 4 Cl layer is 1 to claim, characterized in that a step of forming a GaN dot and NH 4 Cl layer by flow of HCl and NH 3 in Ga gas atmosphere 4. A method for manufacturing a GaN-based nitride semiconductor free-standing substrate according to any one of items 3 to 3. 上記GaNドットは、c軸方向に揃えられていることを特徴とする請求項1乃至4のいずれか1項に記載のGaN系窒化物半導体自立基板の作製方法。   5. The method for producing a GaN-based nitride semiconductor free-standing substrate according to claim 1, wherein the GaN dots are aligned in a c-axis direction. 上記低温バッファ層は、GaN、AlN、InN、BN、及びこれらの混晶半導体のうちのいずれかを構成材料とする層であることを特徴とする請求項1乃至5のいずれか1項に記載のGaN系窒化物半導体自立基板の作製方法。   The said low-temperature buffer layer is a layer which uses either GaN, AlN, InN, BN, and these mixed crystal semiconductors as a constituent material, The any one of Claim 1 thru | or 5 characterized by the above-mentioned. GaN-based nitride semiconductor free-standing substrate manufacturing method. 上記低温バッファ層は、400℃以上800℃以下の温度で形成することを特徴とする請求項1乃至6のいずれか1項に記載のGaN系窒化物半導体自立基板の作製方法。   The method for manufacturing a GaN-based nitride semiconductor free-standing substrate according to any one of claims 1 to 6, wherein the low-temperature buffer layer is formed at a temperature of 400 ° C or higher and 800 ° C or lower. 上記各工程は、単一のHVPE装置内で連続して行うことを特徴とする請求項1乃至7のいずれか1項に記載のGaN系窒化物半導体自立基板の作製方法。   The method for manufacturing a GaN-based nitride semiconductor free-standing substrate according to any one of claims 1 to 7, wherein each of the steps is continuously performed in a single HVPE apparatus.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2362412B1 (en) 2010-02-19 2020-04-08 Samsung Electronics Co., Ltd. Method of growing nitride semiconductor
JP2011192752A (en) * 2010-03-12 2011-09-29 Stanley Electric Co Ltd Method of manufacturing semiconductor element
JP4980476B2 (en) * 2011-04-28 2012-07-18 エー・イー・テック株式会社 Method and apparatus for manufacturing gallium nitride (GaN) free-standing substrate
KR101420265B1 (en) * 2011-10-21 2014-07-21 주식회사루미지엔테크 Method of manufacturing a substrate
JP5631952B2 (en) * 2011-10-21 2014-11-26 ルミジエヌテック カンパニー リミテッド Substrate manufacturing method
US9136430B2 (en) 2012-08-09 2015-09-15 Samsung Electronics Co., Ltd. Semiconductor buffer structure, semiconductor device including the same, and method of manufacturing semiconductor device using semiconductor buffer structure
US8946773B2 (en) 2012-08-09 2015-02-03 Samsung Electronics Co., Ltd. Multi-layer semiconductor buffer structure, semiconductor device and method of manufacturing the semiconductor device using the multi-layer semiconductor buffer structure
JP2014172797A (en) * 2013-03-11 2014-09-22 Aetech Corp MANUFACTURING METHOD OF GALLIUM NITRIDE (GaN) SELF-STANDING SUBSTRATE AND MANUFACTURING APPARATUS OF THE SAME
JP2017218347A (en) * 2016-06-07 2017-12-14 信越半導体株式会社 Method for manufacturing free-standing substrate
CN109312491B (en) * 2016-06-16 2021-10-12 赛奥科思有限公司 Nitride semiconductor template, method for manufacturing nitride semiconductor template, and method for manufacturing nitride semiconductor free-standing substrate
CN108493304B (en) * 2018-02-01 2019-08-02 华灿光电(苏州)有限公司 A kind of preparation method of LED epitaxial slice
CN108409332B (en) * 2018-02-12 2020-04-24 山东大学 Preparation method of self-supporting film of endo-growth [153] oriented Ta3N5
CN109887869B (en) * 2019-03-14 2022-11-08 南通中铁华宇电气有限公司 Laser stripping structure
CN111501102A (en) * 2020-06-02 2020-08-07 无锡吴越半导体有限公司 HVPE-based self-supporting gallium nitride single crystal and preparation method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006117530A (en) * 2006-01-11 2006-05-11 Sumitomo Electric Ind Ltd SINGLE-CRYSTAL GaN SUBSTRATE
JP2006191074A (en) * 2005-01-07 2006-07-20 Samsung Corning Co Ltd Method for manufacturing epitaxial wafer
JP2006191073A (en) * 2005-01-07 2006-07-20 Samsung Corning Co Ltd Method for manufacturing epitaxial wafer

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW417315B (en) * 1998-06-18 2001-01-01 Sumitomo Electric Industries GaN single crystal substrate and its manufacture method of the same
CN1140915C (en) * 2002-05-31 2004-03-03 南京大学 Technology for obtaining large-area high-quality GaN self-supporting substrate
CN100359636C (en) * 2005-11-04 2008-01-02 南京大学 Improved laser stripped method of preparing self-supporting gallium nitride substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006191074A (en) * 2005-01-07 2006-07-20 Samsung Corning Co Ltd Method for manufacturing epitaxial wafer
JP2006191073A (en) * 2005-01-07 2006-07-20 Samsung Corning Co Ltd Method for manufacturing epitaxial wafer
JP2006117530A (en) * 2006-01-11 2006-05-11 Sumitomo Electric Ind Ltd SINGLE-CRYSTAL GaN SUBSTRATE

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