JP4653764B2 - Semiconductor device design method, design support system, and program - Google Patents

Description

  The present invention relates to a design method for the purpose of power integrity of a semiconductor chip in a semiconductor package, a design support system and a program for supporting a design according to the design method.

  When designing a semiconductor package or a system including a semiconductor package, voltage fluctuations in the power supply pad and / or ground pad of the semiconductor chip must be less than an allowable value, and analysis of voltage fluctuations is necessary to determine the suitability. Has been done.

  Conventionally, a transient analysis using a SPICE model has been generally performed as an analysis of the voltage fluctuation. In the case of such transient analysis, when the voltage fluctuation exceeds the allowable value, for example, the layout is corrected, and the transient analysis is performed again to determine whether or not the voltage fluctuation is below the allowable value. (For example, Patent Document 1).

  On the other hand, recently, an attempt to introduce analysis in the frequency domain instead of the time domain has been proposed (for example, Patent Document 2).

JP 2004-045422 A JP-A-2005-196406

  However, in the analysis in the time domain as typified by Patent Document 1, since the transient analysis is performed every time the layout is corrected, the calculation amount is large, and the design period cannot be prolonged.

  On the other hand, the technique proposed in Patent Document 2 is mainly intended for a layout on a semiconductor chip included in a semiconductor package, and is applied to the design of a semiconductor package using a semiconductor chip that has already been designed. It is difficult.

  Accordingly, the present invention proposes a new design method capable of shortening the design period even when designing a semiconductor package using a semiconductor chip that has already been designed, and has followed the design method. An object of the present invention is to provide a design support system and program for supporting design.

  In designing a semiconductor package using a semiconductor chip that has already been designed, it is possible to change the design so as to reflect the result of the voltage variation analysis, specifically, the part other than the semiconductor chip, specifically the package wiring.

  On the other hand, in a semiconductor chip typified by a DRAM chip or the like, voltage fluctuations occur in the power pad and / or the ground pad, for example, when the driver of the output stage switches and the output of the semiconductor chip transitions. This is because a transient current flows through the ground pad.

  Therefore, in the present invention, the output of the semiconductor chip transitions from “L” to “H” (L → H: referred to as “first transition case”) and the transition from “H” to “L” (H → L: A semiconductor chip is modeled for each of the two cases of “second transition case”), and analysis in the frequency domain is performed using the modeled semiconductor chip (referred to as “chip model”). As a result, an accurate analysis result is obtained with a small amount of calculation, and a design guideline or a design change guideline for an adjustment target system such as package wiring is provided.

Specifically, the present invention is a method for designing a semiconductor package including a semiconductor chip,
An adjustment target value calculation step of calculating a first adjustment target value and a second adjustment target value based on a first chip model, a second chip model, and an adjustment target system impedance model that are different from each other, wherein the first chip model, The second chip model corresponds to each of two transition cases, a first transition case in which the output value of the semiconductor chip transitions from a low level to a high level and a second transition case in which the output value transitions from a high level to a low level. It is a model created so as to represent the semiconductor chip in a frequency domain, and the adjustment target system impedance model is an adjustment target composed of adjustment target components of components other than the semiconductor chip in the semiconductor package A model created by expressing the system in the frequency domain, and the first adjustment target value Fine said second adjustment target value, said an adjustment target value in each of the first transition case and the second transition case, the adjustment target value calculation step,
An adjustment target value selection step of comparing the first adjustment target value and the second adjustment target value and selecting one of the higher adjustment needs;
A design guideline for the adjustment target system based on the comparison result by comparing a predetermined constraint value in the frequency domain with the adjustment target value selected from the first adjustment target value and the second adjustment target value. A design method comprising a design guideline determining step for determining

Further, the present invention provides a design support system that supports design according to the design method.
A chip model providing unit that provides a first chip model and a second chip model that are different from each other, wherein the output value of the semiconductor chip transitions from a low level to a high level in the first chip model and the second chip model. A chip that is a model created by expressing the semiconductor chip in the frequency domain in correspondence with each of two transition cases, a first transition case and a second transition case that transitions from a high level to a low level. A model provider,
An impedance model providing unit that provides an adjustment target system impedance model that expresses an adjustment target system including an adjustment target component of components other than the semiconductor chip in the semiconductor package in a frequency domain;
A first adjustment target value that is an adjustment target value in each of the first transition case and the second transition case by connecting each of the first chip model and the second chip model to the adjustment target system impedance model; An adjustment target value calculation unit for calculating a second adjustment target value;
An adjustment target value selection unit that compares the first adjustment target value and the second adjustment target value and selects one of the higher adjustment needs;
A constraint value providing unit that provides a predetermined constraint value in the frequency domain;
A design support that compares the constraint value with a selected adjustment target value among the first adjustment target value and the second adjustment target value and determines design support information for the adjustment target system based on the comparison result. An information determination unit;
A design support system comprising a display unit for displaying the design support information is provided.

Furthermore, the present invention provides a design support system for supporting a design according to the design method by causing the calculation unit to execute predetermined processing in a computer system including a calculation unit, a storage unit, and a display unit. Is a program for functioning as
The predetermined process is:
An adjustment target value calculation step of calculating a first adjustment target value and a second adjustment target value based on a first chip model, a second chip model, and an adjustment target system impedance model that are different from each other, wherein the first chip model, The second chip model corresponds to each of two transition cases, a first transition case in which the output value of the semiconductor chip transitions from a low level to a high level and a second transition case in which the output value transitions from a high level to a low level. It is a model created so as to represent the semiconductor chip in a frequency domain, and the adjustment target system impedance model is an adjustment target composed of adjustment target components of components other than the semiconductor chip in the semiconductor package A model created by expressing the system in the frequency domain, and the first adjustment target value Fine said second adjustment target value, said an adjustment target value in each of the first transition case and the second transition case, the adjustment target value calculation step,
An adjustment target value selection step of comparing the first adjustment target value and the second adjustment target value and selecting one of the higher adjustment needs;
A design support for the adjustment target system based on the comparison result by comparing a predetermined restriction value in the frequency domain with the adjustment target value selected from the first adjustment target value and the second adjustment target value. A design support information determination step for determining information;
A display step of displaying the design support information on the display unit is provided.

  According to the present invention, the first chip model and the second chip corresponding to the two cases of the first transition case (L → H) and the second transition case (H → L) as the cases where the power supply / GND voltage fluctuates. Since the analysis is performed using the chip model, an accurate analysis result can be obtained. In addition, processing in the frequency domain, such as calculation of the first adjustment target value and the second adjustment target value based on the first chip model, the second chip model, and the adjustment target system impedance model, and comparison between one value and the constraint value is used. Therefore, the amount of calculation can be reduced as compared with the transient analysis.

  Hereinafter, a case where the present invention is applied to the design of a multichip package (MCP) 100 including the semiconductor chip 10 and the semiconductor chip 20 as shown in FIG. 1 will be described as a design method according to the embodiment of the present invention. The illustrated semiconductor chip 10 is a DRAM chip, and the illustrated semiconductor chip 20 is a logic chip on which a processor or the like is mounted.

  The semiconductor chip 10 is provided with a power pad 11 and a ground pad 12. In an actual chip, as schematically shown in FIG. 1, a plurality of power supply pads 11 and a plurality of ground pads 12 are provided. The power supply pad 11 and one ground pad 12 are handled.

  A plurality of output drivers are provided between the power supply pad 11 and the ground pad 12 of the semiconductor chip 10. Although each output driver is not shown in FIG. 1, a pMOS circuit and an nMOS circuit are connected in series, and an output pad 13 is drawn from a connection portion between the pMOS circuit and the nMOS circuit. Yes. In an actual chip, output drivers and output pads 13 corresponding to at least the number of data lines (DQ lines) are provided. However, in the design method described below, a plurality of output pads and a plurality of output drivers are provided. The power supply / GND voltage fluctuations in the power supply pad 11 and the ground pad 12 are analyzed together.

  In the present embodiment, the MCP 100 as shown in FIG. 1 is divided into a model obtained by modeling the semiconductor chip 10 as shown in FIG. 2 and an impedance model such as package wiring, and these are connected. By calculating the voltage fluctuations at the power supply pad 11 and the ground pad 12 and comparing them with a predetermined limit value in the frequency domain, it is determined whether or not the fluctuation of the power supply / GND voltage is within an allowable value. to decide. In the following, a circuit network to be adjusted, such as package wiring or wiring on a printed wiring board, is referred to as an adjustment target system, and its impedance model is referred to as an adjustment target system impedance model.

Here, the internal impedance Z _{chp_int} (f) 14 shown in FIG. 2 is a power pad when a portion excluding the output driver (pMOS circuit and nMOS circuit) in the configuration included in the semiconductor chip 10 is viewed from the output side. 11 and the impedance seen between the ground pad 12. _{Further, Z p_x} and _{Z N_y} are those generically illustrated despite the pMOS circuit, and nMOS circuit constituting the output driver in each of the states, the specific states of the pMOS circuit, and nMOS circuit constituting the output driver In the figure created considering the above, Z _{p_on} (impedance of the pMOS circuit in the on state) or Z _{p_off} (impedance of the pMOS circuit in the off state) and Z _{n_on} (impedance of the nMOS circuit in the on state) or Z _{n_off} ( This is expressed as the impedance of the nMOS circuit in the off state.

  More specifically, in the design method according to the present embodiment, as a chip model of the semiconductor chip 10, a chip model considering the four cases of FIGS. 3 to 6 is prepared, and each of them is referred to as an adjustment target system impedance model. Let's connect.

  Among these, the chip model shown in FIGS. 3 and 4 is a first chip model obtained by modeling the semiconductor chip 10 assuming a first transition case in which the output value of the semiconductor chip 10 transitions from a low level to a high level. It is. In the first chip model, a pMOS circuit impedance and an nMOS circuit impedance obtained by representing impedances of a pMOS circuit and an nMOS circuit, respectively, connected in series are connected between the power supply pad 11 and the ground pad 12, and in parallel with the internal impedance. 14, and further, a first current source that is a current source considering the fluctuation current value in the first transition case is connected in parallel to the pMOS circuit impedance.

Specifically, the first chip model shown in FIG. 3 is a chip model for calculating the voltage fluctuation value in the power supply pad 11, and the pMOS circuit impedance is the impedance in the ON state of the pMOS circuit, and the nMOS circuit impedance is the nMOS circuit. The first current source _{Is_L2H_vdq} for calculating the power supply voltage fluctuation value is connected in parallel to the pMOS circuit impedance using the impedance in the off state.

Further, the first chip model shown in FIG. 4 is a chip model for calculating a voltage fluctuation value in the ground pad 12, and both the pMOS circuit impedance and the nMOS circuit impedance corresponding to the impedance in the on state of the pMOS circuit and the nMOS circuit are shown. And the first current source _{Is_L2H_vsq} for calculating the ground voltage fluctuation value is connected in parallel to the pMOS circuit impedance.

  On the other hand, the chip model shown in FIGS. 5 and 6 is a second chip model obtained by modeling the semiconductor chip 10 assuming a second transition case in which the output value of the semiconductor chip 10 transitions from a high level to a low level. is there. In the second chip model, a pMOS circuit impedance and an nMOS circuit impedance connected in series are connected between the power supply pad 11 and the ground pad 12, and an internal impedance 14 is connected in parallel therewith. Further, in the second transition case, The second current source, which is a current source taking into consideration the fluctuation current value, is created so as to be connected in parallel to the nMOS circuit impedance.

Specifically, the second chip model shown in FIG. 5 is a chip model for calculating the voltage fluctuation value in the power supply pad 11, and the pMOS circuit and the nOS circuit corresponding to both the pMOS circuit impedance and the nMOS circuit impedance are turned on. Using the impedance, the second current source l _{s_H2L_vdq} for calculating the power supply voltage fluctuation value is connected in parallel to the nMOS circuit impedance.

Further, the second chip model shown in FIG. 6 is a chip model for calculating a voltage fluctuation value in the ground pad 12. The pMOS circuit impedance is the impedance in the OFF state of the pMOS circuit, and the nMOS circuit impedance is the nMOS circuit impedance. The second current source l _{s_H2L_vsq} for calculating the ground voltage fluctuation value is connected in parallel to the nMOS circuit impedance after using the impedance in the ON state.

  Note that the equivalent circuit models of the pMOS circuit and the nMOS circuit shown in FIGS. 3 to 6 are symmetrical with respect to the output pad 13 when the capacitor and the resistor are connected in series in consideration of the physical picture. It is arranged in. More specifically, when the power pad 11 and the GND pad 12 side are viewed from the output pad 13, the capacitor and the resistor are first arranged so that the capacitor can be seen. However, an equivalent circuit model of a pMOS circuit and an nMOS circuit may be configured by arranging capacitors and resistors connected in series so as to be asymmetric with respect to the output pad 13. That is, for example, when the power pad 11 and the GND pad 12 side are viewed from the output pad 13, the pMOS circuit may be arranged in the order of resistance and capacitor, while the nMOS circuit may be arranged in the order of capacitor and resistance.

  FIGS. 7 to 10 show examples using an equivalent circuit model different from the equivalent circuit models of the pMOS circuit impedance and the nMOS circuit impedance shown in FIGS. 7 to 10 correspond to FIGS. 3 to 6, respectively.

  3 to 6, the same equivalent circuit model is used for each of the pMOS circuit and the nMOS circuit regardless of the on / off state. However, referring to FIGS. 7 to 10, each of the pMOS circuit and the nMOS circuit is used. For the above, different equivalent circuit models are used in the on state and the off state. This is because, in the pMOS circuit and the nMOS circuit, the resistance component is dominant in the on state, whereas the capacitor component is dominant in the off state.

  More specifically, the pMOS circuit impedance in the on state is expressed by an equivalent circuit model in which a capacitor and a resistor are connected in parallel between the power supply pad 11 and the output pad 13, and the pMOS circuit impedance in the off state is This is expressed by an equivalent circuit model in which a capacitor and a resistor are connected in series between the power supply pad 11 and the output pad 13. Similarly, the nMOS circuit impedance in the on state is expressed by an equivalent circuit model in which a capacitor and a resistor are connected in parallel between the output pad 13 and the GND pad 12, and the nMOS circuit impedance in the off state is 13 and the GND pad 12 are expressed by an equivalent circuit model in which a capacitor and a resistor are connected in series. If the pMOS circuit impedance / nMOS circuit impedance in the on / off state is calculated using such an equivalent circuit model, a more accurate analysis result can be obtained as compared with the examples shown in FIGS. Can do.

  Hereinafter, the design method according to the present embodiment will be specifically described with reference to FIGS. 11 to 22 as well as the above-described four types of chip model creation methods.

  First, from information such as design data about the semiconductor chip 10, a first chip model (for power supply voltage fluctuation / for GND voltage fluctuation) as shown in FIGS. 3 and 4 (or FIGS. 7 and 8) and FIG. A second chip model (for power supply voltage fluctuation / for GND voltage fluctuation) as shown in FIG. 6 (or FIG. 9 and FIG. 10) is created (FIG. 11: step S101).

  Specifically, as shown in FIG. 12, the Z parameter is calculated by AC analysis of the SPICE model for the semiconductor chip 10. In the present embodiment, the Z parameter is directly calculated. Alternatively, the S parameter may be calculated first, and then the S parameter may be converted into the Z parameter.

On the other hand, when only the portion related to the impedance is extracted from the chip model in the present embodiment, it is as shown in FIG. As described in connection with FIG. _{2, Z p_x} and _{Z N_y} regardless of the state of the output driver, a notation is introduced to represent the pMOS circuit, and nMOS circuit. That is, specifically, when the output value of the semiconductor chip 10 is at a high _{level, Z p_x} represents the impedance _{Z P_On} the pMOS circuit in the on _{state, Z N_y} shows the impedance _{Z N_off} of nMOS circuit in the OFF state . Similarly, when the output value of the semiconductor chip 10 is _{low, Z p_x} represents the impedance _{Z P_off} the pMOS circuit in the off _{state, Z N_y} shows the impedance _{Z N_on} of nMOS circuit in the on state.

  A circuit shown in FIG. 14 is obtained by modifying the impedance model shown in FIG. 13 into a more easily understandable form as a two-port network. The Z parameter in the circuit network shown in FIG. 14 is expressed by the following equation (1).

By arranging the relationship of each element of the matrix included in the equation (1) and solving for each of Z _{p — x} , Z _{n — y} and Z _{chp — int} , equations (2) to (4) listed below are obtained.

As understood from the equations (2) and (3), Z _{p_on} and Z _{n_off} can be calculated by using Z ₁₁ , Z ₁₂ and Z ₂₂ when the output value of the output driver is high level, Z _{p_off} and Z _{n_on} can be calculated by using Z ₁₁ , Z ₁₂ and Z ₂₂ when the output value of the output driver is at a low level. In the present embodiment, the impedance of each part is obtained based on Z ₁₁ , Z ₁₂ , Z ₂₁ and Z ₂₂ calculated by SPICE analysis, but Z ₁₁ , Z ₁₂ , Z ₂₁ and Z ₂₂ are measured. However, the result may be used. That is, Z ₁₁ , Z ₁₂ , Z ₂₁ and Z ₂₂ are measured for each of the cases where the output value of the output driver is high level and low level (or I1, I2, V1, V2 in FIG. 13 are measured). the Te calculates _{Z 11, Z 12, Z 21} and _{Z 22),} and substitutes the so _{Z 11, Z 12, Z 21} and _{Z 22} obtained in the equation (2) and (3) Thus, the impedance in each state of the pMOS circuit 24 and the nMOS circuit 25 may be calculated.

  After obtaining the impedance values as described above, the first current source (for power supply / GND) and the second current source (for power supply / GND) are connected as shown in FIGS. To derive. Here, FIG. 15 is a diagram relating to derivation of the first current source for calculating the power supply voltage fluctuation value, and FIG. 16 is a diagram relating to derivation of the first current source for calculating the ground voltage fluctuation value. FIG. 17 is a diagram relating to derivation of the second current source for calculating the power supply voltage fluctuation value, and FIG. 18 is a diagram relating to derivation of the second current source for calculating the ground voltage fluctuation value. 15 to 18, CR parallel circuits are used as equivalent circuit models of the on-state pMOS circuit and the on-state nMOS circuit, respectively. However, both the pMOS circuit and the nMOS circuit have resistance in the on-state. Therefore, each equivalent circuit may be expressed only by resistance. Depending on the accuracy required for the analysis result, a CR series circuit may be used as an equivalent circuit model of an on-state pMOS circuit or nMOS circuit, as shown in FIGS.

When deriving the first current source _{Is_L2H_vdq} for calculating the power supply voltage fluctuation value, first, as shown in FIG. 15, a predetermined external load model Z _load (no load) is provided between the output pad 13 and the ground pad 12. But you can connect). Here, assuming that the impedance Z _load of a predetermined external load model is much smaller than the nMOS circuit impedance Z _{n_off in the} off state, most of the current I _{v_L2H} flowing through the power supply pad 11 in the first transition case (L → H). _{Will flow} to the pMOS circuit impedance Z _{p_on} in the ON state and the predetermined external load model Z _load . In this case, if the current _{Iv_L2H} flowing through the power supply pad 11 is known in the first transition case (L → H), the current value _{Is_L2H_vdq} of the first current source can be derived from the following equation (5).

Similarly, when deriving the first current source _{Is_L2H_vsq} for calculating the ground voltage fluctuation value, first, as shown in FIG. 16, a predetermined external load model Z _{load is provided} between the output pad 13 and the ground pad 12. Connect with no load. Here, _assuming that the on-state nMOS circuit impedance Z _{n_on} is much smaller than the impedance Z _load of the predetermined external load model, most of the current _{Ig_L2H} flowing through the ground pad 12 in the first transition case (L → H). _Will flow to the pMOS circuit impedance Z _{p_on in the} on state and the nMOS circuit impedance Z _{n_on} in the on state. In that case, if the current _{Ig_L2H} flowing through the ground pad 12 in the first transition case (L → H) is known, the current value _{Is_L2H_vsq} of the first current source can be derived from the following equation (6).

When deriving the second current source _{Is_H2L_vdq} for calculating the power supply voltage fluctuation value, first, as shown in FIG. 17, a predetermined external load model Z _load (no load) is provided between the output pad 13 and the ground pad 12. But you can connect). Here, assuming that the impedance Z _load of the predetermined external load model is much larger than the nMOS circuit impedance Z _{n_on in the} ON state, most of the current I _{v_H2L} flowing through the power supply pad 11 in the second transition case (H → L). _Flows to the pMOS circuit impedance Z _{p_on} in the on state and the nMOS circuit impedance Z _{n_on} in the on state. In this case, if the current _{Iv_H2L} flowing through the power supply pad 11 is known in the second transition case (H → L), the current value _{Is_H2L_vdq} of the second current source can be derived from the following equation (7).

Similarly, when deriving the second current source _{Is_H2L_vsq} for calculating the ground voltage fluctuation value, first, as shown in FIG. 18, a predetermined external load model Z _load between the output pad 13 and the ground pad 12 is obtained. Connect with no load. Here, the impedance _{Z load} of a predetermined external load model assuming also pMOS circuit impedance _{Z P_On} Gayori the off state much smaller, the current _{I G_H2L} flowing through the ground pad 12 at the second transition case (H → L) Most will flow through the nMOS circuit impedance Z _{n_on} in the on state and the impedance Z _load of the predetermined external load model. In this case, if the current _{Ig_H2L} flowing through the ground pad 12 in the second transition case (H → L) is known, the current value _{Is_H2L_vsq} of the second current source can be derived from the following equation (8).

In the present embodiment, the current flowing through the power supply pad 11 and the ground pad 12 in the first transition case (L → H) and the second transition case (H → L) is calculated by SPICE transient analysis. , by performing a Fourier transformation process, but it was decided to obtain a current _{I V_L2H} and current _{I G_L2H} and _{I V_H2L} and current _{I G_H2L} by a frequency domain representation, instead of this, the subject by using a spectrum analyzer or an oscilloscope semiconductor The state of the chip pad may be directly measured.

  Thus, in the present embodiment, the first chip model and the second chip model for the first transition case and the second transition case are respectively used for calculating the power supply voltage fluctuation value based on the semiconductor chip information. Two types of GND voltage fluctuation value calculation (thus, a total of four types of chip models) are created (FIG. 11: Step S101). As described above, when creating these chip models, transient analysis of the SPICE model is also conceivable, but once the chip model is created, it will be created as long as the configuration of the semiconductor chip 10 does not change. A chip model can be used.

On the other hand, an adjustment target system impedance model as shown in FIG. 2 is created based on the information of the adjustment target system such as the package wiring length (FIG. 11: step S102). Each of the first chip model and the second chip model for calculating the GND fluctuation value is connected to the adjustment target system impedance model created in step S102 as shown in FIG. 19 to FIG. By solving, the power supply / GND voltage fluctuation spectrum is calculated without performing transient analysis. Here, FIG. 19 is a diagram related to power supply voltage fluctuation spectrum calculation in the first transition case, and FIG. 20 is a diagram related to ground voltage fluctuation spectrum calculation in the first transition case. FIG. 21 is a diagram related to power supply voltage fluctuation spectrum calculation in the second transition case, and FIG. 22 is a diagram related to ground voltage fluctuation spectrum calculation in the second transition case. Here, in creating FIGS. 19 to 22, Z _{vc_mcp} was opened, and Z _{gc_mcp} , Z _{v_mcp 3} , and Z _{g_mcp 3} were set to zero.

When calculating the power supply voltage fluctuation spectrum ΔV _{DDQ_L2H} as the adjustment target value in the first transition case, a circuit equation is established for the three closed loops shown in FIG. 19 (the following equation (9)), and the following equation is obtained by solving it. The power supply voltage fluctuation spectrum ΔV _{DDQ_L2H} shown in (10) is obtained.

  Here, | A |, E, and Z are represented by the following formulas (11) to (13), respectively.

Similarly, when the ground voltage fluctuation spectrum ΔV _{SSQ_L2H} is calculated as the adjustment target value in the first transition case, a circuit equation is established for the three closed loops shown in FIG. 20 (formula (14) below) and is solved. A power supply voltage fluctuation spectrum ΔV _{SSQ_L2H} represented by the following formula (15) is obtained.

  Here, | A |, E, and Z are represented by the following formulas (16) to (18), respectively.

On the other hand, when calculating the power supply voltage fluctuation spectrum ΔV _{DDQ_H2L} as the adjustment target value in the second transition case, a circuit equation is established for the three closed circuits shown in FIG. 21 (the following equation (19)), and by solving it, A power supply voltage fluctuation spectrum ΔV _{DDQ_H2L} represented by the following equation (20) is obtained.

  Here, | A |, E, and Z are represented by the following formulas (21) to (23), respectively.

Similarly, when the ground voltage fluctuation spectrum ΔV _{SSQ_H2L} is calculated as the adjustment target value in the second transition case, a circuit equation is established for the three closed circuits shown in FIG. 22 (the following equation (24)), and is solved. Thus, a power supply voltage fluctuation spectrum ΔV _{SSQ_H2L} represented by the following equation (25) is obtained.

  Here, | A |, E, and Z are represented by the following formulas (26) to (28), respectively.

In the present embodiment, as described above, Z _{vc_mcp} is opened, and Z _{gc_mcp} , Z _{v_mcp3} , and Z _{g_mcp} 3 are set to zero, respectively. Instead, for each of the four types of chip models and the combination of the meter impedance model to be adjusted, a circuit equation may be established in consideration of the four cycles.

  In this way, after calculating the adjustment target value for both the first transition case and the second transition case (FIG. 11: step S103), the power supply / GND voltage fluctuation spectrum and the second transition case in the first transition case. Is compared with the power supply / GND voltage fluctuation spectrum in step S104, and one of the higher adjustment needs is selected (step S104).

  Here, in the present embodiment, the constraint values are also the constraint values set assuming the first and second transition cases, which are the constraint values set assuming the first transition case. Two types of second constraint values are prepared, and the first constraint value and the second constraint value are determined according to the adjustment target value selection information indicating which transition case the power supply / GND voltage fluctuation spectrum is selected in step S104. Either one is selected (step S105).

  Next, the power supply / GND voltage fluctuation spectrum in the first transition case or the second transition case selected in step S104 is compared with the first constraint value or the second constraint value selected in step S105 (step S106). A design guideline is determined based on the comparison result (step S107).

  Here, as examples of design guidelines to be determined, for example, 1) the voltage fluctuation value in the power / ground pads 11 and 12 and the result of quality determination of the power / ground wiring in the MCP, 2) the impedance of the MCP power / ground wiring Optimum values, 3) Optimum values of the width / length / thickness of the power / ground wiring in the MCP, 4) Optimum distances from the power / ground pads 11, 12 to the power / ground terminals, 5) Package substrate layer The optimum value of the number, 6) the optimum wiring width with respect to the wiring length of the power supply / ground wiring in the MCP, and 7) the optimum wiring length with respect to the wiring width of the power supply / ground wiring in the MCP. Instead of this, it is also possible to identify a location that is likely to cause a problem in the adjustment target system from the voltage fluctuation spectrum and point out that location as the adjustment target location.

  As described above, according to the present embodiment, once the chip model has been created, the adjustment target value related to the adjustment target system can be calculated simply by solving the circuit equation for the associated cycle. Therefore, the recheck can be performed easily and in a short time, for example, when the design is changed by adjusting the package wiring length.

  In step S105 (FIG. 11) in the above-described embodiment, one of the pair of first constraint values and second constraint values is selected. For example, as shown in FIG. In addition, a plurality of constraint value pairs such as an absolute reference pair (a pair that can be selected regardless of use conditions) and a plurality of constraint value pairs 1 to 3 are prepared based on a semiconductor package whose operation has already been confirmed. A constraint value pair is selected based on selection basic information indicating conditions (such as operating frequency and load) (FIG. 23: step S105a), and then, in step S105a, according to the adjustment target value selection information related to the selection result in step S104. And selecting one of the first constraint value and the second constraint value constituting the constraint value pair selected in step S105b. It may be.

  As shown in FIG. 23, after the design guideline is determined (step S107), the adjustment target system information is changed according to the design guideline (step S108), and then the adjustment target system impedance model is calculated again. (Step S102) Based on the combination of the adjustment target system impedance model and the first chip model and the second chip model created in the previous processing, the processing after Step S103 may be automatically performed again. .

  As described above, the case of a multi-chip package has been described as an example. However, it is apparent that the concept of the present invention can be applied not only to a multi-chip package but also to a single-chip package.

  The concept of the present invention can be applied not only to package design but also to the design of a system equipped with a package as shown in FIG.

  Referring to FIG. 24, the system includes a power supply device 110 having a power supply (PS) unit and a ground (GND) unit, a printed wiring board (PCB) 120, and a multichip package (MCP) 100. On the printed circuit board 120, as an electrical component, a large-capacitance capacitor 122, a power supply wiring on the PCB (or a power supply plane on the PCB) 124, a bypass capacitor 126 on the PCB, a bypass capacitor 128 provided on the back surface of the PCB, etc. Is provided. The multichip package 100 is formed by stacking a semiconductor chip 10 having a power pad 11 and a ground pad 12 and a semiconductor chip 20 on a package substrate 101. Power is supplied to the power supply pads 11 of the semiconductor chip 10 through the power supply terminals (balls) 102, the through holes 103, the power supply wirings 104 in the MCP, and the like. On the other hand, the ground pad 12 of the semiconductor chip 10 is connected to the ground through a ground terminal (ball) 105, a through hole 106, a ground wiring 107 in the MCP, and the like.

  The electrical components of such a system can be expressed as a passive circuit block consisting entirely of RLC, as shown in the upper part of FIG. As shown in FIG. 2, the adjustment target system impedance model composed of the passive circuit block is connected to each chip model shown in FIGS. 3 to 6, and the circuit equation as described with reference to FIGS. By solving the equation, although the calculation amount is somewhat increased, the transformation variation value can be calculated with a smaller calculation amount than the transient analysis.

  Then, for example, as shown in step S106 of FIG. 11, by comparing the adjustment target value with the constraint value, the adjustment target system corresponding to the frequency portion where the adjustment target value exceeds the constraint value. A part may be specified, and the design guideline may be determined with the part as an adjustment target part (in the lower part of FIG. 25, the MCP-PKG power supply wiring part).

  The design method described above can be embodied as a design support program and a design support system by programming at least a part thereof.

  Hereinafter, an implementation example of the design support system will be described. As shown in FIG. 26, the design support system according to the implementation includes a calculation unit 210, a main memory 220, an auxiliary storage 230, an input unit 240, and a display unit 250.

  The main memory 220 is composed of, for example, a DRAM device, and the auxiliary memory 230 is composed of, for example, an HDD or a CD-ROM. The input unit 240 is configured with, for example, a keyboard and a mouse, and the display unit 250 is configured with, for example, a CRT, a liquid crystal display, or the like.

  More specifically, a program in which at least a part of the design method in each embodiment described above is implemented is stored in the auxiliary storage 230. This program is expanded on the main memory 220 and executed by the arithmetic unit 210. When the arithmetic unit 210 executes the program, the system shown in FIG. 26 embodies at least a part of the design method described above and functions as a design support system. Further, on the main memory 220, data generated while the arithmetic unit 210 is operating according to the program and data used by the arithmetic unit 210 are temporarily stored. In general, when the present invention is realized on a computer system, a configuration in which the main memory 220 and the auxiliary memory 230 are divided as described above is mainly employed. However, conceptually, both are collectively regarded as a storage unit. Is also possible.

  When a design support system is constructed by implementing the design method according to each of the above-described embodiments on a program, a design guideline determined based on a comparison result in the frequency domain between the adjustment target value and the constraint value is displayed on the display unit 250. A step of displaying may be further provided.

It is a figure which shows schematic structure of the semiconductor package made into design object in embodiment of this invention. It is the figure which modeled the semiconductor package shown by FIG. It is a figure which shows the 1st chip model (L-> H) for power supply voltage fluctuation | variation spectrum calculation. It is a figure which shows the 1st chip model (L-> H) for GND voltage fluctuation spectrum calculation. It is a figure which shows the 2nd chip model (H-> L) for power supply voltage fluctuation | variation spectrum calculation. It is a figure which shows the 2nd chip model (H-> L) for GND voltage fluctuation spectrum calculation. It is a figure which shows the other example of the 1st chip model (L-> H) for power supply voltage fluctuation | variation spectrum calculation. It is a figure which shows the other example of the 1st chip model (L-> H) for GND voltage fluctuation spectrum calculation. It is a figure which shows the other example of the 2nd chip model (H-> L) for power supply voltage fluctuation | variation spectrum calculation. It is a figure which shows the other example of the 2nd chip model (H-> L) for GND voltage fluctuation spectrum calculation. It is a flowchart which shows the design method by embodiment of this invention. It is a figure for demonstrating the procedure which determines the impedance value of a 1st chip model and a 2nd chip model. It is another figure for demonstrating the procedure which determines the impedance value of a 1st chip model and a 2nd chip model. It is another figure for demonstrating the procedure which determines the impedance value of a 1st chip model and a 2nd chip model. It is a figure for demonstrating the calculation procedure of the electric current value of the 1st current source for power supply voltage fluctuation | variation spectrum calculation. It is a figure for demonstrating the calculation procedure of the electric current value of the 1st current source for GND voltage fluctuation spectrum calculation. It is a figure for demonstrating the calculation procedure of the electric current value of the 2nd current source for power supply voltage fluctuation | variation spectrum calculation. It is a figure for demonstrating the calculation procedure of the electric current value of the 2nd current source for GND voltage fluctuation spectrum calculation. It is a figure for demonstrating the calculation process of a power supply voltage fluctuation spectrum. It is a figure for demonstrating the calculation process of a GND voltage fluctuation spectrum. It is a figure for demonstrating the calculation process of a power supply voltage fluctuation spectrum. It is a figure for demonstrating the calculation process of a GND voltage fluctuation spectrum. It is a flowchart which shows the modification of the design method shown by FIG. It is a figure which shows schematic structure of the semiconductor system which can apply this invention. It is a figure which shows the example which applied this invention to the semiconductor system shown by FIG. It is a block diagram which shows the structure of the design support system based on the design method by this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor chip 11 Power supply pad 12 Ground pad 13 Output pad 14 Internal impedance 20 Semiconductor chip 100 Multichip package 101 Package board 102 Power supply terminal (ball)
103 Through hole 104 Power supply wiring in MCP 105 Ground terminal (ball)
106 Through-hole 107 Ground wiring in MCP 110 Power supply 120 Printed wiring board (PCB)
122 Large capacity capacitor 124 PCB power supply wiring / plane 126 Bypass capacitor 128 Bypass capacitor 210 Arithmetic unit 220 Main memory 230 Auxiliary memory 240 Input unit 250 Display unit

Claims (40)

A design method for a semiconductor package including a semiconductor chip, which causes a computer unit to function as a design support system by causing the calculation unit to execute a program stored in the storage unit in a computer system including a calculation unit and a storage unit. And
The arithmetic unit, in calculation output step calculate a first voltage fluctuation of power supply / GND spectrum and the second voltage fluctuation of power supply / GND spectrum based on the mutually different first chip model and a second chip model and adjusted based impedance model The first chip model and the second chip model include a first transition case in which an output value of the semiconductor chip transits from a low level to a high level and a second transition case in which the output value transits from a high level to a low level. It is a model created by expressing the semiconductor chip in the frequency domain corresponding to each of the two transition cases, and the adjustment target system impedance model is a component of the semiconductor package other than the semiconductor chip. To express the adjustment target system consisting of the adjustment target components in the frequency domain And a model created by the first voltage fluctuation of power supply / GND spectrum and said second voltage fluctuation of power supply / GND Spectrum voltage fluctuation of power supply / GND in each of the first transition case and the second transition case it is a spectrum, and the step de San,
The calculation unit, said first power supply / GND voltage selection step you select one of fluctuation spectrum and the second voltage fluctuation of power supply / GND spectrum,
The arithmetic unit compares the selected voltage fluctuation of power supply / GND spectrum of predetermined constraint value and the first voltage fluctuation of power supply / GND spectrum and said second voltage fluctuation of power supply / GND spectrum in the frequency domain And a design guideline determining step for determining a design guideline for the adjustment target system based on the comparison result. Of the first constraint value, which is a constraint value set assuming the first transition case, and the second constraint value, which is a constraint value set assuming the second transition case, constraints of transitions case corresponding to the selected voltage fluctuation of power supply / GND spectrum by hexene-option step, said selecting as a predetermined constraint value used for the comparison in the design guidelines determining step, the constraint value selection step In addition,
The design method according to claim 1. The computing unit creates the first chip model and the second chip model based on semiconductor chip information about the semiconductor chip, and based on adjustment target system information about the adjustment target system, creating adjustment object system impedance model, and further comprising an impedance model building step,
Prior hexane out step, the arithmetic unit, the adjustment target the second chip model with and connecting the first chip model to the adjustment target system impedance model to calculate a first voltage fluctuation of power supply / GND Spectrum Connecting to a system impedance model to calculate the second power supply / GND voltage fluctuation spectrum ;
Design method according to any one of claims 1 to 2. The semiconductor chip includes a power supply pad and a ground pad, an output part composed of a pMOS circuit and an nMOS circuit connected between the power supply pad and the ground pad, an output pad drawn from a connection part with the pMOS circuit and the nMOS circuit, And an internal component represented by an internal impedance inserted in parallel with the output unit between the power supply pad and the ground pad,
The processing executed by the calculation unit in the chip model creation step is as follows:
An output impedance obtained by connecting a pMOS circuit impedance and an nMOS circuit impedance representing impedance of the pMOS circuit and the nMOS circuit in series and an internal impedance are connected in parallel between the power supply pad and the ground pad. In addition, the first chip model is obtained by connecting a first current source, which is a current source in consideration of a fluctuation current value in the first transition case, in parallel to the pMOS circuit impedance corresponding to the first transition case. A first chip model creation step to be created;
An output impedance obtained by connecting a pMOS circuit impedance and an nMOS circuit impedance representing impedance of the pMOS circuit and the nMOS circuit in series and an internal impedance are connected in parallel between the power supply pad and the ground pad. In addition, the second chip model is obtained by connecting a second current source, which is a current source considering the fluctuation current value in the second transition case, in parallel to the nMOS circuit impedance corresponding to the second transition case. The design method according to claim 3 , further comprising: a second chip model creation step of creating. When creating a model for power supply voltage fluctuation,
In the first chip model creating step , the arithmetic unit uses the pMOS circuit impedance corresponding to the pMOS circuit in the on state and uses the nMOS circuit impedance corresponding to the nMOS circuit in the off state. Create a chip model,
In the second chip model creation step , the calculation unit creates the second chip model using the pMOS circuit impedance and the nMOS circuit impedance corresponding to the pMOS circuit and the nMOS circuit , both of which are on. ,
The design method according to claim 4 . The on-state pMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in parallel between the power supply pad and the output pad,
The off-state nMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in series between the output pad and the ground pad.
The design method according to claim 5, wherein the on-state nMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in parallel between the output pad and the ground pad. In the first chip model creation step, the calculation unit connects the predetermined external load model between the output pad and the ground pad, and then the impedance of the predetermined external load model is in an off state. Assuming that it is much smaller than the nMOS circuit impedance corresponding to the circuit, most of the current flowing through the power supply pad in the first transition case is the pMOS circuit impedance corresponding to the pMOS circuit in the on state and the predetermined The first current source is calculated by flowing into the external load model of
In the second chip model creation step, the computing unit connects the predetermined external load model between the output pad and the ground pad, and the impedance of the predetermined external load model is in an ON state. Assuming that it is much larger than the nMOS circuit impedance corresponding to the nMOS circuit, most of the current flowing through the power supply pad in the second transition case is substantially equal to the pMOS circuit impedance corresponding to the on-state pMOS circuit. Flow into the nMOS circuit impedance corresponding to the nMOS circuit in the state, and calculate the second current source;
The design method according to claim 5 or 6 . When creating a model for GND voltage fluctuation,
In the first chip model creation step , the calculation unit creates the first chip model using the pMOS circuit impedance and the nMOS circuit impedance corresponding to the pMOS circuit and the nMOS circuit , both of which are in the on state. ,
In the second chip model creating step , the arithmetic unit uses the pMOS circuit impedance corresponding to the pMOS circuit in the off state and uses the nMOS circuit impedance corresponding to the nMOS circuit in the on state. Create a chip model,
Design method according to any one of claims 4 to 7. The on-state pMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in parallel between the power supply pad and the output pad,
The off-state pMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in series between the power supply pad and the output pad,
The design method according to claim 8, wherein the on-state nMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in parallel between the output pad and the ground pad. In the first chip model creation step, the computing unit connects a predetermined external load model between the output pad and the ground pad, and the impedance of the predetermined external load model is on. Assuming that it is much larger than the nMOS circuit impedance corresponding to the circuit, most of the current flowing through the ground pad in the first transition case is the pMOS circuit impedance corresponding to the pMOS circuit in the on state and the on state. A current flowing through the nMOS circuit impedance corresponding to the nMOS circuit, and calculating the first current source,
In the second chip model creation step, the computing unit connects the predetermined external load model between the output pad and the ground pad, and the impedance of the predetermined external load model is in an off state. Assuming that it is much smaller than the pMOS circuit impedance corresponding to the pMOS circuit, most of the current flowing through the ground pad in the second transition case is the nMOS circuit impedance corresponding to the nMOS circuit in the on state and the The second current source is calculated by flowing through a predetermined external load model.
The design method according to claim 8 or 9 . Prior hexane out step, the arithmetic unit is connected to the first chip model and the adjustment target system impedance model, by solving the closed circuit equation, while calculating the first voltage fluctuation of power supply / GND Spectrum The second power supply / GND voltage fluctuation spectrum is calculated by connecting the adjustment target system impedance model and the second chip model and solving a closed circuit equation.
Design method according to any one of claims 1 to 10. The adjustment target system includes an electrical component on a printed wiring board on which the semiconductor package is mounted,
The adjustment target system impedance model is created on the assumption of the adjustment target system.
Design method according to any one of claims 1 to 11. In the design guideline determination step , the calculation unit sets the design target part as a part to be adjusted corresponding to a frequency part where the selected power supply / GND voltage fluctuation spectrum exceeds the constraint value. Determine the guidelines,
Design method according to any one of claims 1 to 12. A design support system for a semiconductor package including a semiconductor chip,
A chip model providing unit that provides a first chip model and a second chip model that are different from each other, wherein the output value of the semiconductor chip transitions from a low level to a high level in the first chip model and the second chip model. A chip that is a model created by expressing the semiconductor chip in the frequency domain in correspondence with each of two transition cases, a first transition case and a second transition case that transitions from a high level to a low level. A model provider,
An impedance model providing unit that provides an adjustment target system impedance model that expresses an adjustment target system including an adjustment target component of components other than the semiconductor chip in the semiconductor package in a frequency domain;
A first power supply that is a power supply / GND voltage fluctuation spectrum in each of the first transition case and the second transition case by connecting each of the first chip model and the second chip model to the adjustment target system impedance model. a calculation output section you calculate a / GND voltage fluctuation spectrum and the second voltage fluctuation of power supply / GND spectrum,
And that selection selecting section to select one of the first voltage fluctuation of power supply / GND spectrum and the second voltage fluctuation of power supply / GND spectrum,
A constraint value providing unit that provides a predetermined constraint value in the frequency domain;
The restriction value is compared with the selected power supply / GND voltage fluctuation spectrum of the first power supply / GND voltage fluctuation spectrum and the second power supply / GND voltage fluctuation spectrum, and the adjustment target system is based on the comparison result. A design support information determination unit for determining design support information for
A design support system comprising: a display unit that displays the design support information. Before cyclohexene selecting section, the first voltage fluctuation of power supply / GND spectrum and the second power supply / GND power supply information indicating the selected one of the voltage fluctuation spectrum with respect to the constraint value providing unit / GND voltage fluctuation spectrum Output as selection information,
The constraint value providing unit includes:
A constraint value holding unit that holds at least a first constraint value that is a constraint value set assuming the first transition case and a second constraint value that is a constraint value set assuming the second transition case; ,
In accordance with the power supply / GND voltage fluctuation spectrum selection information, either the first constraint value or the second constraint value related to the transition case corresponding to the selected power supply / GND voltage fluctuation spectrum is determined in the design guideline determination unit. The design support system of Claim 14 provided with the constraint value selection part selected as the said predetermined constraint value used for the said comparison. The semiconductor chip includes a power supply pad and a ground pad, an output part composed of a pMOS circuit and an nMOS circuit connected between the power supply pad and the ground pad, an output pad drawn from a connection part with the pMOS circuit and the nMOS circuit, And an internal component represented by an internal impedance inserted in parallel with the output unit between the power supply pad and the ground pad,
The chip model providing unit includes:
An output impedance obtained by connecting a pMOS circuit impedance and an nMOS circuit impedance representing impedance of the pMOS circuit and the nMOS circuit in series and an internal impedance are connected in parallel between the power supply pad and the ground pad. In addition, the first chip model is obtained by connecting a first current source, which is a current source in consideration of a fluctuation current value in the first transition case, in parallel to the pMOS circuit impedance corresponding to the first transition case. A first chip model creation unit to be created;
An output impedance obtained by connecting a pMOS circuit impedance and an nMOS circuit impedance representing impedance of the pMOS circuit and the nMOS circuit in series and an internal impedance are connected in parallel between the power supply pad and the ground pad. In addition, the second chip model is obtained by connecting a second current source, which is a current source considering the fluctuation current value in the second transition case, in parallel to the nMOS circuit impedance corresponding to the second transition case. The design support system according to any one of claims 14 to 15, further comprising: a second chip model creation unit to create. The first chip model creation unit uses the pMOS circuit impedance corresponding to the pMOS circuit in the on state and the nMOS circuit impedance corresponding to the nMOS circuit in the off state when creating a model for power supply voltage fluctuation The first chip model is created using
The second chip model creation unit uses the pMOS circuit impedance and the nMOS circuit impedance corresponding to the pMOS circuit and the nMOS circuit, both of which are turned on, when creating a model for power supply voltage fluctuation, Create a second chip model,
The design support system according to claim 16 . The on-state pMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in parallel between the power supply pad and the output pad,
The off-state nMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in series between the output pad and the ground pad.
18. The design support system according to claim 17, wherein the on-state nMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in parallel between the output pad and the ground pad. . The first chip model creating unit connects a predetermined external load model between the output pad and the ground pad when creating a model for power supply voltage fluctuation, and then determines the predetermined external load model. Assuming that the impedance is much smaller than the nMOS circuit impedance corresponding to the nMOS circuit in the off state, most of the current flowing through the power supply pad in the first transition case corresponds to the pMOS circuit in the on state. The pMOS circuit impedance and the predetermined external load model are assumed to flow, and the first current source is calculated.
The second chip model creation unit connects the predetermined external load model between the output pad and the ground pad when generating a model for power supply voltage fluctuation, and then the predetermined external load model Assuming that the impedance of the nMOS circuit is much larger than the nMOS circuit impedance corresponding to the nMOS circuit in the on state, most of the current flowing through the power supply pad corresponds to the pMOS circuit in the on state in the second transition case. The second current source is calculated by flowing into the pMOS circuit impedance and the nMOS circuit impedance corresponding to the on-state nMOS circuit.
The design support system according to claim 17 or claim 18 . The first chip model creation unit uses the pMOS circuit impedance and the nMOS circuit impedance corresponding to the pMOS circuit and the nMOS circuit, both of which are turned on, when creating a model for GND voltage fluctuation, Create the first chip model,
The second chip model creating unit uses the pMOS circuit impedance corresponding to the pMOS circuit in the off state and the nMOS circuit impedance corresponding to the nMOS circuit in the on state when creating a model for GND voltage fluctuation. The second chip model is created using
The design support system according to any one of claims 16 to 19 . The on-state pMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in parallel between the power supply pad and the output pad,
The off-state pMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in series between the power supply pad and the output pad,
The design support system according to claim 20, wherein the on-state nMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in parallel between the output pad and the ground pad. . The first chip model creation unit connects a predetermined external load model between the output pad and the ground pad when creating a GND voltage variation model, and then determines the predetermined external load model. Assuming that the impedance is much larger than the nMOS circuit impedance corresponding to the nMOS circuit in the on state, most of the current flowing through the ground pad in the first transition case corresponds to the pMOS circuit in the on state. The first current source is calculated by flowing into the nMOS circuit impedance corresponding to the pMOS circuit impedance and the nMOS circuit in the on state.
The second chip model creation unit connects the predetermined external load model between the output pad and the ground pad when creating a GND voltage variation model, and then the predetermined external load model. Assuming that the impedance of the pMOS circuit is much smaller than the pMOS circuit impedance corresponding to the pMOS circuit in the off state, most of the current flowing through the ground pad in the second transition case corresponds to the nMOS circuit in the on state. The nMOS circuit impedance and the predetermined external load model are assumed to flow, and the second current source is calculated.
The design support system according to claim 20 or claim 21 . Before hexane detecting section, and connect the first chip model and the adjustment target system impedance model, by solving the closed circuit equation, while calculating the first voltage fluctuation of power supply / GND spectrum, the adjustment object system Calculating the second power supply / GND voltage fluctuation spectrum by connecting an impedance model and the second chip model and solving a closed circuit equation;
The design support system according to any one of claims 14 to 22 . The adjustment target system includes an electrical component on a printed wiring board on which the semiconductor package is mounted,
The adjustment target system impedance model is created on the assumption of the adjustment target system.
The design support system according to any one of claims 14 to 23 . The design support information determination unit determines the design support information by using a part of the adjustment target system corresponding to a frequency portion where the selected power supply / GND voltage fluctuation spectrum exceeds the constraint value as an adjustment target part. To
The design support system according to any one of claims 14 to 24 . A program for causing a computer unit to perform predetermined processing in a computer system including a calculation unit, a storage unit, and a display unit, and causing the computer system to function as a design support system for a semiconductor package including a semiconductor chip. ,
The predetermined process is:
A calculated output step you calculate a first voltage fluctuation of power supply / GND spectrum and the second voltage fluctuation of power supply / GND spectrum based on the mutually different first chip model and a second chip model and adjusted based impedance model, the first The one-chip model and the second chip model include two transition cases, a first transition case in which the output value of the semiconductor chip transitions from a low level to a high level and a second transition case in which the output value transitions from a high level to a low level. It is a model created so as to represent the semiconductor chip in the frequency domain in correspondence with each, and the adjustment target system impedance model is an adjustment target configuration among components other than the semiconductor chip in the semiconductor package Created to express the adjustment target system consisting of elements in the frequency domain. A model, the first voltage fluctuation of power supply / GND spectrum and said second voltage fluctuation of power supply / GND spectrum is voltage fluctuation of power supply / GND spectrum at each of the said first transition case the second transition case, calculation Step out,
A selection step you select one of the first voltage fluctuation of power supply / GND spectrum and the second voltage fluctuation of power supply / GND spectrum,
By comparing the selected voltage fluctuation of power supply / GND spectrum of predetermined constraint value and the first voltage fluctuation of power supply / GND spectrum and said second voltage fluctuation of power supply / GND spectrum in the frequency domain, the comparison result Design support information determination step for determining design support information for the adjustment target system based on
A display step of displaying the design support information on the display unit. The storage unit holds at least a first constraint value that is a constraint value set assuming the first transition case and a second constraint value that is a constraint value set assuming the second transition case. Has been
The predetermined process is either before the first constraint of transitions case corresponding to the selected voltage fluctuation of power supply / GND spectrum by hexene-option step or the second constraint value, in the design guideline decision step Further comprising a constraint value selection step of selecting the predetermined constraint value used for the comparison.
The program according to claim 26 . The predetermined processing is based on the chip model creation step of creating the first chip model and the second chip model based on the semiconductor chip information on the semiconductor chip, and on the adjustment target system information on the adjustment target system, An impedance model creating step of creating the adjustment target system impedance model,
Before hexane output step, connecting said first chip model to the adjustment target system impedance model the second chip model to calculate the first voltage fluctuation of power supply / GND spectrum connected to the adjustment target system impedance model And calculating the second power supply / GND voltage fluctuation spectrum .
The program according to any one of claims 26 to 27 . The semiconductor chip includes a power supply pad and a ground pad, an output part composed of a pMOS circuit and an nMOS circuit connected between the power supply pad and the ground pad, an output pad drawn from a connection part with the pMOS circuit and the nMOS circuit, And an internal component represented by an internal impedance inserted in parallel with the output unit between the power supply pad and the ground pad,
The chip model creation step includes
An output impedance obtained by connecting a pMOS circuit impedance and an nMOS circuit impedance representing impedance of the pMOS circuit and the nMOS circuit in series and an internal impedance are connected in parallel between the power supply pad and the ground pad. In addition, the first chip model is obtained by connecting a first current source, which is a current source in consideration of a fluctuation current value in the first transition case, in parallel to the pMOS circuit impedance corresponding to the first transition case. A first chip model creation step to be created;
An output impedance obtained by connecting a pMOS circuit impedance and an nMOS circuit impedance representing impedance of the pMOS circuit and the nMOS circuit in series and an internal impedance are connected in parallel between the power supply pad and the ground pad. In addition, the second chip model is obtained by connecting a second current source, which is a current source considering the fluctuation current value in the second transition case, in parallel to the nMOS circuit impedance corresponding to the second transition case. The program according to claim 28 , further comprising: a second chip model creating step for creating. The first chip model creating step uses the pMOS circuit impedance corresponding to the pMOS circuit in the on state and the nMOS circuit impedance corresponding to the nMOS circuit in the off state when creating a model for power supply voltage fluctuation. The first chip model is created using
The second chip model creating step uses the pMOS circuit impedance and the nMOS circuit impedance corresponding to the pMOS circuit and the nMOS circuit, both of which are turned on, when creating a model for power supply voltage fluctuation, Create a second chip model,
30. The program according to claim 29 . The on-state pMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in parallel between the power supply pad and the output pad,
The off-state nMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in series between the output pad and the ground pad.
The program according to claim 30, wherein the on-state nMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in parallel between the output pad and the ground pad. In the first chip model creation step, when creating a model for power supply voltage fluctuation, a predetermined external load model is connected between the output pad and the ground pad, and then the predetermined external load model Assuming that the impedance is much smaller than the nMOS circuit impedance corresponding to the nMOS circuit in the off state, most of the current flowing through the power supply pad in the first transition case corresponds to the pMOS circuit in the on state. The pMOS circuit impedance and the predetermined external load model are assumed to flow, and the first current source is calculated.
The second chip model creation step includes the step of connecting the predetermined external load model between the output pad and the ground pad when generating a model for power supply voltage fluctuation, and then the predetermined external load model. Assuming that the impedance of the nMOS circuit is much larger than the nMOS circuit impedance corresponding to the nMOS circuit in the on state, most of the current flowing through the power supply pad corresponds to the pMOS circuit in the on state in the second transition case. The second current source is calculated by flowing into the pMOS circuit impedance and the nMOS circuit impedance corresponding to the on-state nMOS circuit.
The program according to claim 30 or 31 . The first chip model creating step, when creating a model for power supply voltage fluctuation, Fourier transforms a current waveform obtained by performing a transient analysis on the SPICE model related to the semiconductor chip with respect to the first transition case, Calculating a spectrum of current flowing through the power pad in the first transition case;
The second chip model creating step, when creating a model for power supply voltage fluctuation, Fourier transforms the current waveform obtained by performing a transient analysis on the SPICE model related to the semiconductor chip with respect to the second transition case, The program according to claim 32 , wherein a spectrum of a current flowing through the power supply pad is calculated in a second transition case. The first chip model creation step uses the pMOS circuit impedance and the nMOS circuit impedance corresponding to the pMOS circuit and the nMOS circuit, both of which are in an on state when creating a model for GND voltage fluctuation, Create the first chip model,
The second chip model creating step uses the pMOS circuit impedance corresponding to the pMOS circuit in the off state and the nMOS circuit impedance corresponding to the nMOS circuit in the on state when creating a model for GND voltage fluctuation. The second chip model is created using
The program according to any one of claims 29 to 33 . The on-state pMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in parallel between the power supply pad and the output pad,
The off-state pMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in series between the power supply pad and the output pad,
The program according to claim 34, wherein the on-state nMOS circuit impedance is calculated using an equivalent circuit model in which a capacitor and a resistor are connected in parallel between the output pad and the ground pad. In the first chip model creation step, when creating a model for GND voltage variation, a predetermined external load model is connected between the output pad and the ground pad, and then the predetermined external load model Assuming that the impedance is much larger than the nMOS circuit impedance corresponding to the nMOS circuit in the on state, most of the current flowing through the ground pad in the first transition case corresponds to the pMOS circuit in the on state. The first current source is calculated by flowing into the nMOS circuit impedance corresponding to the pMOS circuit impedance and the nMOS circuit in the on state.
In the second chip model creation step, when creating a model for GND voltage fluctuation, the predetermined external load model is connected between the output pad and the ground pad, and then the predetermined external load model is connected. Assuming that the impedance of the pMOS circuit is much smaller than the pMOS circuit impedance corresponding to the pMOS circuit in the off state, most of the current flowing through the ground pad in the second transition case corresponds to the nMOS circuit in the on state. The nMOS circuit impedance and the predetermined external load model are assumed to flow, and the second current source is calculated.
36. The program according to claim 34 or claim 35 . In the first chip model creation step, when a model for GND voltage fluctuation is created, the current waveform obtained by performing a transient analysis on the SPICE model related to the semiconductor chip with respect to the first transition case is Fourier-transformed, Calculating the spectrum of the current flowing through the ground pad in the first transition case;
In the second chip model creation step, when a model for GND voltage fluctuation is created, the current waveform obtained by performing a transient analysis on the SPICE model related to the semiconductor chip with respect to the second transition case is Fourier-transformed, The program according to claim 36 , wherein a spectrum of a current flowing through the ground pad is calculated in a second transition case. Before hexane output step is to connect the first chip model and the adjustment target system impedance model, by solving the closed circuit equation, while calculating the first voltage fluctuation of power supply / GND spectrum, the adjustment object system Calculating the second power supply / GND voltage fluctuation spectrum by connecting an impedance model and the second chip model and solving a closed circuit equation;
The program according to any one of claims 26 to 37 . The adjustment target system includes an electrical component on a printed wiring board on which the semiconductor package is mounted,
The adjustment target system impedance model is created on the assumption of the adjustment target system.
The program according to any one of claims 26 to 38 . In the design support information determining step, the design support information is determined by using a part of the adjustment target system corresponding to a frequency portion where the selected power supply / GND voltage fluctuation spectrum exceeds the constraint value as an adjustment target part. To
40. The program according to any one of claims 26 to 39 .

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