JP4517056B2 - DC-DC converter - Google Patents

Description

  The present invention relates to a DC-DC converter, and relates to a current detection circuit and a slope compensation circuit suitable for a current feedback type DC-DC converter circuit.

  Conventionally, a current feedback type DC-DC converter circuit of the type shown in Non-Patent Document 1 has been proposed and used. In the current feedback type DC-DC converter circuit shown in Non-Patent Document 1, a circuit configuration as shown in FIG. 2 is used, and a constant output voltage with high stability is always generated.

In FIG. 2, Vin is an input voltage applied to the DC-DC converter, Vout is an output voltage of the DC-DC converter, and RL is obtained by replacing the load with a resistor. In the figure, a step-down type with Vin ≧ Vout is realized. In this case, the transistor 10 (Q1) becomes conductive in a part of the period T (D × T, D is duty). Here, T is the oscillation period of the oscillator 210 (OSC). When the transistor 10 (Q1) is turned on, the current I _Lf flows through the transistor 10 (Q1) and the inductor element 12 (L), and at the same time, the inductor element 12 (L) is charged with energy. since in the state Vin and Vout is constant, the average voltage applied across the inductor element 12 (L) is constant, the current of the inductor element 12 (L) in this period, the current I _L flowing through the load R _L As a value, the waveform increases with time.

On the other hand, between the time (D × T) and T, the transistor 10 (Q1) is turned off and the diode 11 (D) is turned on. At this time, the current I _Lb flows in the direction shown in the figure through the diode 11 (D) and the inductor element 12 (L), and the energy stored in the inductor element 12 (L) is discharged. Also in this case, the voltage applied to both ends of the inductor element 12 (L) is constant, and the current of the inductor element 12 (L) has a waveform that decreases with time, with the current flowing through the load RL as an average value.

  As described above, within one oscillation period T of the oscillator 210 (OSC), the inductor element 12 (L) is charged with energy from the input terminal, and the accumulated energy is discharged within the remaining time, and the energy is applied to the load RL. Delivered. Since this operation is repeated only once the oscillation frequency of the OSC per second, a large load current can be supplied even if the energy transfer in one cycle is small, or the inductance value of the inductor element 12 (L) can be reduced. It can be done.

  This energy transfer is controlled by a negative feedback loop. For example, when the load resistance becomes small (corresponding to the case where the load current increases and the power consumption at the load becomes large), the discharge of the accumulated energy becomes large, so that the charged energy is also large. Must. However, the charged energy ratio is always constant as long as the voltage across the inductor element 12 (L) does not change. The only way to increase the energy charged is to increase the charging time.

  In FIG. 2, the information that the power consumption at the load has increased (the load current has increased) can be obtained by amplifying the difference voltage between the Vout voltage and the reference voltage by the error amplifier 300. When the load current increases and the Vout voltage decreases slightly, the output voltage Ve of the error amplifier 300 increases.

  In FIG. 2, OSC (210) serves to supply the latch 220 with a set pulse for starting the charging time every time T, and the output of the comparator 230 outputs a reset pulse for ending the charging time. It serves to supply the latch 220. If Ve becomes large, the voltage of the negative phase input terminal (indicated by −) of the comparator 230 becomes large. Therefore, if the voltage Vs of the positive phase input terminal (indicated by +) of the comparator 230 is also large, the reset pulse Cannot be generated. Vs is created by supplying a current proportional to the current flowing through the inductor element 12 (L) to the resistance element 250 (Rs). Since the current increases at a constant rate during the charging time, a reset pulse is output from the comparator 230 to the latch 220 at the moment when the value of Vs becomes larger than the voltage of the negative phase input terminal of the comparator 230. However, when Ve is large, it is necessary to increase the value of Vs by extending the charging time. Accordingly, the charging period is increased, and as a result, the charged energy is increased. As the charged energy increases, the load current also increases, resulting in an increase in Vout. With the above operation, the Vout voltage is kept constant even when the power consumption at the load increases.

However, in order to generate Vs, it is necessary to generate a current I _LP that is proportional to the current flowing through the inductor element 12 (L) during the charging period. Since the current flowing through the inductor element 12 (L) and the current flowing through the transistor 10 (Q1) are equal during the charging period, in general, a resistance element is connected in series with the transistor 10 (Q1), and the voltage at both ends thereof is used. For example, a method of generating Vs, or a method of using a current flowing in a similar transistor connected in parallel to the transistor 10 (Q1).

  In this case, however, a large current having the same level as the load current flows through the inserted resistance element. When the load current is large, the value of the load 100 (RL) is small. Therefore, even if the resistance value of the resistor element is small, the resistance ratio with respect to the load is relatively large. Therefore, the load 100 (RL) The ratio of the power consumption of the resistance element is larger than that of the power consumption. This corresponds to a reduction in the efficiency of the DC-DC converter, and it is necessary to take out a current proportional to the current flowing through the inductor element 12 (L) without inserting a resistor.

  In the method of connecting similar transistors in parallel, the transistor 10 (Q1) is in an on state (operating in a linear region) during the charging period, and the similar transistors connected in parallel are saturated to obtain the current output. Since the operation is performed in the region, the operation regions of the two transistors are different. Therefore, the current flowing through the similar transistor is different from the current of the transistor 10 (Q1), that is, the current of the inductor element 12 (L).

  Furthermore, as shown in Non-Patent Document 1 and FIG. 3, the following stability problem occurs in the configuration of FIG.

3 shows that the output voltage Ve of the error amplifier 300 in FIG. 2, the slope compensation voltage Vc, and the current I _LP proportional to the current flowing through the inductor element 12 (L) (where the proportionality constant is K) is the resistance 250 (Rs). This shows the mutual relationship with the voltage Vs generated by flowing through the. However, the current I _LP flows through the resistor 250 (Rs) only during the charging period. However, the operation of the entire system in FIG. 2 is the current flowing through the inductor element 12 (L) during the entire period. Therefore, for the purpose of discussing the stability of the system, as shown in FIG. 3, a current similar to the current flowing through the inductor element 12 (L) in the entire period of one cycle is considered, and this is the resistance 250 ( Rs) is considered to be generated as a voltage Vs.

In particular, in FIG. 3A, if the slope compensation voltage Vc is not introduced, the ratio (referred to as duty (D)) between the period of charging and the time T of one cycle of charging / discharging exceeds 50%. It is a figure which shows that stability of a system is impaired in a case. In this case, it is assumed that the voltage applied to both ends of the inductor element 12 (L) is constant for each of the charging period and the discharging period. The solid line in FIG. 3 (a) shows the voltage waveform across the resistor (ie, Vs) when a current I _LP similar to the current of the inductor element 12 (L) flows through the resistor Rs during the entire period of one cycle. Represents. The waveform of the actual I _LP, as described above, in the form of only the current flows period for charging, which is a waveform shown in FIG.

で表され、時間と共に直線的に増加する電流となるので、インダクタ素子Ｌ（１２）に流れる電流に比例した電流I_LPが流れて発生するVsの電圧も、図３（a）のように直線的に上昇する形となる。ただし（１）式のI_L0は、時刻ゼロにおけるインダクタ素子１２（L）の電流を表わしている。この時のVsの傾きｍ１は、該電流の増加の割合をK倍したものであるから、

である。 In FIG. 2, the transistor 10 (Q1) is turned on at time zero. At this time, in FIG. 3A, Vs is at a lower voltage level than Ve. In FIG. 2, when the transistor 10 (Q1) is turned on, current is supplied from the Vin to the inductor element 12 (L). This current I _Lf is assumed that the voltage at the emitter terminal of the transistor 10 (Q1) matches Vin. If

Since the current increases linearly with time, the voltage Vs generated when the current I _LP proportional to the current flowing through the inductor element L (12) flows is also a straight line as shown in FIG. Ascending form. However, I _L0 in the expression (1) represents the current of the inductor element 12 (L) at time zero. Since the slope m1 of Vs at this time is obtained by multiplying the rate of increase of the current by K,

It is.

  In this way, Vs continues to increase with time, and becomes the same voltage as Ve after time D × T. When Vs becomes the same voltage as Ve, the output of the comparator 230 is inverted in FIG. 2, and the previous logic 0 state changes to the logic 1 state, so that a pulse is input to the reset terminal (R) of the latch 220. As a result, the output of the latch 220 changes to a logic 0 state, and the transistor 10 (Q1) turns off.

When the transistor 10 (Q1) is turned off, I _LP does not flow, so the voltage of Vs returns to 0 and the output of the comparator 230 returns to the logic 0 state again as shown in FIG. Is not changed and is maintained in a logic 0 state, so that the transistor 10 (Q1) remains off from time D × T until T.

となる。ただしI_LDTは時刻D×Tにおけるインダクタ素子１２（L）の電流を示す。（３）式より、I_Lbは時間と共に減少する電流である事がわかる。この減少する電流に比例する電流が図２の抵抗Rsに流れたと考えて、Vsの変化を模擬的に図３（a）上に描くと、図３（a）の傾きｍ２を持つ直線となる。 Immediately after the transistor 10 (Q1) is turned off, the inductor element 12 (L) has energy stored during the charging period. This energy becomes _ILb in FIG. 2 and is discharged during the period T after time D × T, which is a period in which the transistor 10 (Q1) is off. If I _Lb is constant Vout and the voltage drop due to the diode 11 (D) can be ignored,

It becomes. However, I _LDT indicates the current of the inductor element 12 (L) at time D × T. From equation (3), it can be seen that I _Lb is a current that decreases with time. Assuming that a current proportional to the decreasing current flows through the resistance Rs in FIG. 2, if a change in Vs is simulated on FIG. 3A, a straight line having an inclination m2 in FIG. 3A is obtained. .

で表される形である。 Therefore m2 is

It is a form represented by

Note that the average value of I _Lf and I _{Lb in} FIG. 2 in one cycle T is equal to the current I _RL flowing through the load 100 (RL). Since I _Lf and I _Lb are monotonically increasing and decreasing currents, there is a difference from the average value at each time. This difference is charged to the capacitor 13 (C) or supplied from the capacitor 13 (C). The The charge in and out of the capacitor 13 (C) in the steady state is zero when considered in one cycle.

  The above operation is repeated, and the circuit of FIG. 2 continues to supply a constant current to the load 100 (RL).

  Let us consider a case where the current flowing through the inductor element 12 (L) fluctuates by ΔI0 for some reason (such as a change in the load current) at time zero. In this case, the voltage of Vs in FIG. 2 changes like a waveform indicated by a dotted line in FIG. That is, Vs changes by the voltage of K · ΔI0 · Rs. However, even if the inductor current fluctuates, the output voltage does not fluctuate greatly, and the voltage across the inductor is considered to be constant. Therefore, as shown in the waveform shown by the dotted line in FIG. There is no change in the value m1 proportional to the increase rate of the inductor current and the value m2 proportional to the decrease rate of the discharge period.

  Here, in FIG. 3A, the fluctuation amount K · ΔI1 · Rs from the stable state at time T after one cycle is calculated. If this value is larger than the voltage fluctuation K · ΔI0 · Rs applied at the time zero, the fluctuation becomes larger after one cycle, and the fluctuation is thought to further expand with every cycle. It is done. Therefore, it can be said that this system is unstable. On the other hand, if the fluctuation amount K · ΔI1 · Rs is smaller than the voltage fluctuation K · ΔI0 · Rs applied at the time zero, the fluctuation becomes smaller after one cycle, and the fluctuation is reduced with each cycle. . Therefore, it can be said that such a system is stable.

が成り立つ。更に（２）式および（４）式を考慮すると、

となる。（６）式は、インダクタ素子１２（Ｌ）に起こった電流変動ΔI0が１周期後には（ｍ２/ｍ１）倍だけ増幅されてΔI1となる、という事を示している。ただし、ΔI1はΔI0の方向と逆向きとなっているので、（６）式の第２項にはマイナス符号が付く。デューティ５０％以上の場合には｜ｍ２｜＞｜ｍ１｜となるから（式（６）から考えて言い換えると、Vout＞（Vin/２）の状態）、ΔI1はΔI0より大となる事がわかる。 In FIG. 3A, using the slopes m1 and m2 of the Vs waveform and the fluctuation amount K · ΔI0 · Rs at time zero,

Holds. Furthermore, when considering the equations (2) and (4),

It becomes. The expression (6) indicates that the current fluctuation ΔI0 occurring in the inductor element 12 (L) is amplified by (m2 / m1) times and becomes ΔI1 after one cycle. However, since ΔI1 is opposite to the direction of ΔI0, a minus sign is attached to the second term of equation (6). When the duty is 50% or more, | m2 |> | m1 | is satisfied (in other words, in the state of Vout> (Vin / 2) in view of equation (6)), it can be seen that ΔI1 is larger than ΔI0. .

  This means that the current fluctuation that has occurred in the inductor element 12 (L) gradually increases as the period increases and eventually diverges, that is, the system is unstable.

  The above discussion shows that the circuit configuration of FIG. 2 is unstable and cannot be used when the duty is 50% or more. In order to solve this problem, a slope compensation voltage Vc that changes linearly with time is introduced as shown in FIG. Let the slope of the slope compensation voltage be -m (m is a positive value).

  Here, similarly to the discussion in FIG. 3A, let us consider that the current flowing through the inductor element 12 (L) fluctuates by ΔI0 for some reason (for example, the load current has changed) at time zero. In this case, the voltage Vs changes like a waveform indicated by a dotted line in FIG. That is, Vs changes by the voltage of K · ΔI0 · Rs. However, even if the inductor current fluctuates, the output voltage does not fluctuate greatly, and the voltage across the inductor is considered to be constant. Therefore, as shown in the waveform shown by the dotted line in FIG. There is no change in the value m1 proportional to the increase rate of the inductor current and the value m2 proportional to the decrease rate of the discharge period.

すなわち、

と計算される。（８）式は、インダクタ素子１２（Ｌ）に起こった電流変動ΔI0が１周期後には（ｍ２＋ｍ）/（ｍ１＋ｍ）倍だけ増幅されてΔI1となる、という事を示している。 The fluctuation amount K · ΔI1 · Rs from the stable state at time T after one cycle is obtained by using the slopes m1 and m2 of the Vs waveform, the slope −m of the Vc waveform and K · ΔI0 · Rs.

That is,

Is calculated. Equation (8) indicates that the current fluctuation ΔI0 occurring in the inductor element 12 (L) is amplified by (m2 + m) / (m1 + m) times to ΔI1 after one cycle.

であれば、ΔI1はΔI0より小さくなる。すなわち系が安定となる。実際、ｍ１とｍは正の値を取り、ｍ２は負の値をとるので、（ｍ１＋ｍ）の値はｍ１の値よりも増加し、｜ｍ２＋ｍ｜の値は｜ｍ２｜の値に比し減少する。したがってｍの値を適正に取れば、（９）式を満足させる事が出来る。（ｍ１＋ｍ）が正の値を取り、（ｍ２＋ｍ）の値が負となるとすれば、（９）式の条件は、

すなわち、

と書ける。 here,

Then, ΔI1 is smaller than ΔI0. That is, the system becomes stable. In fact, since m1 and m take positive values and m2 takes a negative value, the value of (m1 + m) increases from the value of m1, and the value of | m2 + m | decreases compared to the value of | m2 | To do. Therefore, if the value of m is properly taken, the expression (9) can be satisfied. If (m1 + m) takes a positive value and (m2 + m) takes a negative value, the condition of equation (9) is

That is,

Can be written.

とする必要がある。（１１）式および（１２）式は、デユーティに依存して必要なｍの値が変る事、およびデユーティが大となるにしたがってｍの値も増加させる必要のある事、を示している。 Since m2 = −m1 when the duty is 50%, the condition of the equation (11) is m ≧ 0, and the value of m may be zero, but when the duty is 100% (when Vin = Vout) Is equivalent to m1 = 0 from the equation (2).

It is necessary to. Expressions (11) and (12) indicate that the required value of m changes depending on the duty, and that the value of m needs to be increased as the duty increases.

However, in an actual circuit, since it is difficult to change the value of m depending on the duty, it is usually fixed to the value of m that is maximum under the use conditions.
As described above, the required value of m differs depending on the difference in the utility. Therefore, when the maximum value of m is used, the stability of the system is ensured, but the required value of m in each duty value is not provided.

  In addition, as shown in Fig. 5 of Patent Document 1, a method is used in which the value of m is changed step by step using a D / A converter or counter, as in a line graph. Yes. This is intended to provide the value of m required for each duty value, but additional functions such as D / A converters and counters are required, increasing the power consumption of the circuit, and as a DC-DC converter. Will reduce the efficiency.

"UNITRODE Application Note, U-97, 3-43 to 3-48" 1999UNITRODE CORPORATION US Pat. No. 6,177,787 “Circuits and Methods for Controlling Timing and Slope Compensation in Switching Regulators”

  As described above, in the circuit configuration of FIG. 2 and the slope compensation method of FIG. 3 proposed in Non-Patent Document 1, a switch transistor is used to detect a current proportional to the current flowing through the inductor element 12 (L). It is necessary to insert a resistor (power consumption occurs) in series with the element, or even if a similar transistor is connected in parallel, the current flowing through the inductor element 12 (L) cannot be accurately detected, and the duty changes There is a problem that it is not possible to provide the optimum slope guarantee voltage corresponding to In addition, the slope voltage waveform creation method proposed in Patent Document 1 can create a slope compensation voltage corresponding to a change in duty, but the hardware scale becomes large and extra power is generated. There are drawbacks.

  Therefore, the present invention is not a method of detecting the current flowing through the inductor element 12 (L) by connecting a resistor in series with the switching transistor element or by connecting a similar transistor in parallel, and more easily and with low power consumption. A first object is to provide means for detecting a current flowing through the inductor element 12 (L) with electric power.

  Furthermore, since the optimum value of the slope of the slope compensation voltage depends on the duty, a second object is to provide a simple means for generating a slope corresponding to a change in the duty.

  A first form of the DC-DC converter according to the present invention includes a switching transistor element having one terminal connected to an input voltage source and performing an on / off operation with or without a control input, and the other of the switching transistor elements. An output circuit having an inductor element connected between the terminal and the output terminal, a current detection circuit for detecting a current flowing through the inductor element in the output circuit and generating a current proportional to the current, and a constant A slope compensation current generating circuit that generates a current proportional to the power of the voltage that changes at a rate, and a current combined voltage generating circuit that combines the two currents and generates a voltage proportional to the combined current.

  The current detection circuit includes first and second switch elements connected in series between a connection point between the switching transistor element and the inductor element and an input voltage source, and the first and second switch elements. And amplifying means for applying a voltage change appearing at the connection point to both ends of the first impedance element, and outputting a current flowing through the first impedance element. As a result, a current proportional to the current flowing through the inductor element in the output circuit is generated.

  A second form of the DC-DC converter according to the present invention includes a switching transistor element having one terminal connected to an input voltage source and performing on / off operation with or without a control input, and the other of the switching transistor elements. An output circuit having an inductor element connected between the terminal and the output terminal, a current detection circuit for detecting a current flowing through the inductor element in the output circuit and generating a current proportional to the current, and a constant A slope compensation current generating circuit that generates a current proportional to the power of the voltage that changes at a rate, and a current combined voltage generating circuit that combines the two currents and generates a voltage proportional to the combined current.

  The slope compensation current generating circuit includes a capacitor, a potential shift element, and a current source that supplies a constant current connected in series between the input voltage source and another power source, and a third switch element connected in parallel to the capacitor. And a non-linear voltage-current conversion element that generates a current proportional to a voltage at a connection point between the potential shift element and the current source supplying the constant current and a power of a voltage change between the input voltage sources. The output current of the non-linear voltage-current conversion element is a current proportional to the power of the voltage changing at the constant rate.

  According to a third embodiment of the DC-DC converter of the present invention, a switching transistor element having one terminal connected to an input voltage source and performing an on / off operation with or without a control input, and the other of the switching transistor elements An output circuit having an inductor element connected between the terminal and the output terminal, a current detection circuit for detecting a current flowing through the inductor element in the output circuit and generating a current proportional to the current, and a constant A slope compensation current generating circuit that generates a current proportional to the power of the voltage that changes at a rate, and a current combined voltage generating circuit that combines the two currents and generates a voltage proportional to the combined current.

  The current combined voltage generation circuit supplies a combined current of the current output from the current detection circuit and the current output from the slope compensation current generation circuit to the second impedance element, and the second impedance element The voltage generated at both ends is defined as the output voltage.

  According to the present invention, with a simple circuit configuration and low power consumption, without connecting a resistor in series to the output switch transistor element, or without connecting a similar transistor in parallel to the output switch transistor element, A waveform proportional to the inductor current can be generated in the form of a voltage. In addition, it is possible to generate a slope compensation voltage such that the slope gradually increases in proportion to the duty, and the change is continuous and smooth. If these voltages are combined and used by a combining means, a DC-DC converter having characteristics such as high-speed response and stable operation can be configured.

  Hereinafter, embodiments of the present invention will be described in detail based on examples. FIG. 1 is a circuit diagram showing an embodiment of the present invention.

  In FIG. 1, transistors 10 (MP1) and 11 (MN1) are a PMOS switch transistor element and an NMOS switch transistor element of the output circuit, respectively. An external inductor element 12 (L), a capacitive element 13 (C), and a load 100 (RL) are connected to the output circuit. In FIG. 1 of the present invention, MOS transistors are used in place of the NPN switching transistor element (10) and the switching diode element (11) of FIG.

  Since the control waveforms indicated by 19 and 20 are respectively applied to the gate terminals of the transistors 10 (MP1) and 11 (MN1), the transistor 10 (MP1) is turned on during the D × T period, and the transistor 11 (MN1) ) Is off. Therefore, current flows through L from the input Vin. This period is a charging period. On the other hand, in a period excluding D × T in the period T, the transistor 10 (MP1) is turned off and the transistor 11 (MN1) is turned on. The energy stored in the inductor element 12 (L) is discharged through the load 100 (RL) and the transistor 11 (MN1) (discharge period). In FIG. 2, the Vs voltage waveform is proportional to the current flowing through the inductor element 12 (L) during the period when the transistor 10 (MP1) is on. Therefore, it is necessary to create a current proportional to the current flowing through the inductor element 12 (L) during the period.

In FIG. 1, _ID that is the output current of the current detection circuit 200 is a current proportional to the current flowing through the inductor element 12 (L). _ID is generated using the switching elements 201 (SW1) and 202 (SW2), the operational amplifier 203, the transistor 204 (MP2), and the resistance element 205 (RD) as follows.

と表す事が出来る。ここで
β＝（μ_pＣ_oχW_MP1）／（Ｌ_MP1）、μ_p：ホールの移動度、Ｃ_oχ：MP1の単位面積当りのゲート容量、W_MP1：MP1のゲート幅、Ｌ_MP1：MP1のゲート長、Ｖ_GS：MP1のゲート・ソース間電圧、V_th：MP1のスレッショルド電圧、V_DS：MP1のドレイン・ソース間電圧であり、それぞれトランジスタ１０（MP1）のデバイスパラメータおよび端子間電圧で規定される量である。 First, _note that the current I _Lf flowing through the inductor element 12 (L) during the D × T period is equal to the current flowing through the transistor 10 (MP1). The drain current I _d of the transistor 10 (MP1) during this period is that MP1 is in the on state, that is, operating in the linear region,

Can be expressed. Where β = (μ _{p Coχ} W _MP1 ) / (L _MP1 ), μ _p : hole mobility, C _oχ : gate capacitance per unit area of _MP1 , W _MP1 : gate width of _MP1 , L _MP1 : MP1 Gate length, V _GS : MP1 gate-source voltage, V _th : MP1 threshold voltage, V _DS : MP1 drain-source voltage, transistor 10 (MP1) device parameter and terminal voltage, respectively. It is a specified amount.

で計算されるが、MP1はオン状態であり、Ｖ_ＤＳ≒０と考えて良いので、

で近似される、と考えられる。ここでDC−DCコンバータの通常の使用状態（安定状態を指す）では、β、Vin、Vthpは一定であるので、Ron（MP1）も一定値となる。 At this time, the on-resistance Ron (MP1) of the transistor 10 (MP1) is V _GS = V _in .

Since MP1 is in the on state and V _DS ≈0 can be considered,

It is thought that it is approximated by. Here, in the normal use state (indicating a stable state) of the DC-DC converter, β, Vin, and Vthp are constant, so Ron (MP1) is also a constant value.

となる。ただしこの場合のLは、インダクタ素子のインダクタンスを表している。 On the other hand, since the current ILf flowing through the inductor element 12 (L) is given by the equation (1), the voltage Vo at the terminal A in FIG.

It becomes. However, L in this case represents the inductance of the inductor element.

In the normal use state (indicating a stable state) of the DC-DC converter, β, L, Vin, Vthp, and Vout in equation (16) are all constant values, and I _L0 is also a constant value determined by the load 100. Therefore, equation (16) indicates that the voltage Vo at point A drops at a constant rate with time.

で、インダクタ素子に流れる電流ILｆに比例した電圧Vs´が得られる。 When the switch element 201 (SW1) is turned on and the switch element 202 (SW2) is turned off during this period, the voltage of the positive phase input terminal (indicated by +) of the operational amplifier 203 coincides with the voltage at point A. In a circuit comprising an operational amplifier 203, a transistor element 204 (MP2), a resistance element 205 (RD), and a resistor Rs (hereinafter referred to as a resistance element 250 (Rs)) which is the only component of the current synthesis voltage generation circuit 250, First, the voltage at the positive phase input terminal of the operational amplifier 203 and the voltage at the point B that is the negative phase input terminal (indicated by −) of the operational amplifier 203 connected to the source terminal of the transistor element 204 (MP2) match. Therefore, the voltage at point B matches the voltage at point A. Second, since the current flowing through the resistance element 205 (RD) flows through the transistor element 204 (MP2) and flows into the resistance element 250 (Rs), the voltage generated when _ID flows through the resistance element 250 (Rs). Vs ′ operates so as to be multiplied by (Rs / RD) times (Vin−A point voltage Vo). That is,

Thus, a voltage Vs ′ proportional to the current ILf flowing through the inductor element is obtained.

  Note that in the discharge period in which the transistor element 11 (MN1) is turned on, the switch element 201 (SW1) is turned off and the switch element 202 (SW2) is turned on. In this case, the voltage difference between both ends of the resistance element 205 (RD) is zero, and Vs is also zero. When the transistor element 10 (MP1) switches from the off state to the on state, an excessive current flows through the transistor element 10 (MP1), and a spiked voltage may appear in the voltage Vo at the point A. Even in this case, it is not necessary to transmit such an abnormal voltage to Vs by shifting the timing of turning on the switch element 201 (SW1).

  On the other hand, the slope compensation current generation circuit 400 for generating the slope compensation voltage includes a capacitive element 401 (Cs), a switch element 402 (SW3), an offset voltage source 403 (Vof), a constant current source 404 (Ic), and a transistor element. 405 (MP3). The output of the slope compensation current generation circuit 400 is a current Is, and this current flows through the resistance element 250 (Rs) to generate a voltage corresponding to the slope compensation that is a part of Vs.

である。このVcsとオフセット電圧源４０３（Vof）の電圧の和が、トランジスタ素子４０５（MP3）のゲート・ソース間に加わるので、トランジスタ素子４０５（MP3）が飽和領域で動作する事を仮定すると、スロープ補償電流発生回路４００の出力電流I_sは、

となり、時間と共に増加する２次曲線となる。 The switch element 402 (SW3) is a switch that is turned off during the charging period of the inductor current and turned on during the discharging period. When the switching element 402 (SW3) is turned off during the charging period in which the transistor element 10 (MP1) is turned on, the current of the constant current source 404 (Ic) flows to the capacitive element 401 (Cs), and the capacitive element 401 (Cs ) Increases linearly with time. The voltage difference Vcs at both ends is

It is. Since the sum of the voltage Vcs and the voltage of the offset voltage source 403 (Vof) is applied between the gate and the source of the transistor element 405 (MP3), assuming that the transistor element 405 (MP3) operates in the saturation region, slope compensation is performed. output current I _s of the current generation circuit 400,

It becomes a quadratic curve that increases with time.

However, β _MP3 = (μ _{p Coχ} W _MP3 ) / (L _MP3 ), μ _p : hole mobility, C _oχ : gate capacitance per unit area of _MP3 , W _MP3 : gate width of _MP3 , L _MP3 : MP3 gate length, V _th : MP3 threshold voltage, which is a device parameter of the transistor 405 (MP3).

Since I _s is supplied to the resistive element 250 (Rs), as the slope compensation voltage of the Vs, the shape of the voltage waveform of the secondary curve is obtained. Since the slope of the quadratic curve increases with time, the slope of the slope voltage also increases with time.

  When the above results are combined, a desired voltage waveform as shown in FIG. 4 is obtained as Vs.

  As described above, according to the configuration of FIG. 1, a simple circuit configuration and low power consumption can be obtained without connecting a resistor in series with the output switch transistor element or in parallel with the output switch transistor element. It can be seen that a waveform proportional to the inductor current can be generated in the form of a voltage without connecting a transistor. It can also be seen that it is possible to generate a slope compensation voltage whose slope gradually increases in proportion to the duty, and whose change is continuous and smooth. A DC-DC converter with features such as high-speed response and stable operation is constructed using the voltage obtained by combining these voltages.

  Next, an example in which a step-down DC-DC converter IC is actually constructed using the current detection circuit 200 and the slope compensation current generation circuit 400 of FIG. 1 of the present invention will be described. This is shown in FIG. FIG. 5 shows an output switching transistor element 10 (MP1), a transistor 11 (MN1), an error amplifier 300 having a resistance element 22 (Rf) and a capacitance element 23 (Cf) in a feedback circuit, and a reference voltage source 21. (VREF), the oscillator 210 (OSC), the flip-flop 220 (FF1), the comparator 230, the current detection circuit 200 of the present invention, the slope compensation current generation circuit 400, and the resistance element 250 ( Rs). As an output circuit, a voltage divider composed of an inductor 12 (L), a capacitor 13 (C), a load 100 (RL), and resistive elements 14 (R1) and 15 (R2) is assumed as an external circuit.

  In the DC-DC converter shown in FIG. 5, the flip-flop 220 (FF1) is set by the output of the oscillator 210 (OSC) having the period T. As a result, the Q / output becomes low and the transistor 10 (MP1) is turned on. The charging period begins. At this time, the transistor 11 (MN1) is turned off. The Q / output of the flip-flop 220 (FF1) is applied to both the gate terminal of the transistor 10 (MP1) and the gate terminal of the transistor 11 (MN1), but the transistor 10 (MP1) and the transistor 11 (MN1) At the same time, the Q / signal is slightly delayed to prevent the through current from flowing from Vin to the ground terminal. The reason why the two Q / and Q / 'signals are output from the flip-flop 220 (FF1) is to distinguish them.

  Simultaneously with the start of the charging period, the current detection circuit 200 and the slope compensation current generation circuit 400 operate, and the voltage Vs across the resistance element 250 (Rs) also begins to rise. On the other hand, a voltage obtained by dividing the voltage Vout across the load 100 (RL) by the resistance elements 14 (R1) and 15 (R2) is compared with the voltage of the reference voltage source 21 (VREF) and amplified by the error amplifier 300. Is input to the negative phase input terminal (indicated by-) of the comparator 230. When the voltage Vs across the resistance element 250 (Rs) rises and becomes higher than the voltage Ve applied to the negative phase input terminal (indicated by −) of the comparator 230, the comparator 230 causes the flip-flop 220 ( Reset pulse is input to FF1). When the reset pulse is input, the Q / output and Q / ′ output of the flip-flop 220 (FF1) become high, so that the transistor 10 (MP1) is turned off and the transistor 11 (MN1) is turned on. No. 5 DC-DC converter enters a discharge period. There is no output current from the current detection circuit 200 and the slope compensation current generation circuit 400 during this discharge period. Although the output of the comparator 230 is low, the output of the flip-flop 220 (FF1) is not changed, so that the next trigger pulse is sent from the oscillator 210 (OSC) to the flip-flop 220 (FF1) during the discharge period. Continue until entered.

  The above operation is repeated, and the DC-DC converter of FIG. 5 continues to supply a stable current to the load 100 (RL).

The operation of the DC-DC converter of FIG. 5 incorporating the circuit of the present invention of FIG. 1 was confirmed by SPICE circuit simulation. This is shown in FIG. The device parameters of the transistors were those of CMOS elements with a design rule of 0.6 μm. Vin was 3.6V and Vout was 2.5V. The parameter values of each element in FIG. 5 are as follows.
fosc = 4 MHz (T = 250 nS), L = 2.2μH, C = 10μF, RL = 20Ω, R1 = 400 kΩ, R2 = 100 kΩ, VREF = 0.5 V, Rf = 1,200 kΩ, Cf = 20 pF, Rs = 30 kΩ.

  FIG. 6A shows the waveform of Vo, which is the voltage at point A in FIG. 5, and the Vout waveform. In the Vo waveform, the portion where the voltage is high indicates a charging period in which the transistor 10 (MP1) is on and energy is stored in the inductor element 12 (L). The low voltage portion corresponds to the discharge period when the transistor 11 (MN1) is in the on state. It can be seen that the charging period is longer than the discharging period, and in this case, the duty is 50% or more. In the high voltage portion of the charging period, the voltage decreases linearly with time. This is as shown in the equation (16). The Vout waveform is kept constant throughout the entire period.

  FIG. 6B shows a waveform of a current flowing through the inductor element 12 (L) in FIG. It can be seen that a stable repetitive waveform is obtained. During the charging period, the current flowing through the inductor element 12 (L) increases linearly. It can be seen that the waveform decreases linearly during the discharge period, and the waveform shown in the figure is obtained.

FIG. 6 (c) shows the Vs waveform and Ve waveform of FIG. The Vs waveform changes only during the charging period, and is kept constant during the discharging period. In the discharging period, the switch element 201 (SW1) in FIG. 1 is off and both 202 (SW2) and 402 (SW3) are on. I _D and I _s in this case in Figure 1 is entirely not become zero, so flows slight current, the voltage of Vs waveform shown in FIG. 6 (c), not zero, and small voltage appears . However, there is no change in current and the voltage value of the Vs waveform is constant. In the charging period, the Vs waveform is composed of a sum of a change in voltage proportional to the current flowing through the inductor element 12 (L) of FIG. 5 that linearly increases with time and a slope compensation voltage in the form of a quadratic curve. It can be seen that the operation of the circuit of the present invention shown in FIG. As described above, when the voltage of the Vs waveform exceeds the voltage of the Ve waveform, the reset pulse is output from the comparator 230 in FIG. 5 and the charging period ends.

  From the above, it is shown that the DC-DC converter of FIG. 5 using the circuit of the present invention of FIG. 1 operates stably even when the duty exceeds 50%. This shows the effectiveness of the inventive circuit of FIG.

  The circuit of the present invention can be applied to various configurations that require a slope current compensation circuit, such as a current mode type DC-DC converter.

It is a figure which shows the circuit structure of the slope current compensation circuit of the Example of this invention. It is a figure which shows the circuit structure of the current mode type DC-DC converter of a prior art example. It is a figure which shows the necessity of the slope compensation circuit in the current mode type DC-DC converter of a prior art example. It is a figure which shows the slope compensation voltage waveform produced | generated by the circuit of this invention. It is a figure which shows the circuit structure of the current mode type DC-DC converter of the Example to which the circuit of this invention is applied. It is a figure which shows the result of having simulated the voltage of the connection point of the transistor element for a switch, and an inductor element, an inductor current, and a slope compensation voltage waveform in the current mode type DC-DC converter of the Example to which the circuit of this invention is applied.

Explanation of symbols

Vin input voltage source
Vout Final output voltage with external circuit required for DC-DC converter added
Vo Switching transistor voltage and inductor element connection voltage
Vs Voltage proportional to the current flowing through the inductor element
Ve Error amplifier output voltage
Vc slope compensation voltage
T period
D duty
I _Lf , I _Lb Current flowing in the inductor element during charging and discharging
Output current of I _D and _Is current detection circuit and slope current generation circuit
I _RL load current
I _LP The slope of currents m1 and m2 Vs in proportion to the inductor current in the conventional circuit
m Vc slope
K proportional coefficient ΔI0, ΔI1 Inductor current fluctuation 10,11 Switching transistor (or diode) element 12 Inductance element (L)
13 Capacitance element in output circuit (C)
14 and 15 Resistors 19 and 20 for dividing the output voltage Voltage waveform applied to the gate of the switching transistor element 21 Reference voltage sources 22 and 23 Error amplifier feedback resistor and feedback capacitor 100 Load (RL)
200 Current detection circuit 201, 202 Switch 203 in current detection circuit Operational amplifier 204 Transistor element 205 in current detection circuit Resistance element 210 in current detection circuit Oscillation circuit (OSC)
220 Latch 230 Comparator 240 Subtractor 250 Resistor element 300 that generates Vs voltage Error amplifier 400 Slope compensation current generation circuit 401 Capacitance element 402 in slope compensation current generation circuit Switch element 403 in slope compensation current generation circuit Offset voltage source 404 Constant current source 405 Transistor element in slope compensation current generation circuit

Claims (3)

A switching transistor element having one terminal connected to an input voltage source and performing an on / off operation with or without a control input; and an inductor element connected between the other terminal of the switching transistor element and an output terminal; An output circuit having
A current detection circuit for detecting a current flowing through the inductor element in the output circuit and generating a current proportional to the current;
A slope compensation current generation circuit that generates a current proportional to the power of a voltage that changes at a constant rate;
A current synthesis voltage generation circuit that synthesizes the two currents and generates a voltage proportional to the synthesis current;
The current detection circuit includes first and second switch elements connected in series between a connection point between the switching transistor element and the inductor element and an input voltage source, and the first and second switches. A DC-DC converter characterized by having an amplifying means for applying a voltage change appearing at a connection point of the elements to both ends of the first impedance element, and outputting a current flowing through the first impedance element. A switching transistor element having one terminal connected to an input voltage source and performing an on / off operation with or without a control input; and an inductor element connected between the other terminal of the switching transistor element and an output terminal; An output circuit having
A current detection circuit for detecting a current flowing through the inductor element in the output circuit and generating a current proportional to the current;
A slope compensation current generation circuit that generates a current proportional to the power of a voltage that changes at a constant rate;
A current synthesis voltage generation circuit that synthesizes the two currents and generates a voltage proportional to the synthesis current;
The slope compensation current generation circuit includes a capacitor, a potential shift element, and a current source for supplying a constant current connected in series between an input voltage source and another power source, and a third switch connected in parallel to the capacitor. A non-linear voltage-current conversion element that generates a current proportional to the power of the voltage change between the input voltage source and the voltage at the connection point of the element, the potential shift element and the current source that supplies the constant current DC-DC converter characterized by things. A switching transistor element having one terminal connected to an input voltage source and performing an on / off operation with or without a control input; and an inductor element connected between the other terminal of the switching transistor element and an output terminal; An output circuit having
A current detection circuit for detecting a current flowing through the inductor element in the output circuit and generating a current proportional to the current;
A slope compensation current generation circuit that generates a current proportional to the power of a voltage that changes at a constant rate;
A current synthesis voltage generation circuit that synthesizes the two currents and generates a voltage proportional to the synthesis current;
The current combined voltage generation circuit supplies a combined current of a current output from the current detection circuit and a current output from the slope compensation current generation circuit to a second impedance element, and the second impedance element DC-DC converter, characterized in that the voltage generated at both ends is the output voltage.

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