JP4479736B2 - Imaging device and camera - Google Patents

Description

  The present invention relates to an imaging apparatus and a camera including an imaging element such as a charge coupled device (CCD) and a complementary metal oxide semiconductor (CMOS) sensor.

  A CMOS image pickup device using CMOS is used as an image pickup element such as a camera, and has a function such as partial reading, which is difficult with a CCD image pickup device, and is advantageous for low power consumption and miniaturization of the image pickup device.

  With the recent increase in the number of pixels in CMOS imaging devices, there is a demand for pixel miniaturization. However, since the CMOS imaging device has many drive elements such as a photodiode, a transfer transistor, a reset transistor, an amplification transistor, and a select transistor in the pixel circuit, it is difficult to reduce the pixel size.

As one of solutions for pixel miniaturization, there is a method in which transistors in a pixel are shared, the number of transistors per pixel is reduced, and the pixel size is reduced (see, for example, Patent Document 1). For example, a transfer transistor is arranged for each of a plurality of photodiodes, and a select transistor, a reset transistor, and an amplification transistor are shared by the plurality of photodiodes and the transfer transistors.
In the case where the transistors are not shared, the number of transistors can be reduced to 1.75 per pixel by sharing three transistors with four pixels, while the number of transistors is generally four. Note that there is a configuration in which a select transistor is not provided depending on a transistor driving method or the like. (For example, see Patent Document 2).

JP 2001-298177 A JP 2006-54276 A

  In the solution described above, the number of components is reduced because a plurality of components are shared, but the layout in each pixel becomes non-uniform depending on the shape, size, etc. of each component.

  Next, the layout non-uniformity will be described.

FIG. 1 is a diagram for explaining non-uniform layout when a plurality of components are shared.
In the layout shown in FIG. 1, two photoelectric conversion units 1 diagonally adjacent to the charge voltage conversion unit 2 share the charge voltage conversion unit 2, and these photoelectric conversion units 1 have a width in the gate length direction. The transistor regions 3a (the width L3a in the gate length direction) and the transistor regions 3b (the width L3b in the gate length direction) that are different from each other are connected by the wiring 4. The transistor region referred to here is a circuit formed by transistors constituting a pixel. For example, the transistor region 3a is a reset transistor, and the transistor region 3b is formed by an amplifying transistor and a select transistor.

When a pixel is miniaturized, when all the transistors in the pixel are arranged, the width L in the gate length direction of the transistor becomes longer than the width of one side of one pixel. For this reason, the transistor region is divided and arranged in the arrangement layout shown in FIG.
In the case of the layout shown in FIG. 1, the occupied size of the transistor region differs depending on the combination of the shared transistors. The transistor regions 3b having larger occupying dimensions than the transistor region 3a are likely to interfere with each other in terms of the layout, and it is difficult to dispose transistors to prevent such interference. In addition, the occupied size of the transistor region easily affects the noise characteristics, and the larger the occupied size, the better the noise characteristics.

  The relationship between this occupied dimension and noise characteristics will be described using the following equation.

(Equation 1)
<V _n ² > ∝ 1 / (WL) (1)

The expression (1) is a general expression of the 1 / f noise amount for the amplification transistor that amplifies the voltage of the charge-voltage conversion unit, and the average value <V _n ² > of the square in the noise variance V _n of the voltage It shows that the gate area WL is inversely proportional to the product of the width W of the transistor and the gate length L.

  Therefore, according to the equation (1), as the occupied size of the transistor region, for example, the gate area WL of the amplification transistor is larger, the 1 / f noise amount is reduced and is not easily affected by random noise.

  However, when the pixels are reduced as the number of pixels is increased, it is necessary to reduce the occupied size of the transistor region. In this case, the noise characteristics of the amplification transistor are particularly deteriorated, and random noise due to charge trapping at the gate interface also increases. Furthermore, the dimensions of the components also affect the layout of the components.

  When the arrangement layout is limited by the dimensions of the constituent elements, improvement of the manufacturing process is an effective means for eliminating the limiting factor. However, in order to eliminate this limiting factor, it is necessary to shift to a fine process. This is premised on capital investment, and the number of manufacturing processes increases. Further, in a CCD or CMOS imaging device, the pixel portion often has a different structure from the circuit around the pixel portion, and there is a problem that the development cost increases.

  As another means for eliminating the limiting factor, there is a means for increasing the number of pixels by sharing the components described above. However, with this means, in addition to increasing the non-uniformity of the layout described above, the layout of the wiring is congested due to the wiring of the distant pixels, and the floating node capacitance of the input portion of the amplification transistor is increased, thereby increasing the conversion efficiency. It leads to decline.

  Therefore, by optimizing the arrangement layout of the components, it is necessary to increase the area utilization rate on the semiconductor substrate and to make the occupied area of the transistor region as large as possible.

  It is an object of the present invention to provide an imaging device and a camera that can increase the area utilization efficiency on a semiconductor substrate and increase the occupied size of a transistor region.

The first aspect imaging apparatus of the present invention includes: a plurality of photoelectric conversion portions for converting incident light into signal charges, is shared by each of the plurality of photoelectric conversion unit, the signal charges obtained by the photoelectric conversion portion A plurality of shared blocks including a plurality of shared blocks including a reset transistor that resets the voltage of the photoelectric conversion unit, and a plurality of transistors that convert the voltage of the photoelectric conversion unit. The transistor arrangement region in each shared block is divided into a first arrangement region in which the reset transistor is arranged and a second arrangement region in which the amplification transistor is arranged. and it is wired, the plurality of shared blocks has a first shared block, in a direction orthogonal to the wiring direction of said first shared block, the first A second shared block arranged adjacent to the shared block, wherein the first shared block and the second shared block are within the first shared area and the second shared block in the first shared block. The second arrangement region is adjacent to each other, and the sum of the widths of the first arrangement regions adjacent to each other in the gate length direction and the width of the second arrangement region in the gate length direction matches between the columns in each wiring direction. As shown in FIG.

  Preferably, the plurality of photoelectric conversion units arranged so as to be adjacent to each other in the diagonal direction share the plurality of transistors.

  Preferably, the plurality of photoelectric conversion units arranged so as to be adjacent to each other in the wiring direction share the plurality of transistors.

The camera of the 2nd viewpoint of this invention has an imaging device as described in any one of Claim 1 to 3, and the optical system which guides incident light with respect to the imaging area of the said imaging device.

  According to the present invention, in a shared block composed of a plurality of photoelectric conversion units and a plurality of transistors, the photoelectric conversion unit is shared by the plurality of transistors, and the occupied dimensions of the plurality of transistors are arranged at different positions. A plurality of shared blocks are alternately arranged.

  According to the present invention, the area utilization efficiency on the semiconductor substrate can be increased, and the occupied size of the transistor region can be increased.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 2 is a block diagram illustrating a configuration example of a main part of the imaging apparatus according to the embodiment of the present invention.

  2 includes a pixel circuit (PIXEL) 11, a pixel array unit (corresponding to the imaging area of the present invention) 12, a horizontal scan circuit (HSCN) 13, an analog-digital converter (AD) 131, and a vertical scan circuit. (VSCN) 14, analog front end unit 15, output buffer 16, and timing generator (TG) 17.

  In the pixel array unit 12, for example, pixel circuits 11 including a photoelectric conversion unit are arranged in a matrix with a predetermined arrangement form, and a reset line RSTL and a transfer selection line TRFL are arranged in each row (row) of the vertical scan circuit 14 and the pixel arrangement. And the select line SELL are connected to each other, and the vertical signal line VSGNL is arranged in each row (column) of the pixel array. Each pixel circuit 11 of the pixel array unit 12 is controlled by a vertical scan circuit 14. A photoelectric conversion unit (not shown) included in the pixel circuit 11 converts incident light into an electrical signal according to the amount of light, and outputs the electrical signal to the horizontal scan circuit 13 via the vertical signal line VSGNL. .

  The vertical scan circuit 14 is connected to each pixel circuit 11 of the pixel array unit 12 by a reset line RSTL, a transfer selection line TRFL, and a select line SELL, and a timing generator 17 disposed outside the vertical scan circuit 14. It is connected. The vertical scan circuit 14 propagates a reset signal, a transfer signal, and a select signal to the reset line RSTL, the transfer selection line TRFL, and the select line SELL in synchronization with a predetermined clock from the timing generator 17, respectively. 11 is controlled.

  The horizontal scan circuit 13 has an analog-to-digital converter (simply referred to as an AD converter) 131 connected to each vertical signal line VSGNL inside, and is connected to the analog front end unit 15 by the horizontal signal line HSCNL. In addition, the timing generator 17 is connected. The horizontal scan circuit 13 converts the input electric signal into a digital signal by the AD converter 131 in synchronization with a predetermined clock from the timing generator 17, and sends it to the analog front end unit 15 via the horizontal signal line HSCNL. Output. Note that an amplifier can be used instead of the AD converter 131 depending on the configuration of the imaging apparatus.

  The analog front end unit 15 has an input side connected to the horizontal scan circuit 13 and a horizontal signal line HSCNL, and an output side connected to the output buffer 16. The analog front end unit 15 is connected to the timing generator 17. The analog front end unit 15 adjusts the signal level of the digital signal input from the horizontal scan circuit 13 in synchronization with a predetermined clock from the timing generator 17 and outputs the adjusted signal level to the output buffer 16. Depending on the configuration of the imaging apparatus, an amplifier or an analog-digital converter can be used instead of the analog front end unit 15.

  The output buffer 16 has an input side connected to the analog front end unit 15 and an output side connected to, for example, a signal processing circuit. The output buffer 16 outputs the input digital signal to the signal processing circuit.

The timing generator 17 generates a predetermined clock and controls the horizontal scan circuit 13, the vertical scan circuit 14, and the analog front end unit 15.

  Next, a configuration example of the imaging apparatus according to the present embodiment will be described using a circuit diagram. In the following description, a CMOS imaging device is shown as an example.

  FIG. 3 is an equivalent circuit diagram illustrating a configuration example of the imaging apparatus according to the present embodiment.

  The pixel array unit 12 of the imaging apparatus 10 according to the present embodiment includes a shared block BLK10 as illustrated in FIG. 3, and the shared block BLK10 includes a photoelectric conversion unit (PD) 111 and a transfer transistor (TTR) 112. The pixel circuit 11 includes a reset transistor (RTR) 121, an amplification transistor (ATR) 122, a select transistor (STR) 123, and a node ND121. Hereinafter, such a configuration is referred to as a shared block. Note that, for example, a photodiode is used for the photoelectric conversion unit 111 (in FIG. 3, a photodiode symbol is used for the photoelectric conversion unit 111, which will be described as a photodiode hereinafter).

  As shown in FIG. 3, the photoelectric conversion unit (photodiode) 111 of the pixel circuit 11 has an anode grounded and a cathode connected to the source of the transfer transistor 112. The transfer transistor 112 has a source connected to the cathode of the photoelectric conversion unit 111, a drain commonly connected to the node ND121, and a gate connected to the transfer selection line TRFL.

  The reset transistor 121 has a source connected to the node ND121, a drain connected to the power supply potential VDD, and a gate connected to the reset line RSTL. The amplification transistor 122 and the select transistor 123 are connected in series between the source and the drain. The amplifying transistor 122 has a drain connected to the power supply potential VDD and a gate connected to the node ND121. The select transistor 123 has a source connected to the vertical signal line VSGNL and a gate connected to the select line SELL.

In the configuration example described above, the photoelectric conversion unit 111 generates and accumulates signal charges according to the amount of incident light by photoelectric conversion.
When the state of the reset line RSTL is switched from, for example, a low level to a high level, the reset transistor 121 is turned on (conductive state), and the potential of the node ND121 is reset to the power supply potential VDD.
Further, when the state of the transfer selection line TRFL is switched to a high level, the transfer transistor 112 is turned on, and the signal charge accumulated in the photoelectric conversion unit 111 is transferred to the node ND121.
The amplification transistor 122 amplifies the potential of the node ND121 while the transfer transistor 112 is turned on.
Further, when the state of the select line SELL is switched to a high level, the select transistor 123 is turned on, and the signal charge is output to the vertical signal line VSGNL.

  As described above, the drains of the transfer transistors 112 in the pixel circuits 11 are commonly connected to the node ND121, and the four sets of pixel circuits 11 share the reset transistor 121, the amplification transistor 122, and the select transistor 123.

  By adopting the imaging apparatus having such a configuration, the present embodiment reduces the number of elements and the number of wirings in the pixel circuit, miniaturizes the pixels, and speeds up the imaging apparatus.

(First arrangement layout example)
Next, a first arrangement layout example in which each component of the equivalent circuit described in FIG. 3 is laid out on a semiconductor substrate will be described.

  FIG. 4 is a diagram illustrating a first arrangement layout example according to the present embodiment.

In the imaging apparatus according to the present embodiment, the equivalent circuit having the configuration described in FIG. 3 is laid out on a semiconductor substrate.
Specifically, the shared block BLK10 includes a photoelectric conversion unit 111, a transfer transistor 112, a charge / voltage conversion unit FD121, a wiring SGNL, and transistor regions TRGN1 and TRGN2. The transfer transistor 112 has a transfer gate 1121. This transistor region TRGN1 is formed of a reset transistor 121, and its width in the gate length direction is L1. Note that the reset transistor 121 has a source 1212 and a reset gate 1211. Further, the transistor region TRGN2 is formed by the amplification transistor 122 and the select transistor 123, and the width in the gate length direction is L2. Note that the amplification transistor 122 has an amplification gate 1221, and the select transistor 123 has a select gate 1231.

  In the first arrangement layout according to this embodiment, the two pixel circuits 11 including the photoelectric conversion unit 111 and the transfer transistor 112 share the charge-voltage conversion unit FD121, and the two photoelectric conversion units 111 include the charge-voltage conversion unit. They are arranged diagonally across the FD 121. Further, in the single shared block BLK10, the two charge-voltage conversion units FD121 include transistor regions TRGN1 in which the electrodes FD121E, the gate electrodes 1221E of the amplification gates 1221 and the source electrodes 1212E of the reset transistors 121 are arranged in a distributed manner. The wirings SGNL are connected so as to share TRGN2. Therefore, the single shared block BLK10 has four photoelectric conversion units 111.

  Further, as shown in FIG. 4, in the first arrangement layout, a plurality of shared blocks BLK10 are alternately arranged, and transistor regions TRGN1 and TRGN2 having different widths in the gate length direction are arranged differently. At this time, the total occupied size (L1 + L2) of the transistor regions TRGN1 and TRGN2 in the gate length direction is constant.

  Next, the operation of the imaging apparatus 10 employed in the present embodiment will be described using a timing chart. In order to simplify the description, a single pixel circuit 11 among the pixel circuits shown in FIG. 3 will be described.

  FIG. 5 is a timing chart for explaining the operation of the equivalent circuit according to the present embodiment.

  FIG. 5A is a timing chart of the select signal SEL propagated to the select line SELL, FIG. 5B is a timing chart of the reset signal RST propagated to the reset line RSTL, and FIG. 4 is a timing chart of a transfer selection signal TRF propagated to a transfer selection line TRFL.

  At time t1, incident light enters the photoelectric conversion unit 111. At this time, the transfer transistor 112, the reset transistor 121, and the select transistor 123 are off (non-conducting state).

  From time t1 to time t2, the photoelectric conversion unit 111 converts incident light into signal charges by the photoelectric effect. Then, the photoelectric conversion unit 111 accumulates signal charges until time t2 when the reset transistor 121 is turned on. The period from time t1 to time t2 is the signal charge accumulation time.

  At time t2, the high level select signal SEL is transmitted from the vertical scan circuit 14 to the select line SELL, and the select transistor 123 is turned on. From time t2 to time t10, the select transistor 123 is kept on.

  At time t2, the voltage of the node ND121 is reset. In the reset transistor 121, the high level reset signal RST is propagated from the vertical scan circuit 14 to the reset line RSTL and is turned on, and the potential of the node ND 121 is reset to the power supply potential VDD.

  At time t3, the low level reset signal RST is propagated from the vertical scan circuit 14 to the reset line RSTL, the reset transistor 121 is turned off, and the voltage reset of the node ND121 is completed.

  From time t4 to time t5, the potential of the node ND121 is read as a reference signal. The reading period of this reference signal is Read1.

At time t6, the high-level transfer selection signal TRF is propagated from the vertical scan circuit 14 to the transfer selection line TRFL, and the transfer transistor 112 is turned on to transfer the signal charge accumulated in the photoelectric conversion unit 111 to the node ND121. .
Further, the transfer transistor 112 is kept on from time t6 to time t7.

  At time t7, the low-level transfer selection signal TRF is propagated from the vertical scan circuit 14 to the transfer selection line TRFL, and the transfer transistor 112 is turned off.

  From time t8 to time t9, the difference between the voltage of the node ND121 and the voltage of the reference signal read in the reading period Read1 is read as a signal based on the signal charge transferred from the node ND121. This signal readout period is referred to as Read2. At the time of this signal reading, the amplification transistor 122 is turned on, amplifies the potential of the node ND121, and outputs the amplified voltage signal to the vertical signal line VSGNL via the signal output terminal 211b.

  At time t10, the low level select signal SEL is propagated from the vertical scan circuit 14 to the select line SELL, the select transistor 123 is turned off, and the output of the voltage signal to the horizontal scan circuit 13 is completed.

  In this embodiment, by adopting such a layout, the empty area around the photoelectric conversion unit 111 and the like is reduced, and the semiconductor substrate surface can be used efficiently. Therefore, in this embodiment, it is not necessary to reduce the use area of the component such as the transistor area. In this embodiment, since the gate length of the transistor can be increased, the minimum pixel size in the same process generation can be reduced. Furthermore, in this embodiment, since the gate length of the amplification transistor can be increased, the gate area can be increased and random noise can be reduced.

(Second arrangement layout example)
Next, a second layout example in which each component of the equivalent circuit described in FIG. 3 is laid out on a semiconductor substrate will be described.

  FIG. 6 is a diagram illustrating a second arrangement layout example according to the present embodiment.

  As shown in FIG. 6, the present arrangement layout example includes a shared block BLK10 having the same configuration as that of the first arrangement layout example. Furthermore, although the plurality of shared blocks BLK10 are alternately arranged and the transistor regions TRGN1 and TRGN2 having different widths in the gate length direction are arranged differently, the arrangement form of the photoelectric conversion units 111 is different.

Specifically, as illustrated in FIG. 6, the two photoelectric conversion units 111 are arranged perpendicular to the wiring SGNL direction with the charge-voltage conversion unit FD121 interposed therebetween.
As shown in FIG. 6, the second layout layout is such that the shared block BLK10 is combined so that the transistor regions TRGN1 and TRGN2 having different widths in the gate length direction are adjacent to each other. At this time, the total occupied size (L1 + L2) of the transistor regions TRGN1 and TRGN2 in the gate length direction is constant.

  Also in this arrangement layout example, since the surface of the semiconductor substrate can be used efficiently and the gate length of the transistor can be increased, the same effect as in the first arrangement layout example according to the present embodiment can be obtained.

(Third arrangement layout example)
Next, a third arrangement layout example in which each component of the equivalent circuit described in FIG. 3 is laid out on a semiconductor substrate will be described.

  FIG. 7 is a diagram showing a third arrangement layout example according to the present embodiment.

  In this arrangement layout example, as shown in FIG. 7, the arrangement form of the photoelectric conversion units 111 has the same shared block BLK10 as in the first arrangement layout example, but the arrangement form by the plurality of shared blocks BLK10 is different.

  Specifically, as shown in FIG. 7, the shared blocks BLK10 are arranged so as to be shifted for each column. In this arrangement layout example, the shared block BLK10 is shifted for each column, and the total (L1 + L2 +...) Width in the gate length direction of the transistor regions TRGN1 and TRGN2 of the same column is arranged to be constant.

  However, since the shared block BLK10 is laid out by shifting for each column as shown in FIG. 7, the row to which the shared block BLK10 belongs is different between adjacent columns.

  Next, the shift of the row to which the shared block BLK10 belongs will be described with reference to FIG.

FIG. 8 is a diagram for explaining a shift of a row to which the shared block BLK10 belongs.

In FIG. 8, VSL of the shared block BLK10 indicates the photoelectric conversion unit 111, TRF1 to TRF4 indicate the first to fourth transfer gates 1121, RST indicates the reset gate 1211, and SEL indicates the select gate 1231, respectively.
In the single shared block BLK10 shown in FIG. 8, two photoelectric conversion units 111 sharing the charge-voltage conversion unit FD121 are connected by a wiring SGNL. Therefore, the single shared block BLK10 has four photoelectric conversion units 111.
The shared block BLK10 having such a configuration is laid out such that the sum of the widths in the gate length direction of the transistor regions TRGN1 and TRGN2 in the same column is constant for each column.

Specifically, reset gates 1211 in the same row are commonly connected by a reset line RSTL, and select gates 1231 in the same row are commonly connected by a select line SELL. However, the reset gate 1211 and the select gate 1231 are respectively connected to a reset line RSTL and a select line SELL that differ depending on the column. For example, as shown in FIG. 7, when the reset line RSTL or the select line SELL is arranged in a row, the reset gate 1211 and the select gate 1231 in the i row and j column and the i row (j + 2) column are connected in common, and (i + 1) The reset gate 1211 and the select gate 1231 in the row (j + 1) column and the (i + 1) row (j + 3) column are connected in common.
Further, the first transfer gate 1121 (TRF1) and the third transfer gate 1121 (TRF3) in the same row are commonly connected by the transfer selection line TRFL, and the second transfer gate 1121 (TRF2) in the same row is connected. The fourth transfer gate 1121 (TRF4) is commonly connected by the transfer selection line TRFL.

  As shown in FIG. 8, since the first to fourth transfer gates 1121 in the same row direction are commonly connected by a transfer selection line TRFL, the first to fourth transfer transistors 112 can be controlled for each row. It is. However, the reset gate 1211 and the select gate 1231 in each column are connected to different reset lines RSTL and select lines SELL, respectively, shifted by one row. Accordingly, the vertical scan circuit 14 (see FIG. 2) shifts the reset signal and the select signal for controlling the reset transistor 121 and the select transistor 123 to the reset line RSTL and the select line SELL by shifting the row by one row according to the column. Propagate.

  Also in this arrangement layout example, since the surface of the semiconductor substrate can be used efficiently and the gate length of the transistor can be increased, the same effects as those in the first and second arrangement layout examples according to this embodiment can be obtained. it can.

The arrangement form of the photoelectric conversion units 111 employed in this arrangement layout example is the same as the first arrangement layout, but the same arrangement form as the second arrangement layout may be adopted.
Even in this case, the same effects as those of the first, second, or third arrangement layout examples according to the present embodiment can be obtained.

  Next, a camera according to an embodiment of the present invention will be described. FIG. 9 is a block diagram showing an outline of the configuration of the camera according to the embodiment of the present invention.

  The camera 20 includes an imaging device 10, an optical system that guides incident light to the pixel array unit 12 of the imaging device 10, for example, a lens 21 that forms incident light (image light) on an imaging surface, and the imaging device 10. The signal processing circuit 22 for processing the output signal is included.

  In the camera 20, the imaging device 10 according to the above embodiment is used as the imaging device 10. The signal processing circuit 22 performs various signal processing on the output signal Vout from the output buffer 16 of the imaging apparatus 10 and outputs a video signal.

  According to the camera 20, by using the imaging device 10 according to the above-described embodiment, a high-quality captured image corresponding to the increase in the number of pixels can be obtained.

  The imaging device 10 of the present invention may be an imaging device formed as a single chip or a module type imaging device formed as an aggregate of a plurality of chips. In the case of an imaging device formed as an aggregate of a plurality of chips, the imaging device may be divided into a sensor chip that performs imaging, a signal processing chip that performs digital signal processing, and the like, and may further include an optical system.

  As described above, this embodiment has a transistor region formed of a reset transistor, a transistor region formed of a select transistor and an amplification transistor, and a plurality of photoelectric conversion units share these transistor regions. Form a shared block. The shared block is laid out so that the transistor regions are adjacent to each other so that the total occupied dimension in the gate length direction in the transistor region is constant.

  For this reason, the empty area around the photoelectric conversion portion or the like is reduced, and the semiconductor substrate surface can be used efficiently. Furthermore, since the gate length of the amplification transistor can be increased, there is an advantage that the gate area is increased and the amplification transistor is less susceptible to noise.

  In the present embodiment, a transistor region formed by a reset transistor and a transistor region formed by a select transistor and an amplification transistor are provided. A combination of components forming the transistor region is not limited as long as the shared elements are arranged in a plurality of locations. In addition, the transistors of the constituent elements employed in this embodiment may be either n-channel type or p-channel type.

It is a figure for demonstrating the layout nonuniformity at the time of sharing a some component. It is a block diagram which shows one structural example of the principal part of the imaging device which concerns on embodiment of this invention. 1 is an equivalent circuit diagram illustrating a configuration example of an imaging apparatus according to the present embodiment. It is a figure which shows the 1st arrangement layout example which concerns on this embodiment. 5 is a timing chart for explaining the operation of the equivalent circuit according to the present embodiment. It is a figure which shows the 2nd arrangement layout example which concerns on this embodiment. It is a figure which shows the 3rd arrangement layout example which concerns on this embodiment. It is a figure for demonstrating the shift | offset | difference of the row to which the shared block BLK10 which concerns on this embodiment belongs. It is a block diagram which shows the outline of a structure of the camera which concerns on embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Pixel circuit (PIXEL), 12 ... Pixel array part, 13 ... Horizontal scan circuit (HSCN), 131 ... AD converter, 14 ... Vertical scan circuit (VSCN), 15 ... Analog front end part, 16 ... Output buffer, DESCRIPTION OF SYMBOLS 17 ... Timing generator (TG), BLK10 ... Shared block, 111 ... Photoelectric conversion part (PD), 112 ... Transfer transistor (TTR), 121 ... Reset transistor (RTR), 122 ... Amplification transistor (ATR), 123 ... Select transistor (STR), FD121 ... charge voltage converter, TRGN1, TRGN2 ... transistor region, 1121 ... transfer gate, 1212 ... source of reset transistor, 1211 ... reset gate, 1221 ... amplification gate, 1231 ... select gate, L1, L2 ... gate Ogata Width, SGNL ... wiring, RSTL ... reset line, RSTL ... transfer selection line, SELL ... select lines, VSGNL ... vertical signal lines, HSCNL ... horizontal signal line.

Claims (4)

A plurality of photoelectric conversion units for converting incident light into signal charges;
Is shared by each of the plurality of photoelectric conversion portions, a plurality of transistors for outputting by converting the signal charges obtained by the photoelectric conversion units into a voltage,
A plurality of shared blocks including
The plurality of transistors include:
A reset transistor for resetting the voltage of the photoelectric conversion unit;
An amplification transistor for amplifying the voltage of the photoelectric conversion unit;
Including
The transistor placement area in each shared block is
A first placement region where the reset transistor is arranged is divided into a second arrangement area in which the amplifying transistor is placed, and is wired,
The multiple shared blocks are
A first shared block;
A second shared block disposed adjacent to the first shared block in a direction orthogonal to the wiring direction in the first shared block;
Including
The first shared block and the second shared block are
The first arrangement area in the first shared block and the second arrangement area in the second shared block are adjacent to each other, and the width of the first arrangement area in the gate length direction and the second arrangement area are adjacent to each other. Imaging devices arranged in the wiring direction so that the sum of the width in the gate length direction matches between the columns in each wiring direction . The plurality of photoelectric conversion units arranged so as to be diagonally adjacent to each other,
Imaging device according to claim 1, wherein sharing the plurality of transistors. The plurality of photoelectric conversion units arranged so as to be adjacent in the wiring direction,
Imaging device according to claim 1, wherein sharing the plurality of transistors. The imaging device according to any one of claims 1 to 3,
An optical system for guiding incident light to the imaging area of the imaging device;
Having a camera .

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