JP4413674B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a data line charging operation during high-speed reading of a flash memory.

  In recent years, in flash memories, various methods for high-speed reading have been sought (for example, see Patent Document 1).

  For example, for example, the threshold value (current) of the reference cell is approximately halfway between the threshold value (current) of the on-cell storing “1” data and the threshold value (current) of off-cell storing “0” data. Set to. In addition, each data line of the main body cell and the reference cell is given capacitance equivalence, and each data line is charged using a sense amplifier (S / A) load having the same capability. As a result, a method is known in which data can be determined even before the potential of the data line of the main cell reaches an equilibrium state of charge corresponding to the on-cell and off-cell (transient state).

  However, in the case of the above-described method, by adding a dummy capacitor to the data line of the reference cell, the capacitance generated in each data line of the main body cell and the reference cell is made equivalent. In the case of a flash memory, as the bank configuration is diversified and the capacity is increased, the capacity generated in the data line of the main body cell is also diversified and increased. For this reason, there is a problem that the dummy capacity added to the data line of the reference cell increases with the diversification and increase of the capacity generated in the data line of the main body cell.

As described above, when dummy capacitance is added to the data line of the reference cell in accordance with the capacity of the data line of the main body cell in order to enable high-speed reading, diversification of the capacity generated in the data line of the main body cell With the increase, there is a problem that the dummy capacitance added to the data line of the reference cell increases.
JP2003-338185A

The present invention can suppress an increase in the dummy capacitance added to the data line of the reference cell while maintaining the charge equivalence of the data line against the diversification and increase of the capacity generated in the data line of the main body cell. , that provides memory device capable of high-speed reading.

According to one aspect of the present invention, a sense amplifier circuit, a first data line connected to a first sense terminal of the sense amplifier circuit, and a first sense amplifier load that charges the first data line And a second data line for reference connected to the second sense terminal of the sense amplifier circuit, and a second sense amplifier load for charging the second data line, A capacity difference is provided between the first sense amplifier load and the second sense amplifier load according to the difference between the capacity of the data line and the capacity of the second data line, and the first sense amplifier load and The second sense amplifier load includes a first charging load having the same capability and a second charging load having a capability different from that of the first charging load, and the first and second data lines. When the charge equilibrium state is reached, the first The first and second data lines are charged by the first and second charging loads during a charging transition period until the first and second data lines are charged by the electric load and the charging equilibrium state is reached. A semiconductor memory device for rapidly charging a line is provided.

  According to the present invention, the data line of the main body cell and the data line of the reference cell can be charged with the optimum charging load, respectively. It is possible to provide a semiconductor memory device that can suppress an increase in the dummy capacitance added to the data line of the reference cell while preserving the charge equivalence of the line and can perform high-speed reading.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 shows a basic configuration of a semiconductor memory device according to a first embodiment of the present invention. Here, as an example of a semiconductor memory device, a flash memory (for example, a DINOR type 8M bit flash memory) capable of electrically erasing input / output data at once will be described.

  In FIG. 1, the memory cell array 11 has a plurality of blocks 12. Each block 12 is a minimum unit for collectively erasing input / output data. Each block 12 has a main body cell region 12a and a redundancy cell region 12b. The main body cell region 12a is provided with a plurality of memory cells (main body cells) MC for storing input / output data. Each memory cell MC is disposed at each intersection of the word line WL and the bit line BL. In the redundancy cell region 12b, a plurality of redundancy cells RMC for replacing defective cells (× MC) in the block 12 are provided. Each redundancy cell RMC is disposed at each intersection of the word line WL and the redundancy bit line RBL. Note that each of the plurality of memory cells MC and the plurality of redundancy cells RMC is configured by an insulated gate field effect transistor having a two-layer gate structure.

  In the present embodiment, one to a plurality of redundancy bit lines RBL are provided for each block 12. The defective cell (× MC) in the block 12 is replaced with the redundancy cell RMC in units of bit lines BL. Thereby, defect repair in the memory cell array 11 is performed. The defective address information associated with the defect relief is held by, for example, a specific memory cell in the memory cell array 11 or a non-volatile memory or fuse different from the memory cell array 11.

  As will be described later, the bit line BL and the redundancy bit line RBL are connected to the data lines DL and RDL via the column gates 21a and 21b in the gate section 21, respectively. The data lines DL and RDL are connected to a sense amplifier unit 23 provided in common to each block 12.

  A Y (row) decoder 27 is connected to the Y address buffer 25 to which the address data A0 to A7 are inputted. The Y decoder 27 is connected to the gate section 21. On the other hand, an X (column) decoder 31 is connected to the X address buffer 29 to which the address data A8 to A18 are inputted. The X decoder 31 is connected to the word line WL of each block 12.

  A multiplexer 35 is connected to the input / output buffer 33 to which the input / output data I / O0 to I / O15 and the address data A1 are input / output. A status / ID register 37, a write state machine (WSM) 39, and the sense amplifier unit 23 are connected to the multiplexer 35. A command user interface (CUI) 41 is connected to the WSM 39. For example, in addition to the chip enable signal / CE, the output enable signal / OE, and the write enable signal / WE, various control signals / WP, / RP, / BYTE, and the like are input to the CUI 41. Also, for example, a ready / busy signal RDY · / Busy is input to the WSM 39.

  Here, a method of RD replacement accompanying defect repair will be described. For example, the number of redundancy bit lines RBL is “2”. In order not to restrict access, the data of the memory cell MC (for 16 · I / O) and the data of the redundancy cell RMC (for 2 · I / O) are always performed by the sense amplifier unit 23 during a normal read operation. Are read out almost simultaneously. In this way, it is assumed that any one of the input address data A0 to A7 coincides with the defective address information stored in the chip after the data of 18 · I / O is read. Then, the multiplexer 35 replaces the data of the defective cell with the data of the redundancy cell RMC and outputs it from the input / output buffer 33 as input / output data for 16 · I / O.

  FIG. 2 shows a configuration example of the sense amplifier unit 23. Here, the capacitance (parasitic capacitance) of the data line DL on the main body side is 3C, and the capacitance of the data line Ref-DL on the reference (Ref) side is C, which is equivalent to the data line capacitance of the memory cell MC and the reference cell Ref-C. The charge equivalence of the data line is preserved by charging the main body data line DL and the Ref data line Ref-DL by the sense amplifier loads 23a and 23b having the capability according to the data line capacity. A description will be given of a case where the reference dummy capacitance is reduced.

  Here, for example, as shown in FIG. 3, the sense amplifier unit 23 uses the threshold (current) Reference of the reference cell Ref-C as the threshold of the ON (ON) cell that stores “1” data in the memory cell MC. (Current) and the threshold value (current) of an OFF cell that stores “0” data are set approximately in the middle. In addition, each of the data lines DL and Ref-DL connected to the memory cell MC and the reference cell Ref-C is used with sense amplifier (S / A) loads 23a and 23b having a capacity corresponding to the respective capacitance (3C: C). Charge. As a result, data can be determined even before the potential of the main body data line DL reaches an equilibrium state of charge corresponding to the on-cell and off-cell (transient state), that is, high-speed reading is possible.

  That is, the sense amplifier unit 23 is configured to include a sense amplifier circuit S / A, a main body sense amplifier load 23a, a Ref sense amplifier load 23b, and a latch circuit 23c, for example, as shown in FIG. In the present embodiment, the main body sense amplifier load 23a is composed of a p-channel MOS transistor and has a charging capacity of 3Isa according to the capacity (3C) of the main body data line DL. The main body sense amplifier load 23a is connected to the main body data line DL and, for example, connected to the main body sense line SL connected to the non-inverting input terminal (first sense terminal) of the sense amplifier circuit S / A. Yes. On the other hand, the Ref sense amplifier load 23b is composed of a p-channel MOS transistor and has a charging capacity of Isa according to the capacitance (C) of the Ref data line Ref-DL. The Ref sense amplifier load 23b is connected to the Ref data line Ref-DL and, for example, to the Ref sense line Ref-SL connected to the inverting input terminal (second sense terminal) of the sense amplifier circuit S / A. It is connected. The output terminal of the sense amplifier circuit S / A is connected to the multiplexer 35 through the latch circuit 23c.

  Thus, for example, if the capacity of the main body data line DL connected to the memory cell MC is three times the capacity of the Ref data line Ref-DL connected to the reference cell Ref-C, the load 23b for charging the Ref data line Ref-DL The main body data line DL is charged with a load 23a having three times the capacity. As a result, high-speed reading can be realized while preserving the charge equivalence of the data lines without increasing the reference dummy capacity according to the capacity of the main body data line DL.

  FIG. 4 shows operating points (relationship between the cell current Id and the sense voltage Vsa) on the main body side in the sense amplifier unit 23 having the configuration shown in FIG. As is apparent from this figure, when the load characteristic (capacity) of the main body sense amplifier load 23a is three times the load characteristic of the Ref sense amplifier load 23b, the potential reached by the main body sense line SL on the off-cell “0” side ( Vsa “0” = Vcc−Vthp (Vthp is the threshold voltage of the p-channel MOS transistor) does not change. On the other hand, the ultimate potential (Vsa “1” 3 times) of the main body sense line SL on the on-cell “1” side is obtained when the load characteristic of the main body sense amplifier load 23a is the same as the load characteristic of the Ref sense amplifier load 23b ( Vsa “1”) (4a> 4b).

  As described above, according to the capacity of the main body data line DL, the main body data line DL and the Ref data line Ref-DL are charged with the loads 23a and 23b having different capacities. That is, the main body data line DL of the memory cell MC and the Ref data line Ref-DL of the reference cell Ref-C can be charged by the optimum charging load (23a, 23b) corresponding to the respective capacities. As a result, the dummy capacitance added to the Ref data line Ref-DL increases as the capacity increases while the charge equivalence of the data line is preserved against the diversification and increase of the capacity generated in the main body data line DL. Therefore, high-speed reading can be performed.

  Moreover, as a result of suppressing the increase in dummy capacitance, the chip area can be reduced.

[Second Embodiment]
FIG. 5 shows a configuration example of the sense amplifier unit 23A according to the second embodiment of the present invention. Here, an example (rapid charge) in the case where the deterioration of the sense margin (anti-noise characteristic) in the first embodiment described above is improved will be described. Note that the same parts as those in FIG.

  That is, in the first embodiment, as shown in FIG. 4, for example, the ultimate potential (Vcc−Vthp) of the main body sense line SL on the off cell “0” side does not change, but the main body on the on cell “1” side. The arrival potential of the sense line SL is higher than that when the sense amplifier load has the same size (load characteristic), which means that the amplitude difference (d) of the arrival potential is reduced. This decrease in the amplitude difference (d) deteriorates the sense margin / noise characteristic.

  Therefore, in the present embodiment, as shown in FIG. 5, for example, the quick charge loads 23e and 23f and the quick charge load control switches 23g and 23h are provided separately from the main body sense amplifier load 23a ′ and the Ref sense amplifier load 23b ′. Provide. At this time, the main body sense amplifier load 23a 'and the Ref sense amplifier load 23b' have the same capacity on the main body side and the reference side (Isa). On the other hand, the quick charge loads 23e and 23f have different capacities according to the capacity difference between the main body data line DL and the Ref data line Ref-DL (Iacc1> Iacc2). That is, when the capacitance of the main body data line DL is 3C and the capacitance of the Ref data line Ref-DL is C, the load characteristics (load current) of the main body sense amplifier load 23a ′ and the quick charge load 23e on the main body side are set. The sum (Iacc1 + Isa) of the supply capability) is set to be three times the sum of the load current supply capabilities (Iacc2 + Isa) of the Ref sense amplifier load 23b ′ and the quick charge load 23f on the reference side.

  In such a configuration, at the initial stage of the charging operation, the quick charge load control switch 23g is turned on, and the main body data line DL is quickly connected using both the quick charge load 23e and the main body sense amplifier load 23a ′. Charge. Similarly, the quick charge load control switch 23h is turned on, and the Ref data line Ref-DL is rapidly charged using both the quick charge load 23f and the Ref sense amplifier load 23b '. Thus, in the transient state, the quick charge load control switches 23g and 23h are turned off when the equilibrium state is reached from the transient state while maintaining the data line charging equivalence. Thereby, at the time of high-speed reading, it is possible to suppress a decrease in the amplitude difference (d) of the final arrival potential of the main body sense line SL, and it is possible to improve the deterioration of the sense margin / noise characteristic.

[Third Embodiment]
FIG. 6 shows a basic configuration of the sense amplifier unit 23B according to the third embodiment of the present invention. Here, an example will be described in which the quick charge load is switched in accordance with the change in the capacity of the data line caused by the bank to be read. 2A shows an example of the configuration of the sense amplifier unit 23B, and FIG. 2B shows an example of the configuration of the bank decoding circuit. The same parts as those in FIG. I won't go into detail.

  Here, in the flash memory, in order to realize a function (simultaneous execution function) of performing a read operation during a write / erase operation, for example, as shown in FIG. 7, one to a plurality of blocks including a plurality of memory cells MC A plurality of 12 banks 13 are configured. For each bank 13, a method of decoding a write / erase address or a read address (Address), a data line, and a power source is used.

  In the bank 13, for example, as indicated by Banks 0, 1, 2, and 3 in FIG. 7, the capacity of the data lines is not necessarily the same (in this example, 1: 3: 3: 1). The capacitance of the data line DL generated on the main body side also changes depending on whether the positional relationship between the bank 13 and the sense amplifier unit 23B is physically close or far.

  Therefore, in the present embodiment, for example, as shown in FIG. 6A, a quick charge load 23e having optimum load characteristics (Iacc1, Iacc2) with respect to the capacity (2C) of the data line DL generated in Bank0 / 3. , 23f, and quick charge loads 23i, 23j and fast charge having different load capacities (Iacc1 ', Iacc2') with respect to the capacity (3C) of the data line DL generated in Bank 1/2 Load control switches (Bank1 / 2 selection switches) 23m and 23n are prepared. For example, as shown in FIG. 6B, a bank decode circuit 14 including AND circuits 14a, 14b, 14c and 14d and NOR circuits 14e and 14f for decoding the bank 13 read from the input address is provided. Thus, the selection of the quick charge loads 23e and 23f or the quick charge loads 23i and 23j is switched according to the change in the capacity of the data line DL caused by the bank 13 to be read. This makes it possible to suppress bank dependency on data line charging equivalence.

  According to such a configuration, it is possible to provide charge equivalence to the diversification of the capacity of the main body data line DL, which will be a problem when diversifying and increasing the capacity of the flash memory bank configuration in the future. It becomes.

[Fourth Embodiment]
FIG. 8 shows a basic configuration of a sense amplifier unit 23C according to the fourth embodiment of the present invention. Here, an example will be described in which the dummy capacitance added to the Ref data line Ref-DL is switched according to the change in the capacitance of the data line caused by the bank to be read. 2A shows an example of the configuration of the sense amplifier 23C, and FIG. 2B shows an example of the configuration of the bank decoding circuit. The same parts as those in FIG. I won't go into detail.

  That is, in the case of the present embodiment, as shown in FIG. 8A, for example, a Ref dummy capacitor 16a having an optimum capacity (2C) with respect to the capacity (2C) of the data line DL generated in Bank0 / 3, A Ref dummy capacitor 16b having a capacity (3C) optimum for the capacity (3C) of the data line DL generated in Bank 1/2, and a changeover switch 17 for switching between these Ref dummy capacitors 16a and 16b. And prepare. For example, as shown in FIG. 8B, a bank decode circuit 14 including AND circuits 14a, 14b, 14c and 14d and NOR circuits 14e and 14f for decoding the bank 13 read from the input address is provided. Thus, the connection of the Ref dummy capacitor 16a or the Ref dummy capacitor 16b with the Ref data line Ref-DL is switched according to the change in the capacity of the data line DL caused by the bank 13 to be read. Thereby, by charging the data lines DL and Ref-DL with the charging loads 23a 'and 23b' having the same capability (Isa), it is possible to suppress the bank dependence on the data line charging equivalence.

  Even with such a configuration, it is possible to provide charge equivalence to the diversification of the capacity of the main body data line DL, which will be a problem in the future when the flash memory bank configuration is diversified and increased in capacity. Become.

  In addition, the present invention is not limited to the above (each) embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above (each) embodiment includes various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if several constituent requirements are deleted from all the constituent requirements shown in the (each) embodiment, the problem (at least one) described in the column of the problem to be solved by the invention can be solved. When the effect (at least one of the effects) described in the “Effect” column is obtained, a configuration from which the constituent requirements are deleted can be extracted as an invention.

1 is a circuit diagram showing a basic configuration of a semiconductor memory device (flash memory) according to a first embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration example of a sense amplifier unit in a flash memory. The figure shown in order to demonstrate data line charge equivalence. The figure shown in order to demonstrate the operation point by the side of the main body in a sense amplifier part. The circuit diagram which shows the structural example of the sense amplifier part according to the 2nd Embodiment of this invention. The circuit diagram which shows the structural example of the sense amplifier part according to the 3rd Embodiment of this invention. Schematic shown about the bank structure of flash memory. The circuit diagram which shows the structural example of the sense amplifier part according to the 4th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Memory cell array, 12 ... Block, 12a ... Main body cell area, 12b ... Redundancy cell area, 13 ... Bank (Bank0, 1, 2, 3), 14 ... Bank decoding circuit, 14a, 14b, 14c, 14d ... AND circuit 14e, 14f ... NOR circuit, 16a, 16b ... Ref dummy capacitance, 17 ... changeover switch, 21 ... gate part, 21a, 21b ... column gate, 23, 23A, 23B, 23C ... sense amplifier part, 23a ... main body sense amplifier Load (first sense amplifier load), 23a '... body sense amplifier load (first charging load), 23b ... Ref sense amplifier load (second sense amplifier load), 23b' ... Ref sense amplifier load (first ), 23c... Latch circuit, 23e, 23f... Rapid charging load (second charging load) 23i, 23j ... Rapid charging load (third charging load), 23g, 23h ... Rapid charging load control switch (Bank 0/3 selection switch), 23m, 23n ... Bank 1/2 selection switch, 25 ... Y address buffer, 27 ... Y (row) decoder, 29 ... X address buffer, 31 ... X (column) decoder, 33 ... input / output buffer, 35 ... multiplexer, 37 ... status / ID register, 39 ... write state machine (WSM), 41 ... Command user interface (CUI), MC ... Memory cell (main body cell), WL ... Word line, BL ... Bit line, RMC ... Redundancy cell, RBL ... Redundancy bit line, DL ... Data line (main body side) ), RDL: Data line for redundancy, Ref-DL: Data line (reference side) Ref-C ... reference cell, SL ... body sense lines, Ref-SL ... Ref sense line, S / A ... sense amplifier circuit.

Claims (4)

A sense amplifier circuit;
A first data line connected to a first sense terminal of the sense amplifier circuit;
A first sense amplifier load for charging the first data line;
A second data line for reference connected to a second sense terminal of the sense amplifier circuit;
A second sense amplifier load for charging the second data line;
In accordance with the difference between the capacity of the first data line and the capacity of the second data line, a capacity difference is provided between the first sense amplifier load and the second sense amplifier load ;
The first sense amplifier load and the second sense amplifier load are:
A first charging load with the same capacity;
A second charging load having a different capacity from the first charging load;
Each with
When the charge equilibrium state of the first and second data lines is reached, the first and second data lines are charged by the first charging load,
In the charge transition period until the charge equilibrium state is reached, the first and second data lines are rapidly charged by the first and second charge loads.
A semiconductor memory device. A sense amplifier circuit;
A first data line connected to a first sense terminal of the sense amplifier circuit;
A second data line for reference connected to a second sense terminal of the sense amplifier circuit;
A first sense amplifier load for charging the first data line and having a capacity according to a capacity of the first data line;
A second sense amplifier load for charging the second data line and having a capacity corresponding to a capacity of the second data line, and the first sense amplifier load and the second sense amplifier load. Is
A first charging load with the same capacity;
A second charging load having a capacity different from that of the first charging load and having a capacity corresponding to the capacity of the data line caused by the first bank;
A third charging load having a capacity different from that of the first and second charging loads and having a capacity corresponding to the capacity of the data line caused by the second bank;
Each with
2. The semiconductor memory device according to claim 1, wherein the second and third charging loads are selected by an output of a decoding circuit that decodes an address of the first or second bank . A sense amplifier circuit;
A first data line connected to a first sense terminal of the sense amplifier circuit;
A second data line for reference connected to a second sense terminal of the sense amplifier circuit;
A first sense amplifier load for charging the first data line and having a capacity according to a capacity of the first data line;
A second sense amplifier load for charging the second data line and having a capacity corresponding to a capacity of the second data line;
And the first sense amplifier load and the second sense amplifier load are:
A first charging load with the same capacity;
A second charging load having a different capacity from the first charging load,
When the charge equilibrium state of the first and second data lines is reached, the first and second data lines are charged by the first charging load,
Wherein the first to charge transition to reach the charge equilibrium, the second charging load, the first semi-conductor memory device you characterized by rapidly charging the second data line. A sense amplifier circuit;
A first data line connected to a first sense terminal of the sense amplifier circuit;
A first sense amplifier load for charging the first data line;
A second data line for reference connected to a second sense terminal of the sense amplifier circuit;
A second sense amplifier load for charging the second data line;
Comprising
In accordance with the difference between the capacity of the first data line and the capacity of the second data line, a capacity difference is provided between the first sense amplifier load and the second sense amplifier load;
The first sense amplifier load and the second sense amplifier load are:
A first charging load with the same capacity;
A second charging load having a capacity different from that of the first charging load and having a capacity corresponding to the capacity of the data line caused by the first bank;
The first and second charging loads have different capacities, and each has a third charging load having a capability according to the capacity of the data line caused by the second bank,
The second, third charging load, the first or semi-conductor memory device you being selected by the output of the decoding circuit for decoding the address of the second bank.

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