JP4371645B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device composed of MOS transistors (insulated gate field effect transistors). More specifically, the present invention relates to a semiconductor device in which a voltage applied to a gate insulating film of a MOS transistor is reduced. More specifically, the present invention relates to a configuration for stably generating an output signal while guaranteeing the reliability of a gate insulating film of a MOS transistor without being affected by variations in process parameters in a MOS output circuit. . More specifically, the present invention relates to a configuration of a circuit that generates a display element selection signal of an image display device.
[0002]
[Prior art]
A circuit using a MOS transistor (insulated gate field effect transistor) has an advantage of low power consumption, and is widely used in applications such as integrated circuits.
[0003]
In a MOS transistor, a voltage is applied to a control electrode (gate) separated from a substrate region by an insulating film to control conduction / non-conduction of the MOS transistor. When the insulating film (gate insulating film) directly under the gate causes dielectric breakdown, the gate and the substrate region are short-circuited and a large current flows. Therefore, it is necessary to sufficiently ensure the breakdown voltage characteristics of the gate insulating film. In particular, when the element is miniaturized, the gate insulating film is generally thinned, and the tolerance of the voltage applied to the gate is lowered, so that the breakdown voltage characteristic of the gate insulating film is generally guaranteed. .
[0004]
Even if the voltage applied to the gate insulating film is within an allowable range, if a voltage is applied to the gate over a long period of time, voltage stress is applied to the gate insulating film, and this stress is accumulated, causing the gate insulating film to break down. Occurs. Such a phenomenon is known as a temporal dielectric breakdown (TDDB) of the gate insulating film. In order to prevent such breakdown of the gate insulating film, a configuration for reducing the voltage applied to the gate insulating film is shown in Patent Document 1 (Japanese Patent Laid-Open No. 11-149773).
[0005]
FIG. 26 is a diagram illustrating a configuration of the CMOS inverter disclosed in Patent Document 1 described above. In FIG. 26, the CMOS inverter has a source coupled to power supply node 900 receiving power supply voltage VCC and a gate connected to P channel MOS transistor PQ0 receiving input signal IN2, and a source connected to ground node 902 receiving ground voltage VSS. N channel MOS transistor NQ0 connected and receiving input signal IN1 at its gate, and a voltage relaxation circuit 905 for relaxing the voltage applied to the gate insulating films of these MOS transistors PQ0 and NQ0 are included.
[0006]
Voltage relaxation circuit 905 is connected between MOS transistor PQ0 and output node 910 and receives a bias voltage VP at its gate, is connected between output node 910 and MOS transistor NQ0 and is connected to its gate. N channel MOS transistor NQ1 receiving bias voltage VN is included.
[0007]
Bias voltage VP is generated based on power supply voltage VCC, and bias voltage VN is generated based on ground voltage VSS. Output signal OUT0 is output from output node 910, output signal OUT2 is output from connection node 911 of MOS transistors PQ0 and PQ1, and output signal OUT1 is output from a connection node of MOS transistors NQ1 and NQ0.
[0008]
The input signal IN1 changes between the ground voltage and the voltage VN-VTN, and the input signal IN2 changes between the power supply voltage VCC and the voltage VP-VTP. Voltages VTP and VTP indicate threshold voltages of N channel MOS transistors NQ0 and NQ1, respectively, and voltage VTP indicates a threshold voltage of P channel MOS transistors PQ0 and PQ1. By limiting the amplitude of input signals IN1 and IN2, the voltage applied to the gate insulating films of MOS transistors PQ0 and NQ0 is relaxed.
[0009]
FIG. 27 shows the power supply voltage dependence of bias voltages VP and VN shown in FIG. In FIG. 27, the vertical axis represents voltage, and the horizontal axis represents the voltage level of the power supply voltage VCC. Bias voltage VP is at a voltage level lower than power supply voltage VCC by voltage V0, and increases linearly with power supply voltage VCC. On the other hand, the bias voltage VN is fixed to the voltage V0 when the power supply voltage VCC exceeds the voltage V0. The bias voltage VN increases with the power supply voltage VCC until the power supply voltage VCC exceeds the voltage V0. The voltage V0 is, for example, 2V, and the absolute value of the threshold voltage of the MOS transistor is lower than 1V. Therefore, the voltage V0 is higher than 2 · VTN and 2 · | VTP |.
[0010]
FIG. 28 is a diagram showing voltage levels of input / output signals when a high level signal is output. As shown in FIG. 28, the input signal IN1 is set to the ground voltage VSS (= 0V), and the input signal IN2 is set to the voltage VP + | VTP |. In this state, MOS transistor NQ0 has a gate and a source at the same voltage level, and maintains a non-conductive state. The output signal OUT1 is set to the voltage level of the voltage VN-VTN by the source follower operation of the MOS transistor NQ1.
[0011]
On the other hand, MOS transistor PQ0 receives voltage VP + | VTP | as input signal IN2 at its gate. Bias voltage VP is VCC-V0, and voltage V0 is higher than 2 · | VTP |. Therefore, when the input signal IN2 is the voltage VP + | VTP |, the MOS transistor PQ0 becomes conductive, and the voltage level of the output signal OUT2 becomes the power supply voltage VCC level. Since bias voltage VP is 2 · | VTP | or more lower than power supply voltage VCC, MOS transistor PQ1 is also conductive, and output signal OUT0 is also at power supply voltage VCC level.
[0012]
Under the voltage application condition shown in FIG. 28, the voltage applied to the gate insulating film of MOS transistor PQ0 is expressed by the following equation.
[0013]
VCC-VP- | VTP | = V0- | VTP | ≧ | VTP |
In MOS transistor PQ1, a voltage of VCC-VP (= V0) is applied to its gate insulating film. In MOS transistor NQ1, voltage VCC-VN is applied to its gate insulating film. In MOS transistor NQ0, voltage VN−VTN ≦ V0−VTN is applied to the gate insulating film.
[0014]
Therefore, only a voltage lower than power supply voltage VCC is applied to the gate insulating films of these MOS transistors PQ0, PQ1, NQ1 and NQ0. Even when the power supply voltage is high, the voltage applied to the gate insulating film of these MOS transistors can be reliably reduced, and the reliability of the gate insulating film can be guaranteed.
[0015]
FIG. 29 is a diagram showing voltage levels of input / output signals when a low level signal is output. When this low level signal is output, the input / output IN1 is set to voltage VN−VTN ≧ VTN, and the input signal IN2 is set to the power supply voltage VCC level. In this state, since the MOS transistor PQ0 is in the off state, the output signal OUT2 is maintained at the voltage level of the voltage VP + | VTP | by the source follower operation of the MOS transistor PQ1.
[0016]
On the other hand, the MOS transistor NQ0 is turned on in accordance with the voltage VN−VTN of the input signal IN1, and sets the output signal OUT1 to the ground voltage VSS (= 0V). Here, the bias voltage VN is at a voltage level higher than 2 · VTN. Therefore, the MOS transistor NQ1 is also turned on, and the output signal OUT0 becomes the ground voltage VSS (= 0V).
[0017]
Even under the voltage application condition shown in FIG. 29, the voltage applied to the gate insulating film of MOS transistor PQ0 is voltage VCC-VP- | VTP |. The voltage applied to the gate insulating film of the MOS transistor PQ1 becomes the maximum VP (the output signal OUT0 is at the ground voltage level). In MOS transistor NQ1, the voltage applied to its gate insulating film is equal to bias voltage VN. In MOS transistor NQ0, the voltage applied to the gate insulating film is VN-VTN.
[0018]
Therefore, also in this case, the voltage applied to the gate insulating films of MOS transistors PQ0, PQ1, NQ1, and NQ0 can be made lower than power supply voltage VCC.
[0019]
The output signal OUT0 is a large-amplitude signal that changes between the power supply voltage VCC and the ground voltage. On the other hand, the output signal OUT1 is a small amplitude signal that changes between the ground voltage VSS and the voltage VN−VTN, and the output signal OUT2 also has a small amplitude signal that changes between the power supply voltage VCC and the voltage VP + | VTP |. It is.
[0020]
In order to set the voltage levels of the input signals IN1 and IN2 or to set the voltage levels of the output signals OUT0 to OUT2, it is necessary to stably generate the bias voltages VP and VN. In the above-described Patent Document 1, a configuration in which the bias voltages VP and VN are generated using a current mirror circuit is shown.
[0021]
FIG. 30 is a diagram showing the configuration of the bias voltage generating circuit disclosed in Patent Document 1 described above. In FIG. 30, the bias voltage generating circuit is connected in series between power supply line 920 and output node 924, each of which includes N channel MOS transistors NQT1 and NQT2 whose gates and drains are interconnected, output node 924 and ground. N-channel MOS transistor NQ3 connected between line 922, N-channel MOS transistor NQ4 which forms a current mirror circuit with MOS transistor NQ3, and is connected to the drain of MOS transistor NQ4 Resistance element RZ and a P channel MOS transistor PQ3 connected between resistance element RZ and power supply line 920 and having the gate and drain thereof connected to each other are included.
[0022]
MOS transistors NQT1 and NQT2 have their back gates (substrate regions) connected to the sources to cancel the influence of the substrate effect on the threshold voltage.
[0023]
This bias voltage generating circuit is further coupled to power supply line 920, connected in series between MOS transistor PQ3 and P channel MOS transistor PQ4 constituting a current mirror circuit, output node 926 and ground line 922, and each of them. N channel MOS transistors NQT3 and NQT4 whose gates and drains are interconnected. These MOS transistors NQT3 and NQT4 also have their back gates connected to their sources to cancel the influence of the substrate effect on the threshold voltage.
[0024]
A bias voltage VP is generated from the output node 924, and a bias voltage VN is generated at the output node 926. A decoupling capacitor CP is provided between the power supply line 920 and the output node 924, and a decoupling capacitor CN is provided between the output node 926 and the ground line 922.
[0025]
MOS transistors NQT1-NQT4 have their threshold voltages set to ½ of voltage V0 by ion implantation or the like. The current driving capability of these MOS transistors NQT1-NQT4 is sufficiently increased.
[0026]
The magnitude of current Ir flowing through MOS transistors PQ3 and NQ4 and resistance element RZ is determined by the channel resistance of MOS transistors PQ3 and NQ4 and the resistance value of resistance element RZ. MOS transistors NQ4 and NQ3 form a current mirror circuit, and mirror current Ip of current Ir flowing through MOS transistor NQ4 flows through MOS transistor NQ3. This mirror current Ip is sufficiently smaller than the current that can be driven by MOS transistors NQT1 and NQT2. Therefore, MOS transistors NQT1 and NQT2 operate in the diode mode, and the voltage drop of each threshold voltage is reduced. Cause it to occur. Now, it is assumed that the threshold voltage of MOS transistors NQT1-NQT4 is VTH. In that case, the bias voltage VP from the node 924 becomes the voltage level of the voltage VCC-2 · VTH. Therefore, by setting VTH = V0 / 2, the linear voltage characteristic of the bias voltage VP shown in FIG. 27 is obtained.
[0027]
On the other hand, MOS transistors PQ3 and PQ4 form a current mirror circuit, and mirror current In of current Ir flowing through MOS transistor PQ3 flows through MOS transistor PQ4. Since mirror current In is sufficiently smaller than the drivable current of MOS transistors NQT3 and NQT4, when MOS transistors NQT3 and NQT4 are turned on, a voltage drop of threshold voltage VTH occurs. Therefore, when power supply voltage VCC is higher than 2 · VTH, bias voltage VN has a voltage level of 2 · VTH. When power supply voltage VCC is lower than 2 · VTH, MOS transistor NQT3 and At least one of the NQTs 4 is non-conductive, and the bias voltage VN changes with the power supply voltage VCC. Thereby, the bias voltage VN having the power supply voltage dependency shown in FIG. 27 can be generated.
[0028]
Further, by using the output circuit as described above, it is possible to ensure the reliability of the gate insulating film of the MOS transistor even when the voltage level of the power supply voltage VCC is high. Even if it is changed over a wide range according to the interface specification, it is possible to operate stably.
[0029]
Patent Document 4 (Japanese Patent Application Laid-Open No. 11-163715) discloses a CMOS output drive circuit that uses the same bias voltage as that of Patent Document 1 described above to guarantee the reliability of the gate insulating film. . However, in Patent Document 4, no consideration is given to the influence of the threshold voltage dependency of the bias voltage on the output signal.
[0030]
[Patent Document 1]
JP-A-11-149773
[0031]
[Patent Document 2]
JP 2000-155617 A
[0032]
[Patent Document 3]
JP 2000-155620 A
[0033]
[Patent Document 4]
Japanese Patent Laid-Open No. 11-163715
[0034]
[Problems to be solved by the invention]
Now, it is assumed that the bias voltage VP is generated using the circuit shown in FIG. 30 and satisfies the condition of the following expression (1).
[0035]
VP = VCC-2 · VTH (1)
Next, consider the voltage application conditions shown in FIG. That is, consider the state where the input signal IN applied to the gate of the MOS transistor PQ0 is at the voltage VP + | VTP |. In this case, the output signals OUT0 and OUT2 are driven to the power supply voltage VCC. The drive speed when output signals OUT0 and OUT2 rise to power supply voltage VCC level depends on the current drive capability of MOS transistor PQ0. The current drive capability of the MOS transistor PQ0 depends on the gate-source voltage of the MOS transistor PQ0. That is, current I0 flowing through MOS transistor PQ0 is represented by the following equation.
[0036]
I0∝ (VGS0-VTP) (2)
Here, VGS0 is a gate-source voltage of the MOS transistor PQ0 and is expressed by the following equation (3).
[0037]
VGS0 = VP + | VTP | −VCC (3)
Substituting the value of the bias voltage VP expressed by the above equation (1) into the above equation (3), the following equation (4) is obtained.
[0038]
VGS0 = VCC-2 · VTH + | VTP | -VCC
= −2 · VTH + | VTP | (4)
Therefore, when the above equation (4) is substituted into the above equation (2), the following equation (5) is obtained.
[0039]
I0∝ (-2 ・ VTH + | VTP | -VTP)
∝ (-2 ・ VTH + 2 ・ | VTP |) (5)
As is clear from the above equation (5), the current drive capability of the MOS transistor PQ0 is affected by variations in the threshold voltages VTP and VTH. Therefore, when threshold voltages VTH and VTP vary due to variations in manufacturing parameters, the current driving capability of MOS transistor PQ0 varies. The potential change speed of the output signal OUT2 varies accordingly, and the operation margin of the next-stage circuit cannot be secured.
[0040]
In order to operate the circuit stably, it is necessary to consider a margin until the output signals OUT0 and OUT2 are stabilized. Therefore, a timing margin for the output signal OUT2 needs to be sufficiently large, and high-speed operation is performed. The problem of being unable to do so arises.
[0041]
When the input signal IN2 is the power supply voltage VCC, the output signal OUT2 has a voltage level of the voltage VP + | VTP |. In this case, the voltage level of the output signal OUT2 is expressed by the following equation (6).
[0042]
OUT2 = VCC-2 · VTH + | VTP | (6)
Therefore, even in this case, the voltage level of the output signal OUT2 is affected by variations in the threshold voltages VTH and VTP. The output signal OUT2 is a small amplitude signal that changes between the power supply voltage VCC and the voltage VCC-2 · VTH + | VTP |. Therefore, when the threshold voltages VTH and VTP vary, there arises a problem that the high level and the low level of the output signal OUT2 cannot be accurately identified.
[0043]
In particular, when the inverter shown in FIG. 26 is cascaded in a plurality of stages, output signals OUT1 and OUT2 are used as input signals IN1 and IN2 of the next-stage inverter. In this case, in the next-stage inverter, the transistor PQ0 cannot be brought into a complete conduction state, and there is a possibility that an accurate circuit operation cannot be guaranteed.
[0044]
As for the bias voltage VN, the bias voltage VN is 2 · VTH. When the input signal IN1 is at the ground voltage level, the voltage level of the output signal OUT1 is expressed by the following equation (7).
[0045]
OUT1 = 2 · VTH−VTN (7)
When the threshold voltages VTH and VTN are equal, the output signal OUT1 has a high level VTH (= VTN), and the voltage level is affected by variations in threshold voltage.
[0046]
When the input signal IN1 is voltage VN−VTN, the gate-source voltage is voltage VN−VTN = 2 · VTH−VTN. Therefore, the drive current Inq0 of the MOS transistor NQ0 in this case is expressed by the following equation (8).
[0047]
Inq0∝ (2.VTH-VTN-VTN)
∝ (VTH-VTN) (8)
Therefore, also in this case, when threshold voltages VTH and VTN fluctuate, similarly, the speed at which output signal OUT1 is driven to the ground voltage level is different, which is the same as the problem with the previous P channel MOS transistor PQ0. A problem also occurs with the output signal OUT1.
[0048]
Therefore, since these output signals OUT1 and OUT2 are affected by the threshold voltage, similarly, the driving speed of the output signal OUT0 is also affected by the variation of the threshold voltage.
[0049]
Further, a problem that the next-stage circuit cannot be operated accurately occurs similarly.
In particular, when this circuit is applied to an image display device or the like, the MOS transistor is composed of a TFT (Thin Film Transistor). The thin film transistor is formed in a semiconductor layer formed on an insulating layer such as a glass substrate or a resin layer. In the case of this thin film transistor, therefore, the variation in threshold voltage is larger than that of a normal MOS transistor formed on the surface of a semiconductor substrate. In the case of a thin film transistor, a semiconductor layer is formed on a resin layer or a glass substrate, and source, channel, and drain regions are formed in the semiconductor layer. For this reason, the influence of the film quality of the semiconductor layer appears greatly on the threshold voltage, and it is difficult to control the film quality as compared with a normal MOS transistor formed on the surface of the semiconductor substrate. In a thin film transistor, impurity implantation into a channel region for adjusting a threshold voltage and application of a back gate bias voltage for stabilizing the threshold voltage are generally not performed.
[0050]
Further, in order to generate the bias voltages VP and VN, the threshold voltage VTH of the MOS transistor for bias voltage generation is set to the absolute value of the threshold voltages VTP and VTN of the transistors of the output circuit by ion implantation or the like. It is different. For this reason, in order to generate a bias voltage, a process such as ion implantation for adjusting a threshold voltage is required, which increases the number of manufacturing processes and increases the manufacturing cost.
[0051]
Further, Patent Document 2 discloses a configuration that stably generates an output voltage of a constant voltage level without being affected by fluctuations in the operating environment and manufacturing parameters. In the configuration of Patent Document 2, the gate voltage of the current drive transistor that generates the internal voltage is maintained at a constant voltage level using a negative feedback circuit. In this configuration, it has been shown that the dependency of the output voltage on the power supply voltage is suppressed. No consideration is given to the influence of the threshold voltage on the output voltage due to the bias voltage of the circuit that guarantees the reliability of the gate insulating film.
[0052]
Here, Patent Document 3 discloses a configuration intended to generate a storage voltage at a constant voltage level regardless of the operating environment. In Patent Document 3, the power supply voltage dependency of the output voltage is suppressed, and the temperature dependency of the output voltage is eliminated by using a source follower transistor. However, no consideration is given to the influence of the threshold voltage dependency of the bias voltage on the output signal in the circuit that ensures the reliability of the gate insulating film.
[0053]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of suppressing the influence of fluctuations in the threshold voltage of a MOS transistor on an output signal.
[0054]
Another object of the present invention is to provide a semiconductor device capable of stably generating an output signal even if the threshold voltage varies.
[0055]
Still another object of the present invention is to provide a circuit for generating a bias voltage for driving an output circuit capable of suppressing the influence of a threshold voltage on an output signal.
[0056]
Still another object of the present invention is to provide a semiconductor device suitable for generating a drive signal in an image display device.
[0057]
Still another object of the present invention is to provide a semiconductor device capable of generating an output signal stably without impairing the reliability of the gate insulating film of a MOS transistor.
[0058]
[Means for Solving the Problems]
  This departureClearlySuch a semiconductor device includes a functional circuit that operates by receiving first and second voltages applied to first and second power supply nodes, respectively, as operating power supply voltages. This functional circuit includes first, second, third and fourth field effect transistors connected in series between first and second power supply nodes. The first and second field effect transistors have different conductivity types from the third and fourth field effect transistors.
[0059]
  This departureClearlyThe semiconductor device further generates first and second bias voltages having different voltage levels based on the first and second voltages, respectively, and applies them to the gates of the second and third field effect transistors, respectively. A bias voltage generation circuit is included. The bias voltage generation circuit generates a corresponding bias of the first and second bias voltages so as to suppress the influence of the threshold voltage of at least one of the first and fourth field effect transistors on the output signal. .
[0060]
  In the first aspect of the present inventionThe bias voltage generation circuit includes a plurality of field effect transistors connected in series between a first node receiving a first voltage and a second node, each of which is diode-connected, and the second node And a voltage level conversion element connected between the output node for outputting the first bias voltage and generating a predetermined voltage difference between the second node and the output node.This voltage level conversion element includes a resistance element.
[0061]
  In the second aspect of the present inventionThe bias voltage generation circuit includes a plurality of field effect transistors connected in series between a first node receiving a second voltage and a second node, each of which is diode-connected, and the second node And a voltage level conversion element that generates a voltage difference of a predetermined magnitude between the second node and the output node.This voltage level conversion element includes a resistance element.
[0066]
Preferably, a constant current circuit for driving a current having a constant magnitude is provided for this resistance element.
[0067]
  In the third aspect of the present inventionIn the bias voltage generation circuit, each connected in series between the node receiving the first voltage and the output node outputting the first bias voltage is diode-connected, and each is the same as the second transistor A series body of a plurality of conductive type field effect transistors and resistance elements, and a constant current source for driving a current of a certain magnitude coupled between an output node and a node receiving a second voltage are included.
[0068]
  In the fourth aspect of the present inventionThe bias voltage generating circuit is connected in series between a node that receives the second voltage and an output node that outputs the second bias voltage, each being diode-connected and each having the same conductivity as the third transistor. And a constant current source coupled between the output node and the node receiving the first voltage to drive a current of a certain magnitude.
[0069]
  In the fifth aspect of the present inventionThe bias voltage generation circuit includes a plurality of field effect transistors and resistor elements each connected in series between a node that receives the first voltage and an output node that outputs the first bias voltage, each of which is diode-connected. A current source transistor driving a constant current coupled between the series body and an output node and a node receiving the second voltage;1A first resistance element connected between the internal power supply node receiving the voltage of the first and the first internal node, and a first internal resistance connected between the first resistance element and the gate of the current source transistor. A first reference transistor of the same conductivity type as a current source transistor having a gate connected to the node, and connected between the internal power supply node and the second internal node and its gate connected to the first internal node A second reference transistor having the same conductivity type as the current source transistor, a gate of the current source transistor,2A third reference transistor having the same conductivity type as that of the current source transistor and having a gate connected to the second internal node and a second internal node and a second internal node2A second resistance element connected to a node receiving the voltage of the second.
[0070]
  In a sixth aspect of the inventionThe bias voltage generation circuit is connected in series between a node that receives the second voltage and an output node that outputs the second bias voltage, each of which is a diode-connected field effect transistor and resistor element And a current source transistor coupled between the output node and the node receiving the first voltage to drive a current of a certain magnitude,2A first resistance element connected between the internal power supply node receiving the voltage of the first and the first internal node, and a first internal resistance connected between the first resistance element and the gate of the current source transistor. A first reference transistor having the same conductivity type as the current source transistor, having a gate connected to the node, and connected between the internal power supply node and the second internal node, and the gate connected to the first internal node Connected between the second reference transistor of the same conductivity type as the current source transistor, the gate of the current source transistor and the node receiving the second voltage, and the gate is connected to the second internal node. And a third reference transistor having the same conductivity type as the current source transistor, and a second resistance element connected between the second internal node and the node receiving the second voltage.
[0071]
  In a seventh aspect, a semiconductor device according to the present inventionFurthermore, a first amplification circuit that differentially amplifies the complementary signal pair to generate a complementary output signal, and a complementary output signal that outputs the first amplification circuit is further differentially amplified, A second amplifying circuit for generating first and second driving signals having the same logic level and different voltage levels applied to the gates of the first and fourth transistors, and an image driven in accordance with an output signal of the functional circuit; Display element andWith. The output signal of this functional circuit is output from the connection point of the second and third field effect transistors.
[0072]
Preferably, the first amplifier circuit includes a first differential stage for differentially amplifying the complementary signal pair, a first latch stage for latching an output signal of the first differential stage, and the first differential stage. A first amplitude limiting stage connected between one differential stage and a first latch stage to limit the amplitude of a signal transferred between the first differential stage and the first latch stage including. The second amplifier circuit includes a second differential stage that differentially amplifies the latch signal of the first latch stage, a second latch stage that latches the output signal of the second differential stage, A second amplitude limiter connected between the second differential stage and the second latch stage to limit the amplitude of the signal transferred between the second differential stage and the second latch stage. Includes steps. The latch signal of the second latch stage and the output signal of the second differential stage are applied to the gates of the first and fourth field effect transistors, respectively.
[0073]
Preferably, the image display element is composed of either a liquid crystal display element or an electroluminescence light emitting element.
[0074]
Each field effect transistor is a thin film transistor.
Preferably, the first voltage is set to a voltage level higher than the second voltage.
[0075]
Instead, the second voltage is set to a higher voltage level than the first voltage.
[0078]
By generating and using a voltage that suppresses the influence corresponding to the output signal of the threshold voltage of the first and fourth field effect transistors as the bias voltage, even if the threshold voltage varies in manufacturing parameters Therefore, the output signal can be generated stably while suppressing the influence of the variation in threshold voltage.
[0079]
In addition, by generating a voltage including a threshold voltage component having the same magnitude as the threshold voltage of the second and third transistors as the bias voltage, the first or fourth threshold voltage component can be used. The influence of variations in the threshold voltage of the transistor can be canceled out, and an output signal can be generated stably.
[0080]
Further, by driving the current source transistor by a circuit composed of a resistance element and a MOS transistor, the gate voltage of the current source transistor can be set to a voltage level independent of the power supply voltage, and the current source transistor can be set to the gate of the current source transistor. A voltage that cancels the influence of the threshold voltage can be applied, and a constant current can be generated stably. Therefore, by applying this circuit to the bias voltage generation circuit, a bias voltage for stably removing the influence of the threshold voltage can be generated based on a constant current that does not depend on the power supply voltage. Accordingly, the dependency of the bias voltage on the power supply voltage can be eliminated.
[0081]
In particular, when this semiconductor device is applied to an image display device, even when a circuit is configured using thin film transistors with large variations in threshold voltage, a bias voltage is stably generated and an output signal is output accordingly. The image display element can be driven by generating.
[0082]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
FIG. 1 shows a configuration of a bias voltage generating circuit according to the first embodiment of the present invention. FIG. 1 shows a configuration of a bias voltage generation circuit BPK that generates a bias voltage VP. Bias voltage VP generated by bias voltage generation circuit BPK is applied to the gate of P channel MOS transistor PQ1 included in functional circuit 1.
[0083]
Similar to the configuration shown in FIG. 26, functional circuit 1 has P channel MOS transistor PQ0 receiving input signal IN2 at its gate, N channel MOS transistor NQ1 receiving bias voltage VN at its gate, and input signal IN1 as its gate. N channel MOS transistor NQ0 for receiving is included.
[0084]
An output signal OUT0 is output from a connection point between the MOS transistor PQ1 and the MOS transistor NQ1.
[0085]
Bias voltage generation circuit BPK includes P channel MOS transistors 101 and 102 and resistance element 103 connected in series between a power supply node and bias output node 106. P channel MOS transistors 101 and 102 have gates connected to nodes 104 and 105, respectively. Resistance element 103 has a resistance value r. These nodes 104 and 105 function as drain nodes of MOS transistors 101 and 102.
[0086]
Bias voltage generation circuit BPK further includes a constant current source 100 connected between output node 106 and the ground node, and a decoupling capacitor 107 connected between the power supply node and output node 106. The constant current source 100 may be coupled to a constant voltage node that supplies a constant voltage such as a negative voltage instead of the ground node. The decoupling capacitor 107 has a capacitor C, removes a noise component of the bias voltage VP due to capacitive coupling, and stabilizes the voltage level of the bias voltage VP.
[0087]
It is assumed that the driving current of constant current source 100 is current I, which is a current level sufficiently smaller than the current that can be driven by MOS transistors 101 and 102. In this case, MOS transistors 101 and 102 operate in a diode mode, causing a voltage drop of the absolute value of threshold voltage VTP. Here, it is assumed that threshold voltage VTP of MOS transistors 101 and 102 is the same as the threshold voltage of P channel MOS transistors PQ1 and PQ0 of functional circuit 1. That is, the bias voltage generation circuit BPK is created in the same manufacturing process as the output circuit 1, and no special ion implantation or the like for setting a threshold voltage for generating the bias voltage is performed.
[0088]
Under this condition, the bias voltage VP is expressed by the following equation (9).
VP = VCC-2 · | VTP | −r · I (9)
Consider a case where the input signal IN2 is at the voltage level of the voltage VP + | VTP | and a voltage is applied between the gate and source of the MOS transistor PQ0. In this case, the voltage VGS0 applied between the gate and source of the MOS transistor PQ is represented by the following equation (10) from the previous equation (3).
[0089]
VGS0 = VP + | VTP | -VCC
= VCC-2 · | VTP | −r · I + | VTP | −VCC
=-| VTP | -r · I (10)
In this case, the drive current I0 of the MOS transistor PQ0 is expressed by the following equation from the above equation (2).
[0090]
I0∝ (-| VTP | -r · I-VTP)
Since threshold voltage VTP is a negative value, the threshold voltage component is canceled out in the above equation, and current I0 is expressed by the following equation (11).
[0091]
I0∝ (−r · I) (11)
As shown in the above equation (11), the drive current of the MOS transistor PQ0 is determined by the resistance value r of the resistance element 103 and the drive current I of the constant current source 100, and is independent of the threshold voltages VTP and VTN. It is. Therefore, since the drive current of MOS transistor PQ0 is not affected by variations in threshold voltages VTP and VTN, it is possible to prevent a reduction in circuit operation margin due to variations in threshold voltages VTP and VTN. it can.
[0092]
In the case of a MOS semiconductor circuit device, the resistance element 103 can be formed using a channel resistance of an MOS transistor, an impurity diffusion layer, or a wiring layer such as polysilicon. When used in a drive circuit integrated in an image display device, the MOS transistor is a thin film transistor. In this case, the resistance element 103 may be formed using a thin film resistor or a gate electrode material.
[0093]
A power supply voltage VCC is applied to the power supply node. However, the bias voltage generation circuit BPK only needs to be at a voltage level that operates stably, and a high voltage may be used instead of the power supply voltage VCC. The same applies to the ground voltage VSS.
[0094]
As described above, according to the first embodiment of the present invention, the bias voltage VP is configured to include the threshold voltage component of the output drive transistor included in the functional circuit 1. The drive current amount can be set to the same current amount as the threshold voltage, and the output signal can be driven stably without receiving variations in the threshold voltage.
[0095]
[Embodiment 2]
FIG. 2 shows a configuration of a bias voltage generating circuit according to the second embodiment of the present invention. The bias voltage generation circuit BPK shown in FIG. 2 uses a current mirror circuit as the constant current source 100 shown in FIG.
[0096]
That is, bias voltage circuit BPK shown in FIG. 2 is connected between a power supply node receiving power supply voltage VCC and resistance element 109 connected between node 99 and node 99 and a ground node receiving ground voltage VSS. N channel MOS transistor 108 having its gate connected to node 99, and N channel MOS transistor 110 having its gate connected to node 99 and connected between output node 106 and the ground node. The other configuration of the bias voltage generating circuit BPK shown in FIG. 2 is the same as the configuration of the bias voltage generating circuit BPK shown in FIG. 1, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.
[0097]
The resistance element 109 has a resistance value R. The magnitude of the current flowing through resistance element 109 and MOS transistor 108 is determined by channel resistance (ON resistance) of resistance element 109 and MOS transistor 108. MOS transistors 110 and 108 constitute a current mirror circuit, and a mirror current of the current flowing through MOS transistor 108 flows through MOS transistor 110.
[0098]
When resistance value R of resistance element 109 is sufficiently larger than the channel resistance of MOS transistor 108, the current flowing through MOS transistor 108 is determined by resistance value R of resistance element 109. When MOS transistors 110 and 108 have the same size (ratio between channel width and channel length) and the mirror ratio is 1, a current having the same magnitude as the current flowing through MOS transistor 108 passes through MOS transistor 110. Flowing. Therefore, when MOS transistors 110 and 108 have the same size (ratio of channel width to channel length) and the mirror ratio is set to 1, MOS transistors 108 and 110 generate the same gate-source voltage.
[0099]
In the component r · I included in the bias voltage VP, the current I can be approximated by VCC / R. In this case, the resistance elements 103 and 109 are formed of the same resistance material so that the same resistance value variation appears in the resistance elements 109 and 103. The influence of the variation in the resistance value r of the resistance element 103 on the bias voltage VP can be offset by the variation in the resistance value of the resistor 109, and the bias voltage VP having a desired voltage level can be generated stably.
[0100]
As described above, according to the second embodiment of the present invention, a current mirror circuit is used to generate a constant current, and the constant current component includes a component that manipulates a resistance component included in the bias voltage. Thus, the bias voltage VP having a constant voltage level can be generated stably without being affected by the resistance variation of the resistance element during manufacturing.
[0101]
[Embodiment 3]
FIG. 3 shows a structure of a bias voltage generating circuit according to the third embodiment of the present invention. The bias voltage generation circuit BPK shown in FIG. 3 differs from the configuration of the bias voltage generation circuit BPK shown in FIG. 2 in the configuration of the circuit that generates the gate voltage of the N-channel MOS transistor 110 connected to the output node 106.
[0102]
That is, in bias voltage generation circuit BPK shown in FIG. 3, gate voltage generation circuit includes resistance element 111 connected between the power supply node and node 114, and is connected between node 114 and node 115 and the gate thereof is connected. N channel MOS transistor 112 connected to node 114, N channel MOS transistor 113 connected between node 115 and ground node and having its gate connected to node 118, and connected between the power supply node and node 118. N channel MOS transistor 116 having its gate connected to node 114, and resistance element 117 connected between node 118 and the ground node are included.
[0103]
Resistance elements 111 and 117 have resistance values R1 and R2, respectively. Resistance values R1 and R2 of resistance elements 111 and 117 are sufficiently larger than channel resistances (ON resistances) of MOS transistors 112, 113, and 116.
[0104]
The gate of MOS transistor 110 is connected to node 115.
The other configuration of the bias voltage generating circuit shown in FIG. 3 is the same as the configuration of the bias voltage generating circuit shown in FIG. 2. Corresponding portions are allotted with the same reference numerals, and detailed description thereof is omitted.
[0105]
In the configuration of the bias voltage generation circuit BPK, the resistance value R1 of the resistance element 111 is set to a value sufficiently larger than the channel resistance (ON resistance) of the MOS transistor 112, and the MOS transistor 112 operates in a diode mode. When conducting, a voltage drop of the threshold voltage VTN occurs.
[0106]
MOS transistor 113 discharges a current corresponding to the voltage of node 118 to the ground node, and sets the voltage level of node 115 to an appropriate value.
[0107]
A voltage lower than power supply voltage VCC is transmitted to node 114 by resistance value R1 of resistance element 111. The voltage level of node 114 is dependent on power supply voltage VCC. The MOS transistor 116 operates in the source follower mode because its gate voltage is lower than the drain voltage (VCC) and its on-resistance is sufficiently smaller than the resistance value R2 of the resistance element 117. Therefore, when the voltage level at node 114 decreases, the increase in voltage at node 114 is transmitted to node 118 by the source follower mode operation of MOS transistor 116. Accordingly, the conductance of MOS transistor 113 increases and the voltage level of node 115 is lowered. As a result, the voltage level of node 114 decreases accordingly.
[0108]
On the contrary, when the voltage level of the node 114 decreases, the voltage level of the node 118 decreases due to the source follower mode operation of the MOS transistor 116, the conductance of the MOS transistor 113 decreases accordingly, and the voltage level of the node 25 increases. To do. Accordingly, the voltage level of node 114 increases.
[0109]
Therefore, by appropriately selecting the sizes of these MOS transistors 112 and 116, the voltage level of node 115 can be maintained at a constant voltage level regardless of fluctuations in power supply voltage VCC.
[0110]
Since the voltage level of node 115 does not depend on power supply voltage VCC, MOS transistor 110 can drive a current that does not depend on power supply voltage VCC. Accordingly, in the functional circuit 1, the drive current can be set to a constant current that does not depend on the power supply voltage VCC, and the functional circuit 1 can be operated stably.
[0111]
A configuration in which a constant voltage that does not depend on the power supply voltage VCC is applied to the gate of the MOS transistor 110 and a constant current is driven through the MOS transistor 110 is generally not a bias voltage generation circuit but a general semiconductor device. Can be applied.
[0112]
[Embodiment 4]
4 schematically shows a configuration of a semiconductor device according to the fourth embodiment of the present invention. In FIG. In the configuration of the semiconductor device shown in FIG. 4, the operating current of functional circuit 1A receiving voltage V3 as one operating power supply voltage is determined by driving current I3 of MOS transistor 110. The functional circuit 1A processes an internal signal to generate an output signal VOUT. If the operating current is a circuit determined by the MOS transistor 110, an arbitrary semiconductor circuit can be applied as the functional circuit 1A. For example, the functional circuit 1A is a differential amplifier circuit in which an operating current is determined by a current source.
[0113]
In order to drive gate node 115 of MOS transistor 110, the same configuration as the gate voltage generation circuit shown in FIG. 3 is used. In the circuit for generating the gate voltage at the node 115 shown in FIG. 4, the same reference numerals are given to the portions corresponding to the gate voltage generating circuit shown in FIG. 3, and the detailed description thereof is omitted.
[0114]
In the configuration of the gate voltage generating circuit shown in FIG. 4, voltages V1 and V2 are used in place of power supply voltage VCC and ground voltage VSS, respectively. The voltage V1 may be at the same voltage level as the one operation power supply voltage V3 of the functional circuit 1A. The voltage V2 may be the ground voltage VSS. The voltage level of the voltage V2 can be set to an arbitrary value as long as it is a voltage level that can generate a constant voltage at the gate node 115. Therefore, the voltage V2 may be a negative voltage. . The voltage V1 may be a high voltage.
[0115]
In the case of a MOS integrated circuit device, resistance elements 117 and 111 can use a channel resistance of a MOS transistor, a resistance of an impurity diffusion layer, and a wiring layer such as polysilicon as a resistance. In addition, when the functional circuit 1A is integrated in an image display device and a thin film transistor (TFT) is used as a constituent element thereof, a thin film resistor or a gate electrode material of the TFT is used as the resistance elements 111 and 117. May be used.
[0116]
In the gate voltage generating circuit shown in FIG. 4, current I2 flowing through MOS transistors 112 and 113 is expressed by the following equation (12).
[0117]
I2 = β112 · (V114−V115−VTN)²/ 2
= Β113 · (V118−V2−VTN)²/ 2 ... (12)
Voltages V114, V115, and V118 indicate the voltages of nodes 114, 115, and 118, respectively. Β112 and β113 are constants determined by the sizes and constituent materials of the MOS transistors 112 and 113, respectively.
[0118]
When MOS transistors 112 and 113 have the same size, since these MOS transistors 112 and 113 are made of the same material, coefficients β112 and β113 are equal to each other. Therefore, the following equation (13) is obtained from the above equation (12).
[0119]
V114-V115-VTN = V118-V2-VTN
V114-V115 = V118-V2
V114−V118 = V115−V2 (13)
This equation (13) shows that the gate-source voltages of the MOS transistors 116 and 110 are at the same voltage level. The MOS transistor 116 is operating in the saturation region. Therefore, by operating the MOS transistor 110 in the saturation region, the mirror current of the current I1 flowing through the MOS transistor 116 can be passed to the MOS transistor 110. When MOS transistors 116 and 110 have the same size (the ratio between the channel length and the channel width is the same), current I3 flowing through MOS transistor 110 is the same as current I1 flowing through MOS transistor 116. .
[0120]
In the case of operating in the saturation region, the MOS transistor 116 is required to have a condition that the difference between the gate-source voltage V114-V118 and the threshold voltage VTN is smaller than the drain-source voltage V1-V118.
[0121]
The same applies to the MOS transistor 110.
Therefore, by utilizing the circuit configuration shown in FIG. 4, when functional circuit 1A is, for example, a current mirror type differential amplifier circuit using a constant current source, a differential amplification operation can be performed stably.
[0122]
By setting voltages V2 and V1 to appropriate voltage levels, MOS transistors 110, 113 and 116 of this circuit can be reliably operated in the saturation region.
[0123]
As described above, according to the fourth embodiment of the present invention, a voltage independent of the power supply voltage is generated using the negative feedback of the MOS transistor, and a constant current is generated using this voltage. Thus, the functional circuit can be stably operated without being affected by the fluctuations of.
[0124]
[Embodiment 5]
FIG. 5 shows a structure of a bias voltage generating circuit according to the fifth embodiment of the present invention. The bias voltage generation circuit BPK shown in FIG. 5 includes diode-connected P-channel MOS transistors 101, 102, and 120 in series between a power supply node that receives the power supply voltage VCC and an output node 106 that outputs the bias voltage VP. A resistance element 122 connected between the output node 106 and the ground node receiving the ground voltage VSS, and a decoupling capacitor 107 connected between the power supply node and the output node 106 are included.
[0125]
Since resistance value R of resistance element 122 is sufficiently larger than the on-resistance of MOS transistors 101, 102, and 120, these MOS transistors 101, 102, and 120 operate in a diode mode, and are each turned on when threshold voltage is reached. This causes a voltage drop of the absolute value of VTP.
[0126]
Therefore, in the case of the bias voltage generating circuit shown in FIG. 5, the bias voltage VP is expressed by the following equation (14).
[0127]
VP = VCC-3 · | VTP | (14)
In this case, in the functional circuit 1, when the input signal IN2 of the MOS transistor PQ0 is the voltage VP + | VTP |, the gate-source voltage VGS0 is expressed by the following equation (15).
[0128]
VGS0 = VP + | VTP | -VCC
= -2 · | VTP | (15)
Therefore, in this case, the drive current I0 of the MOS transistor PQ0 of the functional circuit 1 is expressed by the following equation (16).
[0129]
I∝ (− | VTP |) (16)
Therefore, as shown in the above equation (16), in the functional circuit 1, the drive current of the MOS transistor PQ0 is affected by variations in the threshold voltage VTP. However, compared to a configuration using a constant current source, the circuit configuration is simplified, the number of paths through which current flows is small, and the current flowing through the resistance element 122 is also small, so that the effect of sufficiently reducing power consumption is achieved. can get. Therefore, by applying bias voltage generation circuit 10 shown in FIG. 5 to a MOS semiconductor circuit device having a relatively small variation in threshold voltage VTP, bias voltage VP can be generated with low current consumption. Can do. In this configuration, the reliability of the gate insulating film of the MOS transistor in the functional circuit 1 can be ensured even when the power supply voltage VCC is high.
[0130]
In the bias voltage generating circuit 10 shown in FIG. 5, a diode-connected N-channel MOS transistor may be used instead of the P-channel MOS transistor 120, or a diode element may be used. In this case, a drive current I0 proportional to VTN or VPN is obtained. VTN represents a threshold voltage of a diode-connected N channel MOS transistor, and VPN represents a forward drop voltage of the diode element.
[0131]
[Embodiment 6]
FIG. 6 shows a configuration of bias voltage generation circuit BNK according to the sixth embodiment of the present invention. The bias voltage generation circuit BNK shown in FIG. 6 generates a bias voltage VN to be applied to the gate of the N channel MOS transistor NQ1 included in the functional circuit 1.
[0132]
In FIG. 6, the bias voltage generation circuit BNK includes a constant current source 200 connected between a power supply node that receives the power supply voltage VCC and an output node 206 that outputs the bias voltage VN, and between the constant current source 206 and the node 205. Resistance element 203 to be connected and diode-connected N channel MOS transistors 202 and 201 connected in series between node 205 and a ground node receiving ground voltage VSS are included.
[0133]
The constant current source 200 supplies a current I, and the resistance element 203 has a resistance value r. A decoupling capacitor 199 is provided between the output node 206 and the ground node for suppressing noise caused by capacitive coupling of the bias voltage VN. The decouple capacity 199 has a sufficiently large capacity value C.
[0134]
In bias voltage generating circuit BNK shown in FIG. 6, resistance element 203 causes a voltage drop of voltage r · I. MOS transistors 202 and 201 have gates connected to nodes 205 and 204, respectively, and operate in a diode mode. When conducting, each causes a drop in threshold voltage VTN.
[0135]
Therefore, bias voltage VN from output node 206 is expressed by the following equation (17).
[0136]
VN = 2 · VTN + r · I (17)
When input signal IN1 is voltage VN-VTN, gate-source voltage VGSN0 of N-channel MOS transistor NQ0 is expressed by the following equation (18).
[0137]
VGSN0 = VN-VTN
= R · I + VTN (18)
Therefore, the current In driven by the MOS transistor NQ0 is expressed by the following equation (19).
[0138]
In∝ (r · I + VTN−VTN)
∝ (r · I) (19)
Therefore, when the output signal is driven to the ground voltage level by MOS transistor NQ0, the output node can be driven with a constant current.
[0139]
In Patent Document 1, the threshold voltage is increased by ion implantation, and the gate potentials of MOS transistors NQ0 and NQ1 are set using the difference between threshold voltage VTH and threshold voltage VTN. ing. However, when a circuit for generating such a threshold voltage VTH is used for generating a bias voltage, it is necessary to increase the manufacturing process in order to change the threshold voltage. Therefore, when low cost is required, it may not be possible to generate such a plurality of types of threshold voltages from the viewpoint of cost. Therefore, by making all the threshold voltages of the N channel MOS transistors the same, the output signal can be stably driven to the ground voltage level.
[0140]
As described above, according to the sixth embodiment of the present invention, bias voltage VN is generated using a transistor that generates a threshold voltage having the same magnitude as the MOS transistor of the functional circuit of the output section as bias voltage VN. Therefore, the bias voltage VN that can drive the output signal stably can be generated without increasing the number of manufacturing steps.
[0141]
[Embodiment 7]
FIG. 7 shows a structure of bias voltage generation circuit BNK according to the seventh embodiment of the present invention. In the bias voltage generation circuit BNK shown in FIG. 7, a current mirror circuit is used as the constant current source 200 shown in FIG.
[0142]
That is, bias voltage generation circuit BNK is connected between a power supply node and node 206 and has its gate connected to node 210, and is connected between the power supply node and node 210 and its gate is connected to node 210. P channel MOS transistor 208 connected to node 210 and a resistance element 209 connected between node 210 and the ground node are included. Resistance element 210 has a resistance value R.
[0143]
The other configuration of the bias voltage generating circuit BNK shown in FIG. 7 is the same as the configuration of the bias voltage generating circuit shown in FIG. 6, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.
[0144]
In the configuration of bias voltage generation circuit BNK shown in FIG. 7, a current determined by the channel conductance (ON resistance) of MOS transistor 208 and resistance value R of resistance element 209 passes through MOS transistor 208 and resistance element 209. Flowing. A mirror current of the current flowing through the MOS transistor 208 is supplied to the output node 206 through the MOS transistor 207. Therefore, the current I is expressed by the following equation (20).
[0145]
I = M · VCC / (R + Rcha) (20)
Here, Rcha is the channel resistance of the MOS transistor 208. M represents a mirror coefficient of a current mirror circuit composed of the MOS transistors 207 and 208. Therefore, the bias voltage VN is expressed by the following equation (21).
[0146]
VN = M · VCC · r / (R + Rcha) + 2 · VTN (21)
Therefore, the drive current Inq0 of the MOS transistor NQ0 included in the functional circuit 1 when the input signal IN1 is voltage VN-VTN is expressed by the following equation (22).
[0147]
Inq0∝M · r · VCC / (Rcha + R) (22)
When the Miller coefficient M is 1 and the channel resistance Rcha can be ignored as compared with the resistance value R of the resistance element 209, the manufacturing parameters vary in the resistance values r and R of the resistance elements 209 and 203. The resulting variation in resistance value can be offset.
[0148]
Therefore, even in this case, the driving current of MOS transistor MQ0 can be set stably without being affected by variations in threshold voltage VTN of the MOS transistor. Further, in order to generate bias voltage VN, it is possible to generate a bias voltage using an N channel MOS transistor having the same threshold voltage as N channel MOS transistors NQ1 and NQ0 included in functional circuit 1. A manufacturing process becomes unnecessary and manufacturing cost can be reduced.
[0149]
[Embodiment 8]
FIG. 8 shows a configuration of bias voltage generating circuit BNK according to the eighth embodiment of the present invention. In bias voltage generating circuit BNK shown in FIG. 8, the following constant current source circuit is provided as a circuit for supplying constant current I to output node 206.
[0150]
That is, in FIG. 8, the constant current source circuit is connected between a power supply node and node 215, and P channel MOS transistor 207 connected between power supply node and output node 206 and having its gate connected to node 215. P channel MOS transistor 213 having its gate connected to node 218, P channel MOS transistor 212 having its gate connected to node 214 and having its gate connected to node 214, node 214 and ground node Resistance element 211 connected in between, resistance element 217 connected between the power supply node and node 218, and P-channel MOS transistor connected between node 218 and ground node and having its gate connected to node 214 including.
[0151]
Resistance element 211 has a resistance value R1, and resistance element 217 has a resistance value R2. Resistance value R1 of resistance element 211 has a sufficiently large channel resistance (ON resistance) when MOS transistors 212 and 213 are conductive, and resistance value R2 of resistance element 217 is sufficiently larger than the ON resistance of MOS transistor 216.
[0152]
MOS transistor 212 operates in a diode mode, and causes a voltage drop of voltage | VTP | when conducting. MOS transistor 216 operates in the source follower mode because the voltage level of its gate (node 214) is higher than the voltage level of its drain (ground node).
[0153]
When power supply voltage VCC varies and the amount of current flowing through MOS transistors 213 and 212 increases, the voltage level of node 214 increases. This voltage increase at node 214 is transmitted to node 218 by the source follower mode operation of MOS transistor 214, and the voltage level at node 218 increases. Accordingly, the absolute value of the gate-source voltage of MOS transistor 213 decreases, the supply current of MOS transistor 213 decreases, and the voltage level of node 214 decreases.
[0154]
On the other hand, when the voltage level of node 214 decreases, the voltage decrease of node 214 is transmitted to node 218 by MOS transistor 216. Due to the voltage drop at node 218, the on-resistance of MOS transistor 213 decreases, the supply current of MOS transistor 213 increases, and the voltage level at node 214 increases.
[0155]
Node 214 is therefore at a constant voltage level by feedback control of MOS transistors 213 and 216 regardless of fluctuations in power supply voltage VCC. When resistance values R2 and R1 of resistance elements 217 and 211 are sufficiently high, only a minute current flows through these MOS transistors 213, 212 and 216. MOS transistor 213 inverts and amplifies the voltage at node 218 and transmits it to node 215. Therefore, voltage V218 at node 218 is at a voltage level at which MOS transistor 213 is substantially rendered conductive, and is expressed by the following equation (23).
[0156]
V218 = VCC− | VTP | (23)
The voltage at node 214 is transmitted to node 218 by the source follower mode of MOS transistor 216. Therefore, voltage V214 at node 214 is expressed by the following equation (24).
[0157]
V214 = V218- | VTP |
= VCC-2 · | VTP | (24)
MOS transistor 212 operates in a diode mode, and sets the voltage level of node 215 to a voltage level higher than voltage | VTP | Therefore, voltage V215 at node 215 is expressed by the following equation (25).
[0158]
V215 = V214 + | VTP |
= VCC- | VTP | (25)
MOS transistor 207 supplies current I to node 206 in accordance with voltage V 215 at node 215. Therefore, the gate-source voltage of the MOS transistor 207 is | VTP |, and the current I supplied from the MOS transistor 207 is a constant current independent of the power supply voltage VCC. Here, it is assumed that the threshold voltages of the MOS transistors 212, 213, and 216 are all equal.
[0159]
When MOS transistors 213 and 207 have the same size, the gate-source voltages of these MOS transistors 213 and 207 are the same, and currents of the same magnitude flow. Therefore, MOS transistors 202 and 201 can be operated in a diode mode to stably cause a voltage drop of threshold voltage VTN, and a bias voltage VN independent of power supply voltage VCC can be generated.
[0160]
[Embodiment 9]
The constant current source shown in FIG. 8 can be applied to a general semiconductor circuit device. In the semiconductor circuit device shown in FIG. 9, the circuit that generates the constant current I shown in FIG. 8 is used as a current source for the functional circuit 1B. In the constant current generating circuit shown in FIG. 9, voltage V1 is used instead of power supply voltage VCC, and voltage V2 is used instead of ground voltage VSS. Functional circuit 1B receives low-side power supply voltage V3 as one power supply voltage, and also receives current I3 from MOS transistor 207 as an operating current. The functional circuit 1B is a circuit that requires a constant current, such as a current mirror type differential amplifier circuit, for example, and performs a predetermined process to generate an output signal VOUT.
[0161]
The voltage V3 applied to the functional circuit 1B may be the voltage V2. This voltage V2 may also be the ground voltage VSS.
[0162]
This constant current generating circuit has the same circuit configuration as that of the constant current generating circuit shown in FIG. 8. Corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted. The voltages V1 and V2 may be any power supply voltage level at which the MOS transistors 212, 213, and 216 included in the constant current generating circuit operate in the saturation region.
[0163]
In this constant current generating circuit, resistance elements 211 and 217 are high resistance resistance elements, and in the case of MOSLSI, are constituted by a channel resistance, an impurity diffusion layer, or a wiring layer such as polysilicon. When the functional circuit 1B is used in an image display device and is configured by a TFT circuit, the resistance elements 211 and 217 may be configured by a thin film resistor or a TFT gate electrode material.
[0164]
In the constant current generating circuit shown in FIG. 9, I2 flowing through MOS transistors 212 and 213 is expressed by the following equation (26) because MOS transistors 213 and 213 operate in the saturation region.
[0165]
I2 = β212 · (V214−V215−VTP)²/ 2
= Β213 · (V213−V1−VTP)²/ 2 ... (26)
Here, β212 and β213 indicate the conduction coefficients of MOS transistors 212 and 213, respectively, and V214, V215, and V218 indicate the voltage levels of nodes 214, 215, and 218, respectively.
[0166]
When MOS transistors 212 and 213 are configured with the same size, their conductivity coefficients β212 and β213 are equal. Therefore, when the above equation (26) is arranged, the following equation (27) is obtained.
[0167]
V214−V215−VTN = V218−V1−VTP
V214−V215 = V218−V1
V214−V218 = V215−V1 (27)
The above equation (27) indicates that the gate-source voltages of the MOS transistors 207 and 216 are the same. The MOS transistor 216 operates in the saturation region and discharges the current I1. When resistance values of resistance elements 217 and 211 are sufficiently large, the gate-source voltage of MOS transistor 216 is at the voltage VTP level. Therefore, when the MOS transistor 207 is also operated in the saturation region, the current I3 flowing through the MOS transistor 207 also becomes a current independent of the power supply voltage VCC. When MOS transistors 216 and 207 have the same size, current I1 is equal to current I3.
[0168]
Therefore, as long as voltages V1, V2, and V3 satisfy the condition that MOS transistors 212, 213, 216, and 207 operate in the saturation region, a constant current that does not depend on voltage V1 is supplied to functional circuit 1B. And the functional circuit 1B can be stably operated.
[0169]
[Embodiment 10]
FIG. 10 shows a configuration of bias voltage generation circuit BNK according to the tenth embodiment of the present invention. The bias voltage generation circuit BNK shown in FIG. 10 includes a resistance element 222 connected between a power supply node receiving the voltage VA and the output node 206, and a diode connected in series between the output node 206 and the ground node. N channel MOS transistors 220, 202 and 201 connected are included. Bias voltage VN is output from output node 206. The output node 206 is provided with a decoupling capacitor 199 for stabilizing the bias voltage VN.
[0170]
The voltage VA may be a voltage level at which the MOS transistors 201, 202 and 220 operate stably in the diode mode.
[0171]
In bias voltage generation circuit BNK shown in FIG. 10, resistance value Rb of resistance element 222 is set to a value sufficiently larger than the ON resistance of MOS transistors 220, 202, and 201, and MOS transistors 220, 202, and 201 are in diode mode. Works with. These MOS transistors 220, 202 and 201 cause a voltage drop of threshold voltage VTN when conducting. Therefore, 3 · VTN is obtained as the bias voltage VN. In this case, in the functional circuit 1, when VN-VTN is applied as the input signal IN1 to the MOS transistor NQ0, the drive current Inq0 of the MOS transistor NQ0 is expressed by the following equation (28).
[0172]
Inq0∝ (VN−VTN−VTN) ∝ (VTN) (28)
Therefore, in this case, drive current Inq0 of MOS transistor NQ0 is affected by variations in threshold voltage VTN. However, only diode-connected N-channel MOS transistors 220, 202 and 201 are used, and their threshold voltage VTN can be set to be the same as MOS transistors NQ0 and NQ1 of functional circuit 1. The functional circuit 1 can generate the output signal according to the input signal IN1 by generating the bias voltage BN without increasing the number of manufacturing steps. Further, the circuit configuration is simplified, the resistance value Rb of the resistance element 222 is also a sufficiently large value, the area occupied by the circuit configuration for generating the bias voltage BN can be reduced, and the power consumption can be reduced. it can.
[0173]
[Embodiment 11]
FIG. 11 schematically shows a whole structure of the semiconductor device according to the eleventh embodiment of the present invention. In the eleventh embodiment, bias voltage generation circuits BPK and BNK and functional circuit 1 shown in the first to tenth embodiments are used for driving pixels in the image display device.
[0174]
That is, the semiconductor device according to the eleventh embodiment of the present invention includes a display pixel matrix 300 including a plurality of display pixel elements arranged in a matrix, and data lines (not shown) of display pixel matrix 300 according to pixel data PD. A data driver 304 for driving and a gate driver 302 for selecting pixel elements of the display pixel matrix 300 according to a timing signal are included. The gate driver 302 drives the gate lines arranged corresponding to each display pixel element row of the display pixel matrix 300 in a predetermined sequence.
[0175]
The data driver 304 includes a shift register or a switching transistor, and transmits a voltage corresponding to the pixel data to a data line arranged extending in the direction of each column in the display pixel matrix 300 according to the pixel data PD. At the time of data line driving, each data line may be sequentially selected and driven according to pixel data, and pixel data is simultaneously written to one row of pixel elements connected to one gate line. May be rare.
[0176]
In the gate driver 302, the circuits described in the first to tenth embodiments are used to drive the gate lines for driving the display pixel elements of the display pixel matrix 300 to the selected state.
[0177]
FIG. 12 is a diagram schematically showing a configuration of a portion related to one display pixel element PX of the gate driver 302 and the display pixel matrix 300 shown in FIG. 12, the gate driver 302 receives the timing signal TINi and performs buffer processing to generate complementary signals TIN and ZTIN, and output signals TIN and ZTIN of the amplitude power supply voltage VDD of the input buffer circuit 310, A level conversion circuit 312 for converting the voltage levels to voltages VH and VL and a gate line drive circuit 314 for driving the gate line 44 in accordance with an output signal of the level conversion circuit 312 are included.
[0178]
The level conversion circuit 312 generates a small amplitude signal according to the bias voltages VP and VN, and drives the gate line drive circuit 314 according to the small amplitude signal. Gate line drive circuit 314 corresponds to functional circuit 1 in the first to tenth embodiments, and drives corresponding gate line 44 in accordance with the output signal of level conversion circuit 312 and bias voltages VP and VN.
[0179]
In the display pixel matrix 300, a gate drive line 44 is provided corresponding to each row of the display pixel elements PX, and a data line 45 is provided corresponding to each column of the display pixel elements PX. When the voltage corresponding to the pixel data PD shown in FIG. 11 is transmitted to the data line 45 and the gate line 44 is driven to the selected state, the pixel data transmitted on the data line 45 is stored in the display pixel element PX. Being held.
[0180]
FIG. 13 is a diagram showing an example of the configuration of the image display element PX shown in FIG. In FIG. 13, an image display element PX includes an N-channel MOS transistor 46 that is selectively turned on according to a signal on the gate line 44, and a capacitive element 48 that is connected between a storage node (pixel node) 47 and an electrode node 49. The liquid crystal element 50 connected between the storage node 47 and the counter electrode 51 is included.
[0181]
The MOS transistor 46 is usually composed of a thin film transistor (TFT). When the MOS transistor 46 is turned on, an image signal is transmitted on the data line 45 and the image signal is held in the storage node 47. The polarization state of the liquid crystal element 50 is determined according to the voltage between the counter electrode 51 and the storage node 47.
[0182]
Gate drive line 44 is driven between voltages VH and VL by gate line drive circuit 314 shown in FIG. The voltage VH is a high voltage higher than the power supply voltage VDD, and the voltage VL is a voltage lower than the ground voltage VSS. Hereinafter, the driving operation of the image display element PX will be briefly described.
[0183]
The gate lines 44 are sequentially driven to a selected state in a predetermined sequence. When the gate line 44 is selected and reaches the voltage VH level, the MOS transistor 16 is turned on, and the image signal transmitted to the data line 45 is transmitted to the storage node 47. When writing this image signal, voltage VH applied to gate line 44 is set to a sufficiently high voltage level so that threshold voltage loss of MOS transistor 46 does not occur. Thereby, the image signal applied to data line 45 is written into storage node 47 without receiving the threshold voltage loss of MOS transistor 46.
[0184]
After the writing of the image signal to storage node 47, gate line 44 is driven to the non-selected state, and its voltage level is set to voltage VL level. The image signal of the storage node 47 is held by the capacitive element 48. At this time, in order to prevent the voltage level of the image signal stored in the storage node 47 from changing due to the leak current flowing through the MOS transistor 46, it is required to set the MOS transistor 46 to a deep off state. Is done. Therefore, the negative voltage VL is applied to the gate line 44, and the reverse bias state between the gate and the source of the MOS transistor 46 is set sufficiently deep.
[0185]
The polarization state of the liquid crystal display element 50 is set according to the voltage held in the storage node 47, and the display state of the pixel PX is determined. As a display form of the display pixel element PX, either a reflection type or a transmission type may be used.
[0186]
Since the high voltage VH and the negative voltage VL are supplied to the image display element PX, a voltage higher than the power supply voltage VDD level is supplied to the gate line drive circuit 314. By applying the configuration of the functional circuit 1 shown in Embodiment Modes 1 to 10 to the gate line drive circuit 314, the reliability of the gate insulating film is ensured even when a high voltage is applied.
[0187]
Level conversion circuit 312 generates a signal that changes between voltage VH and voltage VP + | VTP | and a signal that changes between voltage VL and voltage VN−VTN in accordance with output signals TIN and ZTIN of input buffer circuit 310. .
[0188]
FIG. 14 shows a configuration of input buffer circuit 310 shown in FIG. In FIG. 14, input buffer circuit 310 includes a CMOS inverter IV1 receiving input timing signal TINi applied to input node 4, and a CMOS inverter IV2 receiving an output signal of CMOS inverter IV1. A complementary input signal ZTIN is output from the CMOS inverter IV1, and an input signal TIN is output from the CMOS inverter IV2.
[0189]
The input timing signal TINi determines the timing for driving the gate line and the active state period of the gate line, and is activated according to the vertical scanning sequence of the gate line.
[0190]
CMOS inverter IV1 is connected between a power supply node 311 receiving power supply voltage VDD and node 7, and has a P channel MOS transistor 5 whose gate is connected to input node 4, and ground node 312 receiving node 7 and ground voltage VSS. And an N channel MOS transistor 6 having its gate connected to input node 4. A signal ZTIN is output from the node 7.
[0191]
The power supply voltage VDD may be an external power supply voltage VCC as in the previous embodiment, or may be an internally generated power supply voltage. Here, in order to indicate that the power supply voltage is used as the operation power supply voltage in the image display device, the power supply voltage is indicated by the reference symbol VDD.
[0192]
CMOS inverter IV 2 is connected between power supply node 311 and node 10 and has its gate connected to node 7, and is connected between node 10 and ground node 312 and its gate is connected to node 7. N-channel MOS transistor 9 connected to. A signal TIN is output from the node 10.
[0193]
In these input buffer circuits 310, CMOS inverters IV1 and IV2 operate using power supply voltage VDD and ground voltage VSS as operating power supply voltages, and generate complementary input signals TIN and ZTIN in accordance with input timing signal TINi. Therefore, the signal ZTIN output from the CMOS inverter IV1 is a signal whose logic level is complementary to that of the input timing signal TINi, and the logic level of the TIN output from the CMOS inverter IV2 is the same as that of the input timing signal TIINi. is there.
[0194]
FIG. 15 shows a configuration of level conversion circuit 312 and gate line drive circuit 314 shown in FIG. In FIG. 15, level conversion circuit 312 receives level signals TIN and ZTIN of input buffer circuit 310 shown in FIG. 14, and generates a signal that changes between voltage VH and ground voltage. Level shift circuit 312B that receives the output signal of level shift circuit 312A and generates a signal that changes between voltage VH and voltage VP + | VTP | and a signal that changes between voltage VL and voltage VN−VTN is included.
[0195]
That is, the level shift circuit 312A converts the voltage VDD / VSS level of the input signal TIN into the voltage VH / VSS level. The level shift circuit 312B converts the voltage VH / VSS level converted by the level shift circuit 312A into the voltage VH / VL level.
[0196]
Level shift circuit 312A is connected between boost node 324 that receives high voltage VH and node 23a, and has a gate connected to node 24a, and is connected between boost node 324 and node 24a. P channel MOS transistor 12a having its gate connected to node 23a, P channel MOS transistor 19a connected between nodes 23a and 25a and receiving bias voltage VP at its gate, and between node 24a and node 26a P-channel MOS transistor 20a connected and receiving bias voltage VP at its gate, and N-channel MOS transistor 2 connected between nodes 25a and 27a and receiving bias voltage Vn applied to bias node 18a at its gate an N channel MOS transistor 22a connected between node 26a and node 28a and receiving bias voltage Vn at its gate; N connected between node 27a and ground node 322 and receiving input signal TIN at its gate; Channel MOS transistor 13a includes an N channel MOS transistor 14a connected between node 28a and ground node 322 and receiving input signal ZTIN at its gate.
[0197]
The bias voltage Vn is at a voltage level different from the bias voltage VN. This is because in the level shift circuits 312A and 312B, the low-level side power supply voltages are the ground voltage VSS and the negative voltage VL, respectively, and the voltage levels of the low-side power supply voltages are different from each other. The bias voltage Vn satisfies the relationship of the following equation.
[0198]
VN = Vn + | VL |
Bias voltage Vn is at a voltage level higher than the threshold voltage of MOS transistors 21a and 22a, and bias voltage VN is at least twice the threshold voltage VTN as in the seventh to tenth embodiments. Voltage level. The voltage levels of these bias voltages VN and Vn are appropriately determined according to the voltage level of the negative voltage VL.
[0199]
In level shift circuit 312A, MOS transistors 13a and 14a constitute a differential stage for differentially amplifying input signals TIN and ZTIN, and MOS transistors 11a and 12a latch the voltage amplified by this differential amplification stage. A latch stage is configured. MOS transistors 19a-22a are used to limit the amplitude of internal signals in level shift circuit 312A, respectively. Due to this amplitude limitation, even when the high voltage VH is used as the power supply voltage, the voltage applied to the gate insulating film of each MOS transistor is relaxed and the reliability of the gate insulating film is ensured.
[0200]
Level shift circuit 312B is connected between boost node 324 and node 23b and has its gate connected to node 24a, and is connected between boost node 324 and node 24b and has its gate connected to node P channel MOS transistor 12b connected to node 23a, P channel MOS transistor 19b connected between node 23b and node 25b and having its gate receiving bias voltage VP through bias node 17, and between nodes 24b and 26b P channel MOS transistor 20b connected to the gate and receiving bias voltage VP at its gate, and N channel MOS transistor connected between nodes 25b and 27b and having its gate receiving bias voltage VN via bias node 18b 1b, an N channel MOS transistor 22b connected between node 26b and node 28b and receiving a bias voltage VN at its gate, connected between node 27b and negative voltage node 326 and its gate connected to node 28b. N channel MOS transistor 13b, and N channel MOS transistor 14b connected between node 28b and negative voltage node 326 and having its gate connected to node 27b.
[0201]
In level shift circuit 312B, MOS transistors 11b and 12b constitute a differential stage for differentially amplifying complementary signals of level shift circuit 312A, and MOS transistors 13b and 14b are used for differentially amplified signals. A latch stage for latching the low level signal is configured. MOS transistors 19b to 22b function as an amplitude limiting circuit for electric field relaxation.
[0202]
A signal IN2 for the gate line drive circuit 314 is output from the node 23b, and a signal IN1 for the gate line drive circuit 314 is output from the node 27b.
[0203]
Bias voltages VP and VN are similarly applied to gate line drive circuit 314 for electric field relaxation.
[0204]
Gate line drive circuit 314 is connected between boosting node 324 and node 38, and receives at its gate a P-channel MOS transistor 41 receiving signal IN2 from node 23b of level shift circuit 312B, a node 38 and an output node 43 P-channel MOS transistor 40 connected between and having a gate receiving bias voltage VP, N-channel MOS transistor 37 connected between output node 43 and node 39 and receiving the bias voltage VN, and node 39 N channel MOS transistor 42 connected between negative voltage node 316 and having its gate receiving input signal IN1 from node 27b is included.
[0205]
All the MOS transistors in the level conversion circuit 312 and the gate line drive circuit 314 shown in FIG. 15 are formed of thin film transistors (TFTs).
[0206]
In the gate line drive circuit 314, one drive stage is shown. However, when the load on the gate line 44 driven by the gate line drive circuit 314 is large, a plurality of drive stages are cascaded in the gate line drive circuit 314 to drive the large load on the gate line 44 at high speed. It may be configured as follows. In the case of this cascade connection, signals from the nodes 38 and 39 are used as input signals to the next stage circuit. Bias voltages VP and VN are commonly applied to the cascaded circuits. A gate line drive signal DV is output from the node 43 of the final stage drive circuit.
[0207]
FIG. 16 schematically shows a configuration of a circuit for generating bias voltage VP shown in FIG. In FIG. 16, the bias voltage generation circuit BPK generates the bias voltage VP from the high voltage VP at the node 324 and the negative voltage VL at the node 326. As the configuration of the bias voltage generation circuit BPK, any of the configurations of the bias voltage generation circuit BPK described in the first to fifth embodiments may be used. Bias voltage VP is a voltage level of voltage VH−2 · | VTP | −r · I.
[0208]
FIG. 17 schematically shows a configuration of a circuit for generating bias voltage VN shown in FIG. In FIG. 17, the bias voltage generation circuit BNK generates a bias voltage VN from the high voltage VH at the node 324 and the negative voltage VL at the node 326. As the configuration of this bias voltage generation circuit BNK, any of the configurations of the previous seventh to tenth embodiments may be used. The voltage level of the bias voltage VN is 2 · VTN + r · I + VL.
[0209]
FIG. 18 schematically shows a configuration of a circuit for generating bias voltage Vn shown in FIG. The bias voltage generation circuit BNKn generates a bias voltage Vn from the high voltage VH at the node 324 and the ground voltage VSS at the node 322. The bias voltage generation circuit BNKn has a configuration similar to that of the bias voltage generation circuit BNK shown in FIG. 17, and any of the configurations in the previous seventh to tenth embodiments may be used as the circuit configuration. The voltage level of the bias voltage Vn is 2 · VTN + r · I.
[0210]
FIG. 19 is a signal waveform diagram representing operations of level conversion circuit 312 and gate line driving circuit 314 shown in FIG. The operation of the circuit shown in FIG. 15 will be described below with reference to FIG.
[0211]
When the input timing signal TINi (see FIG. 14) rises from the ground voltage VSS level to the power supply voltage VDDL level, the input signal TIN similarly rises from the ground voltage VSS to the power supply voltage VDDL level. On the other hand, complementary input signal ZTIN falls from power supply voltage VDD level to ground voltage VSS level.
[0212]
In this case, in the level shift circuit 312A, the MOS transistor 13a is turned on and the MOS transistor 14a is turned off. Bias voltage Vn is a voltage level at which MOS transistor 21a is turned on when node 27a is driven to the level of ground voltage VSS when MOS transistor 13a is conductive. Therefore, both MOS transistors 13a and 21a are rendered conductive, and the voltage level of node 25a is lowered to the ground voltage level.
[0213]
MOS transistor 19a receives bias voltage VP at its gate. The bias voltage VP is at a voltage level lower than the high voltage VH. Since the voltage level of node 23a is now high voltage VH level, MOS transistor 19a is rendered conductive, and the voltage level of node 23a is lowered. When the voltage level at node 23a decreases, MOS transistor 12a conducts, and the voltage level at node 24a increases, and the conductance of MOS transistor 11a decreases accordingly.
[0214]
When the voltage level of node 23a is discharged by MOS transistors 13a and 21a by MOS transistors 11a and 12a, the voltage level of node 24a rises. When the voltage level of node 23a becomes VP + | VTP |, MOS transistor 19a is turned off. Therefore, the voltage level of node 23a is maintained at the voltage level of voltage VP + | VTP | by the source follower mode of MOS transistor 19a.
[0215]
On the other hand, when the voltage level of the node 23a is the voltage VP + | VTP |, the MOS transistor 12a maintains the conductive state, so that the node 24a rises to the high voltage VH level (VH> VP + 2 · | VTP | ).
[0216]
That is, when the voltage at node 23a is higher than the gate voltage VP of MOS transistor 19a by the absolute value of the threshold voltage, MOS transistor 19a is turned off.
[0217]
VH−VP> | VTP |. Therefore, MOS transistor 20a operates in a non-saturated region when the voltage at node 24a reaches high voltage VH, and the voltage level at node 24a is transmitted to node 26a via MOS transistor 20a without a voltage drop. Therefore, the voltage level of the node 26a becomes the high voltage VH level.
[0218]
The voltage level of the node 25a is the ground voltage VSS level because the MOS transistor 19a is non-conductive and the MOS transistor 21a is conductive.
[0219]
MOS transistor 22a is an N-channel MOS transistor, and bias voltage Vn is at a voltage level lower than high voltage VH. Therefore, MOS transistor 22a operates in the source follower mode because its gate voltage is lower than the drain voltage, and the voltage level of node 28a is set to the following voltage level.
[0220]
V28a = Vn-VTN
Therefore, in the level shift circuit 312A, the voltage applied to the gate insulating film of the MOS transistor is at a voltage level lower than the high voltage VH. Maximum voltage VH-Vn is applied to MOS transistor 22a, and voltage VH-VP is only applied to MOS transistor 20a. Since these voltages are sufficiently lower than the high voltage, the level shift circuit 312A can ensure the reliability of the gate insulating film and accurately convert the signal having the amplitude VDD into the signal having the amplitude VH.
[0221]
When the voltage level of the node 23a of the level shift circuit 312A becomes the voltage VP + | VTP |, the MOS transistor 12b becomes conductive in the level shift circuit 312B. On the other hand, MOS transistor 11b becomes non-conductive because the gate and source voltages thereof are both equal to high voltage VH.
[0222]
When MOS transistor 12b is turned on, the voltage level of node 24b becomes high voltage VH level, and MOS transistor 20b is turned on accordingly. Node 26b is charged through MOS transistors 20b and 12b, and its voltage level rises.
[0223]
Node 28b is at the negative voltage VL level, and the voltage rise at node 26b is transmitted to node 28b via MOS transistor 22b, and MOS transistor 13b is turned on accordingly. When MOS transistor 13b is turned on, the voltage level of node 27b is reduced to the negative voltage VL level, and MOS transistor 14b is turned off. When node 27b falls to negative voltage VL level, MOS transistor 14b is completely turned off.
[0224]
When the voltage level of node 27b is at negative voltage VL level, MOS transistor 21b is in a conductive state, and the voltage level of node 25b decreases. MOS transistor 11b receives high voltage VH at its gate and is in a non-conductive state. By the source follower operation of the MOS transistor 19b, the voltage level of the node electricity 23b is clamped to the voltage level of VP + | VTP |. The voltage level of node 25b is at the negative voltage VL level because MOS transistor 19b is non-conductive and MOS transistor 21b is conductive.
[0225]
On the other hand, since bias voltage VP is lower than voltage VH− | VTP |, MOS transistor 20b maintains the conductive state (operates in the non-saturated region), and node 26b maintains the high voltage VH level. Since bias voltage VN is lower than high voltage VH, MOS transistor 22b operates in the source follower mode, and the voltage level of node 28b becomes the voltage level of VN−VTN.
[0226]
Therefore, also in the level shift circuit 312B, the voltage applied to the gate insulating film of each MOS transistor is lower than the high voltage VH. The maximum voltage VH-VP or VH-VN is only applied to the gate insulating film, and the reliability of the gate insulating film can be sufficiently ensured.
[0227]
Further, the voltage level of the internal signal is set using the source follower operation of the MOS transistor, and a signal having an amplitude corresponding to the bias voltage can be generated accurately.
[0228]
In this state, the voltage level of node 23b is VP + | VTP |, and the voltage level of node 27b is the negative voltage VL level. Therefore, in gate line drive circuit 314, MOS transistor 42 is turned off, MOS transistor 41 is turned on, and gate line drive signal DV transmitted from node 43 to gate line 44 rises to the high voltage VH level.
[0229]
When input signal TIN drops from power supply voltage VDD to ground voltage VSS, level shift circuits 312A and 312B perform the reverse operation, node 23a is at high voltage VH level, and node 24a is at voltage VP +. Is set to a voltage level of | VTP |. Node 24b is lowered to the voltage level of voltage VP + | VTP |, and accordingly node 28b is also lowered to the negative voltage VL level. Node 23b is at the high voltage VH level, and node 27b is at the voltage level of voltage VN-VTN.
[0230]
Therefore, in the gate line drive circuit 314, the MOS transistor 41 is turned off, the MOS transistor 42 is turned on, and the gate line drive signal DV required from the node 43 to the gate line 44 is reduced to the negative voltage VL level. Gate line 44 is deactivated.
[0231]
In the level shift circuits 312A and 312B, the output of the differential stage is latched by a cross-coupled MOS transistor. By placing MOS transistors that receive bias voltages VP and VN or Vn at their gates between the latch stage and the differential stage, the voltage drop function of these MOS transistors applies to the gate insulating films of all MOS transistors. The voltage to be applied can be set to a voltage level lower than the high voltage VH or the negative voltage VL, and the reliability of the gate insulating film can be ensured.
[0232]
Further, by operating a MOS transistor receiving the bias voltages VP and VN in the source follower mode, a signal having a voltage level corresponding to the voltage levels of the bias voltages VP and VN is accurately generated and supplied to the gate line driving circuit 314. Can be given.
[0233]
Also in the gate line driving circuit 314, a signal having an amplitude corresponding to the bias voltage accurately is received as the input signals IN1 and IN2, and a signal that changes between the high voltage VH and the non-voltage VL is received by the gate insulating film. Can be generated without compromising the reliability.
[0234]
As a result, in the image display device, even when the gate line driving circuit is configured using thin film transistors (TFTs), the gate line 44 can be driven stably even if the threshold voltage varies. When driving the line 44, the operation margin can be increased and the gate line 44 can be scanned at high speed.
[0235]
In level shift circuits 312A and 312B, a MOS transistor receiving bias voltages VP and VN or Vn at an intermediate stage is operated in a source follower mode, whereby MOS transistors coupled to a high voltage node and a negative voltage node are connected. The voltage applied to the gate insulating film can be relaxed, the reliability of the gate insulating film can be ensured, and the gate line driving circuit can stably generate a small amplitude signal based on the bias voltage. Can be given to.
[0236]
[Embodiment 12]
FIG. 20 shows a structure of level conversion circuit 312 according to the twelfth embodiment of the present invention. The level conversion circuit 312 shown in FIG. 20 includes a level shift circuit 312C that converts complementary signals TIN and ZTIN having the amplitude VDD from the input buffer circuit 310 shown in FIG. 14 into a signal having the amplitude VDD-VL, and the level shift circuit. It further includes a level shift circuit 312D that converts the output signal of 312C into a signal having an amplitude VH-VL.
[0237]
The gate line driving circuit 314 drives the gate line 44 in accordance with the output signal of the level shift circuit 312D.
[0238]
Level shift circuit 312C is connected between a power supply node 311 receiving power supply voltage VDD and node 23c, and connected to a P channel MOS transistor 11c receiving the input signal TIN at its gate, and connected between node 23c and node 25c. P channel MOS transistor 19c receiving bias voltage Vp via node 17c at the gate, P channel MOS transistor 12c connected between power supply node 311 and node 24c and receiving complementary input signal ZTIN at the gate, P-channel MOS transistor 20c connected between 24c and 26c and receiving bias voltage Vp at its gate, and N-channel connected between node 25c and node 27c and receiving bias voltage VN via bias node 18d at its gate Cha MOS transistor 21c, N-channel MOS transistor 22c connected between nodes 26c and 28c and receiving bias voltage VN at its gate, and connected between node 27c and negative voltage node 326 and having its gate connected to node 28c And N channel MOS transistor 14c connected between node 28c and negative voltage node 326 and having its gate connected to node 27c.
[0239]
The bias voltage Vp is a voltage lower than the power supply voltage VDD. In level shift circuits 312C and 312D, since the voltage level of the high-side power supply voltage is different, bias voltage Vp is used. Bias voltage Vp is a voltage level at which MOS transistors 19c and 20c become conductive when the source voltage is at the power supply voltage level, and satisfies the following conditions.
[0240]
VP = Vp + (VH-VDD)
In this level shift circuit 312C, MOS transistors 11c and 12c constitute a differential stage for differentially amplifying input signals TIN and ZTIN, and MOS transistors 13c and 14c have a gate and a drain cross-coupled to form a latch circuit. Configure.
[0241]
The MOS transistor receiving the bias voltages Vp and VN functions as an amplitude limiting transistor, and also functions as an electric field relaxation transistor for the gate insulating film of the MOS transistor.
[0242]
Level shift circuit 312D is connected between high voltage node 324 and node 23d and has its gate connected to node 24d, and is connected between high voltage node 324 and node 24d and its gate. Is connected between the node 23d, the P-channel MOS transistor 19d connected between the node 23d and the node 25d and receiving the bias voltage VP at its gate, and connected between the node 24d and the node 26d. P channel MOS transistor 20d receiving bias voltage VP at its gate, N channel MOS transistor 21d connected between node 25d and node 27d and receiving bias voltage VN at its gate, and between node 26d and node 28d Connection N channel MOS transistor 22d having its gate receiving bias voltage VN, N channel MOS transistor 13d connected between node 27d and negative voltage node 326 and having its gate connected to node 27c, node 28d and negative N channel MOS transistor 14d connected between voltage node 326 and having its gate connected to node 28c is included.
[0243]
In level shift circuit 312D, MOS transistors 13d and 14d differentially amplify the level shift signal of level shift circuit 312C. Cross-coupled P channel MOS transistors 11d and 12d latch the differentially amplified signal and convert its H level to high voltage VH level.
[0244]
Also in this level shift circuit 312D, the MOS transistors that receive the bias voltages VP and VN function as amplitude limiting transistors, and accurately generate small amplitude signals according to the voltage levels of the bias voltages VP and VN, This can be applied to the gate line driver circuit 314.
[0245]
Gate line drive circuit 314 has a configuration similar to that shown in FIG. 15, P channel MOS transistors 41 and 40 connected in series between high voltage node 324 and output node 43, output node 43 N channel MOS transistors 37 and 42 connected in series between negative voltage nodes 326 are included. The gate of MOS transistor 41 is connected to node 24d of level shift circuit 312D, and the gate of MOS transistor 42 is connected to node 28d of level shift circuit 312D. Bias voltages VP and VN are applied to the gates of MOS transistors 40 and 37, respectively.
[0246]
FIG. 21 schematically shows a configuration of a circuit for generating bias voltage Vp shown in FIG. In FIG. 21, the bias voltage generation circuit BPKp generates the bias voltage Vp according to the power supply voltage VDD of the power supply node 311 and the negative voltage VL of the negative voltage node 326. As the configuration of the bias voltage generation circuit BPKp, the configuration of the bias voltage generation circuit BPK described in the first to fifth embodiments can be used. A power supply voltage VDD is used instead of the power supply voltage VCC, and a negative voltage VL is used instead of the ground potential VSS. In this case, the bias voltage Vp is given by the voltage VDD-2 · | VTP | −r · I. The current I is supplied from a constant current source.
[0247]
Bias voltages VP and VN are generated from structures similar to bias voltage generation circuits BPK and VNK shown in FIGS. 16 and 17, respectively. The bias voltage VP is generated based on the high voltage VH, and the bias voltage VN is generated based on the negative voltage VL. The bias voltage VN is at a voltage level lower than the power supply voltage VDD.
[0248]
FIG. 22 is a signal waveform diagram representing operations of level conversion circuit 312 and gate line drive circuit 314 shown in FIG. Hereinafter, the operations of the level conversion circuit 312 and the gate line driving circuit 314 shown in FIG. 20 will be described with reference to FIG.
[0249]
The bias voltage Vp satisfies the relationship of the following equation (29).
Vp = VP− (VH−VDD) (29)
Consider a case where the input signal TIN rises from the ground potential VSS to the power supply voltage VDD level. In the level shift circuit 312C, the MOS transistor 11c is turned off and the MOS transistor 12c is turned on. Due to the conduction of MOS transistor 12c, node 24c is charged and its voltage level rises to power supply voltage VDD level. Since MOS transistor 20c receiving bias voltage Vp at its gate operates in the non-saturated region, the voltage at node 24c is transmitted to node 26c, and the voltage level at node 26c similarly rises to the power supply voltage level.
[0250]
The voltage level of node 28c is negative voltage VL, MOS transistor 22c receives bias voltage VN at its gate, and transmits the voltage of node 26c to node 28c. Responsively, MOS transistor 13c conducts, and the voltage level of node 27c drops to the negative voltage VL level. When the voltage level of node 27c drops to negative voltage VL level, MOS transistor 14c is turned off.
[0251]
Since bias voltage VN is lower than power supply voltage VDD, MOS transistor 22c operates in the source follower mode, and the voltage level of node 28c is VN-VTN.
[0252]
MOS transistor 21c conducts when node 27c is at the negative voltage level, and lowers the voltage level of node 25c. MOS transistor 11c is in a non-conductive state. MOS transistor 19c operates in the source follower mode, and maintains the voltage level of node 23c at the voltage level of Vp + | VTP |. The voltage level of node 25c is maintained at the negative voltage VL level because MOS transistor 19c is non-conductive and MOS transistor 21c is conductive.
[0253]
Therefore, in this state, the voltage applied to the gate insulating film of each MOS transistor is at the maximum VL−VN + VTN or Vp−VDD level, and the voltage applied to the gate insulating film can be made sufficiently low. .
[0254]
Further, the amplitude of the voltage change at the node can be limited internally, and a small amplitude signal can be accurately generated and applied to the next level shift circuit 312D.
[0255]
In level shift circuit 312D, MOS transistor 14d is turned on by receiving voltage VN-VTN of node 28c at the gate, and discharges node 28d to the level of negative voltage VL. On the other hand, MOS transistor 13d receives a negative voltage VL of gate 27c at its node and becomes non-conductive. In this state, node 27d is clamped to the level of voltage VN-VTN by MOS transistor 21d.
[0256]
When node 28d attains negative voltage VL level, negative voltage VL is lower than bias voltage VN by a threshold voltage VTN or higher, so that negative voltage VL is transmitted to node 26d via MOS transistor 22d. At this time, MOS transistor 20d receives bias voltage VP lower than the high voltage VH level of the voltage level of node 24d at its gate, and conducts to discharge node 24d. The discharge level of the node 24d becomes the voltage level of the voltage VP + | VTP | by the source follower operation of the MOS transistor 19d.
[0257]
High voltage VH is at a voltage level higher than the absolute value of threshold voltage VTP by at least twice as high as bias voltage VP, MOS transistor 11d is rendered conductive, and node 23d is driven to the high voltage VH level. . In response, MOS transistor 12d is turned off. Node 24d is maintained at the voltage level of voltage VP + | VTP | by MOS transistor 20d. Thereby, the low level of the high-side input signal IN2 for the gate line driving circuit 314 can be accurately set according to the bias voltage.
[0258]
In MOS transistor 20d, although voltage VP-VL is applied to the gate insulating film, bias voltage VP is at a voltage level lower than power supply voltage VDD, and voltage VP-VL is set to about power supply voltage VDD level. Thus, the reliability of the gate insulating film of the MOS transistor 20d can be sufficiently ensured.
[0259]
For the remaining MOS transistors, the voltage amplitude of the internal node is limited by the source follower operation of the MOS transistor, and only a voltage sufficiently lower than the high voltage VH is applied. The reliability of the gate insulating film is We can guarantee it enough.
[0260]
Further, by the source follower operation of the MOS transistor that receives the bias voltages VP and VN at the gates, it is possible to generate a small amplitude signal corresponding to the voltage level of the bias voltage accurately for the high side signal and the low side signal.
[0261]
In gate line drive circuit 314, MOS transistor 41 receives voltage VP + | VTP | at its gate, MOS transistor 42 receives voltage VL at its gate, and drives node 43 to the high voltage VH level.
[0262]
On the other hand, when the input signal TIN is discharged to the ground potential VSS level, the MOS transistor 11c is turned on and the MOS transistor 12c is turned off. In this state, the voltage level of node 25c increases, and accordingly the voltage level of node 27d also increases due to charging through MOS transistor 21c. Responsively, MOS transistor 14c is turned on, node 28c is driven to the negative voltage VL level, and MOS transistor 13c is turned off in response. In this state, node 27c is clamped to the voltage level of voltage VN-VTN by the source follower operation of MOS transistor 21c.
[0263]
In level shift circuit 312D, MOS transistor 13d is turned on, MOS transistor 14d is turned off, and node 27d is driven to the negative voltage VL level. Node 28d is clamped to a voltage level of voltage VN-VTN by the source follower operation of MOS transistor 22d.
[0264]
The negative voltage of node 27d is transmitted to node 25d, and accordingly, the voltage level of node 23d is lowered by MOS transistor 19d. Due to the decrease in the voltage level of node 23d, MOS transistor 12d becomes conductive, the voltage level of node 24d increases, and MOS transistor 11d is turned off.
[0265]
In this state, the voltage level of node 24d becomes the voltage level of high voltage VH by MOS transistor 12d. The voltage level of node 23d is clamped to the voltage level of voltage VP + | VTP | by MOS transistor 19d.
[0266]
Therefore, in gate line driving circuit 314, MOS transistor 41 is turned off, while MOS transistor 42 is turned on, and the output signal of node 43 is at the negative voltage VL level.
[0267]
Also in this case, the voltage applied to the gate insulating film can be sufficiently relaxed for any MOS transistor. Further, the voltage level of the node 28d can be accurately set to the voltage VN-VTN in accordance with the source follower operation of the MOS transistor, and a signal having a small amplitude corresponding to the voltage level of the bias voltage can be accurately generated. .
[0268]
The bias voltages VP and VN are set to voltage levels such that the threshold voltages of the MOS transistors 41 and 42 of the gate line drive circuit 314 cancel the influence on the output signal, and the gate line drive signal can be stably output. Can be generated.
[0269]
Further, an input signal to the gate line driving circuit is generated based on the bias voltages VP and VN by using the source follower operation of the MOS transistor, and a small amplitude signal corresponding to the voltage level of the bias voltages VP and VN accurately. Can be generated and supplied to the gate line driver circuit. Therefore, even when the gate line driving circuit 314 is driven using the high voltage VH and the negative voltage VL, the breakdown voltage characteristics of the gate insulating film of the MOS transistor of the gate line driving circuit 314 can be guaranteed.
[0270]
As described above, according to the twelfth embodiment of the present invention, the gate line driving circuit of the image display device is configured to relax the voltage applied to the gate insulating film of the output driving circuit by the bias voltage. Therefore, even when the gate line is driven using the high voltage VH and the negative voltage VL, the voltage applied to the gate of the MOS transistor can be relaxed with certainty. In addition, the source follower operation of the transistor that receives the bias voltage at the gate is used to accurately generate two types of small amplitude signals (high side input signal and low side input signal) according to the voltage level of the bias voltage. Then, it can be given to the gate line driver circuit.
[0271]
In particular, the MOS transistors of these components are thin film transistors (in the case where they are constituted by TFTs, even when their threshold voltages vary greatly, without being affected by variations in threshold voltages, The gate line 44 can be driven by the gate line driving circuit 314.
[0272]
[Embodiment 13]
FIG. 23 schematically shows a structure of a main portion of the semiconductor device according to the thirteenth embodiment of the present invention. In the configuration shown in FIG. 23, an electroluminescence light emitting element that emits light when current flows is used as the image display element PX.
[0273]
That is, the image display element PX is selectively turned on in accordance with the drive signal DV on the gate line 44, and when turned on, the image signal on the data line 45 is transmitted to the storage node (pixel electrode) 47. Capacitance element 48 connected between storage node 47 and constant voltage supply node 49, drive transistor 53 selectively conducting according to the storage potential on storage node 47, and between drive transistor 53 and reference node 55 It includes an electroluminescent display element 54 connected thereto.
[0274]
Drive transistor 53 couples electroluminescent light emitting element 54 to reference node 52 when conductive. Reference voltages VCH and VCL are applied to reference nodes 52 and 55, respectively.
[0275]
When the drive transistor 53 is turned on according to the storage potential of the storage node 47, the electroluminescence light emitting element 54 is coupled to the reference node 52 and emits light according to the amount of current supplied by the drive transistor 53.
[0276]
For gate line 44, as in the previous eleventh and twelfth embodiments, level conversion circuit 312 for level-converting complementary signals TIN and ZTIN generated by buffering the input timing signal, and this level conversion circuit 312 And a gate line drive circuit 314 for generating a drive signal DV in accordance with the output signal.
[0277]
High voltage VH, negative voltage VL, and ground potential VSS are supplied to level conversion circuit 312 as operation power supply voltages. High voltage VH and negative voltage VL are supplied to gate line drive circuit 314 as operating power supply voltages. These level conversion circuit 312 and gate line drive circuit 314 have the configuration of the previous embodiment 11 or 12, and even when generating drive signal DV using high voltage VH and negative voltage VL, the components The electric field applied to the gate insulating film of the thin film transistor (TFT) is relaxed.
[0278]
As shown in FIG. 23, even when an electroluminescence light emitting element 54 is used as an image display element PX, a gate is used to prevent leakage of the signal potential of the storage node 47 and to reliably write a video signal. Line 44 is driven between high voltage VH and negative voltage VL. Therefore, even when this electroluminescent light emitting element 54 is used, the gate line drive signal can be stably provided by utilizing the configuration of the level conversion circuit 312 and the gate line drive circuit 314 similar to those of the previous embodiment 11 or 12. DV can be generated.
[0279]
Note that the level conversion circuit 312 and the gate line drive circuit 314 are thin film transistors (TFTs), which are constituent MOS transistors. The thin film transistor may have a structure in which a semiconductor layer is deposited on a glass substrate and a MOS transistor is formed in the semiconductor layer. In place of the glass substrate, a semiconductor layer may be formed on an insulating substrate such as a resin substrate, and a thin film transistor may be formed on the semiconductor layer. As a configuration of the thin film transistor (TFT), a thin film transistor having the same structure as a transistor switch that forms a pixel matrix in the display pixel matrix may be used in the image display device.
[0280]
[Embodiment 14]
FIG. 24 schematically shows a structure of bias voltage generating circuit BPK according to the fourteenth embodiment of the present invention. 24 is connected in series between a power supply node receiving power supply voltage VCC and node 105, diode-connected P channel MOS transistors 101 and 102, node 105 and output node. The step-down element 350 is connected between the two. The step-down element 350 causes a voltage drop of a predetermined voltage Vr during operation. Bias voltage VP is output from output node 106. A decoupling capacitor 107 is connected between the power supply node and the output node 106.
[0281]
Step-down element 350 may be a diode-connected P-channel MOS transistor, a diode-connected N-channel MOS transistor, or a PN diode. When conducting each, an absolute value of the threshold voltage or a voltage drop of the forward drop voltage is generated.
[0282]
When a resistance element is used as the step-down element 350, a constant current source is connected to the output node 106, and a constant current is passed through the resistance element to cause a voltage drop of a predetermined magnitude.
[0283]
When a diode-connected MOS transistor is used as the step-down element 350, the bias voltage VP has a threshold voltage dependency. However, in this case, the circuit configuration can be simplified and current consumption can be reduced. In the case of the PN diode, only the built-in voltage of the PN junction is used, and the variation is small compared to the threshold voltage. In the functional circuit of the next stage, the influence of the threshold voltage of the drive transistor is offset, An output signal can be generated.
[0284]
The case where the resistance element is used as step-down element 350 is the same as in the first to fourth embodiments.
[0285]
Therefore, if an element that causes a voltage drop of a constant voltage Vr is used between nodes 105 and 106, a bias voltage VP is generated and applied to functional circuit 1, thereby causing a threshold voltage in an output signal of the functional circuit. Can be suppressed.
[0286]
FIG. 25 schematically shows a structure of bias voltage generating circuit BNK according to the fourteenth embodiment of the present invention. In bias voltage generating circuit BNK shown in FIG. 25, N-channel MOS transistors 201 and 202, each of which is diode-connected, are connected in series between a ground node receiving ground voltage VSS and node 205. A boosting element 360 is provided between the node 205 and the output node 206. Boosting element 360 boosts the voltage at node 205 to voltage Vr and transmits the boosted voltage to output node 206. A bias voltage VN is generated at the output node 206. A decoupling capacitor 199 is also connected to the output node 206.
[0287]
As boosting element 360, a PN diode, an N-channel MOS transistor, a diode-connected P-channel MOS transistor, and a resistance element can be used. When a PN diode or a resistor is used as the booster element 360, the bias voltage VN can suppress the influence of the threshold voltage of the drive transistor in the functional circuit on the output signal drive. Further, when a diode-connected MOS transistor is used as the booster element 360, the circuit configuration can be simplified and the current consumption can be reduced.
[0288]
24 and 25, when these bias voltage generation circuits BPK and BNK are used in the image display device, the MOS transistor is formed of a thin film transistor (TFT).
[0289]
In bias voltage generation circuits BPK and BNK, high voltage VH and negative voltage VL may be used instead of power supply voltage VCC and ground voltage VSS, respectively.
[0290]
As described above, according to the fourteenth embodiment of the present invention, a MOS transistor having the same conductivity type as that of the drive transistor included in the functional circuit is diode-connected, and a constant is provided between the diode-connected MOS transistor and the output node. The level conversion element that causes the voltage shift is utilized, and the functional circuit can be driven by generating a bias voltage with low current consumption. Further, when the level-shifted voltage amount is at a special voltage level with the threshold voltage of the MOS transistor, the influence of the threshold voltage of the driving transistor of the functional circuit on the output signal drive can be suppressed.
[0291]
【The invention's effect】
As described above, according to the present invention, in order to ensure the reliability of the gate insulating film, an output signal is generated in accordance with the input signal through the transistor that receives the bias voltage at the gate, and the amplitude of the input signal is changed to the bias voltage. In this configuration, the bias voltage is generated so as to suppress the influence of the threshold voltage of the output transistor on the output signal, and the output signal can be stably output without being affected by variations in the threshold voltage. The circuit operation margin can be secured sufficiently, and the circuit operation can be stabilized. Thereby, signal processing can be speeded up.
[0292]
That is, for the functional circuit in which the first to fourth field effect transistors are connected in series between the first and second power supply nodes, the voltage level is set based on the voltages of the first and second power supply nodes, respectively. A bias voltage generation circuit that generates different first and second bias voltages and applies them to the gates of the second and third field effect transistors is provided. The bias voltage generation circuit is connected to the first and fourth field effect transistors. The first and second bias voltages are generated so as to suppress the influence of at least one threshold voltage on the output signal. Even if the threshold voltage varies, the influence is suppressed. The output signal can be generated stably.
[0293]
A bias voltage generation circuit includes a plurality of field effect transistors, each of which is diode-connected, and a voltage level conversion element that generates a predetermined voltage difference between the field effect transistor and the output node of the first bias voltage. By configuring, it is possible to easily generate a bias voltage that can suppress the influence of the threshold voltage of the first transistor of the functional circuit.
[0294]
Also, the bias voltage generating circuit has a plurality of MOS transistors, each of which is diode-connected, connected in series to the node receiving the second voltage, and between these MOS transistors and the output node of the second bias voltage. In addition, by configuring with a level conversion element that generates a predetermined voltage difference, the influence of the threshold voltage of the fourth transistor on the output signal can be easily suppressed, and the output signal can be output quickly and stably. Can be generated.
[0299]
Further, by providing a constant current circuit for supplying a constant current to the resistance element, a voltage difference of a desired magnitude can be easily generated accurately by the resistance element.
[0300]
Further, the bias voltage generating circuit has a MOS transistor and a resistor element connected in series between the node receiving the first voltage and the first bias voltage output node, respectively, and the first bias voltage output node. In addition, the first bias voltage having a desired voltage level including the threshold voltage as a voltage component can be easily generated by coupling the constant current source.
[0301]
Further, the bias voltage generating circuit has a MOS transistor and a resistor element connected in series between the node receiving the second voltage and the second bias voltage output node, respectively, and the second bias voltage output node. In addition, by coupling the constant current source, the second bias voltage having a desired voltage level including the threshold voltage as a voltage component can be easily generated.
[0302]
Further, as this bias voltage generation circuit, a constant current generation circuit using feedback of a MOS transistor is used, so that a stable and stable threshold voltage component independent of the first or second voltage level is included as a voltage component. A bias voltage can be generated.
[0303]
The complementary signal pair is differentially amplified to generate a complementary output signal, and the complementary output signal is further differentially amplified to be supplied to the gates of the first and fourth transistors. By generating the second drive signal and driving the image display element in accordance with the output signal of the functional circuit, the image display element can be stably and rapidly operated even when a thin film transistor having a large variation in threshold voltage is used. Can be driven.
[0304]
In addition, the amplifier circuit that generates these complementary signals includes a differential stage, a latch stage that latches the output signal of the differential stage, and an amplitude limit that limits the amplitude of the signal between the differential stage and the latch stage. By constituting with the circuit stage, it is possible to easily generate a differentially amplified and level-converted signal without impairing the reliability of the gate insulating film. Accordingly, the image display element can be stably driven with a signal having a large amplitude.
[0305]
In particular, when this amplitude limiting circuit stage is configured by a MOS transistor that operates in a source follower mode that receives a bias voltage at the gate, a functional circuit is generated by generating a small-amplitude signal that is accurately amplitude-limited based on the bias voltage. Can be driven. As this amplitude limiting stage, both the high side and the low side receive it, thereby generating a small-amplitude signal whose characteristics are amplitude-limited based on the first and second bias voltages, respectively, and driving the functional circuit. Can do. By limiting the amplitude of the input signal to the functional circuit during the level conversion processing operation, the area occupied by the circuit can be reduced, and a small-amplitude signal can be generated at high speed and provided to the functional circuit.
[0306]
Further, when the image display element is a liquid crystal display element or an electroluminescence element, the gate line can be driven stably and at high speed even when the components of the bias voltage generation circuit and the functional circuit are formed of thin film transistors. .
[0307]
In addition, even when the field effect transistor is formed of a thin film transistor and the variation in threshold voltage is large, it is possible to suppress the influence of the variation in threshold voltage and generate an output signal stably.
[0308]
When the first voltage is higher than the second voltage, the output signal can be driven to the H level stably and at high speed when the output signal is driven to the H level.
[Brief description of the drawings]
FIG. 1 shows a configuration of a bias voltage generating circuit according to a first embodiment of the present invention.
FIG. 2 shows a configuration of a bias voltage generating circuit according to a second embodiment of the present invention.
FIG. 3 shows a configuration of a bias voltage generating circuit according to a third embodiment of the present invention.
FIG. 4 shows a configuration of a constant current circuit according to a fourth embodiment of the present invention.
FIG. 5 shows a structure of a bias voltage generation circuit according to a fifth embodiment of the present invention.
FIG. 6 shows a configuration of a bias voltage generating circuit according to a sixth embodiment of the present invention.
FIG. 7 shows a configuration of a bias voltage generating circuit according to a seventh embodiment of the present invention.
FIG. 8 shows a structure of a bias voltage generating circuit according to an eighth embodiment of the present invention.
FIG. 9 shows a structure of a constant current circuit according to the ninth embodiment of the present invention.
FIG. 10 shows a structure of a bias voltage generating circuit according to a tenth embodiment of the present invention.
FIG. 11 schematically shows a structure of a main portion of a semiconductor device according to an eleventh embodiment of the present invention.
12 is a diagram schematically showing a configuration of the gate driver shown in FIG. 11. FIG.
13 is a diagram showing an example of the configuration of the image display element shown in FIG.
14 is a diagram showing a configuration of an input buffer circuit shown in FIG. 12. FIG.
15 is a diagram showing a configuration of a level conversion circuit shown in FIG. 12. FIG.
16 is a diagram schematically showing a configuration of a circuit for generating bias voltage VP shown in FIG. 15. FIG.
17 is a diagram schematically showing a configuration of a circuit for generating bias voltage VN shown in FIG.
18 is a diagram schematically showing a configuration of a circuit for generating bias voltage Vn shown in FIG. 15. FIG.
FIG. 19 is a signal waveform diagram representing an operation of the level conversion circuit shown in FIG. 15;
FIG. 20 shows a structure of a level conversion circuit according to a twelfth embodiment of the present invention.
FIG. 21 is a diagram schematically showing a configuration of a circuit that generates bias voltage Vp shown in FIG. 20;
22 is a signal waveform diagram representing an operation of the level conversion circuit shown in FIG. 20;
FIG. 23 schematically shows a structure of a main portion of a semiconductor device according to the thirteenth embodiment of the present invention.
FIG. 24 shows a structure of a bias voltage generating circuit according to the fourteenth embodiment of the present invention.
FIG. 25 shows a structure of another bias voltage generating circuit according to the fourteenth embodiment of the present invention.
FIG. 26 is a diagram showing a configuration of a conventional output drive circuit.
27 is a diagram showing a relationship between a bias voltage and a power supply voltage shown in FIG.
FIG. 28 is a diagram showing input / output signal voltages when the output drive circuit shown in FIG. 26 outputs a high-level signal.
29 is a diagram showing input / output signal voltages when the output drive circuit shown in FIG. 26 outputs a low-level signal.
FIG. 30 is a diagram showing a configuration of a conventional bias voltage generating circuit.
[Explanation of symbols]
1 functional circuit, PQ0, PQ1 P channel MOS transistor, NQ0, NQ1 N channel MOS transistor, 101, 102 P channel MOS transistor, 103 resistance element, 100 constant current source, BPK, BNK bias voltage generation circuit, 108, 110 N channel MOS transistor, 109, 111 resistance element, 112, 113, 116 N channel MOS transistor, 117 resistance element, 120 P channel MOS transistor, 201, 202 N channel MOS transistor, 203 resistance element, 200 constant current source, 207, 208 P Channel MOS transistor, 209, 211, 217 resistance element, 213, 212, 216 P channel MOS transistor, 1A, 1B functional circuit, 220 N channel MOS transistor 222 resistor element, 300 display pixel matrix, 302 gate driver, 304 data driver, 310 input buffer circuit, 312 level conversion circuit, 312A, 312B, 312C, 312D level shift circuit, 314 gate line drive circuit, 50 liquid crystal display element, 11a , 11b, 12a, 12b, 19a, 19b, 20a, 20b, 40, 41 P-channel MOS transistors, 21a, 21b, 22a, 22b, 13a, 13b, 14a, 14b, 37, 42 N-channel MOS transistors, 11c, 12c , 12d, 19c, 19d, 20c, 20d P-channel MOS transistor, 21c, 21d, 22c, 22d, 13c, 13d, 14c, 14d N-channel MOS transistor, 54 electroluminescence Optical device, 350 buck device, 360 boosting device.

Claims (12)

A functional circuit that operates by receiving first and second voltages applied to the first and second power supply nodes, respectively, as an operation power supply voltage, and the functional circuit is interposed between the first and second power supply nodes; First, second, third and fourth field effect transistors connected in series, wherein the first and second field effect transistors are different in conductivity type from the third and fourth field effect transistors. ,
A bias voltage generating circuit for generating first and second bias voltages having different voltage levels based on the first and second voltages, respectively, and applying the first and second bias voltages to the gates of the second and third field effect transistors, respectively; And the bias voltage generation circuit includes the first and second bias voltages so that a threshold voltage of at least one of the first and fourth field effect transistors suppresses an influence on an output signal of the functional circuit. Produces
The bias voltage generation circuit includes:
A plurality of field effect transistors connected in series between each of a first node and a second node that receive the first voltage, each of which is diode-connected;
A voltage level conversion element connected between the second node and an output node that outputs the first bias voltage and causing a predetermined voltage difference between the second node and the output node; Prepared,
Said level conversion element Ru with a resistive element, semi-conductor devices. A functional circuit that operates by receiving first and second voltages applied to the first and second power supply nodes, respectively, as an operation power supply voltage, and the functional circuit is interposed between the first and second power supply nodes; First, second, third and fourth field effect transistors connected in series, wherein the first and second field effect transistors are different in conductivity type from the third and fourth field effect transistors. ,
Bias voltage generating circuits for generating first and second bias voltages having different voltage levels based on the first and second voltages, respectively, and applying the first and second bias voltages to the gates of the second and third field effect transistors, respectively; And the bias voltage generation circuit includes the first and second bias voltages so that a threshold voltage of at least one of the first and fourth field effect transistors suppresses an influence on an output signal of the functional circuit. Produces
The bias voltage generation circuit includes:
A plurality of field effect transistors connected in series between a first node receiving the second voltage and a second node, each diode connected;
Voltage level conversion connected between the second node and an output node that outputs the second bias voltage, and causing a voltage difference of a predetermined magnitude between the second node and the output node With elements,
It said level conversion element, a resistor element, semi-conductor devices. 3. The semiconductor according to claim 1, wherein the bias voltage generation circuit further includes a constant current circuit that is coupled to the resistance element via the output node and causes a current of a certain magnitude to flow in the resistance element. apparatus. A functional circuit that operates by receiving first and second voltages applied to the first and second power supply nodes, respectively, as an operation power supply voltage, and the functional circuit is interposed between the first and second power supply nodes; First, second, third and fourth field effect transistors connected in series, wherein the first and second field effect transistors are different in conductivity type from the third and fourth field effect transistors. ,
Bias voltage generating circuits for generating first and second bias voltages having different voltage levels based on the first and second voltages, respectively, and applying the first and second bias voltages to the gates of the second and third field effect transistors, respectively; And the bias voltage generation circuit includes the first and second bias voltages so that a threshold voltage of at least one of the first and fourth field effect transistors suppresses an influence on an output signal of the functional circuit. And the bias voltage generation circuit generates
Plurality, each connected in series are each One or a diode-connected of said second transistor of the same conductivity type between the output node for outputting the first bias voltage and the node receiving the first voltage A series body of a field effect transistor and a resistance element of
And a constant current source for driving the constant magnitude of the current is coupled between a node receiving said second voltage and said output node, semiconductors devices. A functional circuit that operates by receiving first and second voltages applied to the first and second power supply nodes, respectively, as an operation power supply voltage, and the functional circuit is interposed between the first and second power supply nodes; First, second, third and fourth field effect transistors connected in series, wherein the first and second field effect transistors are different in conductivity type from the third and fourth field effect transistors. ,
A bias voltage generating circuit for generating first and second bias voltages having different voltage levels based on the first and second voltages, respectively, and applying the first and second bias voltages to the gates of the second and third field effect transistors, respectively; And the bias voltage generation circuit includes the first and second bias voltages so that a threshold voltage of at least one of the first and fourth field effect transistors suppresses an influence on an output signal of the functional circuit. Produces
The bias voltage generation circuit includes:
A plurality of electric fields each connected in series between a node receiving the second voltage and an output node outputting the second bias voltage are diode-connected and each has the same conductivity type as the third transistor. A series body of an effect transistor and a resistance element;
And a constant current source for driving the constant magnitude of the current is coupled between a node receiving said and said output node first voltage, semiconductors devices. A functional circuit that operates by receiving first and second voltages applied to the first and second power supply nodes, respectively, as an operation power supply voltage, and the functional circuit is interposed between the first and second power supply nodes; First, second, third and fourth field effect transistors connected in series, wherein the first and second field effect transistors are different in conductivity type from the third and fourth field effect transistors. ,
A bias voltage generating circuit for generating first and second bias voltages having different voltage levels based on the first and second voltages, respectively, and applying the first and second bias voltages to the gates of the second and third field effect transistors, respectively; And the bias voltage generation circuit includes the first and second bias voltages so that a threshold voltage of at least one of the first and fourth field effect transistors suppresses an influence on an output signal of the functional circuit. Produces
The bias voltage generation circuit includes:
A series body of a plurality of field-effect transistors and resistor elements each connected in diodes, connected in series between a node receiving the first voltage and an output node outputting the first bias voltage;
A current source transistor coupled between the output node and a node receiving the second voltage to drive a constant magnitude current;
A first resistance element connected between an internal power supply node that receives the first voltage and a first internal node;
A first reference transistor of the same conductivity type as the current source transistor, connected between the first resistance element and the gate of the current source transistor and having a gate connected to the first internal node;
A second reference transistor of the same conductivity type as the current source transistor, connected between the internal power supply node and a second internal node and having its gate connected to the first internal node;
A third reference transistor of the same conductivity type as the current source transistor, connected between the gate of the current source transistor and a node receiving the second voltage, and having the gate connected to the second internal node. When,
Including a second resistive element connected between a node receiving said second voltage and said second internal node, semiconductors devices. A functional circuit that operates by receiving first and second voltages applied to the first and second power supply nodes, respectively, as an operation power supply voltage, and the functional circuit is interposed between the first and second power supply nodes; First, second, third and fourth field effect transistors connected in series, wherein the first and second field effect transistors are different in conductivity type from the third and fourth field effect transistors. ,
A bias voltage generating circuit for generating first and second bias voltages having different voltage levels based on the first and second voltages, respectively, and applying the first and second bias voltages to the gates of the second and third field effect transistors, respectively; And the bias voltage generation circuit includes the first and second bias voltages so that a threshold voltage of at least one of the first and fourth field effect transistors suppresses an influence on an output signal of the functional circuit. Produces
The bias voltage generation circuit includes:
Series of a plurality of field effect transistors and resistive elements, each diode-connected in series connected between the output node for outputting said second of receiving a voltage node second bias voltage,
A current source transistor coupled between the output node and a node receiving the first voltage to drive a constant magnitude current;
A first resistance element connected between an internal power supply node that receives the second voltage and a first internal node;
A first reference transistor of the same conductivity type as the current source transistor, connected between the first resistance element and the gate of the current source transistor and having the gate connected to the first internal node;
A second reference transistor of the same conductivity type as the current source transistor, connected between the internal power supply node and a second internal node and having its gate connected to the first internal node;
A third reference of the same conductivity type as the current source transistor, connected between the gate of the current source transistor and a node receiving the first voltage, and having the gate connected to the second internal node. A transistor,
And a second resistor element connected between a node receiving said second voltage and said second internal node, semiconductors devices. A functional circuit that operates by receiving first and second voltages applied to the first and second power supply nodes, respectively, as an operation power supply voltage, and the functional circuit is interposed between the first and second power supply nodes; First, second, third and fourth field effect transistors connected in series, wherein the first and second field effect transistors are different in conductivity type from the third and fourth field effect transistors. ,
Bias voltage generating circuits for generating first and second bias voltages having different voltage levels based on the first and second voltages, respectively, and applying the first and second bias voltages to the gates of the second and third field effect transistors, respectively; And the bias voltage generation circuit includes the first and second bias voltages so that a threshold voltage of at least one of the first and fourth field effect transistors suppresses an influence on an output signal of the functional circuit. Produces
A first amplifier circuit that differentially amplifies the complementary signal pair to generate a complementary output signal;
It said first amplifying circuit is further differentially amplifying the complementary output signal to be output, the first and second driving equivalent logic level with each other to be respectively applied to the gates of the first and fourth field-effect transistor A second amplifier circuit for generating a signal;
Further comprising an image display element driven according to an output signal of the functional circuit,
The output signal of the functional circuit is output from a connection point between the second and third field effect transistors, semi-conductor devices. The first amplifier circuit includes:
A first differential stage for differentially amplifying the complementary signal pair;
A first latch stage for latching an output signal of the first differential stage;
The first differential stage is connected between the first differential stage and the first latch stage and limits the amplitude of a signal transferred between the first differential stage and the first latch stage. And an amplitude limiting stage,
The second amplifier circuit includes:
A second differential stage for differentially amplifying the latch signal of the first latch stage;
A second latch stage for latching the output signal of the second differential stage;
The second latch is connected between the second latch stage and the second differential stage, and limits the amplitude of a signal transferred between the second differential stage and the second latch stage. And an amplitude limiting stage,
9. The semiconductor device according to claim 8 , wherein the latch signal of the second latch stage and the output signal of the second differential stage are respectively applied to the gates of the first and fourth field effect transistors. The semiconductor device according to claim 8 , wherein the image display element includes any one of a liquid crystal display element and an electroluminescence light emitting element. The semiconductor device according to claim 1, wherein each field effect transistor is a thin film transistor. The semiconductor device according to claim 1, wherein the first voltage is higher than the second voltage.

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