JP4212228B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having a strained Si layer.
[0002]
[Prior art]
Various semiconductor elements using silicon crystals are widely used. In order to improve the performance of this semiconductor element, it is one of effective means to increase the traveling speed (mobility) of electrons traveling in the silicon crystal.
[0003]
However, the upper limit of the mobility of electrons traveling in the silicon crystal is determined by the physical properties of the silicon crystal, and even if the structure of the semiconductor element is devised, the upper limit of the mobility cannot be exceeded. However, in recent years, it has been reported that the mobility of electrons is increased in a strained silicon crystal obtained by adding strain to the original silicon crystal.
[0004]
As a means of applying strain to silicon crystals, a base crystal having a slightly different lattice constant from that of silicon crystal is prepared, and a silicon layer thinner than the critical film thickness (layer thickness at which the crystal relaxes) is grown on the base crystal. The method of growing is generally taken. Specifically, a SiGe mixed crystal layer having a Ge composition of about 20% is prepared as a base crystal (in this case, the lattice constant of the SiGe crystal is about 0.8% larger than the lattice constant of the Si crystal), and the SiGe crystal layer is formed on the SiGe crystal layer. A strained Si layer is obtained by thin film growth of a silicon layer having a critical layer thickness of 100 nm or less.
[0005]
However, since it is difficult to obtain a SiGe crystal substrate that is mass-produced industrially and is inexpensive and excellent in quality, a thickness (critical film thickness) that normally uses a silicon wafer as a substrate and lattice-relaxes the SiGe layer thereon. The SiGe underlayer having a lattice-relaxed structure is obtained by vapor phase growth.
[0006]
However, in this method, since a SiGe layer having a Ge composition of 20% is directly grown on the Si substrate, many defects such as dislocations are generated when the SiGe layer is lattice-relaxed, and strained silicon is grown on the SiGe layer. There is a problem that dislocations penetrate through the layer with this defect as a nucleus.
[0007]
Therefore, there is a method in which a buffer layer is formed on a silicon substrate and a lattice-relaxed SiGe layer is formed thereon in order to prevent defects in the SiGe layer when the lattice is relaxed. This buffer layer is a graded composition in which Ge atoms are gradually mixed into a sufficiently thick SiGe layer or Si crystal layer having the same composition (same lattice constant) as the normal lattice-relaxed SiGe layer, and the composition of Ge is gradually increased. A buffer layer is used. Thus, since the desired SiGe layer is obtained by gradually increasing the Ge composition, the difference from the lattice constant with the underlying layer does not change abruptly, and a good lattice-relaxed SiGe layer can be obtained.
[0008]
However, when such a buffer layer and a lattice-relaxed SiGe layer are combined, it becomes a very thick layer, which hinders subsequent device fabrication. For example, when the elements are integrated, it is necessary to separate the fine elements, but the SiGe layer having a thickness of 1 μm or more is too thick to separate the elements. In SOI (SILICON ON INSULATOR) technology, which is expected to reduce the junction capacitance, the SiGe layer (with buffer layer) of 1 μm or more on the buried oxide film is too thick, increasing the junction capacitance of the device. There is a problem to make.
[0009]
[Problems to be solved by the invention]
As described above, conventionally, if the lattice-relaxed SiGe layer is not formed thick together with the buffer layer, a high-quality strained Si layer cannot be obtained, and not only element isolation but also a problem of increasing the coupling capacity of the element occurs. is there.
[0010]
The present invention has been made to solve the above-described problem, and a semiconductor in which a thin and good lattice relaxed SiGe layer is formed on an oxide layer, and a high-quality strained Si layer is formed on the lattice relaxed SiGe layer. An object is to provide a method for manufacturing a device.
[0011]
It is another object of the present invention to provide a method for manufacturing a semiconductor device capable of re-growing a high-quality strained Si layer on a lattice-relaxed SiGe layer.
[0012]
[Means for Solving the Problems]
  In order to achieve the above object, the first invention includes a step of forming a strained SiGe layer on a substrate, a step of forming a Si cap layer on the strained SiGe layer, and the strained SiGe layer through the Si cap layer. An oxygen introduction step for introducing oxygen into the strained SiGe layer by implanting oxygen ions into the oxygen diffusion layer, and an oxide layer is formed in the oxygen introduction portion by heat treatment after the oxygen introduction stepAnd beforeThe strained SiGe layer located above the oxide layer is lattice-relaxed to form a lattice-relaxed SiGe layerFurthermore, the Si cap layer is oxidized from the surface.A heat treatment step;Removing the Si cap layer including the surface oxidized by the heat treatment step;And a step of growing a strained Si layer on the lattice-relaxed SiGe layer.
[0015]
  The method further comprises an etching step of etching the surface of the lattice-relaxed SiGe layer, and the strained Si layer is grown after the etching step.LetIt is preferable.
[0016]
  In addition, a hydrogen termination step of terminating the lattice-relaxed SiGe layer surface by HF treatment is further provided, and the strained Si layer is grown after the hydrogen termination step.LetIt is preferable.
[0017]
Moreover, it is preferable to remove hydrogen on the surface of the lattice-relaxed SiGe layer terminated with hydrogen after the hydrogen termination step.
[0018]
  Also, on the surface of the lattice relaxed SiGe layeranotherAn oxidation step for forming an oxide layer, and after the oxidation step, by heat treatment under vacuum,anotherAn oxide layer removing step for removing the oxide layer, and growing the strained Si layer after the oxide layer removing step.LetIt is preferable.
[0019]
Preferably, the method further includes a step of forming a buffer layer made of SiGe on the substrate, and the strained SiGe layer is formed on the buffer layer.
[0020]
The substrate is preferably a Si substrate.
[0021]
The substrate is preferably a silicon-on-insulator substrate.
[0022]
The oxide layer formed by the heat treatment step separates the strained SiGe layer into a strained SiGe located above the oxide layer and a strained SiGe layer located below the oxide layer. Is preferred.
[0023]
In the oxygen introduction step, it is preferable that oxygen ions are implanted into the strained SiGe layer under a condition that the implantation range is shallower than the thickness of the strained SiGe layer.
[0024]
In the first invention, oxygen is introduced into the strained SiGe layer, and an oxide layer is formed in the SiGe layer by heat treatment. By this oxide layer, the strained SiGe layer is separated into an upper layer of the lattice-relaxed SiGe layer and a lower layer of the SiGe layer. The separated SiGe upper layer can be set to be thin by adjusting the oxygen implantation range, and when the oxide film is formed by heat treatment, the strain on the SiGe upper layer is absorbed by this oxide layer, Defects such as dislocations are not introduced, and thin and good lattice relaxed SiGe can be formed.
[0025]
  Also,The surface of the lattice relaxed SiGe layer was etched and etchedLattice relaxed SiGe layerofSurface is hydrogen-terminated by HF treatmentLetA hydrogen termination step,Hydrogen terminatedGrowth of strained Si layer on lattice relaxed SiGe layer surfaceLetProcessIt is preferable to have.
[0027]
  At this time,After the hydrogen termination step,Before the growth process of the strained Si layer,The lattice relaxed SiGe layerofSurface hydrogenBy heat treatmentMore steps to removePossess,Hydrogen was removed in this wayLattice relaxed SiGe layerofGrowing the strained Si layer on the surfaceLetIt is preferable.
[0028]
  Also, a SiGe layer is grown on the lattice relaxed SiGe layerLetAnd further comprising the step of growing the strained Si layer on the SiGe growth layer.LetIt is preferable.
[0029]
  in this way,Surface of lattice relaxed SiGe layer is hydrogen terminated by HF treatmentLetA good strained Si layer can be formed by removing hydrogen and regrowing strained Si in the same chamber before protecting the surface and regrowing the strained Si layer.
[0030]
  The lattice relaxed SiGe layerofOn the surfaceanotherOxide layerAs a protective layerForming an oxidation step;The substrateBy heat treatment under vacuum,protectionRemove layerprotectionA layer removal step;protectionGrowing strained Si layer on the surface of lattice-relaxed SiGe layer with the layer removedLetProcessIt is preferable to have.
[0031]
  At this time,Before the oxidation step,The lattice relaxed SiGe layerofRemove part of the surfaceLattice relaxed SiGe layer removalProcessThefurtherHavethisLattice relaxed SiGe layer removalIt is preferable to perform the oxidation step after the step.
[0032]
  Also,After the protective layer removing step, before the strained Si layer growing step, the protective layerRelaxed SiGe layer from which is removedSurface ofaboveNew lattice relaxationGrowing SiGe layerMakeFurther processHave this new lattice relaxationSiGe layerSurface ofGrowing strained Si layer on topLetIt is preferable.
[0033]
  in this way,The surface of the lattice relaxed SiGe layerAnother protective layerBefore the regrowth of the strained Si layer, protected by the oxide layer, heat treatment under vacuum in the same chamber,protectionA good strained Si layer can be formed by re-growing strained Si after removing the layer.
[0034]
  First2The invention ofA step of forming a strained SiGe layer on the substrate, an oxygen introduction step of introducing oxygen into the strained SiGe layer by implanting oxygen ions into the strained SiGe layer, and an oxygen introduction by heat treatment after the oxygen introduction step. A heat treatment step of forming a lattice-relaxed SiGe layer by lattice-relaxing a strained SiGe layer positioned above the oxide layer, and growing a SiGe layer on the lattice-relaxed SiGe layer; A method of manufacturing a semiconductor device, comprising: forming a SiGe growth layer; and growing a strained Si layer on the SiGe growth layer.I will provide a.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0037]
(Embodiment 1)
As shown in FIG. 1, Si is formed on a p-type Si substrate 11 by an ultrahigh vacuum CVD (chemical vapor deposition) apparatus._1-XGe_XThe graded composition layer 12 is grown. This p-type Si substrate 11 has a specific resistance of 4.5 Ωcm to 6 Ωcm, and the main surface has a (100) plane. Si_1-XGe_XIn the graded composition layer 12, the Ge composition ratio X is gradually increased from 0 to 0.2 from the beginning to the end of the growth, and the layer thickness is set to 1800 nm. This Si_1-XGe_XThe gradient composition layer 12 functions as a buffer layer.
[0038]
Si_1-XGe_XThe source gas of the layer 12 is Si₂H₆And GeH₄No dopant is added. The film formation conditions are substrate temperature 650 ° C., Si₂H₆The source gas partial pressure is 30 mPa, GeH₄A gradient composition was formed by gradually increasing the raw material gas partial pressure to 60 mPa. GeH₄The feed gas partial pressure can be increased by gradually increasing the flow meter setting. At this time, the Si composition ratio X varies from 2% to 18% with a step thickness of 2% for each layer thickness of 200 nm._1-xGe_xBy laminating the layers, Si having an approximate thickness of 1800 nm is obtained._1-xGe_xThe gradient composition layer 12 can also be created.
[0039]
Next, in an ultra-high vacuum CVD apparatus, Si_1-XGe_X(X: 0 → 0.2) Strained Si continuously on the gradient composition layer 12_1-XGe_XLayer 13 is grown. Strain Si_1-XGe_XFrom the beginning to the end of the growth, the layer 13 has a Ge composition ratio X fixed at 0.2 and a layer thickness of 1000 nm. At this time, strained Si_0.8Ge_0.2Layer 13 has its layer thickness and the underlying Si_1-xGe_x(X: 0 → 0.2) Depending on the layer thickness of the gradient composition layer 12, it may be partially distorted but partially relaxed. Si_1-XGe_XThe (X: 0 → 0.2) gradient composition layer 12 acts as a buffer layer, and strained Si_0.8Ge_0.2Generation of threading dislocations in the layer 13 can be suppressed.
[0040]
Strain Si_0.8Ge_0.2The source gas for the layer 13 is Si.₂H₆And GeH₄No dopant is added. The film formation conditions are substrate temperature 650 ° C., Si₂H₆Source gas partial pressure is 30 mPa, GeH₄The raw material gas partial pressure is set to 60 mPa.
[0041]
Next, in a high vacuum CVD apparatus, strained Si_0.8Ge_0.2A Si cap layer 14 is continuously grown on the layer 13 to a thickness of 30 nm.
[0042]
The raw material gas for the Si cap layer 14 is Si.₂H₆No dopant is added. The film formation conditions are substrate temperature 650 ° C., Si₂H₆The raw material gas partial pressure is set to 30 mPa.
[0043]
Next, as shown in FIG. 2, the substrate is moved from the ultra-high vacuum CVD apparatus to the ion implantation apparatus, and oxygen ion implantation is performed. At this time, strained Si_0.8Ge_0.2Strained Si so that oxygen ions remain in layer 13._0.8Ge_0.2Oxygen ions are implanted under the condition that the implantation range is shallower than the layer thickness (1 μm) of the layer 13. The acceleration energy at this time is 180 keV, and the implantation dose is 4 × 10.¹⁷cm^-2And With this energy, the driving range is 400 nm, but fluctuations of ± 100 nm also occur.
[0044]
The depth at which the buried oxide layer is formed can be adjusted by changing the implantation energy. For example, if the implantation energy is increased, the implantation range is increased, and a buried oxide layer is formed at a deeper position. On the other hand, if the driving energy is lowered, the driving range can be reduced. However, when the implantation range is reduced, the magnitude of the fluctuation is not so small, and if the implantation energy is too low, the distribution of implanted oxygen will spread to the substrate surface centering on the implantation range. So be careful. Specifically, the implantation energy is preferably 25 keV or more.
[0045]
Also, strained Si_0.8Ge_0.2About 150 nm or more and 600 nm or less are preferable from the surface of the layer 13.
[0046]
Next, as shown in FIG. 3, the substrate is taken out from the ion implantation apparatus and subjected to heat treatment at 1350 ° C. for 4 hours. By this heat treatment step, a buried oxide layer 15 having a thickness of 100 nm is formed around a depth of 400 nm from the surface. This buried oxide layer 15 causes strained Si._0.8Ge_0.2Layer 13 is Si_1-XGe_XLower layer 13a and Si_1-XGe_XSeparated into upper layer 13b. This heat treatment process also allows Si_1-XGe_XThe upper layer 13b is lattice-relaxed.
[0047]
In this heat treatment step, temperature setting is the most important. When oxygen ions are implanted into the SiGe layer and the lattice is relaxed by heat treatment as compared with the Si layer, it is desirable to set the temperature lower because it causes surface degradation such as unevenness with respect to heat load. For example, a temperature of 1200 ° C. to 1350 ° C. is preferable.
[0048]
Further, during this heat treatment, the crystal surface of the Si cap layer 14 changes to a thin oxide layer 18, so that Si_0.8Ge_0.2It becomes possible to maintain the surface state of the layer 13 well. For this reason, a method of adding a trace amount of oxygen gas to the heat treatment atmosphere is effective.
[0049]
For example, by introducing about 0.5% oxygen gas into an inert gas such as argon gas as a heat treatment atmosphere, the heat treatment can be performed while thinly oxidizing the surface of the Si cap layer 14. Here, the kind of the inert gas may be a rare gas or nitrogen in addition to argon.
[0050]
At this time, the thickness of the Si cap layer 14 is set to 30 nm. However, the Si cap layer 14 may be left under the condition that the thickness of the surface oxide layer 18 is less than 30 nm. The remaining non-oxidized Si layer of the Si cap layer 14 includes a lower Si layer._0.8Ge_0.2Ge diffuses from the layer 13 to form a SiGe layer, and since this SiGe layer is lattice-relaxed, there is no problem.
[0051]
Even when this heat treatment is performed without forming the Si cap layer 14, Si_0.8Ge_0.2In order to maintain the surface state of the layer 13 satisfactorily, it is better to oxidize the surface very slightly in an atmosphere containing a very small amount of oxygen gas. These oxide layers are etched away in a later step.
[0052]
There is almost no Ge element in the buried oxide layer 15 formed in this heat treatment step._1-XGe_XLower layer 13a and Si_1-XGe_XIt diffuses into the upper layer 13b. Therefore, the buried oxide layer 15 is made of SiO._xIt becomes.
[0053]
On the other hand, in this heat treatment step, Si_1-XGe_XIn the lower layer 13a, Ge is Si._1-XGe_X(X: 0 → 0.2) The Ge composition X is slightly lower than 0.2 by diffusing into the buffer layer 12.
[0054]
In addition, Si on the buried oxide layer 15_1-xGe_xWhen the upper layer 13b is lattice-relaxed, Si_1-xGe_xIn order to release the strain energy to the amorphous buried oxide layer 15 and not to the lower layer 13a, the thin lattice relaxation Si without generation of new dislocations._1-xGe_xThe upper layer 13b can be obtained.
[0055]
Next, the silicon oxide layer 18 formed on the surface of the Si cap layer 14 is removed by etching with hydrofluoric acid or ammonium fluoride.
[0056]
Next, HF + HNO₃A non-oxidized Si layer of the Si cap layer 14 and Si_1-xGe_xThe surface of the upper layer 13b is etched. By doing this, lattice relaxation Si_1-xGe_xA good surface layer of the upper layer 13b can be obtained.
[0057]
HF + HNO at this time₃The composition of the system etchant is (HF: H₂O: HNO₃) = 1: 20: 50, and the etching rate at room temperature is 600 nm / min with respect to Si._0.8Ge_0.2Is 1300 nm / min. At this time, it is possible to further reduce the etching rate by reducing the concentration of hydrofluoric acid and nitric acid. For example (HF: H₂O: HNO₃) = 1: 100: 500, Si_0.8Ge_0.2Is 70 nm / min.
[0058]
Also, lattice relaxation Si_1-xGe_xThe step of etching the surface of the upper layer 13b is not necessarily required, but it is preferable for thinning the SiGe layer formed on the buried oxide layer 15. By this etching process, lattice relaxation Si_1-XGe_XThe thickness of the upper layer 13b is reduced to 100 nm or less, ideally about 5 nm to 10 nm.
[0059]
Next, the etched lattice relaxed Si_1-XGe_XThe surface of the upper layer 13b is terminated with hydrogen by a hydrogen fluoride (HF) solution treatment.
[0060]
Where lattice relaxation Si_1-XGe_XSince the surface of the upper layer 13b is once exposed to the atmosphere after the etching process, the lattice relaxation Si_1-XGe_XUnless the hydrogen termination step is performed, the surface of the upper layer 13b is easily oxidized and contaminated by moisture and oxygen in the atmosphere. Therefore, in order to protect against oxidation and contamination, lattice relaxation Si_1-XGe_XA protective layer is formed by terminating the surface of the upper layer 13b with hydrogen. In this way, the lattice-relaxed Si is re-grown after the subsequent strained Si layer is regrown._1-xGe_xA good strained Si layer can be formed on the upper layer 13b.
[0061]
Next, as shown in FIG. 4, the substrate is again carried into the ultra-high vacuum CVD apparatus, and the lattice relaxation Si is subjected to hydrogen termination treatment by one-end heat treatment._1-xGe_xSurface hydrogen and residual impurities of the upper layer 13b are removed.
[0062]
Next, lattice relaxation Si is performed by an ultrahigh vacuum CVD apparatus._1-xGe_xLattice relaxed Si on the upper layer 13_0.8Ge_0.2Layer 16 is regrowth with a layer thickness of 100 nm. Lattice relaxation Si_0.8Ge_0.2The source gas for the layer 16 is Si.₂H₆, GeH₄And The film formation conditions are as follows: substrate temperature is 650 ° C.₂H₆Source gas partial pressure is 30 mPa, GeH₄The raw material gas partial pressure is set to 60 mPa.
[0063]
Next, lattice relaxation Si is performed by ultra-high vacuum CVD._0.8Ge_0.2A strained Si layer 17 is continuously formed on the regrown layer 16 so as to have a thickness of 20 nm. The source gas of the strained Si layer 17 is Si₂H₆And The growth conditions are as follows: substrate temperature is 650 ° C., Si₂H₆The raw material gas partial pressure is set to 30 mPa.
[0064]
At this time, lattice relaxation Si_1-xGe_xWithout forming the strained Si layer 17 directly on the upper layer 13b,_0.8Ge_0.2By re-growing the layer 16 as a new buffer layer, the strained Si layer 17 having a better crystal structure can be formed. Of course, lattice relaxation Si_1-xGe_xThe strained Si layer 17 may be directly regrown on the upper layer 13b.
[0065]
This lattice relaxation Si_0.8Ge_0.2Buffer layer 16 and lattice relaxation Si_1-xGe_xTogether with the upper layer 13b, it is desirable to set the layer thickness to 200 nm or less, ideally 10 nm or less.
[0066]
Further, the thickness of the strained Si layer 17 is 30 nm or less, ideally 5 nm to 10 nm.
[0067]
Thus thin Si relaxed on the buried oxide layer 15 by lattice relaxation._1-xGe_xA good strained Si layer 17 can be formed on the layers 13 b and 16. In the strained Si layer formed in this way, the electron mobility is about 1.76 times that of the unstrained Si layer. When forming an element, each element may be processed and formed on the buried oxide layer 15, and element isolation processing may be performed on the oxide layer 15. The buffer layer 12 does not need to be element-separated. An example of processing of the element is shown in the fourth embodiment.
[0068]
FIG. 5 shows the required minimum concentration of the HF solution in the hydrogen termination treatment described in the present embodiment and the lattice relaxation Si that is the treatment surface._1-xGe_xThe relationship with the Ge composition ratio X of the upper layer 13b is shown. Here, lattice relaxation Si_1-xGe_xA substrate having a Ge composition ratio X of the upper layer 13b different from 0%, 10%, 20%, and 30% is prepared, and the HF concentration in the hydrofluoric acid solution is changed to change the lattice relaxed Si._1-xGe_xThe experimental result which carried out the hydrogen termination process on the surface of the upper layer 13b is shown.
[0069]
The HF concentration shown here is a desirable minimum value. When a HF solution having a concentration lower than this is used, hydrogen termination treatment is insufficient, and lattice relaxation Si_1-xGe_xOxygen impurities on the surface of the upper layer 13b cannot be sufficiently removed, which may cause problems such as impurities remaining at the interface after regrowth and deterioration of crystallinity of the regrowth layer.
[0070]
As a result, it is preferable to increase the HF concentration in the hydrogen termination treatment, for example, lattice relaxation Si_1-xGe_xIt can be seen that a solution having an HF concentration of 1.5% or more is desirable when the Ge composition ratio X of the upper layer 13b is 20%.
[0071]
Also, hydrogen terminated lattice relaxed Si_1-xGe_xSince the surface of the upper layer 13b begins to desorb hydrogen from 400 ° C. to 500 ° C., the regrowth temperature can be easily adjusted.
[0072]
However, in order to remove oxygen and carbon impurities slightly remaining on the surface, it is preferable to perform not only hydrogen desorption at 400 ° C. to 500 ° C. but also heat treatment at about 850 ° C. to 900 ° C. However, lattice relaxation Si_1-xGe_xThe surface of the upper layer 13b is vulnerable to high-temperature heat treatment, and when subjected to high-temperature heat treatment for a long time, problems such as the occurrence of irregularities and the like that cause surface deterioration are seen. Therefore, lattice-relaxed Si having a Ge composition of 20%_1-xGe_xIn the case of the upper layer 13b, the heat treatment conditions for removing oxygen and carbon impurities within a range that does not cause surface deterioration are preferably 20 minutes or less at 850 ° C. or 5 minutes or less at 900 ° C.
[0073]
(Embodiment 2)
In the present embodiment, the lattice relaxation Si in the first embodiment._1-xGe_xInstead of performing hydrogen termination treatment as a protective layer on the surface of the layer 13b, lattice relaxation Si_1-xGe_xAn oxide layer is formed as a protective layer on the surface of the layer 13b.
[0074]
Accordingly, the steps from FIG. 1 to FIG. 3 are the same as those in the first embodiment, and the description thereof will be omitted.
[0075]
Lattice relaxed Si described in the first embodiment_1-xGe_xAfter removing a part of the surface of the upper layer 13b by etching, this lattice relaxation Si_1-xGe_xThe surface of the layer 13b is oxidized to form an oxide layer (protective layer). In this case, the thickness of the oxide layer is preferably 3 nm or less, and ideally about 1.5 nm. In this oxidation step, acid chemical treatment with hydrochloric acid and hydrogen peroxide mixture is effective. For example, when a mixed solution of (hydrochloric acid: hydrogen peroxide solution: water) = 1: 1: 6 is heated to 90 ° C. or higher, a good quality oxide layer can be formed.
[0076]
Next, this substrate is carried into an ultra-high vacuum CVD apparatus, and the oxide layer as a protective layer is removed by heat treatment under vacuum.
[0077]
The heat treatment conditions for removing the oxide layer are desirably 850 ° C. to 900 ° C. In this case, the heat treatment for removing the oxide layer needs to have a larger heat load than that in the case of hydrogen termination, but specifically, lattice relaxed Si having a Ge composition of 20%._1-xGe_xIn the case of a layer, a heat treatment at 850 ° C. for 30 minutes or less is desirable.
[0078]
Next, as shown in FIG. 4, the lattice-relaxed Si from which the oxide layer has been removed by an ultra-high vacuum CVD apparatus._1-xGe_xLattice relaxed Si on the surface of the upper layer 13_0.8Ge_0.2Layer 16 is regrowth with a layer thickness of 100 nm. Lattice relaxation Si_0.8Ge_0.2The source gas for the layer 16 is Si.₂H₆, GeH₄And The film formation conditions are as follows: substrate temperature is 650 ° C.₂H₆Source gas partial pressure is 30 mPa, GeH₄The raw material gas partial pressure is set to 60 mPa.
[0079]
Next, lattice relaxation Si is performed by ultra-high vacuum CVD._0.8Ge_0.2A strained Si layer 17 is continuously formed on the regrown layer 16 so as to have a thickness of 20 nm. The source gas of the strained Si layer 17 is Si₂H₆And The growth conditions are as follows: substrate temperature is 650 ° C., Si₂H₆The raw material gas partial pressure is set to 30 mPa.
[0080]
At this time, lattice relaxation Si_1-xGe_xWithout forming a strained Si layer directly on the upper layer 13b,_0.8Ge_0.2By re-growing the layer 16 as a new buffer layer, the strained Si layer 17 having a better crystal structure can be formed. Of course, lattice relaxation Si_1-xGe_xThe strained Si layer 17 may be directly regrown on the upper layer 13b.
[0081]
This lattice relaxation Si_0.8Ge_0.2Buffer layer 16 and lattice relaxation Si_1-xGe_xTogether with the upper layer 13b, it is desirable to set the layer thickness to 200 nm or less, ideally 10 nm or less.
[0082]
The thickness of the strained Si layer 17 is 30 nm or less, ideally 5 nm to 10 nm.
[0083]
Thus thin Si relaxed on the buried oxide layer 15 by lattice relaxation._1-xGe_xIt is possible to create a structure in which the layers 13b and 16 and the strained Si layer 17 are stacked.
[0084]
(Embodiment 3)
FIG. 7 is a diagram showing each step of the manufacturing method of the semiconductor device shown in the third embodiment of the present invention. This embodiment is an embodiment according to the second invention of the present invention.
[0085]
The present embodiment is a method of forming a lattice-relaxed SiGe layer by epitaxially growing a strained SiGe layer on an SOI layer using an SOI (silicon on insulator) substrate.
[0086]
First, in FIG. 7A, an SOI substrate is prepared in which a silicon oxide layer 42 having a thickness of 100 nm and a silicon single crystal layer 43 having a thickness of 20 nm are formed in this order on a silicon substrate 41.
[0087]
Such an SOI substrate is produced industrially and is easily available. In general, an SOI substrate that can be obtained at a low cost often has a thickness of the silicon single crystal layer 43 as thick as 100 nm or more. In that case, the SOI layer (Si layer on the buried oxide layer 42) 43 can be thinned by oxidizing the silicon single crystal layer 43 in a normal thermal oxidation furnace. For example, when the thickness of the initial SOI layer 43 is 100 nm, if the surface is thermally oxidized under conditions for forming an oxide layer of about 160 nm, the SOI layer 43 of about 20 nm remains. At this time, the thermal oxide layer formed on the surface is peeled off by etching or the like.
[0088]
Next, as shown in FIG. 7B, an Si substrate having a layer thickness of 100 nm is formed on the SOI substrate._0.85Ge_0.15The case where the layer 44 (Ge composition 15%) is grown at a low temperature of about 500 ° C. will be described. In order to realize low temperature growth, in addition to the ultrahigh vacuum CVD method described in the first and second embodiments, an MBE (molecular beam epitaxy) method using a solid material is also effective. In the present embodiment, a method of forming using an MBE method using a solid raw material will be described.
[0089]
In the MBE method using a solid material, an Si beam is heated by applying an electron beam, and silicon vapor is supplied to a substrate heated by another heat source (substrate heater). Further, a mixed crystal layer of SiGe can be formed by taking out vapor from a Ge source heated at the same time and supplying Si and Ge vapor onto the substrate at the same time. At this time, by controlling the temperatures of the Si source and the Ge source, the vapor pressure of both can be adjusted and a predetermined Ge composition can be designed.
A 100 nm thick Si layer is formed on the SOI layer 43 by the MBE method._0.85Ge_0.15The layer 44 (Ge composition 15%) is grown at a low temperature of about 500 ° C.
[0090]
This Si_0.85Ge_0.15In the stage immediately after the end of the growth of the layer 44, Si_0.85Ge_0.15The layer 44 has tensile strain due to the Si crystal layer 43.
[0091]
Next, as shown in FIG. 7C, after the substrate is taken out into the atmosphere, it is introduced into a heat treatment furnace and subjected to a high temperature annealing treatment at 1100 ° C. for 1 hour. By removing it into the atmosphere, Si_0.85Ge_0.15A very thin oxide layer 45 can be formed on the surface of the layer 44, and precipitation or agglomeration of Ge atoms during heat treatment can be suppressed. By this heat treatment, slip dislocation occurs between the buried oxide layer 42 and the underlying SOI layer 43, and Si_0.85Ge_0.15Layer 44 is substantially lattice relaxed.
[0092]
After each step, since the Si oxide layer 45 is formed on the surface of the lattice-relaxed SiGe layer 44, the surface oxide layer is removed by HF treatment, and at the same time, the surface of the lattice-relaxed SiGe layer 44 is hydrogenated by HF treatment. Terminate. The conditions for the HF treatment are the same as in the first embodiment.
[0093]
Next, as shown in FIG. 7D, this substrate is again introduced into the thin film growth apparatus, the lattice-relaxed SiGe layer 46 is regrown to adjust the crystallinity, and the strained Si layer 47 is grown as the uppermost layer. In this way, the strained Si layer 47 / Si_1-xGe_xA stacked structure of the layers 46, 44 / Si layer 43 / Si oxide layer 42 is obtained. In the structure thus obtained, when the heat treatment temperature is high, Ge atoms diffuse from the SiGe layer 46 formed thereafter in the initial SOI layer, so that the Ge concentration is reduced on average, and the above-described structure is obtained. In the example, it is 12.5%.
[0094]
In this embodiment, the hydrogen termination treatment is performed after the heat treatment and the growth of the strained Si layer 47 is started. However, the hydrogen termination treatment is performed after removing a part of the surface of the lattice-relaxed SiGe layer 44 by etching, and the strained Si layer 47 is formed. If formed, an extremely thin lattice relaxed SiGe layer 44 can be obtained. For example, the relaxed SiGe layer 44 having a layer thickness of 120 nm and a Ge composition of 12.5% formed after the heat treatment in the above example is removed from the surface by 90 nm etching, leaving a layer thickness of 30 nm, and a strained Si layer 47 having a layer thickness of 15 nm. Re-grow up.
[0095]
Also in this method, a high-temperature heat treatment step is required to obtain a high-quality lattice-relaxed SiGe layer 44, and the surface layer is oxidized. Even if a Si cap layer is prepared for surface protection, a large amount of Ge is mixed from the SiGe layer, and the Si layer is not preserved. That is, in order to finally obtain a strained Si layer as the uppermost layer, the process of regrowth after the high temperature heat treatment step is important.
[0096]
(Embodiment 4)
Next, an example in which a MOSFET is manufactured using the above laminated structure will be described.
[0097]
As shown in FIG. 6, a buried oxide layer 32 is formed on the Si substrate 31. On the buried oxide layer 32, a lattice-relaxed SiGe layer 35, a strained Si layer 34, a gate oxide layer 35 and a gate electrode 36 are formed. A source / drain 37 is formed on both sides of the gate electrode 36 in the strained Si layer 34.
[0098]
Where lattice relaxation Si_0.7Ge_0.3The layer 35 had a Ge composition of 30%, a thickness of 7 nm, and the strained Si layer 34 had an initial thickness of 6 nm. However, in the MOSFET manufacturing process, the surface of the strained Si layer 34 is thermally oxidized to form a gate oxide layer, and as a result, the 3 nm oxide layer and the 4.5 nm strained Si layer 34 are relaxed SiGe / insulating layer (buried oxide layer). It has a laminated structure.
[0099]
Next, using the first and second inventions of the present invention, the above MOSFET was produced. The method will be described with reference to FIGS.
[0100]
First, as shown in FIG. 8A, a graded composition SiGe layer 82 (thickness 2.5 μm) having a gradually increased Ge composition is formed on a Si substrate 81, and a Si film 2 μm thick is formed thereon._0.7Ge_0.3Layer 83 is laminated. Next, Si_0.7Ge_0.3A Si cap layer 84 having a thickness of 20 nm is formed on the layer 83. This laminated structure is Si₂H₆And GeH₄It is formed using an ultrahigh vacuum CVD method using as a raw material.
[0101]
Next, as shown in FIG. 8B, oxygen ion implantation is performed on the laminated substrate. The acceleration energy at this time is 180 keV, and the implantation dose is 4 × 10.¹⁷cm^-2And
[0102]
Next, after oxygen ion implantation, heat treatment is performed at 1350 ° C. for 4 hours. By this heat treatment process, a buried oxide layer having a thickness of 100 nm is formed around a depth of 400 nm from the surface. This buried oxide layer allows Si_0.7Ge_0.3A buried oxide layer 85 is formed between the layer 83 and the SiGe graded composition layer 82. This heat treatment process also allows Si_0.7Ge_0.3Layer 83 is lattice relaxed.
[0103]
Next, as shown in FIG. 8C, Si having a thickness of 400 nm._0.7Ge_0.3The surface of the layer 83 is etched to 7 nm with a HF: nitric acid mixed solution. At this time, the Si cap layer 84 is also etched. Here, other methods may be used for etching.
[0104]
Next, as shown in FIG. 8D, the film is again introduced into the film forming apparatus, and Si_0.7Ge_0.3A strained Si layer 86 having a thickness of 6 nm is formed on the layer 83.
[0105]
Next, as shown in FIG. 8E, the surface of the strained Si layer 86 is thermally oxidized. The formed thermal oxide layer 87 has a thickness of 3 nm. As a result, a 3 nm oxide layer 87 and a 4.5 nm strained Si layer 86 are formed.
[0106]
Next, as shown in FIG. 8F, a polycrystalline Si layer 88 having a thickness of 50 nm is deposited on the oxide layer 87.
[0107]
Next, as shown in FIG. 9A, an insulating layer is formed on the entire surface of the substrate, and etching is performed by RIE to form a gate sidewall 89 on the side surface of the gate electrode 88.
[0108]
Next, as shown in FIG. 9B, impurities are ion-implanted to reduce the resistance of the polycrystalline Si gate and the source / drain 90 at both ends of the gate. In rapid thermal annealing after ion implantation, it is desirable to keep the temperature at about 850 ° C. If the temperature is too high, the distortion of the channel portion formed in the strained Si layer 86 may be relaxed. Further, if the temperature is too high, there is a concern that the Si / SiGe interface deteriorates due to the diffusion of Ge.
[0109]
Finally, an electrode of aluminum is formed on the source / drain 90 and the gate to complete the device. In the element shown in FIG. 9B, the buried oxide layer 85 corresponds to the buried oxide layer 32 of FIG. Further, the substrate 81 and the gradient composition SiGe layer 82 in FIG. 9B correspond to the substrate 31 in FIG.
[0110]
Since the MOSFET formed in this way uses a strained Si layer as a channel, the speed of the element can be increased.
[0111]
【The invention's effect】
  According to the present invention, when a SiGe layer is stacked on a Si crystal, a thin lattice relaxed SiGe layer can be obtained regardless of the critical film thickness for lattice relaxation, so that the strained Si / relaxed SiGe / insulating layer In the laminated structure, it is possible to obtain extremely thin relaxed SiGe that is equal to or less than the critical layer thickness of the SiGe layer on the Si crystal. Further, since the SiGe layer on which strained silicon is formed is very thin, microfabrication such as element isolation is easy, and the junction capacitance does not increase.
[0112]
Further, since the surface of the lattice-relaxed SiGe layer is hydrogen-terminated or an oxide layer is formed, and then the strained Si layer is re-formed by etching, these interface characteristics are improved, and the device characteristics can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining a method of forming a laminated structure of strained Si / lattice relaxed SiGe / insulating layer according to the present invention.
FIG. 2 is a cross-sectional view for explaining a method of forming a laminated structure of strained Si / lattice relaxed SiGe / insulating layer according to the present invention.
FIG. 3 is a cross-sectional view for explaining a method of creating a laminated structure of strained Si / lattice relaxed SiGe / insulating layer according to the present invention.
FIG. 4 is a cross-sectional view for explaining a method of creating a laminated structure of strained Si / lattice relaxed SiGe / insulating layer according to the present invention.
FIG. 5 is a table showing conditions for surface treatment of a lattice-relaxed SiGe layer when creating a strained Si / lattice-relaxed SiGe / insulating layer structure according to the present invention.
FIG. 6 is a cross-sectional view of a MOSFET using a stacked structure of strained Si / lattice relaxed SiGe / insulating layer according to the present invention.
7 is a cross-sectional view in each step for explaining a method of forming a laminated structure of strained Si / lattice relaxed SiGe / insulating layer according to the present invention. FIG.
FIG. 8 is a cross-sectional view of each step for explaining a method of forming a MOSFET using a laminated structure of strained Si / lattice relaxed SiGe / insulating layer according to the present invention.
FIG. 9 is a cross-sectional view of each step for explaining a method of forming a MOSFET using a laminated structure of strained Si / lattice relaxed SiGe / insulating layer according to the present invention.
[Explanation of symbols]
11 ... Si substrate
12 ... SiGe graded composition layer
13 ... SiGe fixed composition layer
13a ... SiGe layer
13b ... lattice relaxed SiGe layer
14 ... Si cap layer
15 ... buried oxide layer
16: Regrown SiGe layer
17 ... Strained Si layer
31 ... Board
32 ... buried oxide layer
35 ... lattice relaxed SiGe layer
36 ... Gate electrode
37 ... Source / Drain

Claims (11)

Forming a strained SiGe layer on the substrate;
Forming a Si cap layer on the strained SiGe layer;
Introducing oxygen into the strained SiGe layer by implanting oxygen ions into the strained SiGe layer through the Si cap layer;
Wherein after the oxygen introduction step, by heat treatment, an oxide layer is formed on the oxygen introduction, before Symbol the strain SiGe layer located above the oxide layer by lattice relaxation by forming a lattice-relaxed SiGe layer, further wherein the Si cap A heat treatment step for oxidizing the layer from the surface ;
Removing the Si cap layer including the surface oxidized by the heat treatment step;
And a step of growing a strained Si layer on the lattice-relaxed SiGe layer. Forming a strained SiGe layer on the substrate;
An oxygen introduction step of introducing oxygen into the strained SiGe layer by implanting oxygen ions into the strained SiGe layer;
After the oxygen introduction step, a heat treatment step of forming a lattice relaxed SiGe layer by forming an oxide layer in the oxygen introduction portion by heat treatment and further relaxing the strained SiGe layer positioned above the oxide layer,
Growing a SiGe layer on the lattice relaxed SiGe layer to form a SiGe growth layer;
And a step of growing a strained Si layer on the SiGe growth layer. In the step of growing the strained Si layer on the lattice-relaxed SiGe layer, the surface of the lattice-relaxed SiGe layer is etched, the semiconductor device subsequent to grow the strained Si layer and said Rukoto claim 1, wherein Production method.   The oxide layer formed by the heat treatment step separates the strained SiGe layer into a strained SiGe located above the oxide layer and a strained SiGe layer located below the oxide layer. A method for manufacturing a semiconductor device according to claim 1. 2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the oxygen introduction step , oxygen ions are implanted into the strained SiGe layer under a condition that an implantation range is shallower than a thickness of the strained SiGe layer.   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a buffer layer made of SiGe on the substrate, and forming the strained SiGe layer on the buffer layer. Growing a strained Si layer on the lattice relaxed SiGe layer,
Etching the surface of the lattice-relaxed SiGe layer, and the hydrogen termination process Ru thereafter hydrogen-terminated by the surface of the etched lattice-relaxed SiGe layer HF treatment,
The method according to claim 1, wherein further comprising the step of Ru grown strained Si layer on the hydrogen-terminated lattice-relaxed SiGe layer on the surface. After the hydrogen termination step and before the growth step of the strained Si layer, the method further includes a step of removing hydrogen on the surface of the lattice-relaxed SiGe layer by heat treatment, and the hydrogen is removed on the surface of the lattice-relaxed SiGe layer. the method according to claim 7, wherein Rukoto grown strained Si layer. Growing a strained Si layer on the lattice relaxed SiGe layer,
An oxidation step of forming a new oxide layer as a protective layer on the surface of the lattice relaxed SiGe layer;
By annealing the substrate under vacuum, and the protective layer removing step of removing the protective layer,
The method according to claim 1, wherein further comprising the step of Ru grown strained Si layer on the protective layer grating is removed relaxed SiGe layer on the surface. 2. The method according to claim 1 , further comprising a lattice relaxation SiGe layer removal step of removing a part of the surface of the lattice relaxation SiGe layer before the oxidation step, and performing the oxidation step after the lattice relaxation SiGe layer removal step. 9. A method for manufacturing a semiconductor device according to 9 . After the protective layer removing step and before the strained Si layer growing step, the method further comprises a step of growing a new lattice relaxed SiGe layer on the surface of the lattice relaxed SiGe layer from which the protective layer has been removed. 10. The method of manufacturing a semiconductor device according to claim 9, wherein a strained Si layer is grown on the surface of a simple lattice-relaxed SiGe layer.

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