JP4209033B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4209033B2
JP4209033B2 JP14103799A JP14103799A JP4209033B2 JP 4209033 B2 JP4209033 B2 JP 4209033B2 JP 14103799 A JP14103799 A JP 14103799A JP 14103799 A JP14103799 A JP 14103799A JP 4209033 B2 JP4209033 B2 JP 4209033B2
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passivation film
forming
metal wiring
metal electrode
semiconductor device
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JP2000332017A (en
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衛吾 白樫
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置の製造方法に関するものである。
【０００２】
【従来の技術】
従来のＶＬＳＩ等の半導体装置においては、トランジスタ等の半導体素子上に層間絶縁膜および金属配線が形成され、この金属配線の上に、水分、重金属又はアルカリ金属などの不純物が侵入することを防止するためにパッシベーション膜が形成される。
【０００３】
以下、従来の半導体装置について、図４を参照しながら説明する。図４（ａ）は従来の半導体装置の要部断面図である。図４（ａ）に示すように、半導体基板１０１の上に酸化シリコン、窒化シリコン等からなる層間絶縁膜１０２が形成され、この層間絶縁膜１０２の上にアルミニウムもしくはアルミニウムを主成分とするアルミニウム合金よりなる金属配線１０３およびアルミニウム合金よりなる金属電極１０４がそれぞれ形成されている。尚、層間絶縁膜１０２の下にはトランジスタ等の半導体素子が形成されているが、半導体素子については図示の都合上省略している。金属配線１０３および金属電極１０４の上には、例えばＣＶＤ法によりパッシベーション膜１０５が形成されている。尚、金属電極１０４上面のパッシベーション膜１０５におけるワイヤボンディングを行う領域には開口部１０６が形成され、金属電極１０４とボンディングワイヤ１０７のネールヘッド１０８が超音波併用熱圧着法によって接続されている。
【０００４】
【発明が解決しようとする課題】
ところで、従来のＶＬＳＩ等の半導体装置においては、ＶＬＳＩ等の微細化とチップの小型化・多機能化に伴って、金属配線１０３が微細化すると共に電気信号を入出力する金属電極１０４の数は増加の一途である。それに伴って、金属配線１０３と金属電極１０４および、金属電極１０４と金属電極１０４との間隔が小さくなることによって以下のような問題が発生する。
【０００５】
図４（ｂ）は半導体チップ１０９表面の一部分を示す平面図である。図４（ｂ）に示されるように、半導体チップ１０９の周縁に並ぶ金属電極１０４の数が多くなると、前述したように金属電極１０４と金属電極１０４とを並べる間隔が非常に狭くなる。さらに半導体チップ１０９の多機能化・小型化が進行し、より金属電極１０４の数が増加すると、金属電極１０４の間に間隔が設けられなくなり、各金属電極１０４に対応したパッシベーション膜１０５の開口も困難となる。これに対して従来は、金属電極１０４の形状を縮小化して多数の金属電極１０４を並べる工夫がなされてきた。
【０００６】
しかしながら、図４（ａ）に示したように、ボンディングワイヤ１０７のネールヘッド１０８と金属電極１０４とを超音波を併用した熱圧着で接続するワイヤボンディングはその接着面の接着状態や接着面積で接着強度が決定する。金属電極１０４を縮小化すると、それにあわせて金属電極１０４の外側にはみ出さないように、また、隣接するネールヘッド１０８同士が接触しないように、ネールヘッド１０８も縮小化する必要が生じる。その結果、ネールヘッド１０８と金属電極１０４との接着面積が小さくなるため、しばしばネールヘッド１０８と金属電極１０４との接着不良などが発生する。
【０００７】
また、金属電極１０４の数の増加によって、金属電極１０４を縮小化すると同時に、パッシベーション膜１０５の開口部１０６もできるだけ縮小化する必要が生じる。開口部１０６が縮小化すると、ワイヤボンディング装置の精度には限界が有るので、ネールヘッド１０８とパッシベーション膜１０５の金属電極１０４より上方にある部分とが接触する可能性が大きくなる。この接触が発生した場合、ネールヘッド１０８と金属電極１０４との不着や、さらには、パッシベーション膜１０５にクラックが発生し、半導体チップが耐湿性不良を起こすような致命的なワイヤボンディング不良が発生して半導体装置の信頼性が低下することになる。
【０００８】
また、ボンディングワイヤ１０７の代わりに、半田バンプを用いる場合にも同様の問題がある。すなわち、金属電極１０４の数の増加に伴い、金属電極１０４を縮小化すると、接着面積が小さくなることにより半田バンプと金属電極１０４との接着不良が発生したり、半田バンプとパッシベーション膜１０５との接触により半田バンプと金属電極１０４との接着不良やパッシベーション膜１０５にクラックが発生して半導体装置の信頼性が低下することになる。
【０００９】
本発明の目的は、外部との間で電気信号が入出力される金属電極が縮小化されても、金属電極へのボンディングワイヤのネールヘッドや半田バンプの接続を良好にでき、パッシベーション膜のクラック等を防止して信頼性の高い半導体装置の製造方法を提供することである。
【００１０】
【課題を解決するための手段】
本発明の請求項１に記載の半導体装置の製造方法は、半導体基板上に層間絶縁膜を形成する工程と、層間絶縁膜上に金属配線を形成する工程と、金属配線を覆うようにパッシベーション膜を形成する工程と、金属配線上でパッシベーション膜の所定の位置に複数個のバイアホールを形成する工程と、選択ＣＶＤ法によってバイアホール内を充填しかつパッシベーション膜の表面より上に突起するプラグを形成する工程とを含むことを特徴とする。
【００１１】
この製造方法によれば、製造される半導体装置において、電気信号の入出力部となる金属電極の面積が縮小化されても、金属電極がパッシベーション膜の表面より上に突起した複数個のプラグからなるため、ボンディングワイヤ等との接続を容易かつ強固にできる。また、金属電極の面積の縮小化がより可能となり、より多くの金属電極をチップ周縁部に形成できる。また、金属電極を構成するプラグがパッシベーション膜の表面より上に突起しているため、ボンディングワイヤ等の接続の際にそのボンディングワイヤ等の位置がずれても、ボンディングワイヤ等とプラグの良好な接続が得られるとともに、パッシベーション膜のクラックも防止でき、高信頼性の半導体装置を得ることができる。
【００１８】
本発明の請求項２に記載の半導体装置の製造方法は、半導体基板上に層間絶縁膜を形成する工程と、層間絶縁膜上に金属配線を形成する工程と、金属配線を覆うようにパッシベーション膜を形成する工程と、金属配線上でパッシベーション膜の所定の位置に複数個のバイアホールを形成する工程と、バイアホール内を充填するとともにパッシベーション膜上を覆うように金属電極層を形成する工程と、金属電極層よりパッシベーション膜の方がエッチングレートの速いケミカルメカニカルポリッシング法によって金属電極層およびパッシベーション膜をエッチングすることによりバイアホール内の金属電極層からなりエッチング後のパッシベーション膜の表面より上に突起したプラグを形成する工程とを含むことを特徴とする。
【００１９】
この製造方法により、請求項１に記載の半導体装置の製造方法と同様の効果を奏する。
本発明の請求項３に記載の半導体装置の製造方法は、請求項１または２記載の半導体装置の製造方法において、金属配線はアルミニウム合金、銅合金、銀のいずれかからなるものであって、プラグは、アルミニウム合金、タングステン、銅、チタンのいずれかからなるものであることを特徴とする。
本発明の請求項４に記載の半導体装置の製造方法は、請求項１または２記載の半導体装置の製造方法において、バイアホール形成後、前記金属配線の形成前に、密着層を形成することを特徴とする。
【００２０】
【発明の実施の形態】
以下、本発明の実施の形態における半導体装置およびその製造方法について、図面を参照しながら説明する。
【００２１】
〔第１の実施の形態〕
図１（ａ）は本発明の第１の実施の形態における半導体装置の要部断面図、図１（ｂ）は同半導体装置の一部分の平面図である。
【００２２】
図１（ａ）に示すように、半導体基板１の上には全面に亘って酸化シリコンよりなる層間絶縁膜２が形成されている。半導体基板１上には、例えばＭＯＳトランジスタやＭＯＳダイオード等の半導体素子が形成されており、層間絶縁膜２には半導体素子と層間絶縁膜２上に形成される金属配線３との電気的接続をとるための開口部が形成されているが、半導体素子および開口部は省略して示している。
【００２３】
層間絶縁膜２の上には、アルミニウム合金からなり、半導体基板１に形成された半導体素子と電気的に接続される金属配線３が形成され、金属配線３上には全面に亘って窒化シリコンからなるパッシベーション膜４が形成されている。なお、ここではパッシベーション膜４を窒化シリコン単層としているが、酸化シリコンと窒化シリコンを積層して構成してもよい。
【００２４】
本実施の形態における半導体装置の特徴は、ワイヤボンディングを行うべき部分に、金属配線３と接続された複数個のプラグ５がパッシベーション膜４を貫通して形成され、そのプラグ５はパッシベーション膜４の表面より上に突起していることである。
【００２５】
図１（ｂ）に示すように、半導体チップ６周縁のパッシベーション膜４上にプラグ５を突起させて形成し、ドットが密集した状態に整列した複数個のプラグ５により一つの金属電極を構成し、その金属電極と若干の隙間を空けて順次隣り合う同様の金属電極が形成されている。個々のプラグ５は、パッシベーション膜４の表面から１００ｎｍ以上突起している。また、一つの金属電極は、直径２００〜５０００ｎｍのプラグ５をできるだけ密になるように、１２００〜８０００μｍ2 程度の範囲に形成されている。このプラグ５の突起量（パッシベーション膜４表面からの高さ）、直径はボンディングワイヤ７のボンディングの際の衝撃がパッシベーション膜４を傷つけないように設定する必要がある。また、本実施の形態では、一つの金属電極を構成する複数のプラグ５を形成した範囲は２８００μｍ2 のほぼ円状であるが、その範囲はボンディングワイヤ７のネールヘッド８の直径に合わせて調節設定する。
【００２６】
プラグ５の材質は、金属配線３と同じアルミニウム合金にしたが、ボンディングワイヤ７の材質との接着整合性を考慮して決定する必要がある。また、ボンディングワイヤ７の代わりに半田バンプなどを使用する場合には、半田および金属配線３の材質との接着整合性を考慮して決定する必要がある。
【００２７】
今回は、金属配線３、プラグ５の材質としてアルミニウム合金を使用したが、その他に、金属配線３には銅合金や銀等を用いることができ、プラグ５にはタングステンや銅、チタン等を用いることができる。
【００２８】
このように、ボンディングワイヤ７のネールヘッド８の大きさに合わせて、パッシベーション膜４上にプラグ５を突起させて金属電極を形成することで、ボンディングワイヤ７のネールヘッド８にプラグ５が食込む形となる。従って、個々のプラグ５についてその突起量が大きいほどプラグ５とネールヘッド８との接触面積が大きくなり、プラグ５の突起量に応じて複数のプラグ５からなる一つの金属電極の形成領域の面積を調整できる。そのため、複数のプラグ５からなる金属電極とネールヘッド８との接続を強固にしながら、一つの金属電極の形成領域の面積の縮小化（金属電極の縮小化）が可能となり、半導体チップ６周縁の限られた範囲でより多くの電気信号の入出力が可能となる。また、プラグ５がパッシベーション膜４の表面から突起しているため、ネールヘッド８の位置ずれが生じても、ネールヘッド８とプラグ５の良好な接続が得られるとともに、パッシベーション膜４のクラックも防止でき、高信頼性の半導体装置を得ることができる。
【００２９】
なお、本実施の形態では、プラグ５とプラグ５の隙間などでネールヘッド８がパッシベーション膜４と接触していても、接触していなくても、前述の効果が得られるものである。図４に示された従来例では、ネールヘッド１０８の位置ずれにより、金属電極１０４表面より上の部分のパッシベーション膜１０４にネールヘッド１０８が接触することにより、接続不良やパッシベーション膜１０４にクラックが発生していたが、本実施の形態では、ネールヘッド８の位置ずれの有無に関わらず、ネールヘッド８がパッシベーション膜４と接触しても、面接触状態となりパッシベーション膜１０４にクラックは発生せず、また、前述のようにネールヘッド８にプラグ５が食込む形となるため接続は強固である。
【００３０】
なお、前述のようにボンディングワイヤ７の代わりに半田バンプを用いても同様の効果を得ることができる。
【００３１】
〔第２の実施の形態〕
第２の実施の形態では、第１の実施の形態の半導体装置についてその製造方法の一例を説明する。図２はその製造方法を示す工程断面図である。
【００３２】
まず、図２（ａ）に示すように、例えばＭＯＳトランジスタやＭＯＳダイオードなどの半導体素子が形成されている半導体基板１の上に全面に亘ってＣＶＤ法などにより酸化シリコン膜よりなる層間絶縁膜２を堆積した後、図示は省略するが、層間絶縁膜２に半導体素子と層間絶縁膜２の上に形成される金属配線３との電気的接続をとるための開口部を周知のリソグラフィー技術およびドライエッチング技術により形成する。その後、層間絶縁膜２の上にアルミニウム合金よりなる金属配線３を周知のスパッタリング技術、リソグラフィー技術およびドライエッチング技術により形成する。次に、金属配線３の上にＣＶＤ法により窒化シリコンからなるパッシベーション膜４を全面に亘って堆積形成する。
【００３３】
次に、図２（ｂ）に示すように、リソグラフィー技術、ドライエッチング技術を用いて、パッシベーション膜４の特定個所に金属配線３に到達するバイアホール９を複数個形成する。バイアホール９を形成する位置や直径、個数は第１の実施の形態におけるプラグ５形成条件の範囲で、用途に合わせて設定する。
【００３４】
次に、図２（ｃ）に示すように、選択ＣＶＤ法により、アルミニウム合金をバイアホール９内およびパッシベーション膜４上に突起するまで堆積してプラグ５を形成する。選択ＣＶＤ法によるプラグ５の形成条件としては、例えば、アルゴンガスによるスパッタでバイアホール９内の表面の自然酸化膜を除去した後に、大気に暴露すること無くアルゴンガスをキャリアガスとしてジメチルアルミハイドライドを圧力３０トールで、５００ｓｃｃｍ流してプラグ５を成長させた。その時の基板温度は２５０℃である。これにより、パッシベーション膜４上に突起した複数個のプラグ５を得ることができた。
【００３５】
このようにして、図１と同様の半導体装置を製造することができる。
【００３６】
〔第３の実施の形態〕
第３の実施の形態では、第１の実施の形態の半導体装置についてその製造方法の第２の実施の形態とは異なる例を説明する。図３はその製造方法を示す工程断面図である。
【００３７】
まず、図３（ａ）に示すように、例えばＭＯＳトランジスタやＭＯＳダイオードなどの半導体素子が形成されている半導体基板１の上に全面に亘ってＣＶＤ法などにより酸化シリコン膜よりなる層間絶縁膜２を堆積した後、図示は省略するが、層間絶縁膜２に半導体素子と層間絶縁膜２の上に形成される金属配線３との電気的接続をとるための開口部を周知のリソグラフィー技術およびドライエッチング技術により形成する。その後、層間絶縁膜２の上にアルミニウム合金よりなる金属配線３を周知のスパッタリング技術、リソグラフィー技術およびドライエッチング技術により形成する。次に、金属配線３の上にＣＶＤ法により窒化シリコンからなるパッシベーション膜４を全面に亘って堆積形成する。
【００３８】
次に、図３（ｂ）に示すように、リソグラフィー技術、ドライエッチング技術を用いて、パッシベーション膜４の特定個所に金属配線３に到達するバイアホール９を複数個形成する。バイアホール９を形成する位置や直径、個数は第１の実施の形態におけるプラグ５形成条件の範囲で、用途に合わせて設定する。
【００３９】
次に、図３（ｃ）に示すように、パッシベーション膜４上およびバイアホール９内壁を覆うように、チタン合金からなる密着層１０を、スパッタリング技術を用いて形成する。次に、その上に、アルミニウム合金からなる金属電極層１１をＣＶＤ技術を用いて形成する。この金属電極層１１はバイアホール９内を充填し、かつ密着層１０を介してパッシベーション膜４上に形成する。また、この金属電極層１１の形成の際、非常に小さく深いバイアホール９に金属配線材料を充填する必要がある場合は、高圧ＰＶＤ法、または、リフロー法を用いれば効率よく充填することができる。
【００４０】
次に、図３（ｄ）に示すように、塩素系のガスを用いたドライエッチング技術で、金属電極層１１と密着層１０をパッシベーション膜４が露出するまでエッチングし、バイアホール９内にプラグ５を形成する。
【００４１】
次に、図３（ｅ）に示すように、ドライエッチング技術を用いてパッシベーション膜４をエッチングする。この時に、今回金属電極層１１に用いているアルミニウム合金をエッチングせず、窒化シリコンからなるパッシベーション膜４のみをエッチングする条件、例えば、フロロカーボンと酸素の混合ガスなどでプラズマエッチングを行う。これによって、パッシベーション膜４上に突起したプラグ５を得ることができた。
【００４２】
このようにして、図１と同様の半導体装置を製造することができる。なお、図３の製造方法の場合、バイアホール９内に充填された金属電極層１１からなるプラグ５の周り、すなわちバイアホール９の内壁に密着層１０が形成されているが、金属電極層１１がバイアホール９内に充填され金属配線３およびパッシベーション膜４との密着性が得られれば、密着層１０は必ずしも必要ない。
【００４３】
なお、上記の図３（ｄ）から図３（ｅ）に示した工程は、ドライエッチングの代わりにウエットエッチングの技術を用いてもよいし、ドライエッチングおよびウエットエッチングの技術を組み合せてもよい。
【００４４】
また、図３（ｃ）の金属電極層１１を形成した後、近年、平坦化に用いられるケミカルメカニカルポリッシングの技術、例えば、金属電極層１１のアルミニウム合金よりもパッシベーション膜４の方がエッチングレートが速くなる研磨剤および研磨布等の条件を使用した、ケミカルメカニカルポリッシングを行うことにより、図３（ｅ）と同様のパッシベーション膜４の表面から突起しているプラグ５を形成することができる。
【００４５】
【発明の効果】
本発明の半導体装置の製造方法によると、製造される半導体装置において、電気信号の入出力部となる金属電極の面積が縮小化されても、金属電極がパッシベーション膜の表面より上に突起した複数個のプラグからなるため、ボンディングワイヤ等との接続を容易かつ強固にできる。また、金属電極の面積の縮小化がより可能となり、より多くの金属電極をチップ周縁部に形成できる。また、金属電極を構成するプラグがパッシベーション膜の表面より上に突起しているため、ボンディングワイヤ等の接続の際にそのボンディングワイヤ等の位置がずれても、ボンディングワイヤ等とプラグの良好な接続が得られるとともに、パッシベーション膜のクラックも防止でき、高信頼性の半導体装置を得ることができる。
【００４６】
又、本発明に係る半導体装置の製造方法によると、従来のプラグを形成した後にワイヤボンディング用の金属電極を形成する工程が不必要となり、工程数削減と容易で安価な半導体装置の製造が可能となる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態における半導体装置の要部断面図および平面図。
【図２】本発明の第２の実施形態における半導体装置の製造方法を示す工程断面図。
【図３】本発明の第３の実施形態における半導体装置の製造方法を示す工程断面図。
【図４】従来の半導体装置の要部断面図および平面図。
【符号の説明】
１ 半導体基板
２ 層間絶縁膜
３ 金属配線
４ パッシベーション膜
５ プラグ
６ 半導体チップ
７ ボンディングワイヤ
８ ネールヘッド
９ バイアホール
１０ 密着層
１１ 金属電極層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a manufacturing method of a semiconductor equipment.
[0002]
[Prior art]
In a conventional semiconductor device such as a VLSI, an interlayer insulating film and a metal wiring are formed on a semiconductor element such as a transistor, and impurities such as moisture, heavy metal, or alkali metal are prevented from entering the metal wiring. Therefore, a passivation film is formed.
[0003]
A conventional semiconductor device will be described below with reference to FIG. FIG. 4A is a cross-sectional view of a main part of a conventional semiconductor device. As shown in FIG. 4A, an interlayer insulating film 102 made of silicon oxide, silicon nitride or the like is formed on a semiconductor substrate 101, and aluminum or an aluminum alloy containing aluminum as a main component is formed on the interlayer insulating film 102. A metal wiring 103 made of metal and a metal electrode 104 made of an aluminum alloy are respectively formed. A semiconductor element such as a transistor is formed under the interlayer insulating film 102, but the semiconductor element is omitted for convenience of illustration. A passivation film 105 is formed on the metal wiring 103 and the metal electrode 104 by, for example, a CVD method. Note that an opening 106 is formed in a region of the passivation film 105 on the upper surface of the metal electrode 104 where wire bonding is performed, and the metal electrode 104 and the nail head 108 of the bonding wire 107 are connected by an ultrasonic thermocompression bonding method.
[0004]
[Problems to be solved by the invention]
By the way, in a conventional semiconductor device such as a VLSI, the number of metal electrodes 104 for inputting / outputting electrical signals is reduced as the metal wiring 103 is miniaturized as the VLSI is miniaturized and the chip is miniaturized and multifunctional. It is increasing. Along with this, the following problems occur because the distance between the metal wiring 103 and the metal electrode 104 and between the metal electrode 104 and the metal electrode 104 is reduced.
[0005]
FIG. 4B is a plan view showing a part of the surface of the semiconductor chip 109. As shown in FIG. 4B, when the number of the metal electrodes 104 arranged on the periphery of the semiconductor chip 109 increases, the interval between the metal electrodes 104 and the metal electrodes 104 becomes very narrow as described above. Further, as the semiconductor chip 109 becomes more multifunctional and smaller, and the number of the metal electrodes 104 increases, there is no space between the metal electrodes 104, and the opening of the passivation film 105 corresponding to each metal electrode 104 is also increased. It becomes difficult. On the other hand, conventionally, the metal electrode 104 has been reduced in size and arranged to arrange a large number of metal electrodes 104.
[0006]
However, as shown in FIG. 4A, wire bonding in which the nail head 108 of the bonding wire 107 and the metal electrode 104 are connected by thermocompression using ultrasonic waves is bonded by the bonding state or bonding area of the bonding surface. The strength is determined. When the metal electrode 104 is reduced, it is necessary to reduce the nail head 108 so as not to protrude outside the metal electrode 104 and to prevent the adjacent nail heads 108 from contacting each other. As a result, since the adhesion area between the nail head 108 and the metal electrode 104 is reduced, adhesion failure between the nail head 108 and the metal electrode 104 often occurs.
[0007]
Further, as the number of metal electrodes 104 increases, it is necessary to reduce the size of the metal electrodes 104 and at the same time reduce the opening 106 of the passivation film 105 as much as possible. When the opening 106 is reduced in size, the accuracy of the wire bonding apparatus is limited, so that the possibility that the nail head 108 and the portion of the passivation film 105 above the metal electrode 104 come into contact with each other increases. When this contact occurs, the nail head 108 and the metal electrode 104 do not adhere to each other, and a crack occurs in the passivation film 105, resulting in a fatal wire bonding failure that causes the semiconductor chip to have poor moisture resistance. As a result, the reliability of the semiconductor device is lowered.
[0008]
The same problem occurs when solder bumps are used instead of the bonding wires 107. That is, as the number of metal electrodes 104 increases, if the metal electrodes 104 are scaled down, the bonding area decreases, causing poor bonding between the solder bumps and the metal electrodes 104, or between the solder bumps and the passivation film 105. The contact causes a poor adhesion between the solder bump and the metal electrode 104 and a crack occurs in the passivation film 105, thereby reducing the reliability of the semiconductor device.
[0009]
The object of the present invention is to provide a good connection of the nail head of the bonding wire and the solder bump to the metal electrode even if the metal electrode through which an electric signal is inputted to and outputted from the outside is reduced, and the passivation film cracks. it is to provide a method for manufacturing a highly reliable semiconductor equipment to prevent such.
[0010]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: forming an interlayer insulating film on a semiconductor substrate; forming a metal wiring on the interlayer insulating film; and a passivation film so as to cover the metal wiring. A step of forming a plurality of via holes at predetermined positions on the passivation film on the metal wiring, and a plug that fills the via hole by a selective CVD method and protrudes above the surface of the passivation film. And a step of forming.
[0011]
According to this manufacturing method , in the manufactured semiconductor device, even if the area of the metal electrode serving as the input / output portion of the electrical signal is reduced, the metal electrode is formed from the plurality of plugs protruding above the surface of the passivation film. Therefore, the connection with the bonding wire or the like can be easily and firmly established. Further, the area of the metal electrode can be further reduced, and more metal electrodes can be formed on the peripheral edge of the chip. In addition, since the plug constituting the metal electrode protrudes above the surface of the passivation film, even if the bonding wire or the like is misaligned when the bonding wire or the like is connected, the bonding wire and the plug are well connected. In addition, the passivation film can be prevented from cracking, and a highly reliable semiconductor device can be obtained.
[0018]
According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: forming an interlayer insulating film on a semiconductor substrate; forming a metal wiring on the interlayer insulating film; and a passivation film so as to cover the metal wiring. Forming a plurality of via holes at predetermined positions of the passivation film on the metal wiring, and forming a metal electrode layer so as to fill the via hole and cover the passivation film By etching the metal electrode layer and the passivation film by a chemical mechanical polishing method, which has a faster etching rate than the metal electrode layer, the metal electrode layer is formed in the via hole and protrudes above the surface of the passivation film after etching. Forming a plug.
[0019]
With this manufacturing method, the same effects as those of the semiconductor device manufacturing method according to the first aspect can be obtained.
The method for manufacturing a semiconductor device according to claim 3 of the present invention is the method for manufacturing a semiconductor device according to claim 1 or 2, wherein the metal wiring is made of any one of an aluminum alloy, a copper alloy, and silver, The plug is made of any one of an aluminum alloy, tungsten, copper, and titanium.
The method for manufacturing a semiconductor device according to claim 4 of the present invention is the method for manufacturing a semiconductor device according to claim 1 or 2, wherein the adhesion layer is formed after forming the via hole and before forming the metal wiring. Features.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
[0021]
[First Embodiment]
FIG. 1A is a cross-sectional view of a main part of the semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a plan view of a part of the semiconductor device.
[0022]
As shown in FIG. 1A, an interlayer insulating film 2 made of silicon oxide is formed on the entire surface of a semiconductor substrate 1. A semiconductor element such as a MOS transistor or a MOS diode is formed on the semiconductor substrate 1, and an electrical connection between the semiconductor element and the metal wiring 3 formed on the interlayer insulating film 2 is provided on the interlayer insulating film 2. Although the opening for taking is formed, the semiconductor element and the opening are omitted.
[0023]
A metal wiring 3 made of an aluminum alloy and electrically connected to a semiconductor element formed on the semiconductor substrate 1 is formed on the interlayer insulating film 2, and the entire surface of the metal wiring 3 is made of silicon nitride. A passivation film 4 is formed. Here, although the passivation film 4 is a single silicon nitride layer, it may be formed by stacking silicon oxide and silicon nitride.
[0024]
A feature of the semiconductor device according to the present embodiment is that a plurality of plugs 5 connected to the metal wiring 3 are formed through the passivation film 4 at a portion where wire bonding is to be performed, and the plug 5 is formed of the passivation film 4. It is protruding above the surface.
[0025]
As shown in FIG. 1B, a plug 5 is formed on the passivation film 4 on the periphery of the semiconductor chip 6 so as to project, and a plurality of plugs 5 in which dots are densely arranged constitute one metal electrode. A similar metal electrode is formed adjacent to the metal electrode with a slight gap. Each plug 5 protrudes from the surface of the passivation film 4 by 100 nm or more. One metal electrode is formed in a range of about 1200 to 8000 μm 2 so that the plugs 5 having a diameter of 200 to 5000 nm are as dense as possible. The protrusion amount (height from the surface of the passivation film 4) and the diameter of the plug 5 need to be set so that the impact during bonding of the bonding wire 7 does not damage the passivation film 4. In the present embodiment, the range in which the plurality of plugs 5 constituting one metal electrode are formed is a substantially circular shape of 2800 μm 2. The range is adjusted according to the diameter of the nail head 8 of the bonding wire 7. Set.
[0026]
The material of the plug 5 is the same aluminum alloy as that of the metal wiring 3, but needs to be determined in consideration of adhesion consistency with the material of the bonding wire 7. Further, when using solder bumps or the like instead of the bonding wires 7, it is necessary to determine the bonding consistency with the material of the solder and the metal wiring 3.
[0027]
This time, aluminum alloy is used as the material of the metal wiring 3 and the plug 5, but copper alloy, silver or the like can be used for the metal wiring 3, and tungsten, copper, titanium or the like is used for the plug 5. be able to.
[0028]
In this way, the plug 5 protrudes from the nail head 8 of the bonding wire 7 by forming the metal electrode by projecting the plug 5 on the passivation film 4 according to the size of the nail head 8 of the bonding wire 7. It becomes a shape. Therefore, the contact area between the plug 5 and the nail head 8 increases as the projection amount of each plug 5 increases, and the area of the formation region of one metal electrode comprising a plurality of plugs 5 according to the projection amount of the plug 5. Can be adjusted. Therefore, it is possible to reduce the area of the formation region of one metal electrode (reduction of the metal electrode) while strengthening the connection between the metal electrode composed of the plurality of plugs 5 and the nail head 8, and the periphery of the semiconductor chip 6. More electrical signals can be input and output within a limited range. In addition, since the plug 5 protrudes from the surface of the passivation film 4, even if the nail head 8 is displaced, a good connection between the nail head 8 and the plug 5 can be obtained, and cracks in the passivation film 4 can be prevented. And a highly reliable semiconductor device can be obtained.
[0029]
In the present embodiment, the above-described effects can be obtained regardless of whether the nail head 8 is in contact with the passivation film 4 or not in the gap between the plug 5 and the like. In the conventional example shown in FIG. 4, due to the displacement of the nail head 108, the nail head 108 contacts the passivation film 104 above the surface of the metal electrode 104, resulting in poor connection and cracks in the passivation film 104. However, in the present embodiment, even if the nail head 8 is in contact with the passivation film 4 regardless of whether or not the nail head 8 is misaligned, a surface contact state occurs and no cracks occur in the passivation film 104. In addition, since the plug 5 bites into the nail head 8 as described above, the connection is strong.
[0030]
As described above, the same effect can be obtained by using solder bumps instead of the bonding wires 7.
[0031]
[Second Embodiment]
In the second embodiment, an example of a method for manufacturing the semiconductor device of the first embodiment will be described. FIG. 2 is a process sectional view showing the manufacturing method.
[0032]
First, as shown in FIG. 2A, an interlayer insulating film 2 made of a silicon oxide film is formed over the entire surface of a semiconductor substrate 1 on which a semiconductor element such as a MOS transistor or a MOS diode is formed by CVD or the like. Although not shown in the figure, an opening for electrical connection between the semiconductor element and the metal wiring 3 formed on the interlayer insulating film 2 is formed in the interlayer insulating film 2. It is formed by an etching technique. Thereafter, a metal wiring 3 made of an aluminum alloy is formed on the interlayer insulating film 2 by a known sputtering technique, lithography technique, and dry etching technique. Next, a passivation film 4 made of silicon nitride is deposited on the entire surface of the metal wiring 3 by CVD.
[0033]
Next, as shown in FIG. 2B, a plurality of via holes 9 reaching the metal wiring 3 are formed at specific positions of the passivation film 4 by using a lithography technique and a dry etching technique. The position, diameter, and number of via holes 9 are set in accordance with the application within the range of the plug 5 forming conditions in the first embodiment.
[0034]
Next, as shown in FIG. 2C, an aluminum alloy is deposited by selective CVD until it protrudes into the via hole 9 and on the passivation film 4 to form the plug 5. As a formation condition of the plug 5 by the selective CVD method, for example, after removing a natural oxide film on the surface in the via hole 9 by sputtering with argon gas, dimethylaluminum hydride is used with argon gas as a carrier gas without being exposed to the atmosphere. The plug 5 was grown by flowing 500 sccm at a pressure of 30 Torr. The substrate temperature at that time is 250 ° C. As a result, a plurality of plugs 5 protruding on the passivation film 4 could be obtained.
[0035]
In this manner, a semiconductor device similar to that shown in FIG. 1 can be manufactured.
[0036]
[Third Embodiment]
In the third embodiment, an example different from the second embodiment of the manufacturing method of the semiconductor device of the first embodiment will be described. FIG. 3 is a process sectional view showing the manufacturing method.
[0037]
First, as shown in FIG. 3A, an interlayer insulating film 2 made of a silicon oxide film is formed over the entire surface of a semiconductor substrate 1 on which a semiconductor element such as a MOS transistor or a MOS diode is formed by CVD or the like. Although not shown in the figure, an opening for electrical connection between the semiconductor element and the metal wiring 3 formed on the interlayer insulating film 2 is formed in the interlayer insulating film 2. It is formed by an etching technique. Thereafter, a metal wiring 3 made of an aluminum alloy is formed on the interlayer insulating film 2 by a known sputtering technique, lithography technique, and dry etching technique. Next, a passivation film 4 made of silicon nitride is deposited on the entire surface of the metal wiring 3 by CVD.
[0038]
Next, as shown in FIG. 3B, a plurality of via holes 9 reaching the metal wiring 3 are formed at specific positions of the passivation film 4 by using a lithography technique and a dry etching technique. The position, diameter, and number of via holes 9 are set in accordance with the application within the range of the plug 5 forming conditions in the first embodiment.
[0039]
Next, as shown in FIG. 3C, an adhesion layer 10 made of a titanium alloy is formed using a sputtering technique so as to cover the passivation film 4 and the inner wall of the via hole 9. Next, a metal electrode layer 11 made of an aluminum alloy is formed thereon using a CVD technique. The metal electrode layer 11 fills the via hole 9 and is formed on the passivation film 4 via the adhesion layer 10. When the metal electrode layer 11 is formed, if it is necessary to fill the metal wiring material into the very small and deep via hole 9, it can be filled efficiently by using the high pressure PVD method or the reflow method. .
[0040]
Next, as shown in FIG. 3D, the metal electrode layer 11 and the adhesion layer 10 are etched until the passivation film 4 is exposed by a dry etching technique using a chlorine-based gas, and plugs are formed in the via holes 9. 5 is formed.
[0041]
Next, as shown in FIG. 3E, the passivation film 4 is etched using a dry etching technique. At this time, plasma etching is performed under conditions for etching only the passivation film 4 made of silicon nitride, for example, a mixed gas of fluorocarbon and oxygen, without etching the aluminum alloy used for the metal electrode layer 11 at this time. As a result, a plug 5 protruding on the passivation film 4 was obtained.
[0042]
In this manner, a semiconductor device similar to that shown in FIG. 1 can be manufactured. In the case of the manufacturing method of FIG. 3, the adhesion layer 10 is formed around the plug 5 made of the metal electrode layer 11 filled in the via hole 9, that is, on the inner wall of the via hole 9. Is filled in the via hole 9, and the adhesion layer 10 is not necessarily required if adhesion between the metal wiring 3 and the passivation film 4 is obtained.
[0043]
In the steps shown in FIGS. 3D to 3E, wet etching technology may be used instead of dry etching, or dry etching and wet etching technologies may be combined.
[0044]
In addition, after forming the metal electrode layer 11 of FIG. 3C, the etching rate of the passivation film 4 is higher than that of the chemical mechanical polishing technique used for planarization in recent years, for example, the aluminum alloy of the metal electrode layer 11. The plug 5 protruding from the surface of the passivation film 4 similar to that shown in FIG. 3E can be formed by performing chemical mechanical polishing using conditions such as a faster abrasive and polishing cloth.
[0045]
【The invention's effect】
According to the method for manufacturing a semiconductor device of the present invention, in the manufactured semiconductor device, even when the area of the metal electrode serving as an input / output portion for an electric signal is reduced, the plurality of metal electrodes protrude above the surface of the passivation film. Since it consists of individual plugs, the connection with bonding wires and the like can be made easily and firmly. Further, the area of the metal electrode can be further reduced, and more metal electrodes can be formed on the peripheral edge of the chip. In addition, since the plug constituting the metal electrode protrudes above the surface of the passivation film, even if the bonding wire or the like is misaligned when the bonding wire or the like is connected, the bonding wire and the plug are well connected. In addition, the passivation film can be prevented from cracking, and a highly reliable semiconductor device can be obtained.
[0046]
In addition, according to the method for manufacturing a semiconductor device according to the present invention, a process for forming a metal electrode for wire bonding after forming a conventional plug is unnecessary, and the number of processes can be reduced and an easy and inexpensive semiconductor device can be manufactured. It becomes.
[Brief description of the drawings]
1A and 1B are a cross-sectional view and a plan view of main parts of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention.
4A and 4B are a cross-sectional view and a plan view of main parts of a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Interlayer insulating film 3 Metal wiring 4 Passivation film 5 Plug 6 Semiconductor chip 7 Bonding wire 8 Nail head 9 Via hole 10 Adhesion layer 11 Metal electrode layer

Claims (4)

半導体基板上に層間絶縁膜を形成する工程と、前記層間絶縁膜上に金属配線を形成する工程と、前記金属配線を覆うようにパッシベーション膜を形成する工程と、前記金属配線上で前記パッシベーション膜の所定の位置に複数個のバイアホールを形成する工程と、選択ＣＶＤ法によって前記バイアホール内を充填しかつ前記パッシベーション膜の表面より上に突起するプラグを形成する工程とを含むことを特徴とする半導体装置の製造方法。  Forming an interlayer insulating film on a semiconductor substrate; forming a metal wiring on the interlayer insulating film; forming a passivation film so as to cover the metal wiring; and the passivation film on the metal wiring. Forming a plurality of via holes at predetermined positions, and forming a plug that fills the via hole and protrudes above the surface of the passivation film by a selective CVD method. A method for manufacturing a semiconductor device. 半導体基板上に層間絶縁膜を形成する工程と、前記層間絶縁膜上に金属配線を形成する工程と、前記金属配線を覆うようにパッシベーション膜を形成する工程と、前記金属配線上で前記パッシベーション膜の所定の位置に複数個のバイアホールを形成する工程と、前記バイアホール内を充填するとともに前記パッシベーション膜上を覆うように金属電極層を形成する工程と、前記金属電極層より前記パッシベーション膜の方がエッチングレートの速いケミカルメカニカルポリッシング法によって前記金属電極層および前記パッシベーション膜をエッチングすることにより前記バイアホール内の前記金属電極層からなり前記エッチング後の前記パッシベーション膜の表面より上に突起したプラグを形成する工程とを含むことを特徴とする半導体装置の製造方法。  Forming an interlayer insulating film on a semiconductor substrate; forming a metal wiring on the interlayer insulating film; forming a passivation film so as to cover the metal wiring; and the passivation film on the metal wiring. Forming a plurality of via holes at predetermined positions, forming a metal electrode layer so as to fill the via hole and cover the passivation film, and forming the passivation film from the metal electrode layer. The metal electrode layer and the passivation film are etched by a chemical mechanical polishing method, which has a higher etching rate, and the plug is formed of the metal electrode layer in the via hole and protrudes above the surface of the passivation film after the etching. And a step of forming a semiconductor. Method of manufacturing location. 前記金属配線はアルミニウム合金、銅合金、銀のいずれかからなるものであって、前記プラグは、アルミニウム合金、タングステン、銅、チタンのいずれかからなるものであることを特徴とする請求項１または２記載の半導体装置の製造方法。The metal wiring is made of any one of an aluminum alloy, a copper alloy, and silver, and the plug is made of any one of an aluminum alloy, tungsten, copper, and titanium. 3. A method for producing a semiconductor device according to 2. 前記バイアホール形成後、前記金属配線の形成前に、密着層を形成することを特徴とする請求項１または２に記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein an adhesion layer is formed after the via hole is formed and before the metal wiring is formed.
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