JP3715665B2

JP3715665B2 - Orthogonal transformation device

Info

Publication number: JP3715665B2
Application number: JP23790294A
Authority: JP
Inventors: 慎吾野澤
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 1994-09-30
Filing date: 1994-09-30
Publication date: 2005-11-09
Anticipated expiration: 2020-11-09
Also published as: JPH08101824A

Description

【０００１】
【産業上の利用分野】
本発明は映像信号等の高能率符号化に用いられる直交変換装置に関するものである。
【０００２】
【従来の技術】
従来より画像や音声の高能率符号化を行う場合の手法として、離散コサイン変換（ＤＣＴ）等の直交変換処理が知られている。
図１２は８×８個の画素ブロックから成る入力信号に対する従来の２次元ＤＣＴ処理回路を示したもので、８個の入力信号に対する２つの１次元ＤＣＴ回路と転置回路から成るが、特に１次元ＤＣＴ回路の処理時間が大きいため、いくつかの高速アルゴリズムが考え出されている。図１３は既知の高速アルゴリズムを用いた１次元ＤＣＴの一従来例である。この例ではＤＣＴの変換式が持つ対称性を利用し、あらかじめ入力信号を対称に和差演算し、まとめることで乗算回数を半分に減らしている。
【０００３】
また、ＦＦＴのようなバタフライによる高速アルゴリズムも広く知られている。このアルゴリズムはＤＣＴの変換式に含まれる共通部分をまとめることで、乗算回数を更に減らしている。しかし、高速アルゴリズムを用いた装置の多くは回路規模が大きく、ＬＳＩ化等の応用に不向きであることが指摘されている。
【０００４】
また、人間は高域の周波数に鈍いという視覚特性を利用し、ＤＣＴによって変換した信号に重み付けを行う方式も一般に用いられている。このような方式では、低域を表す信号に大きな重み付けを行い、高域を表す信号に小さな重み付けを行うことにより、符号化の能率を高めようとすることが多い。図１４は重み付けを行う２次元ＤＣＴの従来例である。図１４（ａ）は通常の２次元ＤＣＴ後に重み付けを行う例、図１４（ｂ）は１次元ＤＣＴ毎に重み付けを行う例である。また、ＤＣＴと重み付けの乗数とを共用する方法が特開平２−１１６９６９号公報により公知である。
【０００５】
一方、入力信号が時間のずれを持った２フィールドで構成されるＴＶ映像信号等の高能率符号化では、フィールド間の動きを検出してＤＣＴの方式を切り換える工夫が広く用いられている。図１５はこの方法の従来例の１つである。ＤＣＴ処理を行う前に動き検出回路（図示せず）から動き情報信号がＤＣＴ回路に供給され、動きの有無に応じて８×８個の入力信号を通常の２次元ＤＣＴする方式と、フィールド間の和および差から成る４×８個の入力信号２組に分けて２次元ＤＣＴする方式とを切り換えている。
【０００６】
【発明が解決しようとする課題】
従来のＤＣＴ回路においては、上記の様に高速性や高能率性を向上させる工夫のために、回路規模が大きくなるという問題があった。特にＤＣＴとその逆変換であるＩＤＣＴとの両方を必要とする用途では、更に回路規模が大きくなり、ＬＳＩ化が困難になるという問題があった。
【０００７】
本発明は上記のような問題を解決するためになされたもので、処理を高速化すると共に回路規模を縮小することのできる直交変換装置を得ることを目的としている。
【０００８】
【課題を解決するための手段】
本発明の直交変換装置は、それぞれｎ個（ｎ≧1）の信号からなる２つの信号列を受け取り、当該２つの信号列間の和及び差を算出する和差演算手段と、ｎ個の信号を受け取り、第一の係数列との積和を算出する第一の積和演算手段と、ｎ個の信号を受け取り、第二の係数列との積和を算出する第二の積和演算手段と、水平及び垂直方向に配列された２ｎ×２ｎ個の信号を受け取り、所定の並べ替えを行って出力する転置手段と、前記各手段を制御する制御手段とを備え、前記制御手段は、第一の符号化処理として、２ｎ×２ｎ個の入力信号を前記和差演算手段に順次供給し、前記入力信号の対称要素の和および差の成分を算出し、当該和の成分を前記第一の積和演算手段に順次供給し、当該差の成分を前記第二の積和演算手段に順次供給し、当該第一および第二の積和演算手段の演算結果を前記転置手段に供給し、前記転置手段の出力を前記和差演算手段に順次供給し、前記転置手段の出力の対称要素の和および差の成分を算出し、当該和の成分を前記第一の積和演算手段に順次供給し、当該差の成分を前記第二の積和演算手段に順次供給し、当該第一および第二の積和演算手段の演算結果を出力する制御を行い、かつ、前記制御手段は、第二の符号化処理として、２ｎ×２ｎ個の入力信号を前記和差演算手段に順次供給し、前記入力信号の対称要素の和および差の成分を算出し、当該和の成分を前記第一の積和演算手段に順次供給し、当該差の成分を前記第二の積和演算手段に順次供給し、当該第一および第二の積和演算手段の演算結果を前記転置手段に供給し、当該転置手段の出力を前記和差演算手段に順次供給し、前記転置手段の出力の隣接行の和および差の成分を算出し、当該和の成分を前記第一の積和演算手段に順次供給し、当該差の成分を続いて前記第一の積和演算手段に順次供給し、当該第一の積和演算手段の演算結果を出力する制御を行うことを特徴とする。
【０００９】
本発明の直交変換装置における他の態様は、それぞれｎ個（ｎ≧1）の信号からなる２つの信号列を受け取り、当該２つの信号列間の和及び差を算出する和差演算手段と、ｎ個の信号を受け取り、第一の係数列との積和を算出する第一の積和演算手段と、ｎ個の信号を受け取り、第二の係数列との積和を算出する第二の積和演算手段と、水平及び垂直方向に配列された２ｎ×２ｎ個の信号を受け取り、所定の並べ替えを行って出力する転置手段と、前記各手段を制御する制御手段とを備え、前記制御手段は、第一の復号化処理として、２ｎ×２ｎ個の入力信号を２つのｎ×２ｎ個の信号列に分離し、当該２つのｎ×２ｎ個の信号列の一方を前記第一の積和演算手段に順次供給し、当該２つのｎ×２ｎ個の信号列の他方を前記第二の積和演算手段に順次供給し、当該第一および第二の積和演算手段の演算結果を前記和差演算手段に順次供給し、前記和差演算手段の演算結果を前記転置手段に供給し、前記転置手段の出力を２つのｎ×２ｎ個の信号列に分離し、当該２つのｎ×２ｎ個の信号列の一方を前記第一の積和演算手段に順次供給し、当該２つのｎ×２ｎ個の信号列の他方を前記第二の積和演算手段に順次供給し、当該第一および第二の積和演算手段の演算結果を前記和差演算手段に順次供給し、前記和差演算手段の演算結果を出力する制御を行い、かつ、前記制御手段は、第二の復号化処理として、２ｎ×２ｎ個の入力信号を２つのｎ×２ｎ個の信号列に分離し、当該２つのｎ×２ｎ個の信号列の一方を前記第一の積和演算手段に順次供給し、当該２つのｎ×２ｎ個の信号列の他方を続いて前記第一の積和演算手段に順次供給し、当該第一の積和演算手段の演算結果を前記和差演算手段に順次供給し、前記和差演算手段の演算結果を前記転置手段に供給し、前記転置手段の出力を２つのｎ×２ｎ個の信号列に分離し、当該２つのｎ×２ｎ個の信号列の一方を前記第一の積和演算手段に順次供給し、当該２つのｎ×２ｎ個の信号列の他方を前記第二の積和演算手段に順次供給し、当該第一および第二の積和演算手段の演算結果を前記和差演算手段に順次供給し、前記和差演算手段の演算結果を出力する制御を行うことを特徴とする。
【００１０】
また、本発明の直交変換装置におけるその他の態様は、それぞれｎ個（ｎ≧1）の信号からなる２つの信号列を受け取り、当該２つの信号列間の和及び差を算出する和差演算手段と、ｎ個の信号を受け取り、第一の係数列との積和を算出する第一の積和演算手段と、ｎ個の信号を受け取り、第二の係数列との積和を算出する第二の積和演算手段と、水平及び垂直方向に配列された２ｎ×２ｎ個の信号を受け取り、所定の並べ替えを行って出力する転置手段と、前記各手段を制御する制御手段とを備え、前記制御手段は、第一の符号化処理として、２ｎ×２ｎ個の入力信号を前記和差演算手段に順次供給し、前記入力信号の対称要素の和および差の成分を算出し、当該和の成分を前記第一の積和演算手段に順次供給し、当該差の成分を前記第二の積和演算手段に順次供給し、当該第一および第二の積和演算手段の演算結果を前記転置手段に供給し、当該転置手段の出力を前記和差演算手段に順次供給し、前記転置手段の出力の対称要素の和および差の成分を算出し、当該和の成分を前記第一の積和演算手段に順次供給し、当該差の成分を前記第二の積和演算手段に順次供給し、当該第一および第二の積和演算手段の演算結果を出力する制御を行い、かつ、前記制御手段は、第二の符号化処理として、２ｎ×２ｎ個の入力信号を前記和差演算手段に順次供給し、前記入力信号の対称要素の和および差の成分を算出し、当該和の成分を前記第一の積和演算手段に順次供給し、当該差の成分を前記第二の積和演算手段に順次供給し、当該第一および第二の積和演算手段の演算結果を前記転置手段に供給し、当該転置手段の出力を前記和差演算手段に順次供給し、前記転置手段の出力の隣接行の和および差の成分を算出し、当該和の成分を前記第一の積和演算手段に順次供給し、当該差の成分を続いて前記第一の積和演算手段に順次供給し、当該第一の積和演算手段の演算結果を出力する制御を行い、かつ、前記制御手段は、第一の復号化処理として、２ｎ×２ｎ個の入力信号を２つのｎ×２ｎ個の信号列に分離し、当該２つのｎ×２ｎ個の信号列の一方を前記第一の積和演算手段に順次供給し、当該２つのｎ×２ｎ個の信号列の他方を前記第二の積和演算手段に順次供給し、当該第一および第二の積和演算手段の演算結果を前記和差演算手段に順次供給し、前記和差演算手段の演算結果を前記転置手段に供給し、前記転置手段の出力を２つのｎ×２ｎ個の信号列に分離し、当該２つのｎ×２ｎ個の信号列の一方を前記第一の積和演算手段に順次供給し、当該２つのｎ×２ｎ個の信号列の他方を前記第二の積和演算手段に順次供給し、当該第一および第二の積和演算手段の演算結果を前記和差演算手段に順次供給し、前記和差演算手段の演算結果を出力する制御を行い、かつ、前記制御手段は、第二の復号化処理として、２ｎ×２ｎ個の入力信号を２つのｎ×２ｎ個の信号列に分離し、当該２つのｎ×２ｎ個の信号列の一方を前記第一の積和演算手段に順次供給し、当該２つのｎ×２ｎ個の信号列の他方を続いて前記第一の積和演算手段に順次供給し、当該第一の積和演算手段の演算結果を前記和差演算手段に順次供給し、前記和差演算手段の演算結果を前記転置手段に供給し、前記転置手段の出力を２つのｎ×２ｎ個の信号列に分離し、当該２つのｎ×２ｎ個の信号列の一方を前記第一の積和演算手段に順次供給し、当該２つのｎ×２ｎ個の信号列の他方を前記第二の積和演算手段に順次供給し、当該第一および第二の積和演算手段の演算結果を前記和差演算手段に順次供給し、前記和差演算手段の演算結果を出力する制御を行うことを特徴とする。
また、本発明の直交変換装置におけるその他の態様は、さらに、前記第二の積和演算手段は、ｎ個の信号を受け取り所定の係数を乗じる重み付け手段を含むことを特徴とする。
また、本発明の直交変換装置におけるその他の態様は、さらに、前記第一の積和演算手段は、ｎ個の信号を受け取り所定の係数を乗じる重み付け手段を含むことを特徴とする。
【００１１】
【作用】
本発明によれば、ＤＣＴとＩＤＣＴの処理において構成回路を共有でき、装置の回路規模を大幅に削減できる。
【００１２】
【実施例】
図１は本発明による直交変換装置の実施例を示すブロック図であり、縦横８×８個の画素から成る入力信号を２次元ＤＣＴする場合の例を示す。
図２は本実施例によるＤＣＴの処理過程を表す流れ図である。
図１、図２において本装置は、入力端子１、出力端子２、及び和差演算、積和演算、重み付け、転置、動き検出等の各処理を行う回路３〜８がバス１０で接続された構成になっている。また、バス制御回路９がバス１０のデータの流れを制御すると共に、上記諸回路３〜８と制御信号のやりとりを行い、動作状態の切り換えを制御して、図２に示した流れ図に従って処理を行うように成されている。
【００１３】
入力端子１から１ライン分（画素８個）の信号が取り込まれ、バス１０を介して和差演算回路３に供給される。図３は、和差演算回路３の実施例の１つを示す。図３において、バス１０を介して端子３０１〜３０８に供給された信号の対称要素間の和が加算器３１７〜３２０から端子３０９〜３１２に出力される。また対称要素間の差が減算器３２１〜３２４から端子３１３〜３１６に出力される。この和差演算回路３が端子３０９〜３１２に出力した加算信号列は、バス制御回路９によって積和演算回路４に供給される。同様に和差演算回路３が端子３１３〜３１６に出力した減算信号列はバス制御回路９によって積和演算回路５に供給される。
【００１４】
積和演算回路４の実施例の１つを図４に示す。この実施例は加算器４１０〜４１３を含む１組の４ポイントバタフライ演算器４０１、係数器４１４〜４１９、切り換え器ｓｗ１〜ｓｗ８、加算器４２０、遅延回路４２１〜４２４により図示のように構成されており、ＤＣＴおよびＩＤＣＴ処理両方に対応した積和演算回路４である。図４において、係数器４１４〜４１９は各回路内に示した数字を乗算する。点線は符号の反転を表している。この積和演算回路４は端子４０２〜４０５に供給された信号を２サイクルで処理し、端子４０６〜４０９に出力する。図５はこの回路４がＤＣＴおよびＩＤＣＴ処理を行う際の各サイクルにおける切り換え器ｓｗ１〜ｓｗ８の状態を示したものである。
【００１５】
一方、積和演算回路５の実施例の１つを図６に示す。図６において積和演算回路５は端子６０１に供給された減算信号列を４サイクルにわたってシリアルに係数器６０２〜６０５へ供給する。係数器６０２〜６０５は所定の係数ｋ１〜ｋ４を供給された信号に乗じ、それぞれ乗算結果と乗算結果の符号を点線のように反転した信号とが切り換え器６０６に供給される。切り換え器６０６は供給された信号を各サイクルで切り換え、積算回路６０７〜６１０に供給する。図７は各サイクルにおける切り換え器６０６の状態を示す。切り換え器６０６はＤＣＴとＩＤＣＴとで各サイクルの状態が全く同一である。積算回路６０７〜６１０は、４サイクルにわたって供給される信号を積算し、端子６１１〜６１４に出力する。
【００１６】
端子６１１〜６１４に出力された信号は、重み付け回路６に供給される。図８は重み付け回路６の実施例の１つを示す。図８において、重み付け回路６は端子８０１〜８０４に供給された信号にそれぞれ所定の係数を乗じて端子８０５〜８０８に出力する。図８において８０９〜８１６は係数器でそれぞれ係数ｗ１、ｉｗ１〜ｗ４、ｉｗ４を乗じる。８１７〜８２０は切り換え器である。切り換え器８１７〜８２０はＤＣＴ処理においてはａ側を選択し、ＩＤＣＴ処理においてはｂ側を選択する。
【００１７】
次に積和演算回路４と重み付け回路６の出力は、転置回路７に供給される。このとき、バス制御回路９は、積和演算回路４からの信号列と重み付け回路６からの信号列とを図９（ａ）に示すように互い違いに並べ換えて転置回路７に供給する。転置回路７は８ライン分（６４個）の入力信号についての上記処理結果を保持した後、転置する。
【００１８】
次に動き検出回路８は転置回路７に格納された信号から入力信号中の動き情報を検出する。図１０は動き検出回路８の実施例の１つである。図１０において動き検出回路８は、転置回路７からＤＣ成分列を供給される。ＤＣ成分列は各ラインの直流成分から成るものである。この動き検出回路８は端子１００１〜１００８に供給されたＤＣ成分列を奇数ライン列と偶数ライン列とに分け、それぞれの総和を加算器１０１２〜１０１７で求めた後、各総和同士の差を減算器１０１８で算出し、絶対値器１００９によってその絶対値を求めて検出器１０１０に供給する。検出器１０１０は供給された値を定数２５６と比較し、２５６より小さい時は動き無し、２５６以上の時は動き有りを表す動き情報信号を端子１０１１に出力する。
【００１９】
この動き情報信号は図１の出力端子２から出力されると共にバス制御回路９に供給され、以降の処理方式を決定する。尚、動き検出回路８を設けずに外部から動き情報信号を供給するように構成してもよい。動き無しの場合はバス制御回路９は、転置回路７から供給される８個ずつの信号に図１の入力端子１からの信号列と同様の処理過程を与える。すなわち、図２の分岐ブロック２００から分岐路２０１側を介しての和算演算回路３への流れで処理され、出力端子２から順次出力される。また、動き有りの場合は、図２の分岐ブロック２００から分岐路２０２側を介しての和算演算回路３への流れで処理される。この場合バス制御回路９は転置回路７が出力する８個ずつの信号を、図９（ｂ）の様に並べ換えて和差演算回路３に供給する。
【００２０】
動き無しの場合は、和差演算回路３が出力する加算信号列は積和演算回路４に供給され、前記した処理と同様の処理を同様にまた２サイクルで行うと共に積和演算回路５、重み付け回路６で同様に処理され、各処理結果を出力端子２から出力する。動き有りの場合は、和差演算回路３が出力する減算信号列は、今度は加算信号列と同様に積和演算回路４に供給される。積和演算回路４を図４の実施例のように構成した場合、処理時間が短いため、加算信号列と減算信号列それぞれに対する処理を順次直列に行っても、積和演算回路５と重み付け回路６の各処理時間の和以内の時間で処理可能である。積和演算回路４で処理された減算信号列は出力端子２から出力される。
【００２１】
図１１は図１の実施例によるＩＤＣＴ処理過程を表す流れ図である。図１、図１１、において、ＤＣＴ係数列に先立って動き情報信号が入力端子１に供給される。動き情報信号が動き無しを示している場合はバス制御回路９は以降入力端子１から８個ずつ供給されるＤＣＴ係数列を、分岐ブロック１１０１を介して奇数番と偶数番の４個ずつの信号列に分離し、奇数番信号列を積和演算回路４に偶数番信号列を重み付け回路６に供給する。重み付け回路６は、供給された信号にＩＤＣＴ時の所定の係数を乗じる。図８の重み付け回路６の実施例では、このとき切り換え器８１７〜８２０をｂ側に選択する。重み付け回路６の演算結果は、積和演算回路５に供給される。積和演算回路４を図４の実施例のように構成した場合、図５に従って切り換え器ｓｗ１〜ｓｗ８を選択し、２サイクルで処理を行う。積和演算回路５を図６の実施例のように構成した場合、図７に従って切り換え器６０６を選択し、４サイクルで処理を行う。
【００２２】
積和演算回路４、積和演算回路５の処理結果は、バスを経由して和差演算回路３に供給される。このときバス制御回路９は、図９（ｃ）のように信号を並べ換えて出力端子３０１〜３０８から和差演算回路３に供給する。和差演算回路３は図３の実施例のように、供給された信号を対称的に加減算し、その結果は転置回路７に供給される。
【００２３】
一方、動き情報信号が動き有りを表している場合は、バス制御回路９は、以降８個ずつ入力端子１に供給される信号を分岐ブロック１１０１を介して４つずつ前半信号列と後半信号列とに分離し、順次、積和演算回路４に供給する。積和演算回路４で処理された前半信号列と後半信号列とはバス制御回路９により、図９（ｃ）のように並べ換えられて、和差演算回路３に供給される。
【００２４】
和差演算回路３は図３の実施例のように、供給された信号を対称的に加減算する。バス制御回路９は和差演算回路３の出力を図９（ｄ）のように並べ換え、転置回路７に供給する。これ以降の処理は動き情報信号によらず同一である。転置回路は６４個の信号をバッファに保持した後、転置して信号を８個ずつ出力する。８個ずつの信号は前述した図２の動き無しの場合のＤＣＴ係数列の処理と同様に処理され、出力端子２から順次出力される。
【００２５】
本実施例においては図２、図１１のいずれの処理過程も図１の和差演算回路３、積和演算回路４、積和演算回路５、重み付け回路６及び転置回路７の構成を共有している。即ち、図１における回路３〜８は、図２及び図１１の各回路３〜８と共有される。
【００２６】
【発明の効果】
以上説明したように、本発明によれば、高速性や高能率性を向上させるように成されたアルゴリズムを用いながら、重み付けを行う場合又は行わない場合でＤＣＴとＩＤＣＴの処理において構成回路を共有することができ、装置の回路規模を大幅に削減することができる効果がある。
【図面の簡単な説明】
【図１】本発明の実施例を示すブロック図である。
【図２】図１の装置によるＤＣＴの流れ図である。
【図３】図１の装置における和差演算回路３の実施例を示すブロック図である。
【図４】図１の装置における積和演算回路４の実施例を示すブロック図である。
【図５】図４の切り換え器のサイクル毎の状態を示す構成図である。
【図６】図１の装置における積和演算回路５の実施例を示すブロック図である。
【図７】図６中の切り換え器のサイクル毎の状態を示す構成図である。
【図８】図１の装置における重み付け回路６の実施例を示すブロック図である。
【図９】図１の装置におけるバス制御回路９の信号並べ換え順を示す構成図である。
【図１０】図１の装置における動き検出回路８の実施例を示すブロック図である。
【図１１】図１の装置によるＩＤＣＴの流れ図である。
【図１２】従来例を示すブロック図である。
【図１３】高速アルゴリズムによる従来例を示すブロック図である。
【図１４】重み付けの従来例を示すブロック図である。
【図１５】動き情報に対応した従来例を示すブロック図である。
【符号の説明】
１入力端子
２出力端子
３和差演算回路
４積和演算回路
５積和演算回路
６重み付け回路
７転置回路
８動き検出回路
９バス制御回路
１０バス[0001]
[Industrial application fields]
The present invention relates to an orthogonal transform apparatus used for high-efficiency encoding of video signals and the like.
[0002]
[Prior art]
Conventionally, orthogonal transform processing such as discrete cosine transform (DCT) is known as a technique for performing high-efficiency encoding of images and sounds.
FIG. 12 shows a conventional two-dimensional DCT processing circuit for an input signal composed of 8 × 8 pixel blocks, which is composed of two one-dimensional DCT circuits and a transposition circuit for eight input signals. Due to the large processing time of the DCT circuit, several high-speed algorithms have been devised. FIG. 13 shows a conventional example of a one-dimensional DCT using a known high-speed algorithm. In this example, the symmetry of the DCT conversion formula is used, the input signals are symmetrically summed and calculated in advance, and the number of multiplications is reduced by half.
[0003]
A fast algorithm using butterfly such as FFT is also widely known. This algorithm further reduces the number of multiplications by collecting common parts included in the DCT conversion formula. However, it has been pointed out that many devices using high-speed algorithms have a large circuit scale and are not suitable for applications such as LSI.
[0004]
In addition, a method of weighting a signal converted by DCT using a visual characteristic that a human is dull in a high frequency is generally used. In such a system, in many cases, a high weight is applied to a signal representing a low frequency, and a small weight is applied to a signal representing a high frequency, thereby increasing the efficiency of encoding. FIG. 14 shows a conventional example of two-dimensional DCT that performs weighting. FIG. 14A shows an example in which weighting is performed after normal two-dimensional DCT, and FIG. 14B shows an example in which weighting is performed for each one-dimensional DCT. Japanese Patent Laid-Open No. 2-116969 discloses a method for sharing DCT and weighting multiplier.
[0005]
On the other hand, in high-efficiency encoding of a TV video signal or the like composed of two fields in which an input signal has a time lag, a device for detecting a motion between fields and switching the DCT method is widely used. FIG. 15 shows one conventional example of this method. Before DCT processing, a motion information signal is supplied to a DCT circuit from a motion detection circuit (not shown), and a method of performing normal two-dimensional DCT on 8 × 8 input signals according to the presence or absence of motion, and between fields The two-dimensional DCT method is switched to two sets of 4 × 8 input signals each consisting of the sum and difference.
[0006]
[Problems to be solved by the invention]
The conventional DCT circuit has a problem that the circuit scale becomes large due to the device for improving the high speed and high efficiency as described above. In particular, in applications that require both DCT and IDCT, which is the inverse transform thereof, there has been a problem that the circuit scale is further increased, making LSI implementation difficult.
[0007]
The present invention has been made in order to solve the above-described problems, and an object of the present invention is to obtain an orthogonal transform apparatus capable of speeding up processing and reducing the circuit scale.
[0008]
[Means for Solving the Problems]
The orthogonal transform apparatus of the present invention receives two signal sequences each consisting of n (n ≧ 1) signals, calculates sum and difference between the two signal sequences, and n signals The first product-sum operation means for calculating the product sum with the first coefficient sequence, and the second product-sum operation means for receiving the n signals and calculating the product sum with the second coefficient sequence A transposing means for receiving 2n × 2n signals arranged in the horizontal and vertical directions, outputting the signals after performing a predetermined rearrangement, and a control means for controlling the means, the control means comprising: As one encoding process, 2n × 2n input signals are sequentially supplied to the sum / difference calculating means, and the sum and difference components of the symmetric elements of the input signal are calculated. Sequentially supplying the product-sum operation means, sequentially supplying the difference component to the second product-sum operation means, The calculation results of the first and second product-sum calculation means are supplied to the transposition means, the output of the transposition means is sequentially supplied to the sum-difference calculation means, and the sum and difference of the symmetrical elements of the output of the transposition means The sum component is sequentially supplied to the first product-sum operation means, the difference component is sequentially supplied to the second product-sum operation means, and the first and second products are calculated. The control unit performs control to output the calculation result of the sum calculation unit, and the control unit sequentially supplies 2n × 2n input signals to the sum / difference calculation unit as a second encoding process. Calculating the sum and difference components of the symmetric elements, sequentially supplying the sum components to the first product-sum operation means, sequentially supplying the difference components to the second product-sum operation means, The calculation results of the first and second product-sum calculation means are supplied to the transposition means, and the output of the transposition means is output. Are sequentially supplied to the sum-difference calculating means, the sum and difference components of the adjacent rows of the output of the transposing means are calculated, the sum components are sequentially supplied to the first product-sum calculating means, The components are successively supplied to the first product-sum operation means, and control is performed to output the operation result of the first product-sum operation means.
[0009]
In another aspect of the orthogonal transform apparatus of the present invention, a sum-difference calculating unit that receives two signal sequences each including n (n ≧ 1) signals and calculates a sum and a difference between the two signal sequences; a first product-sum operation unit that receives n signals and calculates a sum of products with the first coefficient sequence; a second product that receives n signals and calculates a product sum with the second coefficient sequence; A product-sum operation means; a transposition means for receiving 2n × 2n signals arranged in the horizontal and vertical directions, performing a predetermined rearrangement and outputting; and a control means for controlling the means. The means separates 2n × 2n input signals into two n × 2n signal sequences as a first decoding process, and converts one of the two n × 2n signal sequences into the first product. Sequentially supplied to the sum operation means, and the other of the two n × 2n signal sequences is supplied to the second product-sum operation means. Next, the operation results of the first and second product-sum operation means are sequentially supplied to the sum-difference operation means, the operation result of the sum-difference operation means is supplied to the transposing means, and the output of the transposing means Are divided into two n × 2n signal sequences, one of the two n × 2n signal sequences is sequentially supplied to the first product-sum operation means, and the two n × 2n signal sequences are supplied. Are sequentially supplied to the second product-sum operation means, the operation results of the first and second product-sum operation means are sequentially supplied to the sum-difference operation means, and the operation result of the sum-difference operation means is obtained. The control means performs the output control, and the control means separates 2n × 2n input signals into two n × 2n signal sequences as a second decoding process, and the two n × 2n signal sequences One of the signal sequences is sequentially supplied to the first product-sum operation means, and the other of the two n × 2n signal sequences is continued. The first product-sum operation means is sequentially supplied, the operation result of the first product-sum operation means is sequentially supplied to the sum-difference operation means, and the operation result of the sum-difference operation means is supplied to the transposition means. The output of the transposing means is separated into two n × 2n signal sequences, one of the two n × 2n signal sequences is sequentially supplied to the first product-sum operation means, and the two n The other of the 2n signal sequences is sequentially supplied to the second product-sum operation means, and the operation results of the first and second product-sum operation means are sequentially supplied to the sum-difference operation means, Control is performed to output the calculation result of the calculation means.
[0010]
Another aspect of the orthogonal transform apparatus according to the present invention is a sum-difference calculating means for receiving two signal sequences each consisting of n (n ≧ 1) signals and calculating a sum and a difference between the two signal sequences. A first sum-of-products operation means for receiving n signals and calculating a product sum with the first coefficient sequence; and a first product-sum operation means for receiving n signals and calculating a product sum with the second coefficient sequence. Two product-sum operation means, transposing means for receiving 2n × 2n signals arranged in the horizontal and vertical directions, performing predetermined rearrangement and outputting, and control means for controlling the means, The control means sequentially supplies 2n × 2n input signals to the sum-difference calculation means as a first encoding process, calculates a sum of symmetric elements of the input signal and a component of the difference, The components are sequentially supplied to the first product-sum operation means, and the difference component is supplied to the second product-sum operation means. Sequentially supplied to the sum calculating means, the calculation results of the first and second product-sum calculating means are supplied to the transposing means, the output of the transposing means is sequentially supplied to the sum-difference calculating means, and the transposing means Calculating the sum and difference components of the output symmetric elements, sequentially supplying the sum components to the first product-sum operation means, and sequentially supplying the difference components to the second product-sum operation means; The control means outputs the calculation results of the first and second product-sum calculation means, and the control means outputs 2n × 2n input signals to the sum-difference calculation means as a second encoding process. Sequentially supplying, calculating the sum and difference components of the symmetric elements of the input signal, sequentially supplying the sum components to the first product-sum operation means, and supplying the difference components to the second product-sum operation Sequentially supplied to the means, and the transposition means outputs the calculation results of the first and second product-sum calculation means. Supply, sequentially supplying the output of the transposing means to the sum-difference calculating means, calculating the sum and difference components of adjacent rows of the output of the transposing means, and calculating the sum of the components as the first product-sum calculating means Are sequentially supplied to the first product-sum operation means, and outputs the operation result of the first product-sum operation means, and the control means includes: As a first decoding process, 2n × 2n input signals are separated into two n × 2n signal sequences, and one of the two n × 2n signal sequences is converted into the first product-sum operation means. Are sequentially supplied to the other of the two n × 2n signal sequences to the second product-sum operation means, and the operation results of the first and second product-sum operation means are calculated. Are sequentially supplied to the means, the calculation result of the sum-difference calculating means is supplied to the transposing means, and two outputs of the transposing means are provided. Are divided into n × 2n signal sequences, one of the two n × 2n signal sequences is sequentially supplied to the first product-sum operation means, and the other of the two n × 2n signal sequences is Are sequentially supplied to the second product-sum operation means, the operation results of the first and second product-sum operation means are sequentially supplied to the sum-difference operation means, and the operation result of the sum-difference operation means is output. And the control means separates 2n × 2n input signals into two n × 2n signal sequences as a second decoding process, and the two n × 2n signal sequences Is sequentially supplied to the first product-sum operation means, the other of the two n × 2n signal sequences is successively supplied to the first product-sum operation means, and the first product-sum operation means is supplied. The calculation result of the calculation means is sequentially supplied to the sum difference calculation means, the calculation result of the sum difference calculation means is supplied to the transposition means, and the transposition means The output of the means is separated into two n × 2n signal sequences, one of the two n × 2n signal sequences is sequentially supplied to the first product-sum operation means, and the two n × 2n signals are supplied. Are sequentially supplied to the second product-sum operation means, and the operation results of the first and second product-sum operation means are sequentially supplied to the sum-difference operation means. Control is performed to output the calculation result.
According to another aspect of the orthogonal transform apparatus of the present invention, the second product-sum operation means further includes weighting means for receiving n signals and multiplying by a predetermined coefficient.
According to another aspect of the orthogonal transform apparatus of the present invention, the first product-sum operation unit further includes a weighting unit that receives n signals and multiplies a predetermined coefficient.
[0011]
[Action]
According to the present invention, constituent circuits can be shared in DCT and IDCT processing, and the circuit scale of the apparatus can be greatly reduced.
[0012]
【Example】
FIG. 1 is a block diagram showing an embodiment of an orthogonal transform apparatus according to the present invention, and shows an example in the case of performing two-dimensional DCT on an input signal composed of vertical and horizontal 8 × 8 pixels.
FIG. 2 is a flowchart showing a DCT processing process according to this embodiment.
1 and 2, this apparatus has an input terminal 1, an output terminal 2, and circuits 3 to 8 for performing various processes such as sum-and-difference operation, product-sum operation, weighting, transposition, and motion detection, which are connected by a bus 10. It is configured. The bus control circuit 9 controls the flow of data on the bus 10 and exchanges control signals with the circuits 3 to 8 to control the switching of the operation state, so that processing is performed according to the flowchart shown in FIG. It is made to do.
[0013]
A signal for one line (eight pixels) is taken from the input terminal 1 and supplied to the sum-difference arithmetic circuit 3 via the bus 10. FIG. 3 shows one embodiment of the sum-difference calculation circuit 3. In FIG. 3, the sum between symmetrical elements of the signals supplied to the terminals 301 to 308 via the bus 10 is output from the adders 317 to 320 to the terminals 309 to 312. Further, the difference between the symmetric elements is output from the subtracters 321 to 324 to the terminals 313 to 316. The addition signal sequence output to the terminals 309 to 312 by the sum / difference arithmetic circuit 3 is supplied to the product / sum arithmetic circuit 4 by the bus control circuit 9. Similarly, the subtraction signal sequence output to the terminals 313 to 316 by the sum-difference arithmetic circuit 3 is supplied to the product-sum arithmetic circuit 5 by the bus control circuit 9.
[0014]
One embodiment of the product-sum operation circuit 4 is shown in FIG. In this embodiment, a set of four-point butterfly computing units 401 including adders 410 to 413, coefficient units 414 to 419, switching units sw1 to sw8, an adder 420, and delay circuits 421 to 424 are configured as shown in the figure. The product-sum operation circuit 4 is compatible with both DCT and IDCT processing. In FIG. 4, coefficient units 414 to 419 multiply the numbers shown in each circuit. The dotted line represents the sign inversion. The product-sum operation circuit 4 processes the signals supplied to the terminals 402 to 405 in two cycles and outputs them to the terminals 406 to 409. FIG. 5 shows the states of the switchers sw1 to sw8 in each cycle when the circuit 4 performs DCT and IDCT processing.
[0015]
On the other hand, one embodiment of the product-sum operation circuit 5 is shown in FIG. In FIG. 6, the product-sum operation circuit 5 serially supplies the subtraction signal sequence supplied to the terminal 601 to the coefficient units 602 to 605 over four cycles. The coefficient units 602 to 605 multiply the supplied signals by predetermined coefficients k1 to k4, and the multiplication results and the signals obtained by inverting the signs of the multiplication results as indicated by dotted lines are supplied to the switching unit 606. The switch 606 switches the supplied signal in each cycle and supplies it to the integrating circuits 607 to 610. FIG. 7 shows the state of the switch 606 in each cycle. In the switch 606, the state of each cycle is exactly the same in DCT and IDCT. The integration circuits 607 to 610 integrate the signals supplied over 4 cycles and output them to the terminals 611 to 614.
[0016]
Signals output to the terminals 611 to 614 are supplied to the weighting circuit 6. FIG. 8 shows one embodiment of the weighting circuit 6. In FIG. 8, the weighting circuit 6 multiplies the signals supplied to the terminals 801 to 804 by predetermined coefficients and outputs the result to the terminals 805 to 808. In FIG. 8, reference numerals 809 to 816 denote coefficient multipliers that multiply the coefficients w1, iw1 to w4, and iw4, respectively. Reference numerals 817 to 820 denote switching units. The switches 817 to 820 select the a side in the DCT process, and select the b side in the IDCT process.
[0017]
Next, the outputs of the product-sum operation circuit 4 and the weighting circuit 6 are supplied to the transposition circuit 7. At this time, the bus control circuit 9 rearranges the signal sequence from the product-sum operation circuit 4 and the signal sequence from the weighting circuit 6 alternately as shown in FIG. The transposition circuit 7 transposes after holding the above processing results for the input signals for 8 lines (64 signals).
[0018]
Next, the motion detection circuit 8 detects motion information in the input signal from the signal stored in the transposition circuit 7. FIG. 10 shows one example of the motion detection circuit 8. In FIG. 10, the motion detection circuit 8 is supplied with a DC component sequence from the transposition circuit 7. The DC component row is composed of DC components of each line. The motion detection circuit 8 divides the DC component sequence supplied to the terminals 1001 to 1008 into an odd line sequence and an even line sequence, obtains the sum of each by the adders 1012 to 1017, and subtracts the difference between the sums. The absolute value is calculated by the absolute value unit 1018 and supplied to the detector 1010. The detector 1010 compares the supplied value with a constant 256, and outputs a motion information signal indicating no motion when it is smaller than 256 to the terminal 1011 when it is greater than 256.
[0019]
The motion information signal is output from the output terminal 2 of FIG. 1 and supplied to the bus control circuit 9 to determine the subsequent processing method. Note that the motion information signal may be supplied from the outside without providing the motion detection circuit 8. When there is no movement, the bus control circuit 9 gives the same processing as the signal sequence from the input terminal 1 of FIG. 1 to each of the 8 signals supplied from the transposition circuit 7. That is, it is processed in the flow from the branch block 200 of FIG. 2 to the sum calculation circuit 3 via the branch path 201 side, and is sequentially output from the output terminal 2. Further, when there is a motion, it is processed in the flow from the branch block 200 of FIG. 2 to the sum calculation circuit 3 via the branch path 202 side. In this case, the bus control circuit 9 rearranges the 8 signals output from the transposition circuit 7 as shown in FIG.
[0020]
When there is no motion, the addition signal sequence output from the sum-and-difference calculation circuit 3 is supplied to the product-sum calculation circuit 4, and the same processing as described above is performed in two cycles as well as the product-sum calculation circuit 5 and weighting. The same processing is performed by the circuit 6, and each processing result is output from the output terminal 2. When there is a motion, the subtraction signal sequence output by the sum-difference calculation circuit 3 is supplied to the product-sum calculation circuit 4 in the same manner as the addition signal sequence. When the product-sum operation circuit 4 is configured as in the embodiment of FIG. 4, since the processing time is short, the product-sum operation circuit 5 and the weighting circuit can be obtained even if the processing for each of the addition signal sequence and the subtraction signal sequence is sequentially performed in series. It is possible to process within a time within the sum of the six processing times. The subtraction signal sequence processed by the product-sum operation circuit 4 is output from the output terminal 2.
[0021]
FIG. 11 is a flowchart showing an IDCT process according to the embodiment of FIG. In FIG. 1 and FIG. 11, a motion information signal is supplied to the input terminal 1 prior to the DCT coefficient sequence. When the motion information signal indicates no motion, the bus control circuit 9 subsequently converts the DCT coefficient sequence supplied by 8 from the input terminal 1 into 4 signals of odd number and even number through the branch block 1101. The odd number signal sequence is supplied to the product-sum operation circuit 4 and the even number signal sequence is supplied to the weighting circuit 6. The weighting circuit 6 multiplies the supplied signal by a predetermined coefficient at the time of IDCT. In the embodiment of the weighting circuit 6 of FIG. 8, at this time, the switches 817 to 820 are selected to the b side. The calculation result of the weighting circuit 6 is supplied to the product-sum calculation circuit 5. When the product-sum operation circuit 4 is configured as in the embodiment of FIG. 4, the switchers sw1 to sw8 are selected according to FIG. 5, and processing is performed in two cycles. When the product-sum operation circuit 5 is configured as in the embodiment of FIG. 6, the switch 606 is selected according to FIG. 7, and processing is performed in four cycles.
[0022]
The processing results of the product-sum operation circuit 4 and the product-sum operation circuit 5 are supplied to the sum-difference operation circuit 3 via the bus. At this time, the bus control circuit 9 rearranges the signals as shown in FIG. 9C and supplies them to the sum / difference calculation circuit 3 from the output terminals 301 to 308. The sum / difference calculation circuit 3 symmetrically adds and subtracts the supplied signal as in the embodiment of FIG. 3 and the result is supplied to the transposition circuit 7.
[0023]
On the other hand, if the motion information signal indicates that there is motion, the bus control circuit 9 subsequently sends four signals, each of which is supplied to the input terminal 1, four by four through the branch block 1101. And sequentially supplied to the product-sum operation circuit 4. The first half signal sequence and the second half signal sequence processed by the product-sum operation circuit 4 are rearranged as shown in FIG. 9C by the bus control circuit 9 and supplied to the sum-difference operation circuit 3.
[0024]
The sum-difference calculation circuit 3 adds and subtracts the supplied signals symmetrically as in the embodiment of FIG. The bus control circuit 9 rearranges the outputs of the sum-difference calculation circuit 3 as shown in FIG. 9D and supplies it to the transposition circuit 7. The subsequent processing is the same regardless of the motion information signal. The transposition circuit holds 64 signals in the buffer and then transposes and outputs eight signals at a time. The eight signals are processed in the same manner as the DCT coefficient sequence in the case of no motion shown in FIG.
[0025]
In this embodiment, the processing steps of FIGS. 2 and 11 share the configurations of the sum-and-difference operation circuit 3, the product-sum operation circuit 4, the product-sum operation circuit 5, the weighting circuit 6 and the transposition circuit 7 in FIG. Yes. That is, the circuits 3 to 8 in FIG. 1 are shared with the circuits 3 to 8 in FIGS.
[0026]
【The invention's effect】
As described above, according to the present invention, a configuration circuit is shared in DCT and IDCT processing with or without weighting using an algorithm designed to improve high speed and high efficiency. As a result, the circuit scale of the apparatus can be greatly reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
2 is a DCT flow diagram for the apparatus of FIG.
FIG. 3 is a block diagram showing an embodiment of a sum / difference calculation circuit 3 in the apparatus of FIG. 1;
4 is a block diagram showing an embodiment of a product-sum operation circuit 4 in the apparatus of FIG. 1. FIG.
FIG. 5 is a configuration diagram showing a state for each cycle of the switching device of FIG. 4;
6 is a block diagram showing an embodiment of a product-sum operation circuit 5 in the apparatus of FIG. 1. FIG.
7 is a block diagram showing the state of each switch in FIG. 6 for each cycle.
8 is a block diagram showing an embodiment of a weighting circuit 6 in the apparatus of FIG.
9 is a configuration diagram showing a signal rearrangement order of the bus control circuit 9 in the apparatus of FIG. 1;
10 is a block diagram showing an embodiment of a motion detection circuit 8 in the apparatus of FIG. 1. FIG.
FIG. 11 is a flowchart of IDCT by the apparatus of FIG. 1;
FIG. 12 is a block diagram showing a conventional example.
FIG. 13 is a block diagram showing a conventional example using a high-speed algorithm.
FIG. 14 is a block diagram showing a conventional example of weighting.
FIG. 15 is a block diagram showing a conventional example corresponding to motion information.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Input terminal 2 Output terminal 3 Sum-difference arithmetic circuit 4 Multiply-sum arithmetic circuit 5 Multiply-sum arithmetic circuit 6 Weighting circuit 7 Transposition circuit 8 Motion detection circuit 9 Bus control circuit 10 Bus

Claims

Sum-difference calculating means for receiving two signal sequences each consisting of n (n ≧ 1) signals and calculating the sum and difference between the two signal sequences;
first product-sum operation means for receiving n signals and calculating a product-sum with the first coefficient sequence;
second product-sum operation means for receiving n signals and calculating a product sum with the second coefficient sequence;
Transposing means for receiving 2n × 2n signals arranged in the horizontal and vertical directions, performing a predetermined rearrangement, and outputting;
Control means for controlling each means,
The control means, as the first encoding process,
2n × 2n input signals are sequentially supplied to the sum / difference calculating means,
Calculating the sum and difference components of the symmetric elements of the input signal;
Sequentially supplying the sum component to the first product-sum operation means;
Sequentially supplying the difference component to the second product-sum operation means;
Supplying operation results of the first and second product-sum operation means to the transposition means;
Sequentially supplying the output of the transposing means to the sum-difference calculating means;
Calculating the sum and difference components of the symmetrical elements of the output of the transposing means;
Sequentially supplying the sum component to the first product-sum operation means;
Sequentially supplying the difference component to the second product-sum operation means;
Perform control to output the calculation results of the first and second product-sum calculation means,
And the said control means is as a 2nd encoding process,
2n × 2n input signals are sequentially supplied to the sum / difference calculating means,
Calculating the sum and difference components of the symmetric elements of the input signal;
Sequentially supplying the sum component to the first product-sum operation means;
Sequentially supplying the difference component to the second product-sum operation means;
Supplying operation results of the first and second product-sum operation means to the transposition means;
Sequentially supplying the output of the transposing means to the sum-difference calculating means;
Calculating the sum and difference components of adjacent rows of the output of the transposing means;
Sequentially supplying the sum component to the first product-sum operation means;
Subsequently, the difference component is successively supplied to the first product-sum operation means,
An orthogonal transformation device that performs control to output a calculation result of the first product-sum calculation means.

Sum-difference calculating means for receiving two signal sequences each consisting of n (n ≧ 1) signals and calculating the sum and difference between the two signal sequences;
first product-sum operation means for receiving n signals and calculating a product-sum with the first coefficient sequence;
second product-sum operation means for receiving n signals and calculating a product sum with the second coefficient sequence;
Transposing means for receiving 2n × 2n signals arranged in the horizontal and vertical directions, performing a predetermined rearrangement, and outputting;
Control means for controlling each means,
The control means, as the first decoding process,
2n × 2n input signals are separated into two n × 2n signal sequences,
One of the two n × 2n signal sequences is sequentially supplied to the first product-sum operation means;
Sequentially supplying the other of the two n × 2n signal sequences to the second product-sum operation means;
The operation results of the first and second product-sum operation means are sequentially supplied to the sum-difference operation means,
Supplying the result of the calculation of the sum-difference calculating means to the transposing means;
Separating the output of the transposing means into two n × 2n signal sequences;
One of the two n × 2n signal sequences is sequentially supplied to the first product-sum operation means;
Sequentially supplying the other of the two n × 2n signal sequences to the second product-sum operation means;
The operation results of the first and second product-sum operation means are sequentially supplied to the sum-difference operation means,
Control to output the calculation result of the sum-difference calculation means,
And the said control means is as a 2nd decoding process,
2n × 2n input signals are separated into two n × 2n signal sequences,
One of the two n × 2n signal sequences is sequentially supplied to the first product-sum operation means;
The other of the two n × 2n signal sequences is successively supplied to the first product-sum operation means,
The operation results of the first product-sum operation means are sequentially supplied to the sum-difference operation means,
Supplying the result of the calculation of the sum-difference calculating means to the transposing means;
Separating the output of the transposing means into two n × 2n signal sequences;
One of the two n × 2n signal sequences is sequentially supplied to the first product-sum operation means;
Sequentially supplying the other of the two n × 2n signal sequences to the second product-sum operation means;
The operation results of the first and second product-sum operation means are sequentially supplied to the sum-difference operation means,
An orthogonal transformation device characterized by performing control to output a calculation result of the sum-difference calculation means.

Sum-difference calculating means for receiving two signal sequences each consisting of n (n ≧ 1) signals and calculating the sum and difference between the two signal sequences;
first product-sum operation means for receiving n signals and calculating a product-sum with the first coefficient sequence;
second product-sum operation means for receiving n signals and calculating a product sum with the second coefficient sequence;
Transposing means for receiving 2n × 2n signals arranged in the horizontal and vertical directions, performing a predetermined rearrangement, and outputting;
Control means for controlling each means,
The control means, as the first encoding process,
2n × 2n input signals are sequentially supplied to the sum / difference calculating means,
Calculating the sum and difference components of the symmetric elements of the input signal;
Sequentially supplying the sum component to the first product-sum operation means;
Sequentially supplying the difference component to the second product-sum operation means;
Supplying operation results of the first and second product-sum operation means to the transposition means;
Sequentially supplying the output of the transposing means to the sum-difference calculating means;
Calculating the sum and difference components of the symmetrical elements of the output of the transposing means;
Sequentially supplying the sum component to the first product-sum operation means;
Sequentially supplying the difference component to the second product-sum operation means;
Perform control to output the calculation results of the first and second product-sum calculation means,
And the said control means is as a 2nd encoding process,
2n × 2n input signals are sequentially supplied to the sum / difference calculating means,
Calculating the sum and difference components of the symmetric elements of the input signal;
Sequentially supplying the sum component to the first product-sum operation means;
Sequentially supplying the difference component to the second product-sum operation means;
Supplying operation results of the first and second product-sum operation means to the transposition means;
Sequentially supplying the output of the transposing means to the sum-difference calculating means;
Calculating the sum and difference components of adjacent rows of the output of the transposing means;
Sequentially supplying the sum component to the first product-sum operation means;
Subsequently, the difference component is successively supplied to the first product-sum operation means,
Control to output the operation result of the first product-sum operation means,
And the said control means is as a 1st decoding process,
2n × 2n input signals are separated into two n × 2n signal sequences,
One of the two n × 2n signal sequences is sequentially supplied to the first product-sum operation means;
Sequentially supplying the other of the two n × 2n signal sequences to the second product-sum operation means;
The operation results of the first and second product-sum operation means are sequentially supplied to the sum-difference operation means,
Supplying the result of the calculation of the sum-difference calculating means to the transposing means;
Separating the output of the transposing means into two n × 2n signal sequences;
One of the two n × 2n signal sequences is sequentially supplied to the first product-sum operation means;
Sequentially supplying the other of the two n × 2n signal sequences to the second product-sum operation means;
The operation results of the first and second product-sum operation means are sequentially supplied to the sum-difference operation means,
Control to output the calculation result of the sum-difference calculation means,
And the said control means is as a 2nd decoding process,
2n × 2n input signals are separated into two n × 2n signal sequences,
One of the two n × 2n signal sequences is sequentially supplied to the first product-sum operation means;
The other of the two n × 2n signal sequences is successively supplied to the first product-sum operation means,
The operation results of the first product-sum operation means are sequentially supplied to the sum-difference operation means,
Supplying the result of the calculation of the sum-difference calculating means to the transposing means;
Separating the output of the transposing means into two n × 2n signal sequences;
One of the two n × 2n signal sequences is sequentially supplied to the first product-sum operation means;
Sequentially supplying the other of the two n × 2n signal sequences to the second product-sum operation means;
The operation results of the first and second product-sum operation means are sequentially supplied to the sum-difference operation means,
An orthogonal transformation device characterized by performing control to output a calculation result of the sum-difference calculation means.

The orthogonal transform device according to any one of claims 1 to 3, wherein the second product-sum operation means includes weighting means for receiving n signals and multiplying by a predetermined coefficient.

5. The orthogonal transform device according to claim 1, wherein the first product-sum operation unit includes a weighting unit that receives n signals and multiplies a predetermined coefficient.