JP3673165B2 - Digital transmission system, encoding device, decoding device, and data processing method in the digital transmission system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital transmission system, an encoding device, a decoding device, and a data processing method in the digital transmission system, and more particularly to a configuration and a method related to a technique for improving error correction.
[0002]
[Prior art]
The turbo code has been attracting attention because of its high coding gain since it was announced in 1993, and its application to channel coding for next-generation mobile communication systems and the like has been determined.
[0003]
For an overview of turbo codes, see “Near Optimum Error Correcting Coding And Decoding: Turbo-Codes (Claude Berrou, IEEE TRANSACTIONS ON COMMUNICATIONS, VOL.44 NO.10, October 1996, pp1261-1271)” Signposts to: "parallel concatenated (Turbo) coding", "Turbo (iterative) decoding" and its surroundings (by Motohiko Isaka and Hideki Imai, IT98-51 (1998-12)).
[0004]
Below, the points of the turbo code are listed briefly. (A) A plurality of encoders having the same configuration are connected in parallel or in series. (B) For the data rate input to each encoder, an interleaver is used so as to eliminate correlation. At this time, it is desirable to use an interleaver with high randomness. (C) On the decoding side, soft decision output is performed on the likelihood information from the soft decision input. (D) Soft decision likelihood information is newly updated on the decoding side. By using it as a simple input, iterative decoding is performed.
[0005]
The principle of the turbo code will be described with reference to FIGS. In the following, the coding rate is 1/3 and the constraint length K = 3 in a general configuration in which encoders are connected in parallel.
[0006]
A conventional turbo encoder 900 includes an interleaver 120, an encoder (RSC1) 100, and an encoder (RSC2) 110, as shown in FIG.
[0007]
The interleaver 120 rearranges the input data string X to create a data string X ′ having the same elements as the input data string X and having a different order.
[0008]
Encoders 100 and 110 are identical in configuration and perform recursive convolution. The encoder RSC (100 and 110) includes a shift register composed of two registers D and modulo-2 adders A1 and A2, as shown in FIG.
[0009]
The internal state (b1, b2) in this encoder is represented by the value of the shift register. The internal states (b1, b2) can take four states: an internal state (00), an internal state (01), an internal state (10), and an internal state (11). Note that there are always two internal states that can transition when an input is given.
[0010]
The transition states in the encoder RSC (100 and 110) are shown in FIG. In the case of the internal state (00), when the input is “0”, the state transitions to the internal state (00) and the code output is “0”. When the input is “1”, the state transitions to the internal state (10) and the code output is “1”.
[0011]
In the case of the internal state (01), when the input is “0”, the state transitions to the internal state (10) and the code output is “0”, and when the input is “1”, the state transitions to the internal state (00) and the code output is “ 1 ".
[0012]
In the case of the internal state (10), when the input is “0”, the state transitions to the internal state (11) and the code output is “1”, and when the input is “1”, the state transitions to the internal state (01) and the code output is It becomes “0”.
[0013]
In the case of the internal state (11), when the input is “0”, the transition is made to the internal state (01) and the code output is “1”, and when the input is “1”, the transition is made to the internal state (11) and the code output. Becomes “0”.
[0014]
Let Y be the data string after encoding by the encoder 100 for the input data string X. Further, a data string after encoding by the encoder 110 that receives the input data string X ′ after interleaving by the interleaver 120 is Y ′.
[0015]
Therefore, the conventional turbo encoder 900 generates the first code string Y and the second code string Y ′ based on the input data string X. The turbo encoder 900 arranges and outputs the data strings X, Y, and Y ′.
[0016]
If the input data string X is {0, 1, 1, 0, 0, 0, 1} and the interleaved data string X ′ is {0, 0, 1, 0, 1, 0, 1}, the code result The data string Y is {0, 1, 0, 0, 1, 1, 1}, and the data string Y ′ is {0, 0, 1, 1, 0, 1, 1}.
[0017]
Here, internal state transition diagrams inside the encoder are shown in FIGS. 15 and 16. FIG. 15 corresponds to an internal state transition diagram relating to the data string Y, and FIG. 16 corresponds to an internal state transition diagram relating to the data string Y ′. In FIG. 15 and FIG. 16, the bold line represents the state transition.
[0018]
Next, a basic configuration of the turbo decoder will be described with reference to FIG. Blocks 600, 610, 620 and 630 written as “Iteration k” (k = 1, 2,..., N) are one unit of decoding. The circuits 600, 610, 620, and 630 are connected to each other, which indicates that the processing is repeatedly performed.
[0019]
FIG. 18 shows processing in a decoding unit block, that is, each circuit (Iteration). The decoding unit block includes soft decision decoders 10 and 11, interleavers 20 and 21, a restoration interleaver 22, and a decoding calculation unit 30.
[0020]
The soft decision decoder 10 and the soft decision decoder 11 are decoders that output a soft decision output based on a soft decision input. Interleavers 20 and 21 perform the same operation as the interleaver used on the encoder side. The restoration interleaver 22 restores the data string rearranged by the interleaver to the original data string. The decoding calculation unit 30 generates data after error correction.
[0021]
The signals input to the decoding unit block are the reception sequence {X, Y, Y ′} and signal likelihood information E. Among these, {X, Y, E} is one set, and error correction processing of the first soft decision soft output is performed. Thereby, an error correction process corresponding to the encoding in the encoder 100 is performed, and as a result, new likelihood information E1 of each signal is created.
[0022]
Next, the following soft decision soft output error correction processing is performed with a combination of {X, Y ', E1}. Since data rearrangement is performed by the interleaver 120 before convolution in the encoder 110, the data is rearranged by the interleaver 20 for the likelihood information E1, and the interleaver 21 for the data string X. Sort data in. As a result, a new data string {X ′, E1 ′} is generated. Soft decision soft output error correction processing is performed by a combination of {X ′, Y ′, E1 ′}.
[0023]
As a result, error correction processing corresponding to encoding in the encoder 110 is performed, and as a result, new likelihood information E2 of each signal is generated.
[0024]
Here, since the data string {X ′, E1 ′} necessary for the encoder 110 is rearranged by the interleaver 20 and the interleaver 21, the likelihood information E2 is rearranged by the restoration interleaver 22. Performed likelihood information E2 ′.
[0025]
The likelihood information E2 ′ is used as likelihood information when the process is repeatedly performed in the decoding unit block. Further, the decoding calculation unit 30 can obtain the decoding result X ″ at this point.
[0026]
There are various methods for decoding the turbo code, but the logarithm is improved in the calculation efficiency of the SOVA (Soft Output Viterbi Algorithm) or the maximum likelihood judgment method characterized in that the output data is soft-output by the application of Viterbi processing. -MAP (Maximum A Posteriori probability) is the mainstream.
[0027]
An example of error correction characteristics by the turbo code is shown in FIG. In FIG. 19, a plot 700 (no-coding) in the legend indicates a case where no encoding is performed. Plot 710 (IT = 1) is for one iteration, plot 720 (IT = 2) is for two iterations, and plot 730 (IT = 3) is for three iterations. Plot 740 (IT = 4) shows the case of 4 iterations, and plot 750 (IT = 5) shows the case of 5 iterations. A plot 760 (Viterbi) shows a BER characteristic in a 5-bit decision Viterbi (constraint length 9, rate = 1/3).
[0028]
As is apparent from the BER characteristics shown in FIG. 19, according to the turbo code, the error correction capability is improved every time the repetition setting is increased.
[0029]
By the way, in next-generation communication such as W-CDMA (Wideband-CDMA: CDMA = Code Division Multiple Access), it is assumed that the number of information bits dynamically changes in communication.
[0030]
A data flow of the W-CDMA system will be described with reference to FIG. In the W-CDMA system, as shown in FIG. 20, processing 800 (CRC addition processing 801, information data string concatenation processing 802, error correction processing 803, interleaving (1) 804, radio frame division is performed on signal TrCH # 1. Processing 805 and rate matching processing 806) are performed. Other signals (not shown) are also processed 800.
[0031]
These multiple signals are multiplexed in multiplex 810. Then, in physical channel division processing 811, the channel is divided into a plurality of channels. After the division, each is interleaved (2) 812 and physical channel mapping 813. Thereby, signals PhCH # 1, PhCH # 2,... Are obtained. In the W-CDMA system, as shown in FIG. 20, a large number of logical channels are multiplexed on the same radio channel.
[0032]
The communication state is changed by dynamically setting information bits. If the total number of information bits is small, the communication rate can be lowered depending on the conditions. This method is called rate matching in the WCDMA system. In rate matching, there are a case where information bits are increased (Repetition) and a case where information bits are decreased (Puncturing), and these are applied depending on the situation.
[0033]
FIG. 21 shows a configuration example of an encoding apparatus corresponding to puncturing rate matching. As shown in FIG. 21, the encoding device 910 includes an input interface unit (I / F) 160, encoders (RCS1, RCS2) 100, 110, an interleaver (fixed) 120, puncture units 130 and 140, and a multiplexing unit. A processing unit (MUX) 150 is included.
[0034]
In addition to the basic configuration of turbo encoder 900, encoding apparatus 910 includes puncturing units 130 and 140 that perform puncturing on data strings Y and Y ′ that are post-coding data.
[0035]
Puncturing sections 130 and 140 create data strings YB and YB ′ as new code word sequences for data strings Y and Y ′ that are post-coding data. In the multiplexing processing unit 150, the data strings X, YB, and YB ′ are multiplexed to form an output series.
[0036]
Japanese Patent Laid-Open No. 2000-68862 (“Error Correction Encoding Device”) shows another configuration example of a turbo code configuration example corresponding to puncturing rate matching. As shown in FIG. 22, the encoding device 920 described in the document includes an input I / F unit 160, a data adding unit 165 for adding data to a data string, an interleaver (fixed) 120, an encoder (RSC1 , RSC2) 100 and 110, and a multiplexing processing unit 150.
[0037]
The communication means used in the transmission side system including such a turbo encoder is performed according to the procedure shown in FIG. Unlike the above procedure, the rate matching process 806 is performed after the information data string concatenation process 802 and before the error correction process 803.
[0038]
[Problems to be solved by the invention]
As described above, in the next generation communication such as the W-CDMA system, it is desired that the information bits processed by the turbo code dynamically change.
[0039]
When the number of information bits changes, it is necessary to change the internal interleaver configuration of the turbo code according to the number of information bits. In general, the interleaver is a complicated process to ensure randomness.
[0040]
The calculation method of the interleaver for turbo codes is described in, for example, 3GPP TS25.212 (V3.0.0, 1999-10, pp17-18). By definition, a considerable number of combinations are possible.
[0041]
In actual communication, it is not necessary to deal with all the number of bits within a possible range, but even in such a case, it is necessary to set the number of information bits of the turbo code within a range of several tens to several hundreds.
[0042]
The channel coating process must be performed in real time, and it is inefficient to perform this calculation every time the number of information bits changes. As a means for solving this, there is a method of storing pre-calculated data as table data, but it is difficult to realize it depending on the required amount of memory.
[0043]
Further, as the intermediate solution, there is a method in which halfway data is stored as table data and the subsequent calculation is performed. However, it cannot be a solution that can solve all the problems of the processing amount and the memory amount.
[0044]
This situation is an unavoidable problem except when dealing with a limited data length, and can also occur for the above-described FIGS. 22 and 23 and other configurations.
[0045]
Therefore, the present invention has been made to solve such a problem, and the object thereof is to realize a correction process that can correspond to the number of information bits processed by a dynamically changing turbo code. The present invention relates to a digital transmission system, an encoding device, a decoding device, and a data processing method in the system.
[0046]
[Means for Solving the Problems]
A digital transmission system according to an aspect of the present invention includes: Using an input interface unit to which a data sequence of variable bit length is input as an input sequence, a data conversion circuit for converting the input sequence input to the input interface unit into a data sequence of a predetermined number of bits, and a turbo code The first and second encoders for encoding the data string converted by the data conversion circuit and the first and second encoders are provided corresponding to the first and second encoders, respectively, and receive the respective outputs to perform puncturing. The first and second puncture units, the data sequences processed by the first and second puncture units, and the input sequence are received, and the output sequence is output as transmission data by bit mapping executed in a predetermined procedure. Order of data strings provided between the multiplexing processing unit, the data conversion circuit, and the second encoder and converted by the data conversion circuit A transmission system including a fixed-length interleaver that executes interleaving processing to be changed and outputs to the second encoder so that the data conversion circuit becomes a fixed-length data string that is interleaved by the interleaver. Convert input series to The The digital transmission system further includes a first data creation circuit that creates a data sequence for decoding based on the output of the transmission system, and a decoder that executes a decoding process corresponding to encoding based on the created data sequence. And a receiving system including a second data generation circuit that receives a decoder output and generates a desired data string.
[0047]
Preferably, the transmission system further includes a selection circuit that selects a predetermined number of bits among the plurality of bit number candidates.
[0048]
In particular, the data conversion circuit includes a circuit that inserts predetermined data (“0”, “1”, or a combination thereof) into a specific portion of the data string. On the other hand, the second data creation circuit deletes data at a specific location.
[0049]
In particular, First and second puncture units Is First and second Encoder Respectively Among the data to be output, a circuit for deleting data at a specific location is included. The first data creation circuit replaces the data at the specific location to be deleted with information for regarding that there is no received data.
[0050]
An encoding device according to a further aspect of the present invention provides: Using an input interface unit to which a variable bit length data sequence is input as an input sequence, a data conversion circuit for converting the input sequence input to the input interface unit into a data sequence having a predetermined number of bits, and a turbo code The first and second encoders for encoding the data string converted by the data conversion circuit and the first and second encoders are provided corresponding to the first and second encoders, respectively, and receive the respective outputs to perform puncturing. The first and second puncture units, the data sequences processed by the first and second puncture units, and the input sequence are received, and the output sequence is output as transmission data by bit mapping executed in a predetermined procedure. Order of data strings provided between the multiplexing processing unit, the data conversion circuit, and the second encoder and converted by the data conversion circuit A transmission system including a fixed-length interleaver that executes interleaving processing to be changed and outputs to the second encoder so that the data conversion circuit becomes a fixed-length data string that is interleaved by the interleaver. Convert input series to The Preferably, the encoding device includes a plurality of bit number candidates. , And a selection circuit for selecting a predetermined number of bits.
[0051]
A decoding apparatus according to a further aspect of the present invention corresponds to the above encoding apparatus, and includes a first data generation circuit for generating a data string for decoding an output sequence, and a code based on the generated data string. And a second data creation circuit for creating a desired data string in response to the output of the decoder.
[0052]
A data processing method in a digital transmission system according to a further aspect of the present invention includes: An input step in which a variable bit length data sequence is input as an input sequence, a data conversion step in which the input sequence is converted into a data sequence having a predetermined number of bits, and an interleave that changes the order of the converted data sequence An interleaving step for performing processing, an encoding step for encoding a data sequence converted using a turbo code, a puncturing step for executing puncturing on the encoded data sequence, and a puncturing process A transmission data creation step for receiving the data sequence and the input sequence, and outputting the output sequence as transmission data by bit mapping executed in a predetermined procedure, wherein the data conversion step is a fixed-length data that is interleaved. Convert input series to be a data string The The data processing method further includes a decoded data generation step for generating a data string for decoding transmission data, a decoding step for executing a decoding process corresponding to encoding based on the generated data string, and a result of the decoding process And an output data creation step of creating a desired data string.
[0053]
As described above, the digital transmission system according to the present invention is provided with means for adjusting the data length before the turbo code. Also, means for adjusting the data length is provided after the turbo code. A data string having an assumed data length is provided for the data string subjected to error correction processing. That is, although the data length subject to error correction changes dynamically, it becomes possible to guarantee the channel coding / combining processing by limiting the processing data length in the turbo code in advance.
[0054]
DETAILED DESCRIPTION OF THE INVENTION
A digital transmission system according to an embodiment of the present invention and processing contents thereof will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same symbols or symbols, and the description thereof is omitted.
[0055]
A transmission-side system constituting the digital broadcasting system according to the embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1, the transmission side system according to the embodiment of the present invention includes an input I / F (interface) unit 160, a data addition unit 170, an interleaver (fixed) 120, an encoder (RSC1, RSC2) 100, and 110, first and second puncturing units 130 and 140, and an encoding apparatus 1000 including a multiplexing processing unit (MUX) 150.
[0056]
Information bits input to the turbo encoder are stored in the input I / F unit 160 as an input sequence. The information bit string X is transferred to the multiplexing processing unit 150 as it is.
[0057]
On the other hand, for the convolution process, the data adding unit 170 adds data to the information bit string X. As a result, a data string XA having a predetermined number of bits is created.
[0058]
The data string XA output from the data adding unit 170 is supplied to the encoder 100 and the interleaver 120.
[0059]
Data sequence XA that is not interleaved is encoded by encoder 100. In addition, the interleaver 120 performs a fixed-length interleaving process on the data string XA. The data string XA ′ created by the interleaver 120 is supplied to the encoder 110.
[0060]
A puncture process (puncture unit 130) is performed on the output data YA of the encoder 100 to create a data string Y that is actually necessary.
[0061]
A puncture process (puncture unit 140) is performed on the output data Y ′ of the encoder 110 to create a data string Y ′ that is actually necessary.
[0062]
The data strings Y and Y ′ are supplied to the multiplexing processing unit 150. The multiplexing processing unit 150 performs bit mapping according to a predetermined procedure to obtain an output series. The data string output from the multiplexing processing unit 150 is transmitted to the receiving system.
[0063]
Next, the configuration of the receiving system included in the digital broadcasting system according to the embodiment of the present invention will be described with reference to FIG. As shown in FIG. 2, the receiving system according to the embodiment of the present invention includes a demultiplexing processing unit (DeMUX) 250, first, second, and third bit filling processing units 200, 210, and 220, an interleaver. The decoding apparatus includes a turbo code decoder 240 including 230 and a data bit selection unit 260.
[0064]
In the demultiplexing processing unit 250, the input sequence that is received data is divided into the data corresponding to X, the data corresponding to Y, and the data corresponding to Y ′ by a predetermined processing procedure.
[0065]
The first bit padding processing unit 200 receives data corresponding to X, the second bit padding processing unit 210 receives data corresponding to Y, and the third bit padding processing unit 220 corresponds to Y ′. Receive data.
[0066]
The bit padding processing units 200, 210, and 220 create data strings XA, YA, and YA ′ necessary for the decoder so that each has the same data length.
[0067]
The turbo code decoder 240 performs a decoding process based on the data strings XA, YA, and YA ′. For the interleaver 230 used for the turbo code decoding process, since the number of input information bits is fixed, the same interleaving process is always performed.
[0068]
Since the decoded sequence XA ′ output from the turbo code decoder 240 includes unnecessary data, the data bit selection unit 260 removes unnecessary data to create a data sequence X ′ that is an output sequence.
[0069]
Next, an extended example of the turbo encoder according to the embodiment of the present invention will be described with reference to FIG. If the data width to be handled is large and the data width is limited to a single fixed information bit, the influence on the error correction characteristics becomes large. Therefore, by providing a processing means for selecting a representative number of bits, the turbo code processing system according to the embodiment of the present invention has flexibility.
[0070]
Therefore, a predetermined number of fixed interleavers are provided, and a switch for determining which interleaver is used is operated by the select control unit 180 from the outside, and the fixed interleaver to be used is determined.
[0071]
Specifically, the circuit shown in FIG. 3 includes a plurality of interleavers (fixed), a plurality of switches (SW), and a select control unit 180 in addition to the circuit shown in FIG. In the figure, as typical examples, interleavers (fixed) 121, 122, 123, a switch 190, and a switch 191 are described.
[0072]
The switch 191 selects an interleaver that performs interleaving processing on the data string XA, and the output of the interleaver selected by the switch 190 is supplied to the encoder 110. Furthermore, the condition of data to be added in the data adding unit 170 is determined by the select control unit 180.
[0073]
On the decoding processing side, a plurality of interleavers corresponding to the turbo encoder are arranged instead of the above-described interleaver 230, and one fixed interleaver to be used is selected according to the selection by the selection control unit 180. Configure.
[0074]
Next, a specific example of the data addition configuration in the data addition unit 170 will be described with reference to FIG. In FIG. 4, data D1 shown on the upper side represents an information bit, and data D2 shown on the lower side represents a data series after adding additional information. The information bit D1 has a variable number of bits, and the data series D2 after data addition has a fixed number of bits.
[0075]
In the figure, the shaded area corresponds to additional data. FIG. 4 shows an example in which additional information (“11... 11”) is added to the end of the information bits (“010110...”).
[0076]
In turbo processing, since information bits are randomly interleaved, it is possible to simply add data to the end of the data as shown in FIG.
[0077]
As the data to be added, all “1” are assumed in the example shown in FIG. 4, but all “0” or other predetermined patterns can be used.
[0078]
A further example of the data addition configuration is shown in FIG. In FIG. 5, data D1 is an information bit, and data D3 represents a data series after data addition. A hatched area attached to the data D3 is an additional data portion. In FIG. 5, the data insertion position is changed at the time of creating additional data, and “1” is inserted every other bit. Note that the data to be added is not limited to “1” as described above.
[0079]
Next, an example of a data structure in the puncturing unit and the multiplexing processing unit will be described with reference to FIG. In FIG. 6, D4 is a data string X (X series), D5 is a data string Y (Y series), D6 is a data string Y '(Y' series), and D7 is a data string after multiplexing processing. Represents each.
[0080]
As for the X series, the data is handled as it is. Regarding the Y series, the data is thinned out according to a specific rule so as to match the required number of bits in the encoded data. Also in the Y ′ series, data is thinned out according to a specific rule so as to match the required number of bits in the encoded data by the same processing. In the example illustrated in FIG. 6, a portion indicated by “−” is data to be punctured.
[0081]
The multiplexing processing unit 150 maps the data of the X series, the Y series, and the Y ′ series according to a predetermined rule. In this example, a method of alternately arranging data of the X series D4, the Y series D5, and the Y ′ series D6 is employed.
[0082]
Next, data structures in the demultiplexing processing unit 250 and the bit padding processing unit in the receiving system will be described with reference to FIG. In FIG. 7, D8 represents a data string to be demultiplexed, and D9, D10, and D11 are a data string X (X series), a data string Y (Y series), and a data string Y ′ after bit padding processing, respectively. (Y ′ series).
[0083]
The example shown in FIG. 7 corresponds to the bit padding process shown in FIG. 6, and the X series, Y series, Y from the data series D8 arranged alternately in the X series, Y series, and Y ′ series. 'Separate each data series of series.
[0084]
For each of the separated data series, a bit padding process is performed to correspond to the puncturing process in FIG.
[0085]
As for the X series, bit padding is performed by adding a specific data pattern to a predetermined position. That is, the processing corresponds to the data addition configuration shown in FIG. 4 or FIG. This example corresponds to the case of FIG. Specifically, data consisting only of “0” is set at the end of the X-series data.
[0086]
For the Y sequence and the Y ′ sequence, a portion where no data originally exists (“−” in FIG. 6) indicates that there is no information bit, that is, no received data, or “1” and “0”. The calculation proceeds as if there was an intermediate input. By this process, an X series, a Y series, and a Y ′ series having a fixed data length can be created. In the example of FIG. 7, the “−” portion in FIG. 6 is replaced with “0”.
[0087]
If the X sequence, the Y sequence, and the Y ′ sequence are determined, the turbo code decoder can operate and a decoding result can be obtained.
[0088]
A procedure for extracting a final decoded sequence from the decoding result will be described with reference to FIG. In FIG. 8, D12 represents a data string output from the turbo code decoder 240, and D13 represents a data string output from the data bit selection unit 260. The number of bits of the data string D12 is fixed, and the number of bits of the data string D13 is variable.
[0089]
FIG. 8 corresponds to the data addition configuration shown in FIG. 4, and the necessary number of bits is determined (taken out) from the beginning of the decoding result as the final decoding result.
[0090]
A further procedure for extracting the final decoded sequence from the decoding result will be described with reference to FIG. In FIG. 9, D <b> 14 represents a data string output from the turbo code decoder 240, and D <b> 15 represents a data string output from the data bit selection unit 260. The number of bits of the data string D14 is fixed, and the number of bits of the data string D15 is variable.
[0091]
FIG. 9 corresponds to the data addition structure shown in FIG. 5, and necessary data is extracted from the position where the decoding result is determined. As a result, a final decoding result can be obtained.
[0092]
Note that the configuration according to the embodiment of the present invention can also be realized by executing a program on a storage device such as a RAM or ROM loaded with a program by a control unit such as a DSP or a CPU.
[0093]
10 and 11 show processing procedures when the processing according to the embodiment of the present invention is realized using software. FIG. 10 corresponds to data processing on the transmission side, and FIG. 11 corresponds to data processing on the reception side.
[0094]
Referring to FIG. 10, turbo code data is created in step S1. In step S2, the first convolution process is executed (corresponding to RSC1). In step S3, data puncturing is performed (corresponding to the puncturing unit 130).
[0095]
In step S4, an interleaving process is performed (corresponding to the interleaver 120). In step S5, the second convolution process is executed (corresponding to RSC2). In step S6, data puncturing is performed (corresponding to the puncturing unit 140). In step S7, data multiplexing is performed (corresponding to the multiplexing processing unit 150).
[0096]
Referring to FIG. 11, on the receiving side, in step S10, the received data is decomposed (corresponding to demultiplexing processing unit 250). In step S11, unnecessary bits of the X series are processed (corresponding to the bit padding processing unit 200). In step S12, unnecessary bits of the Y series are processed (corresponding to the bit padding processing unit 210). In step S13, unnecessary bits of the Y ′ series are processed (corresponding to the bit stuffing processing unit 220).
[0097]
In step S14, turbo decoding processing is executed (corresponding to turbo code decoder 240). In step S15, an information bit is extracted from the decoding result (corresponding to the data bit selection unit 260).
[0098]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0099]
【The invention's effect】
As described above, by using the digital transmission system and the digital transmission method according to the present invention, it is possible to cope with a dynamic change in the number of information bits to be turbo-coded. For this reason, the error correction processing can be reduced without being limited to the number of information bits required for the turbo code.
[0100]
As a result, the system can be simplified as compared with the conventional system. Therefore, the present invention can exert an especially effective effect on quality improvement in a system using a turbo code as an error correction means.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a transmission side system according to an exemplary embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a receiving system according to the embodiment of the present invention.
FIG. 3 is a block diagram showing another configuration example according to the embodiment of the present invention.
FIG. 4 is a diagram illustrating a data configuration example in a data addition process.
FIG. 5 is a diagram illustrating another configuration example of the data configuration example in the data adding unit;
FIG. 6 is a diagram illustrating a data configuration in a puncturing unit and a multiplexing processing unit.
FIG. 7 is a diagram illustrating a data configuration in a bit padding processing unit and a demultiplexing processing unit.
FIG. 8 is a diagram illustrating an example of a data bit selection process.
FIG. 9 is a diagram illustrating an example of a data bit selection process.
FIG. 10 is a flowchart showing transmission data processing (implemented by software) according to the embodiment of the present invention.
FIG. 11 is a flowchart showing received data processing (implemented by software) according to the embodiment of the present invention;
FIG. 12 is a block diagram showing a configuration of a conventional turbo encoder.
FIG. 13 is a block diagram showing a configuration of a conventional encoder (RSC).
FIG. 14 is a diagram for explaining state transition in a turbo code.
FIG. 15 is a diagram illustrating an example of state transition in a turbo code.
FIG. 16 is a diagram illustrating an example of state transition in a turbo code.
FIG. 17 is a diagram for explaining an iterative process in turbo code decoding;
FIG. 18 is a configuration diagram showing a configuration of a turbo code decoder.
FIG. 19 is a diagram illustrating a BER characteristic in a conventional turbo code.
FIG. 20 is a diagram illustrating a data flow for a turbo code.
FIG. 21 is a block diagram showing an outline of a configuration in a conventional encoding device.
FIG. 22 is a block diagram showing an outline of a configuration in a conventional encoding device.
FIG. 23 is a diagram illustrating a data flow for the turbo code in FIG. 22;
[Explanation of symbols]
10,11 Soft decision decoder, 20, 21, 22, 120, 230 interleaver, 30 decoding calculation unit, 100,110 encoder (RSC1, RSC2), 130,140 puncturing unit, 150 multiplexing processing unit, 160 input I / F section, 170 data adding section, 180 select control section, 190,191 switch, 200,210,220 bit padding processing section, 240 turbo code decoder, 250 demultiplexing processing section, 260 data bit selection section.

Claims (27)

An input interface unit to which a variable bit length data sequence is input as an input sequence, a data conversion circuit for converting the input sequence input to the input interface unit into a data sequence having a predetermined number of bits, and a turbo code Are provided corresponding to the first and second encoders for encoding the data string converted by the data conversion circuit, and puncturing by receiving the respective outputs. Receiving the first and second puncture units that perform the data sequence, the data sequence processed by the first and second puncture units, and the input sequence, and transmitting the output sequence by bit mapping executed in a predetermined procedure A multiplexing processing unit that outputs the data, and is provided between the data conversion circuit and the second encoder; Ri Run interleave processing for changing the order of the transformed data string, and outputs to the second encoder, a transmission system comprising a fixed length interleaver,
The data conversion circuit that converts the input sequence such that the fixed-length data string interleaved by the interleaver, a digital transmission system.   A first data generation circuit for generating a data string for decoding the transmission data; a decoder for executing a decoding process corresponding to the encoding based on the generated data string; and an output of the decoder The digital transmission system according to claim 1, further comprising a reception system including a second data generation circuit that receives and generates a desired data string. The transmission system includes:
The digital transmission system according to claim 1 or 2, further comprising a selection circuit that selects the predetermined number of bits among a plurality of bit number candidates. The data conversion circuit includes:
It includes circuitry for inserting a "0" to a specific portion of the data sequence number of said predetermined bits, a digital transmission system according to claim 1. The data conversion circuit includes:
It includes circuitry for inserting a "1" to a specific portion of the data sequence number of bits the predetermined digital transmission system according to claim 1. The data conversion circuit includes:
The digital transmission system according to any one of claims 1 to 3, further comprising a circuit that inserts predetermined data into a specific portion of the data string having the predetermined number of bits . Wherein the first and second puncturing section among the data output of each of the first and second encoders, to delete the data for a particular location, digital transmission according to claim 1 system. The first data creation circuit includes:
The digital transmission system according to claim 7, wherein the data of the specific portion to be deleted is replaced with information for regarding that there is no received data. The second data creation circuit includes:
The digital transmission system according to claim 4, wherein the data at the specific location is deleted. An input interface unit to which a variable bit length data sequence is input as an input sequence, a data conversion circuit for converting the input sequence input to the input interface unit into a data sequence having a predetermined number of bits, and a turbo code Are provided corresponding to the first and second encoders for encoding the data string converted by the data conversion circuit, and puncturing by receiving the respective outputs. Receiving the first and second puncture units that perform the data sequence, the data sequence processed by the first and second puncture units, and the input sequence, and transmitting the output sequence by bit mapping executed in a predetermined procedure A multiplexing processing unit that outputs the data, and is provided between the data conversion circuit and the second encoder; Ri Run interleave processing for changing the order of the transformed data string, and outputs to the second encoder, a transmission system comprising a fixed length interleaver,
The data conversion circuit that converts the input sequence such that the fixed-length data string interleaved by the interleaver, the encoding device.   The encoding device according to claim 10, further comprising a selection circuit that selects the predetermined number of bits among a plurality of bit number candidates. The data conversion circuit includes:
12. The encoding apparatus according to claim 10, further comprising a circuit that inserts “0” at a specific location of the data string having the predetermined number of bits . The data conversion circuit includes:
12. The encoding apparatus according to claim 10, further comprising a circuit that inserts “1” at a specific location of the data string having the predetermined number of bits . The data conversion circuit includes:
12. The encoding device according to claim 10, further comprising a circuit that inserts predetermined data at a specific location of the data string having the predetermined number of bits . Wherein the first and second puncturing section among the data output of each of the first and second encoders, to delete the data for a particular location, the encoding apparatus according to claim 10 or 11. An input interface unit to which a variable bit length data sequence is input as an input sequence, a data conversion circuit for converting the input sequence input to the input interface unit into a data sequence having a predetermined number of bits, and a turbo code Are provided corresponding to the first and second encoders for encoding the data string converted by the data conversion circuit, and puncturing by receiving the respective outputs. Receiving the first and second puncture units that perform the data sequence, the data sequence processed by the first and second puncture units, and the input sequence, and transmitting the output sequence by bit mapping executed in a predetermined procedure A multiplexing processing unit that outputs the data, and is provided between the data conversion circuit and the second encoder; A transmission system including a fixed-length interleaver that performs an interleaving process for changing the order of the converted data strings and outputs the interleaved data to the second encoder, and the data conversion circuit includes: A decoding device that converts the input sequence to be a fixed-length data string to be interleaved ,
A first data creation circuit for creating a data string for decoding the output series;
A decoder that executes a decoding process corresponding to the encoding based on the generated data sequence;
And a second data creation circuit for creating a desired data sequence in response to the output of the decoder. The first and second puncturing units delete data at specific locations from the data output from the first and second encoders,
The first data creation circuit includes:
The decoding device according to claim 16, wherein the data of the specific portion to be deleted is replaced with information for regarding that there is no received data. The data conversion circuit includes:
Inserting predetermined data into a specific location of the data string of the predetermined number of bits ,
The second data creation circuit includes:
The decoding device according to claim 16, wherein the data at the specific location is deleted. An input step in which a variable bit length data sequence is input as an input sequence, a data conversion step in which the input sequence is converted into a data sequence having a predetermined number of bits, and an interleave that changes the order of the converted data sequence An interleaving step for performing processing, an encoding step for encoding a data sequence converted using a turbo code, a puncturing step for performing puncturing on the encoded data sequence, and a puncturing process A transmission data creation step of receiving the data sequence and the input sequence, and outputting the output sequence as transmission data by bit mapping executed in a predetermined procedure ,
Wherein the data conversion step, that converts the input sequence such that the fixed-length data string interleaved, the data processing method in a digital transmission system. A decryption data creation step for creating a data string for decrypting the transmission data;
A decoding step of performing a decoding process corresponding to the encoding based on the generated data sequence;
20. The data processing method in the digital transmission system according to claim 19, further comprising an output data creation step of creating a desired data string in response to the result of the decoding process.   21. The data processing method in the digital transmission system according to claim 19, further comprising a selection step of selecting the predetermined number of bits among a plurality of bit number candidates. The data processing method in the digital transmission system according to any one of claims 19 to 21, wherein, in the data conversion step, "0" is inserted into a specific portion of the data string having the predetermined number of bits . The data processing method in the digital transmission system according to any one of claims 19 to 21, wherein, in the data conversion step, "1" is inserted into a specific portion of the data string having the predetermined number of bits . The data processing method in the digital transmission system according to any one of claims 19 to 21, wherein, in the data conversion step, predetermined data is inserted into a specific portion of the data string having the predetermined number of bits .   The data processing method in the digital transmission system according to any one of claims 19 to 21, wherein in the transmission data creation step, data at a specific location is deleted from the data output from the encoder.   26. The data processing method in the digital transmission system according to claim 25, wherein in the decoded data creation step, the data at the specific location to be deleted is replaced with information for regarding that no received data is present.   The data processing method in the digital transmission system according to any one of claims 22 to 24, wherein the output data creation step deletes data at the specific portion.

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